Commit | Line | Data |
---|---|---|
4bbbc1ad JY |
1 | /* |
2 | * GPMC support functions | |
3 | * | |
4 | * Copyright (C) 2005-2006 Nokia Corporation | |
5 | * | |
6 | * Author: Juha Yrjola | |
7 | * | |
44169075 SS |
8 | * Copyright (C) 2009 Texas Instruments |
9 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
10 | * | |
4bbbc1ad JY |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
fd1dc87d PW |
15 | #undef DEBUG |
16 | ||
db97eb7d | 17 | #include <linux/irq.h> |
4bbbc1ad JY |
18 | #include <linux/kernel.h> |
19 | #include <linux/init.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/clk.h> | |
f37e4580 ID |
22 | #include <linux/ioport.h> |
23 | #include <linux/spinlock.h> | |
fced80c7 | 24 | #include <linux/io.h> |
fd1dc87d | 25 | #include <linux/module.h> |
db97eb7d | 26 | #include <linux/interrupt.h> |
4bbbc1ad | 27 | |
7f245162 | 28 | #include <asm/mach-types.h> |
ce491cf8 | 29 | #include <plat/gpmc.h> |
4bbbc1ad | 30 | |
ce491cf8 | 31 | #include <plat/sdrc.h> |
72d0f1c3 | 32 | |
fd1dc87d | 33 | /* GPMC register offsets */ |
4bbbc1ad JY |
34 | #define GPMC_REVISION 0x00 |
35 | #define GPMC_SYSCONFIG 0x10 | |
36 | #define GPMC_SYSSTATUS 0x14 | |
37 | #define GPMC_IRQSTATUS 0x18 | |
38 | #define GPMC_IRQENABLE 0x1c | |
39 | #define GPMC_TIMEOUT_CONTROL 0x40 | |
40 | #define GPMC_ERR_ADDRESS 0x44 | |
41 | #define GPMC_ERR_TYPE 0x48 | |
42 | #define GPMC_CONFIG 0x50 | |
43 | #define GPMC_STATUS 0x54 | |
44 | #define GPMC_PREFETCH_CONFIG1 0x1e0 | |
45 | #define GPMC_PREFETCH_CONFIG2 0x1e4 | |
15e02a3b | 46 | #define GPMC_PREFETCH_CONTROL 0x1ec |
4bbbc1ad JY |
47 | #define GPMC_PREFETCH_STATUS 0x1f0 |
48 | #define GPMC_ECC_CONFIG 0x1f4 | |
49 | #define GPMC_ECC_CONTROL 0x1f8 | |
50 | #define GPMC_ECC_SIZE_CONFIG 0x1fc | |
948d38e7 | 51 | #define GPMC_ECC1_RESULT 0x200 |
8d602cf5 | 52 | #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */ |
4bbbc1ad | 53 | |
2c65e744 YY |
54 | /* GPMC ECC control settings */ |
55 | #define GPMC_ECC_CTRL_ECCCLEAR 0x100 | |
56 | #define GPMC_ECC_CTRL_ECCDISABLE 0x000 | |
57 | #define GPMC_ECC_CTRL_ECCREG1 0x001 | |
58 | #define GPMC_ECC_CTRL_ECCREG2 0x002 | |
59 | #define GPMC_ECC_CTRL_ECCREG3 0x003 | |
60 | #define GPMC_ECC_CTRL_ECCREG4 0x004 | |
61 | #define GPMC_ECC_CTRL_ECCREG5 0x005 | |
62 | #define GPMC_ECC_CTRL_ECCREG6 0x006 | |
63 | #define GPMC_ECC_CTRL_ECCREG7 0x007 | |
64 | #define GPMC_ECC_CTRL_ECCREG8 0x008 | |
65 | #define GPMC_ECC_CTRL_ECCREG9 0x009 | |
66 | ||
948d38e7 | 67 | #define GPMC_CS0_OFFSET 0x60 |
4bbbc1ad JY |
68 | #define GPMC_CS_SIZE 0x30 |
69 | ||
f37e4580 ID |
70 | #define GPMC_MEM_START 0x00000000 |
71 | #define GPMC_MEM_END 0x3FFFFFFF | |
72 | #define BOOT_ROM_SPACE 0x100000 /* 1MB */ | |
73 | ||
74 | #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ | |
75 | #define GPMC_SECTION_SHIFT 28 /* 128 MB */ | |
76 | ||
59e9c5ae | 77 | #define CS_NUM_SHIFT 24 |
78 | #define ENABLE_PREFETCH (0x1 << 7) | |
79 | #define DMA_MPU_MODE 2 | |
80 | ||
a2d3e7ba RN |
81 | /* Structure to save gpmc cs context */ |
82 | struct gpmc_cs_config { | |
83 | u32 config1; | |
84 | u32 config2; | |
85 | u32 config3; | |
86 | u32 config4; | |
87 | u32 config5; | |
88 | u32 config6; | |
89 | u32 config7; | |
90 | int is_valid; | |
91 | }; | |
92 | ||
93 | /* | |
94 | * Structure to save/restore gpmc context | |
95 | * to support core off on OMAP3 | |
96 | */ | |
97 | struct omap3_gpmc_regs { | |
98 | u32 sysconfig; | |
99 | u32 irqenable; | |
100 | u32 timeout_ctrl; | |
101 | u32 config; | |
102 | u32 prefetch_config1; | |
103 | u32 prefetch_config2; | |
104 | u32 prefetch_control; | |
105 | struct gpmc_cs_config cs_context[GPMC_CS_NUM]; | |
106 | }; | |
107 | ||
f37e4580 ID |
108 | static struct resource gpmc_mem_root; |
109 | static struct resource gpmc_cs_mem[GPMC_CS_NUM]; | |
87b247c4 | 110 | static DEFINE_SPINLOCK(gpmc_mem_lock); |
948d38e7 SG |
111 | static unsigned int gpmc_cs_map; /* flag for cs which are initialized */ |
112 | static int gpmc_ecc_used = -EINVAL; /* cs using ecc engine */ | |
f37e4580 | 113 | |
fd1dc87d | 114 | static void __iomem *gpmc_base; |
4bbbc1ad | 115 | |
fd1dc87d | 116 | static struct clk *gpmc_l3_clk; |
4bbbc1ad | 117 | |
db97eb7d SG |
118 | static irqreturn_t gpmc_handle_irq(int irq, void *dev); |
119 | ||
4bbbc1ad JY |
120 | static void gpmc_write_reg(int idx, u32 val) |
121 | { | |
122 | __raw_writel(val, gpmc_base + idx); | |
123 | } | |
124 | ||
125 | static u32 gpmc_read_reg(int idx) | |
126 | { | |
127 | return __raw_readl(gpmc_base + idx); | |
128 | } | |
129 | ||
948d38e7 SG |
130 | static void gpmc_cs_write_byte(int cs, int idx, u8 val) |
131 | { | |
132 | void __iomem *reg_addr; | |
133 | ||
134 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; | |
135 | __raw_writeb(val, reg_addr); | |
136 | } | |
137 | ||
138 | static u8 gpmc_cs_read_byte(int cs, int idx) | |
139 | { | |
140 | void __iomem *reg_addr; | |
141 | ||
142 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; | |
143 | return __raw_readb(reg_addr); | |
144 | } | |
145 | ||
4bbbc1ad JY |
146 | void gpmc_cs_write_reg(int cs, int idx, u32 val) |
147 | { | |
148 | void __iomem *reg_addr; | |
149 | ||
948d38e7 | 150 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; |
4bbbc1ad JY |
151 | __raw_writel(val, reg_addr); |
152 | } | |
153 | ||
154 | u32 gpmc_cs_read_reg(int cs, int idx) | |
155 | { | |
fd1dc87d PW |
156 | void __iomem *reg_addr; |
157 | ||
948d38e7 | 158 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; |
fd1dc87d | 159 | return __raw_readl(reg_addr); |
4bbbc1ad JY |
160 | } |
161 | ||
fd1dc87d | 162 | /* TODO: Add support for gpmc_fck to clock framework and use it */ |
1c22cc13 | 163 | unsigned long gpmc_get_fclk_period(void) |
4bbbc1ad | 164 | { |
fd1dc87d PW |
165 | unsigned long rate = clk_get_rate(gpmc_l3_clk); |
166 | ||
167 | if (rate == 0) { | |
168 | printk(KERN_WARNING "gpmc_l3_clk not enabled\n"); | |
169 | return 0; | |
170 | } | |
171 | ||
172 | rate /= 1000; | |
173 | rate = 1000000000 / rate; /* In picoseconds */ | |
174 | ||
175 | return rate; | |
4bbbc1ad JY |
176 | } |
177 | ||
178 | unsigned int gpmc_ns_to_ticks(unsigned int time_ns) | |
179 | { | |
180 | unsigned long tick_ps; | |
181 | ||
182 | /* Calculate in picosecs to yield more exact results */ | |
183 | tick_ps = gpmc_get_fclk_period(); | |
184 | ||
185 | return (time_ns * 1000 + tick_ps - 1) / tick_ps; | |
186 | } | |
187 | ||
a3551f5b AH |
188 | unsigned int gpmc_ps_to_ticks(unsigned int time_ps) |
189 | { | |
190 | unsigned long tick_ps; | |
191 | ||
192 | /* Calculate in picosecs to yield more exact results */ | |
193 | tick_ps = gpmc_get_fclk_period(); | |
194 | ||
195 | return (time_ps + tick_ps - 1) / tick_ps; | |
196 | } | |
197 | ||
fd1dc87d PW |
198 | unsigned int gpmc_ticks_to_ns(unsigned int ticks) |
199 | { | |
200 | return ticks * gpmc_get_fclk_period() / 1000; | |
201 | } | |
202 | ||
23300597 KS |
203 | unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns) |
204 | { | |
205 | unsigned long ticks = gpmc_ns_to_ticks(time_ns); | |
206 | ||
207 | return ticks * gpmc_get_fclk_period() / 1000; | |
208 | } | |
209 | ||
4bbbc1ad JY |
210 | #ifdef DEBUG |
211 | static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, | |
2aab6468 | 212 | int time, const char *name) |
4bbbc1ad JY |
213 | #else |
214 | static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, | |
215 | int time) | |
216 | #endif | |
217 | { | |
218 | u32 l; | |
219 | int ticks, mask, nr_bits; | |
220 | ||
221 | if (time == 0) | |
222 | ticks = 0; | |
223 | else | |
224 | ticks = gpmc_ns_to_ticks(time); | |
225 | nr_bits = end_bit - st_bit + 1; | |
1c22cc13 DB |
226 | if (ticks >= 1 << nr_bits) { |
227 | #ifdef DEBUG | |
228 | printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n", | |
229 | cs, name, time, ticks, 1 << nr_bits); | |
230 | #endif | |
4bbbc1ad | 231 | return -1; |
1c22cc13 | 232 | } |
4bbbc1ad JY |
233 | |
234 | mask = (1 << nr_bits) - 1; | |
235 | l = gpmc_cs_read_reg(cs, reg); | |
236 | #ifdef DEBUG | |
1c22cc13 DB |
237 | printk(KERN_INFO |
238 | "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", | |
2aab6468 | 239 | cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000, |
1c22cc13 | 240 | (l >> st_bit) & mask, time); |
4bbbc1ad JY |
241 | #endif |
242 | l &= ~(mask << st_bit); | |
243 | l |= ticks << st_bit; | |
244 | gpmc_cs_write_reg(cs, reg, l); | |
245 | ||
246 | return 0; | |
247 | } | |
248 | ||
249 | #ifdef DEBUG | |
250 | #define GPMC_SET_ONE(reg, st, end, field) \ | |
251 | if (set_gpmc_timing_reg(cs, (reg), (st), (end), \ | |
252 | t->field, #field) < 0) \ | |
253 | return -1 | |
254 | #else | |
255 | #define GPMC_SET_ONE(reg, st, end, field) \ | |
256 | if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \ | |
257 | return -1 | |
258 | #endif | |
259 | ||
260 | int gpmc_cs_calc_divider(int cs, unsigned int sync_clk) | |
261 | { | |
262 | int div; | |
263 | u32 l; | |
264 | ||
a3551f5b | 265 | l = sync_clk + (gpmc_get_fclk_period() - 1); |
4bbbc1ad JY |
266 | div = l / gpmc_get_fclk_period(); |
267 | if (div > 4) | |
268 | return -1; | |
1c22cc13 | 269 | if (div <= 0) |
4bbbc1ad JY |
270 | div = 1; |
271 | ||
272 | return div; | |
273 | } | |
274 | ||
275 | int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) | |
276 | { | |
277 | int div; | |
278 | u32 l; | |
279 | ||
280 | div = gpmc_cs_calc_divider(cs, t->sync_clk); | |
281 | if (div < 0) | |
282 | return -1; | |
283 | ||
284 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on); | |
285 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off); | |
286 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off); | |
287 | ||
288 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on); | |
289 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off); | |
290 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off); | |
291 | ||
292 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on); | |
293 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off); | |
294 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on); | |
295 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off); | |
296 | ||
297 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle); | |
298 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle); | |
299 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access); | |
300 | ||
301 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); | |
302 | ||
cc26b3b0 SMK |
303 | if (cpu_is_omap34xx()) { |
304 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus); | |
305 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access); | |
306 | } | |
307 | ||
1c22cc13 DB |
308 | /* caller is expected to have initialized CONFIG1 to cover |
309 | * at least sync vs async | |
310 | */ | |
311 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
312 | if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) { | |
4bbbc1ad | 313 | #ifdef DEBUG |
1c22cc13 DB |
314 | printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n", |
315 | cs, (div * gpmc_get_fclk_period()) / 1000, div); | |
4bbbc1ad | 316 | #endif |
1c22cc13 DB |
317 | l &= ~0x03; |
318 | l |= (div - 1); | |
319 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l); | |
320 | } | |
4bbbc1ad JY |
321 | |
322 | return 0; | |
323 | } | |
324 | ||
f37e4580 ID |
325 | static void gpmc_cs_enable_mem(int cs, u32 base, u32 size) |
326 | { | |
327 | u32 l; | |
328 | u32 mask; | |
329 | ||
330 | mask = (1 << GPMC_SECTION_SHIFT) - size; | |
331 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
332 | l &= ~0x3f; | |
333 | l = (base >> GPMC_CHUNK_SHIFT) & 0x3f; | |
334 | l &= ~(0x0f << 8); | |
335 | l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8; | |
a2d3e7ba | 336 | l |= GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
337 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
338 | } | |
339 | ||
340 | static void gpmc_cs_disable_mem(int cs) | |
341 | { | |
342 | u32 l; | |
343 | ||
344 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
a2d3e7ba | 345 | l &= ~GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
346 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
347 | } | |
348 | ||
349 | static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size) | |
350 | { | |
351 | u32 l; | |
352 | u32 mask; | |
353 | ||
354 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
355 | *base = (l & 0x3f) << GPMC_CHUNK_SHIFT; | |
356 | mask = (l >> 8) & 0x0f; | |
357 | *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT); | |
358 | } | |
359 | ||
360 | static int gpmc_cs_mem_enabled(int cs) | |
361 | { | |
362 | u32 l; | |
363 | ||
364 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
a2d3e7ba | 365 | return l & GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
366 | } |
367 | ||
c40fae95 | 368 | int gpmc_cs_set_reserved(int cs, int reserved) |
4bbbc1ad | 369 | { |
c40fae95 TL |
370 | if (cs > GPMC_CS_NUM) |
371 | return -ENODEV; | |
372 | ||
f37e4580 ID |
373 | gpmc_cs_map &= ~(1 << cs); |
374 | gpmc_cs_map |= (reserved ? 1 : 0) << cs; | |
c40fae95 TL |
375 | |
376 | return 0; | |
f37e4580 ID |
377 | } |
378 | ||
c40fae95 | 379 | int gpmc_cs_reserved(int cs) |
f37e4580 | 380 | { |
c40fae95 TL |
381 | if (cs > GPMC_CS_NUM) |
382 | return -ENODEV; | |
383 | ||
f37e4580 ID |
384 | return gpmc_cs_map & (1 << cs); |
385 | } | |
386 | ||
387 | static unsigned long gpmc_mem_align(unsigned long size) | |
388 | { | |
389 | int order; | |
390 | ||
391 | size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1); | |
392 | order = GPMC_CHUNK_SHIFT - 1; | |
393 | do { | |
394 | size >>= 1; | |
395 | order++; | |
396 | } while (size); | |
397 | size = 1 << order; | |
398 | return size; | |
399 | } | |
400 | ||
401 | static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) | |
402 | { | |
403 | struct resource *res = &gpmc_cs_mem[cs]; | |
404 | int r; | |
405 | ||
406 | size = gpmc_mem_align(size); | |
407 | spin_lock(&gpmc_mem_lock); | |
408 | res->start = base; | |
409 | res->end = base + size - 1; | |
410 | r = request_resource(&gpmc_mem_root, res); | |
411 | spin_unlock(&gpmc_mem_lock); | |
412 | ||
413 | return r; | |
414 | } | |
415 | ||
416 | int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) | |
417 | { | |
418 | struct resource *res = &gpmc_cs_mem[cs]; | |
419 | int r = -1; | |
420 | ||
421 | if (cs > GPMC_CS_NUM) | |
422 | return -ENODEV; | |
423 | ||
424 | size = gpmc_mem_align(size); | |
425 | if (size > (1 << GPMC_SECTION_SHIFT)) | |
426 | return -ENOMEM; | |
427 | ||
428 | spin_lock(&gpmc_mem_lock); | |
429 | if (gpmc_cs_reserved(cs)) { | |
430 | r = -EBUSY; | |
431 | goto out; | |
432 | } | |
433 | if (gpmc_cs_mem_enabled(cs)) | |
434 | r = adjust_resource(res, res->start & ~(size - 1), size); | |
435 | if (r < 0) | |
436 | r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0, | |
437 | size, NULL, NULL); | |
438 | if (r < 0) | |
439 | goto out; | |
440 | ||
6d135242 | 441 | gpmc_cs_enable_mem(cs, res->start, resource_size(res)); |
f37e4580 ID |
442 | *base = res->start; |
443 | gpmc_cs_set_reserved(cs, 1); | |
444 | out: | |
445 | spin_unlock(&gpmc_mem_lock); | |
446 | return r; | |
447 | } | |
fd1dc87d | 448 | EXPORT_SYMBOL(gpmc_cs_request); |
f37e4580 ID |
449 | |
450 | void gpmc_cs_free(int cs) | |
451 | { | |
452 | spin_lock(&gpmc_mem_lock); | |
e7fdc605 | 453 | if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) { |
f37e4580 ID |
454 | printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs); |
455 | BUG(); | |
456 | spin_unlock(&gpmc_mem_lock); | |
457 | return; | |
458 | } | |
459 | gpmc_cs_disable_mem(cs); | |
460 | release_resource(&gpmc_cs_mem[cs]); | |
461 | gpmc_cs_set_reserved(cs, 0); | |
462 | spin_unlock(&gpmc_mem_lock); | |
463 | } | |
fd1dc87d | 464 | EXPORT_SYMBOL(gpmc_cs_free); |
f37e4580 | 465 | |
948d38e7 SG |
466 | /** |
467 | * gpmc_read_status - read access request to get the different gpmc status | |
468 | * @cmd: command type | |
469 | * @return status | |
470 | */ | |
471 | int gpmc_read_status(int cmd) | |
472 | { | |
473 | int status = -EINVAL; | |
474 | u32 regval = 0; | |
475 | ||
476 | switch (cmd) { | |
477 | case GPMC_GET_IRQ_STATUS: | |
478 | status = gpmc_read_reg(GPMC_IRQSTATUS); | |
479 | break; | |
480 | ||
481 | case GPMC_PREFETCH_FIFO_CNT: | |
482 | regval = gpmc_read_reg(GPMC_PREFETCH_STATUS); | |
483 | status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval); | |
484 | break; | |
485 | ||
486 | case GPMC_PREFETCH_COUNT: | |
487 | regval = gpmc_read_reg(GPMC_PREFETCH_STATUS); | |
488 | status = GPMC_PREFETCH_STATUS_COUNT(regval); | |
489 | break; | |
490 | ||
491 | case GPMC_STATUS_BUFFER: | |
492 | regval = gpmc_read_reg(GPMC_STATUS); | |
493 | /* 1 : buffer is available to write */ | |
494 | status = regval & GPMC_STATUS_BUFF_EMPTY; | |
495 | break; | |
496 | ||
497 | default: | |
498 | printk(KERN_ERR "gpmc_read_status: Not supported\n"); | |
499 | } | |
500 | return status; | |
501 | } | |
502 | EXPORT_SYMBOL(gpmc_read_status); | |
503 | ||
504 | /** | |
505 | * gpmc_cs_configure - write request to configure gpmc | |
506 | * @cs: chip select number | |
507 | * @cmd: command type | |
508 | * @wval: value to write | |
509 | * @return status of the operation | |
510 | */ | |
511 | int gpmc_cs_configure(int cs, int cmd, int wval) | |
512 | { | |
513 | int err = 0; | |
514 | u32 regval = 0; | |
515 | ||
516 | switch (cmd) { | |
db97eb7d SG |
517 | case GPMC_ENABLE_IRQ: |
518 | gpmc_write_reg(GPMC_IRQENABLE, wval); | |
519 | break; | |
520 | ||
948d38e7 SG |
521 | case GPMC_SET_IRQ_STATUS: |
522 | gpmc_write_reg(GPMC_IRQSTATUS, wval); | |
523 | break; | |
524 | ||
525 | case GPMC_CONFIG_WP: | |
526 | regval = gpmc_read_reg(GPMC_CONFIG); | |
527 | if (wval) | |
528 | regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */ | |
529 | else | |
530 | regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */ | |
531 | gpmc_write_reg(GPMC_CONFIG, regval); | |
532 | break; | |
533 | ||
534 | case GPMC_CONFIG_RDY_BSY: | |
535 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
536 | if (wval) | |
537 | regval |= WR_RD_PIN_MONITORING; | |
538 | else | |
539 | regval &= ~WR_RD_PIN_MONITORING; | |
540 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); | |
541 | break; | |
542 | ||
543 | case GPMC_CONFIG_DEV_SIZE: | |
544 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
8ef5d844 YY |
545 | |
546 | /* clear 2 target bits */ | |
547 | regval &= ~GPMC_CONFIG1_DEVICESIZE(3); | |
548 | ||
549 | /* set the proper value */ | |
948d38e7 | 550 | regval |= GPMC_CONFIG1_DEVICESIZE(wval); |
8ef5d844 | 551 | |
948d38e7 SG |
552 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); |
553 | break; | |
554 | ||
555 | case GPMC_CONFIG_DEV_TYPE: | |
556 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
557 | regval |= GPMC_CONFIG1_DEVICETYPE(wval); | |
558 | if (wval == GPMC_DEVICETYPE_NOR) | |
559 | regval |= GPMC_CONFIG1_MUXADDDATA; | |
560 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); | |
561 | break; | |
562 | ||
563 | default: | |
564 | printk(KERN_ERR "gpmc_configure_cs: Not supported\n"); | |
565 | err = -EINVAL; | |
566 | } | |
567 | ||
568 | return err; | |
569 | } | |
570 | EXPORT_SYMBOL(gpmc_cs_configure); | |
571 | ||
572 | /** | |
573 | * gpmc_nand_read - nand specific read access request | |
574 | * @cs: chip select number | |
575 | * @cmd: command type | |
576 | */ | |
577 | int gpmc_nand_read(int cs, int cmd) | |
578 | { | |
579 | int rval = -EINVAL; | |
580 | ||
581 | switch (cmd) { | |
582 | case GPMC_NAND_DATA: | |
583 | rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA); | |
584 | break; | |
585 | ||
586 | default: | |
587 | printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n"); | |
588 | } | |
589 | return rval; | |
590 | } | |
591 | EXPORT_SYMBOL(gpmc_nand_read); | |
592 | ||
593 | /** | |
594 | * gpmc_nand_write - nand specific write request | |
595 | * @cs: chip select number | |
596 | * @cmd: command type | |
597 | * @wval: value to write | |
598 | */ | |
599 | int gpmc_nand_write(int cs, int cmd, int wval) | |
600 | { | |
601 | int err = 0; | |
602 | ||
603 | switch (cmd) { | |
604 | case GPMC_NAND_COMMAND: | |
605 | gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval); | |
606 | break; | |
607 | ||
608 | case GPMC_NAND_ADDRESS: | |
609 | gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval); | |
610 | break; | |
611 | ||
612 | case GPMC_NAND_DATA: | |
613 | gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval); | |
614 | ||
615 | default: | |
616 | printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n"); | |
617 | err = -EINVAL; | |
618 | } | |
619 | return err; | |
620 | } | |
621 | EXPORT_SYMBOL(gpmc_nand_write); | |
622 | ||
623 | ||
624 | ||
59e9c5ae | 625 | /** |
626 | * gpmc_prefetch_enable - configures and starts prefetch transfer | |
948d38e7 | 627 | * @cs: cs (chip select) number |
317379a9 | 628 | * @fifo_th: fifo threshold to be used for read/ write |
59e9c5ae | 629 | * @dma_mode: dma mode enable (1) or disable (0) |
630 | * @u32_count: number of bytes to be transferred | |
631 | * @is_write: prefetch read(0) or write post(1) mode | |
632 | */ | |
317379a9 | 633 | int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode, |
59e9c5ae | 634 | unsigned int u32_count, int is_write) |
635 | { | |
59e9c5ae | 636 | |
317379a9 SG |
637 | if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) { |
638 | pr_err("gpmc: fifo threshold is not supported\n"); | |
639 | return -1; | |
640 | } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) { | |
59e9c5ae | 641 | /* Set the amount of bytes to be prefetched */ |
642 | gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count); | |
643 | ||
644 | /* Set dma/mpu mode, the prefetch read / post write and | |
645 | * enable the engine. Set which cs is has requested for. | |
646 | */ | |
948d38e7 | 647 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) | |
317379a9 | 648 | PREFETCH_FIFOTHRESHOLD(fifo_th) | |
59e9c5ae | 649 | ENABLE_PREFETCH | |
650 | (dma_mode << DMA_MPU_MODE) | | |
948d38e7 SG |
651 | (0x1 & is_write))); |
652 | ||
653 | /* Start the prefetch engine */ | |
654 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1); | |
59e9c5ae | 655 | } else { |
656 | return -EBUSY; | |
657 | } | |
59e9c5ae | 658 | |
659 | return 0; | |
660 | } | |
661 | EXPORT_SYMBOL(gpmc_prefetch_enable); | |
662 | ||
663 | /** | |
664 | * gpmc_prefetch_reset - disables and stops the prefetch engine | |
665 | */ | |
948d38e7 | 666 | int gpmc_prefetch_reset(int cs) |
59e9c5ae | 667 | { |
948d38e7 SG |
668 | u32 config1; |
669 | ||
670 | /* check if the same module/cs is trying to reset */ | |
671 | config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); | |
672 | if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs) | |
673 | return -EINVAL; | |
674 | ||
59e9c5ae | 675 | /* Stop the PFPW engine */ |
676 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0); | |
677 | ||
678 | /* Reset/disable the PFPW engine */ | |
679 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0); | |
948d38e7 SG |
680 | |
681 | return 0; | |
59e9c5ae | 682 | } |
683 | EXPORT_SYMBOL(gpmc_prefetch_reset); | |
684 | ||
fd1dc87d | 685 | static void __init gpmc_mem_init(void) |
f37e4580 ID |
686 | { |
687 | int cs; | |
688 | unsigned long boot_rom_space = 0; | |
689 | ||
7f245162 KP |
690 | /* never allocate the first page, to facilitate bug detection; |
691 | * even if we didn't boot from ROM. | |
692 | */ | |
693 | boot_rom_space = BOOT_ROM_SPACE; | |
694 | /* In apollon the CS0 is mapped as 0x0000 0000 */ | |
695 | if (machine_is_omap_apollon()) | |
696 | boot_rom_space = 0; | |
f37e4580 ID |
697 | gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space; |
698 | gpmc_mem_root.end = GPMC_MEM_END; | |
699 | ||
700 | /* Reserve all regions that has been set up by bootloader */ | |
701 | for (cs = 0; cs < GPMC_CS_NUM; cs++) { | |
702 | u32 base, size; | |
703 | ||
704 | if (!gpmc_cs_mem_enabled(cs)) | |
705 | continue; | |
706 | gpmc_cs_get_memconf(cs, &base, &size); | |
707 | if (gpmc_cs_insert_mem(cs, base, size) < 0) | |
708 | BUG(); | |
709 | } | |
4bbbc1ad JY |
710 | } |
711 | ||
db97eb7d | 712 | static int __init gpmc_init(void) |
4bbbc1ad | 713 | { |
db97eb7d SG |
714 | u32 l, irq; |
715 | int cs, ret = -EINVAL; | |
77aded2f | 716 | int gpmc_irq; |
8d08436d | 717 | char *ck = NULL; |
fd1dc87d PW |
718 | |
719 | if (cpu_is_omap24xx()) { | |
720 | ck = "core_l3_ck"; | |
721 | if (cpu_is_omap2420()) | |
722 | l = OMAP2420_GPMC_BASE; | |
723 | else | |
724 | l = OMAP34XX_GPMC_BASE; | |
77aded2f | 725 | gpmc_irq = INT_34XX_GPMC_IRQ; |
fd1dc87d PW |
726 | } else if (cpu_is_omap34xx()) { |
727 | ck = "gpmc_fck"; | |
728 | l = OMAP34XX_GPMC_BASE; | |
77aded2f | 729 | gpmc_irq = INT_34XX_GPMC_IRQ; |
1a5da219 S |
730 | } else if (cpu_is_omap44xx() || soc_is_omap54xx()) { |
731 | /* Base address and irq number are same for OMAP4/5 */ | |
d79b1267 | 732 | ck = "gpmc_ck"; |
44169075 | 733 | l = OMAP44XX_GPMC_BASE; |
77aded2f | 734 | gpmc_irq = OMAP44XX_IRQ_GPMC; |
fd1dc87d | 735 | } |
4bbbc1ad | 736 | |
8d08436d | 737 | if (WARN_ON(!ck)) |
db97eb7d | 738 | return ret; |
8d08436d | 739 | |
fd1dc87d PW |
740 | gpmc_l3_clk = clk_get(NULL, ck); |
741 | if (IS_ERR(gpmc_l3_clk)) { | |
742 | printk(KERN_ERR "Could not get GPMC clock %s\n", ck); | |
85d7a070 | 743 | BUG(); |
fd1dc87d PW |
744 | } |
745 | ||
746 | gpmc_base = ioremap(l, SZ_4K); | |
747 | if (!gpmc_base) { | |
748 | clk_put(gpmc_l3_clk); | |
749 | printk(KERN_ERR "Could not get GPMC register memory\n"); | |
85d7a070 | 750 | BUG(); |
fd1dc87d PW |
751 | } |
752 | ||
1daa8c1d OJ |
753 | clk_enable(gpmc_l3_clk); |
754 | ||
4bbbc1ad JY |
755 | l = gpmc_read_reg(GPMC_REVISION); |
756 | printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); | |
757 | /* Set smart idle mode and automatic L3 clock gating */ | |
758 | l = gpmc_read_reg(GPMC_SYSCONFIG); | |
759 | l &= 0x03 << 3; | |
760 | l |= (0x02 << 3) | (1 << 0); | |
761 | gpmc_write_reg(GPMC_SYSCONFIG, l); | |
f37e4580 | 762 | gpmc_mem_init(); |
db97eb7d SG |
763 | |
764 | /* initalize the irq_chained */ | |
765 | irq = OMAP_GPMC_IRQ_BASE; | |
766 | for (cs = 0; cs < GPMC_CS_NUM; cs++) { | |
6845664a | 767 | irq_set_chip_and_handler(irq, &dummy_irq_chip, |
77aded2f | 768 | handle_simple_irq); |
db97eb7d SG |
769 | set_irq_flags(irq, IRQF_VALID); |
770 | irq++; | |
771 | } | |
772 | ||
355f8eee | 773 | ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", NULL); |
db97eb7d SG |
774 | if (ret) |
775 | pr_err("gpmc: irq-%d could not claim: err %d\n", | |
77aded2f | 776 | gpmc_irq, ret); |
db97eb7d SG |
777 | return ret; |
778 | } | |
779 | postcore_initcall(gpmc_init); | |
780 | ||
781 | static irqreturn_t gpmc_handle_irq(int irq, void *dev) | |
782 | { | |
783 | u8 cs; | |
784 | ||
db97eb7d SG |
785 | /* check cs to invoke the irq */ |
786 | cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7; | |
787 | if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END) | |
788 | generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs); | |
789 | ||
790 | return IRQ_HANDLED; | |
4bbbc1ad | 791 | } |
a2d3e7ba RN |
792 | |
793 | #ifdef CONFIG_ARCH_OMAP3 | |
794 | static struct omap3_gpmc_regs gpmc_context; | |
795 | ||
b2fa3b7c | 796 | void omap3_gpmc_save_context(void) |
a2d3e7ba RN |
797 | { |
798 | int i; | |
b2fa3b7c | 799 | |
a2d3e7ba RN |
800 | gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG); |
801 | gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE); | |
802 | gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL); | |
803 | gpmc_context.config = gpmc_read_reg(GPMC_CONFIG); | |
804 | gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); | |
805 | gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2); | |
806 | gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL); | |
807 | for (i = 0; i < GPMC_CS_NUM; i++) { | |
808 | gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i); | |
809 | if (gpmc_context.cs_context[i].is_valid) { | |
810 | gpmc_context.cs_context[i].config1 = | |
811 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG1); | |
812 | gpmc_context.cs_context[i].config2 = | |
813 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG2); | |
814 | gpmc_context.cs_context[i].config3 = | |
815 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG3); | |
816 | gpmc_context.cs_context[i].config4 = | |
817 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG4); | |
818 | gpmc_context.cs_context[i].config5 = | |
819 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG5); | |
820 | gpmc_context.cs_context[i].config6 = | |
821 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG6); | |
822 | gpmc_context.cs_context[i].config7 = | |
823 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG7); | |
824 | } | |
825 | } | |
826 | } | |
827 | ||
b2fa3b7c | 828 | void omap3_gpmc_restore_context(void) |
a2d3e7ba RN |
829 | { |
830 | int i; | |
b2fa3b7c | 831 | |
a2d3e7ba RN |
832 | gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig); |
833 | gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable); | |
834 | gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl); | |
835 | gpmc_write_reg(GPMC_CONFIG, gpmc_context.config); | |
836 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1); | |
837 | gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2); | |
838 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control); | |
839 | for (i = 0; i < GPMC_CS_NUM; i++) { | |
840 | if (gpmc_context.cs_context[i].is_valid) { | |
841 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG1, | |
842 | gpmc_context.cs_context[i].config1); | |
843 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG2, | |
844 | gpmc_context.cs_context[i].config2); | |
845 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG3, | |
846 | gpmc_context.cs_context[i].config3); | |
847 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG4, | |
848 | gpmc_context.cs_context[i].config4); | |
849 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG5, | |
850 | gpmc_context.cs_context[i].config5); | |
851 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG6, | |
852 | gpmc_context.cs_context[i].config6); | |
853 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, | |
854 | gpmc_context.cs_context[i].config7); | |
855 | } | |
856 | } | |
857 | } | |
858 | #endif /* CONFIG_ARCH_OMAP3 */ | |
948d38e7 SG |
859 | |
860 | /** | |
861 | * gpmc_enable_hwecc - enable hardware ecc functionality | |
862 | * @cs: chip select number | |
863 | * @mode: read/write mode | |
864 | * @dev_width: device bus width(1 for x16, 0 for x8) | |
865 | * @ecc_size: bytes for which ECC will be generated | |
866 | */ | |
867 | int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size) | |
868 | { | |
869 | unsigned int val; | |
870 | ||
871 | /* check if ecc module is in used */ | |
872 | if (gpmc_ecc_used != -EINVAL) | |
873 | return -EINVAL; | |
874 | ||
875 | gpmc_ecc_used = cs; | |
876 | ||
877 | /* clear ecc and enable bits */ | |
2c65e744 YY |
878 | gpmc_write_reg(GPMC_ECC_CONTROL, |
879 | GPMC_ECC_CTRL_ECCCLEAR | | |
880 | GPMC_ECC_CTRL_ECCREG1); | |
948d38e7 SG |
881 | |
882 | /* program ecc and result sizes */ | |
883 | val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F)); | |
884 | gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val); | |
885 | ||
886 | switch (mode) { | |
887 | case GPMC_ECC_READ: | |
2c65e744 YY |
888 | case GPMC_ECC_WRITE: |
889 | gpmc_write_reg(GPMC_ECC_CONTROL, | |
890 | GPMC_ECC_CTRL_ECCCLEAR | | |
891 | GPMC_ECC_CTRL_ECCREG1); | |
948d38e7 SG |
892 | break; |
893 | case GPMC_ECC_READSYN: | |
2c65e744 YY |
894 | gpmc_write_reg(GPMC_ECC_CONTROL, |
895 | GPMC_ECC_CTRL_ECCCLEAR | | |
896 | GPMC_ECC_CTRL_ECCDISABLE); | |
948d38e7 SG |
897 | break; |
898 | default: | |
899 | printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode); | |
900 | break; | |
901 | } | |
902 | ||
903 | /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ | |
904 | val = (dev_width << 7) | (cs << 1) | (0x1); | |
905 | gpmc_write_reg(GPMC_ECC_CONFIG, val); | |
906 | return 0; | |
907 | } | |
f611b020 | 908 | EXPORT_SYMBOL_GPL(gpmc_enable_hwecc); |
948d38e7 SG |
909 | |
910 | /** | |
911 | * gpmc_calculate_ecc - generate non-inverted ecc bytes | |
912 | * @cs: chip select number | |
913 | * @dat: data pointer over which ecc is computed | |
914 | * @ecc_code: ecc code buffer | |
915 | * | |
916 | * Using non-inverted ECC is considered ugly since writing a blank | |
917 | * page (padding) will clear the ECC bytes. This is not a problem as long | |
918 | * no one is trying to write data on the seemingly unused page. Reading | |
919 | * an erased page will produce an ECC mismatch between generated and read | |
920 | * ECC bytes that has to be dealt with separately. | |
921 | */ | |
922 | int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code) | |
923 | { | |
924 | unsigned int val = 0x0; | |
925 | ||
926 | if (gpmc_ecc_used != cs) | |
927 | return -EINVAL; | |
928 | ||
929 | /* read ecc result */ | |
930 | val = gpmc_read_reg(GPMC_ECC1_RESULT); | |
931 | *ecc_code++ = val; /* P128e, ..., P1e */ | |
932 | *ecc_code++ = val >> 16; /* P128o, ..., P1o */ | |
933 | /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ | |
934 | *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); | |
935 | ||
936 | gpmc_ecc_used = -EINVAL; | |
937 | return 0; | |
938 | } | |
f611b020 | 939 | EXPORT_SYMBOL_GPL(gpmc_calculate_ecc); |
8d602cf5 ID |
940 | |
941 | #ifdef CONFIG_ARCH_OMAP3 | |
942 | ||
943 | /** | |
944 | * gpmc_init_hwecc_bch - initialize hardware BCH ecc functionality | |
945 | * @cs: chip select number | |
946 | * @nsectors: how many 512-byte sectors to process | |
947 | * @nerrors: how many errors to correct per sector (4 or 8) | |
948 | * | |
949 | * This function must be executed before any call to gpmc_enable_hwecc_bch. | |
950 | */ | |
951 | int gpmc_init_hwecc_bch(int cs, int nsectors, int nerrors) | |
952 | { | |
953 | /* check if ecc module is in use */ | |
954 | if (gpmc_ecc_used != -EINVAL) | |
955 | return -EINVAL; | |
956 | ||
957 | /* support only OMAP3 class */ | |
958 | if (!cpu_is_omap34xx()) { | |
959 | printk(KERN_ERR "BCH ecc is not supported on this CPU\n"); | |
960 | return -EINVAL; | |
961 | } | |
962 | ||
963 | /* | |
964 | * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1. | |
965 | * Other chips may be added if confirmed to work. | |
966 | */ | |
967 | if ((nerrors == 4) && | |
968 | (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) { | |
969 | printk(KERN_ERR "BCH 4-bit mode is not supported on this CPU\n"); | |
970 | return -EINVAL; | |
971 | } | |
972 | ||
973 | /* sanity check */ | |
974 | if (nsectors > 8) { | |
975 | printk(KERN_ERR "BCH cannot process %d sectors (max is 8)\n", | |
976 | nsectors); | |
977 | return -EINVAL; | |
978 | } | |
979 | ||
980 | return 0; | |
981 | } | |
982 | EXPORT_SYMBOL_GPL(gpmc_init_hwecc_bch); | |
983 | ||
984 | /** | |
985 | * gpmc_enable_hwecc_bch - enable hardware BCH ecc functionality | |
986 | * @cs: chip select number | |
987 | * @mode: read/write mode | |
988 | * @dev_width: device bus width(1 for x16, 0 for x8) | |
989 | * @nsectors: how many 512-byte sectors to process | |
990 | * @nerrors: how many errors to correct per sector (4 or 8) | |
991 | */ | |
992 | int gpmc_enable_hwecc_bch(int cs, int mode, int dev_width, int nsectors, | |
993 | int nerrors) | |
994 | { | |
995 | unsigned int val; | |
996 | ||
997 | /* check if ecc module is in use */ | |
998 | if (gpmc_ecc_used != -EINVAL) | |
999 | return -EINVAL; | |
1000 | ||
1001 | gpmc_ecc_used = cs; | |
1002 | ||
1003 | /* clear ecc and enable bits */ | |
1004 | gpmc_write_reg(GPMC_ECC_CONTROL, 0x1); | |
1005 | ||
1006 | /* | |
1007 | * When using BCH, sector size is hardcoded to 512 bytes. | |
1008 | * Here we are using wrapping mode 6 both for reading and writing, with: | |
1009 | * size0 = 0 (no additional protected byte in spare area) | |
1010 | * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area) | |
1011 | */ | |
1012 | gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, (32 << 22) | (0 << 12)); | |
1013 | ||
1014 | /* BCH configuration */ | |
1015 | val = ((1 << 16) | /* enable BCH */ | |
1016 | (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */ | |
1017 | (0x06 << 8) | /* wrap mode = 6 */ | |
1018 | (dev_width << 7) | /* bus width */ | |
1019 | (((nsectors-1) & 0x7) << 4) | /* number of sectors */ | |
1020 | (cs << 1) | /* ECC CS */ | |
1021 | (0x1)); /* enable ECC */ | |
1022 | ||
1023 | gpmc_write_reg(GPMC_ECC_CONFIG, val); | |
1024 | gpmc_write_reg(GPMC_ECC_CONTROL, 0x101); | |
1025 | return 0; | |
1026 | } | |
1027 | EXPORT_SYMBOL_GPL(gpmc_enable_hwecc_bch); | |
1028 | ||
1029 | /** | |
1030 | * gpmc_calculate_ecc_bch4 - Generate 7 ecc bytes per sector of 512 data bytes | |
1031 | * @cs: chip select number | |
1032 | * @dat: The pointer to data on which ecc is computed | |
1033 | * @ecc: The ecc output buffer | |
1034 | */ | |
1035 | int gpmc_calculate_ecc_bch4(int cs, const u_char *dat, u_char *ecc) | |
1036 | { | |
1037 | int i; | |
1038 | unsigned long nsectors, reg, val1, val2; | |
1039 | ||
1040 | if (gpmc_ecc_used != cs) | |
1041 | return -EINVAL; | |
1042 | ||
1043 | nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1; | |
1044 | ||
1045 | for (i = 0; i < nsectors; i++) { | |
1046 | ||
1047 | reg = GPMC_ECC_BCH_RESULT_0 + 16*i; | |
1048 | ||
1049 | /* Read hw-computed remainder */ | |
1050 | val1 = gpmc_read_reg(reg + 0); | |
1051 | val2 = gpmc_read_reg(reg + 4); | |
1052 | ||
1053 | /* | |
1054 | * Add constant polynomial to remainder, in order to get an ecc | |
1055 | * sequence of 0xFFs for a buffer filled with 0xFFs; and | |
1056 | * left-justify the resulting polynomial. | |
1057 | */ | |
1058 | *ecc++ = 0x28 ^ ((val2 >> 12) & 0xFF); | |
1059 | *ecc++ = 0x13 ^ ((val2 >> 4) & 0xFF); | |
1060 | *ecc++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF)); | |
1061 | *ecc++ = 0x39 ^ ((val1 >> 20) & 0xFF); | |
1062 | *ecc++ = 0x96 ^ ((val1 >> 12) & 0xFF); | |
1063 | *ecc++ = 0xac ^ ((val1 >> 4) & 0xFF); | |
1064 | *ecc++ = 0x7f ^ ((val1 & 0xF) << 4); | |
1065 | } | |
1066 | ||
1067 | gpmc_ecc_used = -EINVAL; | |
1068 | return 0; | |
1069 | } | |
1070 | EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch4); | |
1071 | ||
1072 | /** | |
1073 | * gpmc_calculate_ecc_bch8 - Generate 13 ecc bytes per block of 512 data bytes | |
1074 | * @cs: chip select number | |
1075 | * @dat: The pointer to data on which ecc is computed | |
1076 | * @ecc: The ecc output buffer | |
1077 | */ | |
1078 | int gpmc_calculate_ecc_bch8(int cs, const u_char *dat, u_char *ecc) | |
1079 | { | |
1080 | int i; | |
1081 | unsigned long nsectors, reg, val1, val2, val3, val4; | |
1082 | ||
1083 | if (gpmc_ecc_used != cs) | |
1084 | return -EINVAL; | |
1085 | ||
1086 | nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1; | |
1087 | ||
1088 | for (i = 0; i < nsectors; i++) { | |
1089 | ||
1090 | reg = GPMC_ECC_BCH_RESULT_0 + 16*i; | |
1091 | ||
1092 | /* Read hw-computed remainder */ | |
1093 | val1 = gpmc_read_reg(reg + 0); | |
1094 | val2 = gpmc_read_reg(reg + 4); | |
1095 | val3 = gpmc_read_reg(reg + 8); | |
1096 | val4 = gpmc_read_reg(reg + 12); | |
1097 | ||
1098 | /* | |
1099 | * Add constant polynomial to remainder, in order to get an ecc | |
1100 | * sequence of 0xFFs for a buffer filled with 0xFFs. | |
1101 | */ | |
1102 | *ecc++ = 0xef ^ (val4 & 0xFF); | |
1103 | *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF); | |
1104 | *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF); | |
1105 | *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF); | |
1106 | *ecc++ = 0xed ^ (val3 & 0xFF); | |
1107 | *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF); | |
1108 | *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF); | |
1109 | *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF); | |
1110 | *ecc++ = 0x97 ^ (val2 & 0xFF); | |
1111 | *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF); | |
1112 | *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF); | |
1113 | *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF); | |
1114 | *ecc++ = 0xb5 ^ (val1 & 0xFF); | |
1115 | } | |
1116 | ||
1117 | gpmc_ecc_used = -EINVAL; | |
1118 | return 0; | |
1119 | } | |
1120 | EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch8); | |
1121 | ||
1122 | #endif /* CONFIG_ARCH_OMAP3 */ |