[deliverable/linux.git] / arch / arm / mach-omap2 / id.c

/*
 * linux/arch/arm/mach-omap2/id.c
 *
 * OMAP2 CPU identification code
 *
 * Copyright (C) 2005 Nokia Corporation
 * Written by Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>

#include <asm/cputype.h>

#include <plat/common.h>
#include <plat/control.h>
#include <plat/cpu.h>

static struct omap_chip_id omap_chip;
static unsigned int omap_revision;

u32 omap3_features;

unsigned int omap_rev(void)
{
	return omap_revision;
}
EXPORT_SYMBOL(omap_rev);

/**
 * omap_chip_is - test whether currently running OMAP matches a chip type
 * @oc: omap_chip_t to test against
 *
 * Test whether the currently-running OMAP chip matches the supplied
 * chip type 'oc'.  Returns 1 upon a match; 0 upon failure.
 */
int omap_chip_is(struct omap_chip_id oci)
{
	return (oci.oc & omap_chip.oc) ? 1 : 0;
}
EXPORT_SYMBOL(omap_chip_is);

int omap_type(void)
{
	u32 val = 0;

	if (cpu_is_omap24xx()) {
		val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
	} else if (cpu_is_omap34xx()) {
		val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
	} else if (cpu_is_omap44xx()) {
		val = omap_ctrl_readl(OMAP44XX_CONTROL_STATUS);
	} else {
		pr_err("Cannot detect omap type!\n");
		goto out;
	}

	val &= OMAP2_DEVICETYPE_MASK;
	val >>= 8;

out:
	return val;
}
EXPORT_SYMBOL(omap_type);


/*----------------------------------------------------------------------------*/

#define OMAP_TAP_IDCODE		0x0204
#define OMAP_TAP_DIE_ID_0	0x0218
#define OMAP_TAP_DIE_ID_1	0x021C
#define OMAP_TAP_DIE_ID_2	0x0220
#define OMAP_TAP_DIE_ID_3	0x0224

#define read_tap_reg(reg)	__raw_readl(tap_base  + (reg))

struct omap_id {
	u16	hawkeye;	/* Silicon type (Hawkeye id) */
	u8	dev;		/* Device type from production_id reg */
	u32	type;		/* Combined type id copied to omap_revision */
};

/* Register values to detect the OMAP version */
static struct omap_id omap_ids[] __initdata = {
	{ .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
	{ .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
	{ .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
	{ .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
	{ .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
	{ .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
};

static void __iomem *tap_base;
static u16 tap_prod_id;

void __init omap24xx_check_revision(void)
{
	int i, j;
	u32 idcode, prod_id;
	u16 hawkeye;
	u8  dev_type, rev;

	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	prod_id = read_tap_reg(tap_prod_id);
	hawkeye = (idcode >> 12) & 0xffff;
	rev = (idcode >> 28) & 0x0f;
	dev_type = (prod_id >> 16) & 0x0f;

	pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
		 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
	pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n",
		 read_tap_reg(OMAP_TAP_DIE_ID_0));
	pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
		 read_tap_reg(OMAP_TAP_DIE_ID_1),
		 (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
	pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n",
		 read_tap_reg(OMAP_TAP_DIE_ID_2));
	pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n",
		 read_tap_reg(OMAP_TAP_DIE_ID_3));
	pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
		 prod_id, dev_type);

	/* Check hawkeye ids */
	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
		if (hawkeye == omap_ids[i].hawkeye)
			break;
	}

	if (i == ARRAY_SIZE(omap_ids)) {
		printk(KERN_ERR "Unknown OMAP CPU id\n");
		return;
	}

	for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
		if (dev_type == omap_ids[j].dev)
			break;
	}

	if (j == ARRAY_SIZE(omap_ids)) {
		printk(KERN_ERR "Unknown OMAP device type. "
				"Handling it as OMAP%04x\n",
				omap_ids[i].type >> 16);
		j = i;
	}

	pr_info("OMAP%04x", omap_rev() >> 16);
	if ((omap_rev() >> 8) & 0x0f)
		pr_info("ES%x", (omap_rev() >> 12) & 0xf);
	pr_info("\n");
}

#define OMAP3_CHECK_FEATURE(status,feat)				\
	if (((status & OMAP3_ ##feat## _MASK) 				\
		>> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { 	\
		omap3_features |= OMAP3_HAS_ ##feat;			\
	}

void __init omap3_check_features(void)
{
	u32 status;

	omap3_features = 0;

	status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);

	OMAP3_CHECK_FEATURE(status, L2CACHE);
	OMAP3_CHECK_FEATURE(status, IVA);
	OMAP3_CHECK_FEATURE(status, SGX);
	OMAP3_CHECK_FEATURE(status, NEON);
	OMAP3_CHECK_FEATURE(status, ISP);
	if (cpu_is_omap3630())
		omap3_features |= OMAP3_HAS_192MHZ_CLK;

	/*
	 * TODO: Get additional info (where applicable)
	 *       e.g. Size of L2 cache.
	 */
}

void __init omap3_check_revision(void)
{
	u32 cpuid, idcode;
	u16 hawkeye;
	u8 rev;

	omap_chip.oc = CHIP_IS_OMAP3430;

	/*
	 * We cannot access revision registers on ES1.0.
	 * If the processor type is Cortex-A8 and the revision is 0x0
	 * it means its Cortex r0p0 which is 3430 ES1.0.
	 */
	cpuid = read_cpuid(CPUID_ID);
	if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
		omap_revision = OMAP3430_REV_ES1_0;
		omap_chip.oc |= CHIP_IS_OMAP3430ES1;
		return;
	}

	/*
	 * Detection for 34xx ES2.0 and above can be done with just
	 * hawkeye and rev. See TRM 1.5.2 Device Identification.
	 * Note that rev does not map directly to our defined processor
	 * revision numbers as ES1.0 uses value 0.
	 */
	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	hawkeye = (idcode >> 12) & 0xffff;
	rev = (idcode >> 28) & 0xff;

	switch (hawkeye) {
	case 0xb7ae:
		/* Handle 34xx/35xx devices */
		switch (rev) {
		case 0: /* Take care of early samples */
		case 1:
			omap_revision = OMAP3430_REV_ES2_0;
			omap_chip.oc |= CHIP_IS_OMAP3430ES2;
			break;
		case 2:
			omap_revision = OMAP3430_REV_ES2_1;
			omap_chip.oc |= CHIP_IS_OMAP3430ES2;
			break;
		case 3:
			omap_revision = OMAP3430_REV_ES3_0;
			omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
			break;
		case 4:
			omap_revision = OMAP3430_REV_ES3_1;
			omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
			break;
		case 7:
		/* FALLTHROUGH */
		default:
			/* Use the latest known revision as default */
			omap_revision = OMAP3430_REV_ES3_1_2;

			/* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
			omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
		}
		break;
	case 0xb868:
		/* Handle OMAP35xx/AM35xx devices
		 *
		 * Set the device to be OMAP3505 here. Actual device
		 * is identified later based on the features.
		 *
		 * REVISIT: AM3505/AM3517 should have their own CHIP_IS
		 */
		omap_revision = OMAP3505_REV(rev);
		omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
		break;
	case 0xb891:
	/* FALLTHROUGH */
	default:
		/* Unknown default to latest silicon rev as default*/
		omap_revision = OMAP3630_REV_ES1_0;
		omap_chip.oc |= CHIP_IS_OMAP3630ES1;
	}
}

void __init omap4_check_revision(void)
{
	u32 idcode;
	u16 hawkeye;
	u8 rev;
	char *rev_name = "ES1.0";

	/*
	 * The IC rev detection is done with hawkeye and rev.
	 * Note that rev does not map directly to defined processor
	 * revision numbers as ES1.0 uses value 0.
	 */
	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	hawkeye = (idcode >> 12) & 0xffff;
	rev = (idcode >> 28) & 0xff;

	if ((hawkeye == 0xb852) && (rev == 0x0)) {
		omap_revision = OMAP4430_REV_ES1_0;
		omap_chip.oc |= CHIP_IS_OMAP4430ES1;
		pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
		return;
	}

	pr_err("Unknown OMAP4 CPU id\n");
}

#define OMAP3_SHOW_FEATURE(feat)		\
	if (omap3_has_ ##feat())		\
		printk(#feat" ");

void __init omap3_cpuinfo(void)
{
	u8 rev = GET_OMAP_REVISION();
	char cpu_name[16], cpu_rev[16];

	/* OMAP3430 and OMAP3530 are assumed to be same.
	 *
	 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
	 * on available features. Upon detection, update the CPU id
	 * and CPU class bits.
	 */
	if (cpu_is_omap3630()) {
		strcpy(cpu_name, "OMAP3630");
	} else if (cpu_is_omap3505()) {
		/*
		 * AM35xx devices
		 */
		if (omap3_has_sgx()) {
			omap_revision = OMAP3517_REV(rev);
			strcpy(cpu_name, "AM3517");
		} else {
			/* Already set in omap3_check_revision() */
			strcpy(cpu_name, "AM3505");
		}
	} else if (omap3_has_iva() && omap3_has_sgx()) {
		/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
		strcpy(cpu_name, "OMAP3430/3530");
	} else if (omap3_has_iva()) {
		omap_revision = OMAP3525_REV(rev);
		strcpy(cpu_name, "OMAP3525");
	} else if (omap3_has_sgx()) {
		omap_revision = OMAP3515_REV(rev);
		strcpy(cpu_name, "OMAP3515");
	} else {
		omap_revision = OMAP3503_REV(rev);
		strcpy(cpu_name, "OMAP3503");
	}

	switch (rev) {
	case OMAP_REVBITS_00:
		strcpy(cpu_rev, "1.0");
		break;
	case OMAP_REVBITS_10:
		strcpy(cpu_rev, "2.0");
		break;
	case OMAP_REVBITS_20:
		strcpy(cpu_rev, "2.1");
		break;
	case OMAP_REVBITS_30:
		strcpy(cpu_rev, "3.0");
		break;
	case OMAP_REVBITS_40:
	/* FALLTHROUGH */
	default:
		/* Use the latest known revision as default */
		strcpy(cpu_rev, "3.1");
	}

	/* Print verbose information */
	pr_info("%s ES%s (", cpu_name, cpu_rev);

	OMAP3_SHOW_FEATURE(l2cache);
	OMAP3_SHOW_FEATURE(iva);
	OMAP3_SHOW_FEATURE(sgx);
	OMAP3_SHOW_FEATURE(neon);
	OMAP3_SHOW_FEATURE(isp);
	OMAP3_SHOW_FEATURE(192mhz_clk);

	printk(")\n");
}

/*
 * Try to detect the exact revision of the omap we're running on
 */
void __init omap2_check_revision(void)
{
	/*
	 * At this point we have an idea about the processor revision set
	 * earlier with omap2_set_globals_tap().
	 */
	if (cpu_is_omap24xx()) {
		omap24xx_check_revision();
	} else if (cpu_is_omap34xx()) {
		omap3_check_revision();
		omap3_check_features();
		omap3_cpuinfo();
		return;
	} else if (cpu_is_omap44xx()) {
		omap4_check_revision();
		return;
	} else {
		pr_err("OMAP revision unknown, please fix!\n");
	}

	/*
	 * OK, now we know the exact revision. Initialize omap_chip bits
	 * for powerdowmain and clockdomain code.
	 */
	if (cpu_is_omap243x()) {
		/* Currently only supports 2430ES2.1 and 2430-all */
		omap_chip.oc |= CHIP_IS_OMAP2430;
		return;
	} else if (cpu_is_omap242x()) {
		/* Currently only supports 2420ES2.1.1 and 2420-all */
		omap_chip.oc |= CHIP_IS_OMAP2420;
		return;
	}

	pr_err("Uninitialized omap_chip, please fix!\n");
}

/*
 * Set up things for map_io and processor detection later on. Gets called
 * pretty much first thing from board init. For multi-omap, this gets
 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
 * detect the exact revision later on in omap2_detect_revision() once map_io
 * is done.
 */
void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
{
	omap_revision = omap2_globals->class;
	tap_base = omap2_globals->tap;

	if (cpu_is_omap34xx())
		tap_prod_id = 0x0210;
	else
		tap_prod_id = 0x0208;
}
Commit	Line	Data
1dbae815 TL	1	/*
	2	* linux/arch/arm/mach-omap2/id.c
	3	*
	4	* OMAP2 CPU identification code
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
	7	* Written by Tony Lindgren <tony@atomide.com>
	8	*
44169075 SS	9	* Copyright (C) 2009 Texas Instruments
	10	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
	11	*
1dbae815 TL	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*/
	16
1dbae815 TL	17	#include <linux/module.h>
	18	#include <linux/kernel.h>
	19	#include <linux/init.h>
fced80c7	20	#include <linux/io.h>
1dbae815	21
0ba8b9b2	22	#include <asm/cputype.h>
1dbae815	23
ce491cf8 TL	24	#include <plat/common.h>
	25	#include <plat/control.h>
	26	#include <plat/cpu.h>
72d0f1c3	27
097c584c	28	static struct omap_chip_id omap_chip;
84a34344 LL	29	static unsigned int omap_revision;
84a34344 LL	30
8384ce07	31	u32 omap3_features;
84a34344 LL	32
	33	unsigned int omap_rev(void)
	34	{
	35	return omap_revision;
	36	}
	37	EXPORT_SYMBOL(omap_rev);
097c584c PW	38
	39	/**
	40	* omap_chip_is - test whether currently running OMAP matches a chip type
	41	* @oc: omap_chip_t to test against
	42	*
	43	* Test whether the currently-running OMAP chip matches the supplied
	44	* chip type 'oc'. Returns 1 upon a match; 0 upon failure.
	45	*/
	46	int omap_chip_is(struct omap_chip_id oci)
	47	{
	48	return (oci.oc & omap_chip.oc) ? 1 : 0;
	49	}
	50	EXPORT_SYMBOL(omap_chip_is);
	51
8e25ad96 KH	52	int omap_type(void)
	53	{
	54	u32 val = 0;
	55
edeae658	56	if (cpu_is_omap24xx()) {
8e25ad96	57	val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
edeae658	58	} else if (cpu_is_omap34xx()) {
8e25ad96	59	val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
737daa03 SS	60	} else if (cpu_is_omap44xx()) {
737daa03 SS	61	val = omap_ctrl_readl(OMAP44XX_CONTROL_STATUS);
edeae658	62	} else {
8e25ad96 KH	63	pr_err("Cannot detect omap type!\n");
	64	goto out;
	65	}
	66
	67	val &= OMAP2_DEVICETYPE_MASK;
	68	val >>= 8;
	69
	70	out:
	71	return val;
	72	}
	73	EXPORT_SYMBOL(omap_type);
	74
	75
a8823143	76	/----------------------------------------------------------------------------/
097c584c	77
a8823143 TL	78	#define OMAP_TAP_IDCODE 0x0204
	79	#define OMAP_TAP_DIE_ID_0 0x0218
	80	#define OMAP_TAP_DIE_ID_1 0x021C
	81	#define OMAP_TAP_DIE_ID_2 0x0220
	82	#define OMAP_TAP_DIE_ID_3 0x0224
097c584c	83
a8823143	84	#define read_tap_reg(reg) __raw_readl(tap_base + (reg))
097c584c	85
a8823143 TL	86	struct omap_id {
	87	u16 hawkeye; /* Silicon type (Hawkeye id) */
	88	u8 dev; /* Device type from production_id reg */
84a34344	89	u32 type; /* Combined type id copied to omap_revision */
a8823143	90	};
097c584c	91
a8823143 TL	92	/* Register values to detect the OMAP version */
	93	static struct omap_id omap_ids[] __initdata = {
	94	{ .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
	95	{ .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
	96	{ .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
	97	{ .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
	98	{ .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
	99	{ .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
	100	};
097c584c	101
a8823143 TL	102	static void __iomem *tap_base;
a8823143 TL	103	static u16 tap_prod_id;
1dbae815	104
5ba02dca	105	void __init omap24xx_check_revision(void)
1dbae815 TL	106	{
1dbae815 TL	107	int i, j;
a8823143	108	u32 idcode, prod_id;
1dbae815	109	u16 hawkeye;
a8823143	110	u8 dev_type, rev;
1dbae815 TL	111
1dbae815 TL	112	idcode = read_tap_reg(OMAP_TAP_IDCODE);
0e564848	113	prod_id = read_tap_reg(tap_prod_id);
1dbae815 TL	114	hawkeye = (idcode >> 12) & 0xffff;
	115	rev = (idcode >> 28) & 0x0f;
	116	dev_type = (prod_id >> 16) & 0x0f;
	117
097c584c PW	118	pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
	119	idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
	120	pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n",
	121	read_tap_reg(OMAP_TAP_DIE_ID_0));
	122	pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
	123	read_tap_reg(OMAP_TAP_DIE_ID_1),
	124	(read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
	125	pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n",
	126	read_tap_reg(OMAP_TAP_DIE_ID_2));
	127	pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n",
	128	read_tap_reg(OMAP_TAP_DIE_ID_3));
	129	pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
	130	prod_id, dev_type);
	131
1dbae815 TL	132	/* Check hawkeye ids */
	133	for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
	134	if (hawkeye == omap_ids[i].hawkeye)
	135	break;
	136	}
	137
	138	if (i == ARRAY_SIZE(omap_ids)) {
	139	printk(KERN_ERR "Unknown OMAP CPU id\n");
	140	return;
	141	}
	142
	143	for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
	144	if (dev_type == omap_ids[j].dev)
	145	break;
	146	}
	147
	148	if (j == ARRAY_SIZE(omap_ids)) {
	149	printk(KERN_ERR "Unknown OMAP device type. "
	150	"Handling it as OMAP%04x\n",
	151	omap_ids[i].type >> 16);
	152	j = i;
	153	}
1dbae815	154
84a34344 LL	155	pr_info("OMAP%04x", omap_rev() >> 16);
	156	if ((omap_rev() >> 8) & 0x0f)
	157	pr_info("ES%x", (omap_rev() >> 12) & 0xf);
097c584c	158	pr_info("\n");
a8823143 TL	159	}
a8823143 TL	160
8384ce07 SP	161	#define OMAP3_CHECK_FEATURE(status,feat) \
	162	if (((status & OMAP3_ ##feat## _MASK) \
	163	>> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
	164	omap3_features \|= OMAP3_HAS_ ##feat; \
	165	}
	166
	167	void __init omap3_check_features(void)
	168	{
	169	u32 status;
	170
	171	omap3_features = 0;
	172
	173	status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
	174
	175	OMAP3_CHECK_FEATURE(status, L2CACHE);
	176	OMAP3_CHECK_FEATURE(status, IVA);
	177	OMAP3_CHECK_FEATURE(status, SGX);
	178	OMAP3_CHECK_FEATURE(status, NEON);
	179	OMAP3_CHECK_FEATURE(status, ISP);
7356f0b2 VB	180	if (cpu_is_omap3630())
7356f0b2 VB	181	omap3_features \|= OMAP3_HAS_192MHZ_CLK;
8384ce07 SP	182
	183	/*
	184	* TODO: Get additional info (where applicable)
	185	* e.g. Size of L2 cache.
	186	*/
	187	}
	188
	189	void __init omap3_check_revision(void)
a8823143 TL	190	{
	191	u32 cpuid, idcode;
	192	u16 hawkeye;
	193	u8 rev;
a8823143	194
e9acb9b6 TL	195	omap_chip.oc = CHIP_IS_OMAP3430;
e9acb9b6 TL	196
a8823143 TL	197	/*
	198	* We cannot access revision registers on ES1.0.
	199	* If the processor type is Cortex-A8 and the revision is 0x0
	200	* it means its Cortex r0p0 which is 3430 ES1.0.
	201	*/
	202	cpuid = read_cpuid(CPUID_ID);
	203	if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
84a34344	204	omap_revision = OMAP3430_REV_ES1_0;
e9acb9b6	205	omap_chip.oc \|= CHIP_IS_OMAP3430ES1;
048f4bd7	206	return;
a8823143 TL	207	}
	208
	209	/*
	210	* Detection for 34xx ES2.0 and above can be done with just
	211	* hawkeye and rev. See TRM 1.5.2 Device Identification.
	212	* Note that rev does not map directly to our defined processor
	213	* revision numbers as ES1.0 uses value 0.
	214	*/
	215	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	216	hawkeye = (idcode >> 12) & 0xffff;
	217	rev = (idcode >> 28) & 0xff;
097c584c	218
2456a10f NM	219	switch (hawkeye) {
	220	case 0xb7ae:
	221	/* Handle 34xx/35xx devices */
a8823143	222	switch (rev) {
048f4bd7 SP	223	case 0: /* Take care of early samples */
048f4bd7 SP	224	case 1:
84a34344	225	omap_revision = OMAP3430_REV_ES2_0;
e9acb9b6	226	omap_chip.oc \|= CHIP_IS_OMAP3430ES2;
a8823143 TL	227	break;
a8823143 TL	228	case 2:
84a34344	229	omap_revision = OMAP3430_REV_ES2_1;
e9acb9b6	230	omap_chip.oc \|= CHIP_IS_OMAP3430ES2;
a8823143 TL	231	break;
a8823143 TL	232	case 3:
84a34344	233	omap_revision = OMAP3430_REV_ES3_0;
e9acb9b6	234	omap_chip.oc \|= CHIP_IS_OMAP3430ES3_0;
a8823143	235	break;
187e688d	236	case 4:
e9acb9b6 TL	237	omap_revision = OMAP3430_REV_ES3_1;
	238	omap_chip.oc \|= CHIP_IS_OMAP3430ES3_1;
	239	break;
	240	case 7:
edeae658	241	/* FALLTHROUGH */
a8823143 TL	242	default:
a8823143 TL	243	/* Use the latest known revision as default */
e9acb9b6 TL	244	omap_revision = OMAP3430_REV_ES3_1_2;
	245
	246	/* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
	247	omap_chip.oc \|= CHIP_IS_OMAP3430ES3_1;
a8823143	248	}
2456a10f	249	break;
4cac6018 SP	250	case 0xb868:
	251	/* Handle OMAP35xx/AM35xx devices
	252	*
	253	* Set the device to be OMAP3505 here. Actual device
	254	* is identified later based on the features.
e9acb9b6 TL	255	*
e9acb9b6 TL	256	* REVISIT: AM3505/AM3517 should have their own CHIP_IS
4cac6018 SP	257	*/
4cac6018 SP	258	omap_revision = OMAP3505_REV(rev);
e9acb9b6	259	omap_chip.oc \|= CHIP_IS_OMAP3430ES3_1;
4cac6018	260	break;
edeae658 FB	261	case 0xb891:
edeae658 FB	262	/* FALLTHROUGH */
2456a10f NM	263	default:
	264	/* Unknown default to latest silicon rev as default*/
	265	omap_revision = OMAP3630_REV_ES1_0;
e9acb9b6	266	omap_chip.oc \|= CHIP_IS_OMAP3630ES1;
a8823143	267	}
1dbae815 TL	268	}
1dbae815 TL	269
b570e0ec SS	270	void __init omap4_check_revision(void)
	271	{
	272	u32 idcode;
	273	u16 hawkeye;
	274	u8 rev;
	275	char *rev_name = "ES1.0";
	276
	277	/*
	278	* The IC rev detection is done with hawkeye and rev.
	279	* Note that rev does not map directly to defined processor
	280	* revision numbers as ES1.0 uses value 0.
	281	*/
	282	idcode = read_tap_reg(OMAP_TAP_IDCODE);
	283	hawkeye = (idcode >> 12) & 0xffff;
	284	rev = (idcode >> 28) & 0xff;
	285
	286	if ((hawkeye == 0xb852) && (rev == 0x0)) {
	287	omap_revision = OMAP4430_REV_ES1_0;
c6a6e6e2	288	omap_chip.oc \|= CHIP_IS_OMAP4430ES1;
b570e0ec SS	289	pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
	290	return;
	291	}
	292
	293	pr_err("Unknown OMAP4 CPU id\n");
	294	}
	295
8384ce07	296	#define OMAP3_SHOW_FEATURE(feat) \
cedf900d KH	297	if (omap3_has_ ##feat()) \
cedf900d KH	298	printk(#feat" ");
8384ce07 SP	299
	300	void __init omap3_cpuinfo(void)
	301	{
048f4bd7 SP	302	u8 rev = GET_OMAP_REVISION();
	303	char cpu_name[16], cpu_rev[16];
	304
	305	/* OMAP3430 and OMAP3530 are assumed to be same.
	306	*
	307	* OMAP3525, OMAP3515 and OMAP3503 can be detected only based
	308	* on available features. Upon detection, update the CPU id
	309	* and CPU class bits.
	310	*/
edeae658	311	if (cpu_is_omap3630()) {
4cac6018	312	strcpy(cpu_name, "OMAP3630");
edeae658	313	} else if (cpu_is_omap3505()) {
4cac6018 SP	314	/*
	315	* AM35xx devices
	316	*/
	317	if (omap3_has_sgx()) {
	318	omap_revision = OMAP3517_REV(rev);
	319	strcpy(cpu_name, "AM3517");
edeae658	320	} else {
4cac6018 SP	321	/* Already set in omap3_check_revision() */
	322	strcpy(cpu_name, "AM3505");
	323	}
edeae658 FB	324	} else if (omap3_has_iva() && omap3_has_sgx()) {
edeae658 FB	325	/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
4cac6018	326	strcpy(cpu_name, "OMAP3430/3530");
0712fb39	327	} else if (omap3_has_iva()) {
048f4bd7	328	omap_revision = OMAP3525_REV(rev);
4cac6018	329	strcpy(cpu_name, "OMAP3525");
0712fb39	330	} else if (omap3_has_sgx()) {
048f4bd7	331	omap_revision = OMAP3515_REV(rev);
4cac6018	332	strcpy(cpu_name, "OMAP3515");
edeae658	333	} else {
048f4bd7	334	omap_revision = OMAP3503_REV(rev);
4cac6018	335	strcpy(cpu_name, "OMAP3503");
048f4bd7 SP	336	}
	337
	338	switch (rev) {
	339	case OMAP_REVBITS_00:
	340	strcpy(cpu_rev, "1.0");
	341	break;
	342	case OMAP_REVBITS_10:
	343	strcpy(cpu_rev, "2.0");
	344	break;
	345	case OMAP_REVBITS_20:
	346	strcpy(cpu_rev, "2.1");
	347	break;
	348	case OMAP_REVBITS_30:
	349	strcpy(cpu_rev, "3.0");
	350	break;
	351	case OMAP_REVBITS_40:
edeae658	352	/* FALLTHROUGH */
048f4bd7 SP	353	default:
	354	/* Use the latest known revision as default */
	355	strcpy(cpu_rev, "3.1");
	356	}
	357
edeae658	358	/* Print verbose information */
cedf900d	359	pr_info("%s ES%s (", cpu_name, cpu_rev);
048f4bd7	360
8384ce07 SP	361	OMAP3_SHOW_FEATURE(l2cache);
	362	OMAP3_SHOW_FEATURE(iva);
	363	OMAP3_SHOW_FEATURE(sgx);
	364	OMAP3_SHOW_FEATURE(neon);
	365	OMAP3_SHOW_FEATURE(isp);
7356f0b2	366	OMAP3_SHOW_FEATURE(192mhz_clk);
cedf900d KH	367
cedf900d KH	368	printk(")\n");
8384ce07 SP	369	}
8384ce07 SP	370
a8823143 TL	371	/*
	372	* Try to detect the exact revision of the omap we're running on
	373	*/
5ba02dca TL	374	void __init omap2_check_revision(void)
5ba02dca TL	375	{
a8823143 TL	376	/*
	377	* At this point we have an idea about the processor revision set
	378	* earlier with omap2_set_globals_tap().
	379	*/
edeae658	380	if (cpu_is_omap24xx()) {
a8823143	381	omap24xx_check_revision();
edeae658	382	} else if (cpu_is_omap34xx()) {
8384ce07	383	omap3_check_revision();
05574bb2	384	omap3_check_features();
8384ce07	385	omap3_cpuinfo();
e9acb9b6	386	return;
edeae658	387	} else if (cpu_is_omap44xx()) {
b570e0ec	388	omap4_check_revision();
44169075	389	return;
edeae658	390	} else {
a8823143	391	pr_err("OMAP revision unknown, please fix!\n");
edeae658	392	}
a8823143 TL	393
	394	/*
	395	* OK, now we know the exact revision. Initialize omap_chip bits
	396	* for powerdowmain and clockdomain code.
	397	*/
	398	if (cpu_is_omap243x()) {
	399	/* Currently only supports 2430ES2.1 and 2430-all */
	400	omap_chip.oc \|= CHIP_IS_OMAP2430;
e9acb9b6	401	return;
a8823143 TL	402	} else if (cpu_is_omap242x()) {
	403	/* Currently only supports 2420ES2.1.1 and 2420-all */
	404	omap_chip.oc \|= CHIP_IS_OMAP2420;
e9acb9b6	405	return;
a8823143	406	}
e9acb9b6 TL	407
e9acb9b6 TL	408	pr_err("Uninitialized omap_chip, please fix!\n");
5ba02dca TL	409	}
5ba02dca TL	410
a8823143 TL	411	/*
	412	* Set up things for map_io and processor detection later on. Gets called
	413	* pretty much first thing from board init. For multi-omap, this gets
	414	* cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
	415	* detect the exact revision later on in omap2_detect_revision() once map_io
	416	* is done.
	417	*/
0e564848 TL	418	void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
0e564848 TL	419	{
84a34344	420	omap_revision = omap2_globals->class;
0e564848 TL	421	tap_base = omap2_globals->tap;
0e564848 TL	422
a8823143	423	if (cpu_is_omap34xx())
0e564848 TL	424	tap_prod_id = 0x0210;
	425	else
	426	tap_prod_id = 0x0208;
	427	}