Commit | Line | Data |
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1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/id.c | |
3 | * | |
4 | * OMAP2 CPU identification code | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
7 | * Written by Tony Lindgren <tony@atomide.com> | |
8 | * | |
e49c4d27 | 9 | * Copyright (C) 2009-11 Texas Instruments |
44169075 SS |
10 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
11 | * | |
1dbae815 TL |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
1dbae815 TL |
17 | #include <linux/module.h> |
18 | #include <linux/kernel.h> | |
19 | #include <linux/init.h> | |
fced80c7 | 20 | #include <linux/io.h> |
1dbae815 | 21 | |
0ba8b9b2 | 22 | #include <asm/cputype.h> |
1dbae815 | 23 | |
4e65331c | 24 | #include "common.h" |
72d0f1c3 | 25 | |
4952af43 | 26 | #include "id.h" |
2e130fc3 | 27 | |
dbc04161 | 28 | #include "soc.h" |
4814ced5 PW |
29 | #include "control.h" |
30 | ||
84a34344 | 31 | static unsigned int omap_revision; |
50a01e64 | 32 | static const char *cpu_rev; |
cc0170b2 | 33 | u32 omap_features; |
84a34344 LL |
34 | |
35 | unsigned int omap_rev(void) | |
36 | { | |
37 | return omap_revision; | |
38 | } | |
39 | EXPORT_SYMBOL(omap_rev); | |
097c584c | 40 | |
8e25ad96 KH |
41 | int omap_type(void) |
42 | { | |
43 | u32 val = 0; | |
44 | ||
edeae658 | 45 | if (cpu_is_omap24xx()) { |
8e25ad96 | 46 | val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); |
971b8a9c | 47 | } else if (soc_is_am33xx()) { |
fb3cfb1f | 48 | val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); |
edeae658 | 49 | } else if (cpu_is_omap34xx()) { |
8e25ad96 | 50 | val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); |
737daa03 | 51 | } else if (cpu_is_omap44xx()) { |
dcf5ef3f | 52 | val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); |
b13e80a8 S |
53 | } else if (soc_is_omap54xx()) { |
54 | val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS); | |
55 | val &= OMAP5_DEVICETYPE_MASK; | |
56 | val >>= 6; | |
57 | goto out; | |
edeae658 | 58 | } else { |
8e25ad96 KH |
59 | pr_err("Cannot detect omap type!\n"); |
60 | goto out; | |
61 | } | |
62 | ||
63 | val &= OMAP2_DEVICETYPE_MASK; | |
64 | val >>= 8; | |
65 | ||
66 | out: | |
67 | return val; | |
68 | } | |
69 | EXPORT_SYMBOL(omap_type); | |
70 | ||
71 | ||
a8823143 | 72 | /*----------------------------------------------------------------------------*/ |
097c584c | 73 | |
a8823143 TL |
74 | #define OMAP_TAP_IDCODE 0x0204 |
75 | #define OMAP_TAP_DIE_ID_0 0x0218 | |
76 | #define OMAP_TAP_DIE_ID_1 0x021C | |
77 | #define OMAP_TAP_DIE_ID_2 0x0220 | |
78 | #define OMAP_TAP_DIE_ID_3 0x0224 | |
097c584c | 79 | |
b235e007 AG |
80 | #define OMAP_TAP_DIE_ID_44XX_0 0x0200 |
81 | #define OMAP_TAP_DIE_ID_44XX_1 0x0208 | |
82 | #define OMAP_TAP_DIE_ID_44XX_2 0x020c | |
83 | #define OMAP_TAP_DIE_ID_44XX_3 0x0210 | |
84 | ||
a8823143 | 85 | #define read_tap_reg(reg) __raw_readl(tap_base + (reg)) |
097c584c | 86 | |
a8823143 TL |
87 | struct omap_id { |
88 | u16 hawkeye; /* Silicon type (Hawkeye id) */ | |
89 | u8 dev; /* Device type from production_id reg */ | |
84a34344 | 90 | u32 type; /* Combined type id copied to omap_revision */ |
a8823143 | 91 | }; |
097c584c | 92 | |
a8823143 TL |
93 | /* Register values to detect the OMAP version */ |
94 | static struct omap_id omap_ids[] __initdata = { | |
95 | { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 }, | |
96 | { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 }, | |
97 | { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 }, | |
98 | { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 }, | |
99 | { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 }, | |
100 | { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 }, | |
101 | }; | |
097c584c | 102 | |
a8823143 TL |
103 | static void __iomem *tap_base; |
104 | static u16 tap_prod_id; | |
1dbae815 | 105 | |
2e130fc3 KRC |
106 | void omap_get_die_id(struct omap_die_id *odi) |
107 | { | |
b13e80a8 | 108 | if (cpu_is_omap44xx() || soc_is_omap54xx()) { |
b235e007 AG |
109 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); |
110 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); | |
111 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); | |
112 | odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3); | |
113 | ||
114 | return; | |
115 | } | |
2e130fc3 KRC |
116 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); |
117 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1); | |
118 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2); | |
119 | odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3); | |
120 | } | |
121 | ||
4de34f35 | 122 | void __init omap2xxx_check_revision(void) |
1dbae815 TL |
123 | { |
124 | int i, j; | |
a8823143 | 125 | u32 idcode, prod_id; |
1dbae815 | 126 | u16 hawkeye; |
a8823143 | 127 | u8 dev_type, rev; |
c46732bb | 128 | struct omap_die_id odi; |
1dbae815 TL |
129 | |
130 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
0e564848 | 131 | prod_id = read_tap_reg(tap_prod_id); |
1dbae815 TL |
132 | hawkeye = (idcode >> 12) & 0xffff; |
133 | rev = (idcode >> 28) & 0x0f; | |
134 | dev_type = (prod_id >> 16) & 0x0f; | |
c46732bb | 135 | omap_get_die_id(&odi); |
1dbae815 | 136 | |
097c584c PW |
137 | pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", |
138 | idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); | |
c46732bb | 139 | pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0); |
097c584c | 140 | pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", |
c46732bb KRC |
141 | odi.id_1, (odi.id_1 >> 28) & 0xf); |
142 | pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2); | |
143 | pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3); | |
097c584c PW |
144 | pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", |
145 | prod_id, dev_type); | |
146 | ||
1dbae815 TL |
147 | /* Check hawkeye ids */ |
148 | for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { | |
149 | if (hawkeye == omap_ids[i].hawkeye) | |
150 | break; | |
151 | } | |
152 | ||
153 | if (i == ARRAY_SIZE(omap_ids)) { | |
154 | printk(KERN_ERR "Unknown OMAP CPU id\n"); | |
155 | return; | |
156 | } | |
157 | ||
158 | for (j = i; j < ARRAY_SIZE(omap_ids); j++) { | |
159 | if (dev_type == omap_ids[j].dev) | |
160 | break; | |
161 | } | |
162 | ||
163 | if (j == ARRAY_SIZE(omap_ids)) { | |
7852ec05 PW |
164 | pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n", |
165 | omap_ids[i].type >> 16); | |
1dbae815 TL |
166 | j = i; |
167 | } | |
1dbae815 | 168 | |
84a34344 LL |
169 | pr_info("OMAP%04x", omap_rev() >> 16); |
170 | if ((omap_rev() >> 8) & 0x0f) | |
171 | pr_info("ES%x", (omap_rev() >> 12) & 0xf); | |
097c584c | 172 | pr_info("\n"); |
a8823143 TL |
173 | } |
174 | ||
50a01e64 VH |
175 | #define OMAP3_SHOW_FEATURE(feat) \ |
176 | if (omap3_has_ ##feat()) \ | |
177 | printk(#feat" "); | |
178 | ||
179 | static void __init omap3_cpuinfo(void) | |
180 | { | |
181 | const char *cpu_name; | |
182 | ||
183 | /* | |
184 | * OMAP3430 and OMAP3530 are assumed to be same. | |
185 | * | |
186 | * OMAP3525, OMAP3515 and OMAP3503 can be detected only based | |
187 | * on available features. Upon detection, update the CPU id | |
188 | * and CPU class bits. | |
189 | */ | |
190 | if (cpu_is_omap3630()) { | |
191 | cpu_name = "OMAP3630"; | |
68a88b98 | 192 | } else if (soc_is_am35xx()) { |
50a01e64 VH |
193 | cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505"; |
194 | } else if (cpu_is_ti816x()) { | |
195 | cpu_name = "TI816X"; | |
971b8a9c | 196 | } else if (soc_is_am335x()) { |
50a01e64 VH |
197 | cpu_name = "AM335X"; |
198 | } else if (cpu_is_ti814x()) { | |
199 | cpu_name = "TI814X"; | |
200 | } else if (omap3_has_iva() && omap3_has_sgx()) { | |
201 | /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ | |
202 | cpu_name = "OMAP3430/3530"; | |
203 | } else if (omap3_has_iva()) { | |
204 | cpu_name = "OMAP3525"; | |
205 | } else if (omap3_has_sgx()) { | |
206 | cpu_name = "OMAP3515"; | |
207 | } else { | |
208 | cpu_name = "OMAP3503"; | |
209 | } | |
210 | ||
211 | /* Print verbose information */ | |
212 | pr_info("%s ES%s (", cpu_name, cpu_rev); | |
213 | ||
214 | OMAP3_SHOW_FEATURE(l2cache); | |
215 | OMAP3_SHOW_FEATURE(iva); | |
216 | OMAP3_SHOW_FEATURE(sgx); | |
217 | OMAP3_SHOW_FEATURE(neon); | |
218 | OMAP3_SHOW_FEATURE(isp); | |
219 | OMAP3_SHOW_FEATURE(192mhz_clk); | |
220 | ||
221 | printk(")\n"); | |
222 | } | |
223 | ||
8384ce07 SP |
224 | #define OMAP3_CHECK_FEATURE(status,feat) \ |
225 | if (((status & OMAP3_ ##feat## _MASK) \ | |
226 | >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ | |
cc0170b2 | 227 | omap_features |= OMAP3_HAS_ ##feat; \ |
8384ce07 SP |
228 | } |
229 | ||
4de34f35 | 230 | void __init omap3xxx_check_features(void) |
8384ce07 SP |
231 | { |
232 | u32 status; | |
233 | ||
cc0170b2 | 234 | omap_features = 0; |
8384ce07 SP |
235 | |
236 | status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); | |
237 | ||
238 | OMAP3_CHECK_FEATURE(status, L2CACHE); | |
239 | OMAP3_CHECK_FEATURE(status, IVA); | |
240 | OMAP3_CHECK_FEATURE(status, SGX); | |
241 | OMAP3_CHECK_FEATURE(status, NEON); | |
242 | OMAP3_CHECK_FEATURE(status, ISP); | |
7356f0b2 | 243 | if (cpu_is_omap3630()) |
cc0170b2 | 244 | omap_features |= OMAP3_HAS_192MHZ_CLK; |
b02b9172 | 245 | if (cpu_is_omap3430() || cpu_is_omap3630()) |
cc0170b2 | 246 | omap_features |= OMAP3_HAS_IO_WAKEUP; |
b02b9172 PW |
247 | if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 || |
248 | omap_rev() == OMAP3430_REV_ES3_1_2) | |
249 | omap_features |= OMAP3_HAS_IO_CHAIN_CTRL; | |
8384ce07 | 250 | |
cc0170b2 | 251 | omap_features |= OMAP3_HAS_SDRC; |
01001712 | 252 | |
1ce02996 MG |
253 | /* |
254 | * am35x fixups: | |
255 | * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as | |
256 | * reserved and therefore return 0 when read. Unfortunately, | |
257 | * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to | |
258 | * mean that a feature is present even though it isn't so clear | |
259 | * the incorrectly set feature bits. | |
260 | */ | |
261 | if (soc_is_am35xx()) | |
262 | omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP); | |
263 | ||
8384ce07 SP |
264 | /* |
265 | * TODO: Get additional info (where applicable) | |
266 | * e.g. Size of L2 cache. | |
267 | */ | |
4de34f35 VH |
268 | |
269 | omap3_cpuinfo(); | |
8384ce07 SP |
270 | } |
271 | ||
4de34f35 | 272 | void __init omap4xxx_check_features(void) |
cc0170b2 A |
273 | { |
274 | u32 si_type; | |
275 | ||
276 | if (cpu_is_omap443x()) | |
277 | omap_features |= OMAP4_HAS_MPU_1GHZ; | |
278 | ||
279 | ||
280 | if (cpu_is_omap446x()) { | |
281 | si_type = | |
282 | read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1); | |
283 | switch ((si_type & (3 << 16)) >> 16) { | |
284 | case 2: | |
285 | /* High performance device */ | |
286 | omap_features |= OMAP4_HAS_MPU_1_5GHZ; | |
287 | break; | |
288 | case 1: | |
289 | default: | |
290 | /* Standard device */ | |
291 | omap_features |= OMAP4_HAS_MPU_1_2GHZ; | |
292 | break; | |
293 | } | |
294 | } | |
295 | } | |
296 | ||
4de34f35 | 297 | void __init ti81xx_check_features(void) |
01001712 | 298 | { |
cc0170b2 | 299 | omap_features = OMAP3_HAS_NEON; |
4de34f35 | 300 | omap3_cpuinfo(); |
01001712 HP |
301 | } |
302 | ||
4de34f35 | 303 | void __init omap3xxx_check_revision(void) |
a8823143 TL |
304 | { |
305 | u32 cpuid, idcode; | |
306 | u16 hawkeye; | |
307 | u8 rev; | |
a8823143 TL |
308 | |
309 | /* | |
310 | * We cannot access revision registers on ES1.0. | |
311 | * If the processor type is Cortex-A8 and the revision is 0x0 | |
312 | * it means its Cortex r0p0 which is 3430 ES1.0. | |
313 | */ | |
314 | cpuid = read_cpuid(CPUID_ID); | |
315 | if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { | |
84a34344 | 316 | omap_revision = OMAP3430_REV_ES1_0; |
50a01e64 | 317 | cpu_rev = "1.0"; |
048f4bd7 | 318 | return; |
a8823143 TL |
319 | } |
320 | ||
321 | /* | |
322 | * Detection for 34xx ES2.0 and above can be done with just | |
323 | * hawkeye and rev. See TRM 1.5.2 Device Identification. | |
324 | * Note that rev does not map directly to our defined processor | |
325 | * revision numbers as ES1.0 uses value 0. | |
326 | */ | |
327 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
328 | hawkeye = (idcode >> 12) & 0xffff; | |
329 | rev = (idcode >> 28) & 0xff; | |
097c584c | 330 | |
2456a10f NM |
331 | switch (hawkeye) { |
332 | case 0xb7ae: | |
333 | /* Handle 34xx/35xx devices */ | |
a8823143 | 334 | switch (rev) { |
048f4bd7 SP |
335 | case 0: /* Take care of early samples */ |
336 | case 1: | |
84a34344 | 337 | omap_revision = OMAP3430_REV_ES2_0; |
50a01e64 | 338 | cpu_rev = "2.0"; |
a8823143 TL |
339 | break; |
340 | case 2: | |
84a34344 | 341 | omap_revision = OMAP3430_REV_ES2_1; |
50a01e64 | 342 | cpu_rev = "2.1"; |
a8823143 TL |
343 | break; |
344 | case 3: | |
84a34344 | 345 | omap_revision = OMAP3430_REV_ES3_0; |
50a01e64 | 346 | cpu_rev = "3.0"; |
a8823143 | 347 | break; |
187e688d | 348 | case 4: |
e9acb9b6 | 349 | omap_revision = OMAP3430_REV_ES3_1; |
50a01e64 | 350 | cpu_rev = "3.1"; |
e9acb9b6 TL |
351 | break; |
352 | case 7: | |
edeae658 | 353 | /* FALLTHROUGH */ |
a8823143 TL |
354 | default: |
355 | /* Use the latest known revision as default */ | |
e9acb9b6 | 356 | omap_revision = OMAP3430_REV_ES3_1_2; |
50a01e64 | 357 | cpu_rev = "3.1.2"; |
a8823143 | 358 | } |
2456a10f | 359 | break; |
4cac6018 | 360 | case 0xb868: |
1f1b0353 PW |
361 | /* |
362 | * Handle OMAP/AM 3505/3517 devices | |
4cac6018 | 363 | * |
1f1b0353 | 364 | * Set the device to be OMAP3517 here. Actual device |
4cac6018 SP |
365 | * is identified later based on the features. |
366 | */ | |
9ed2ba7a PW |
367 | switch (rev) { |
368 | case 0: | |
68a88b98 | 369 | omap_revision = AM35XX_REV_ES1_0; |
50a01e64 | 370 | cpu_rev = "1.0"; |
9ed2ba7a PW |
371 | break; |
372 | case 1: | |
373 | /* FALLTHROUGH */ | |
374 | default: | |
68a88b98 | 375 | omap_revision = AM35XX_REV_ES1_1; |
50a01e64 | 376 | cpu_rev = "1.1"; |
9ed2ba7a | 377 | } |
4cac6018 | 378 | break; |
edeae658 | 379 | case 0xb891: |
b0a1a6ce | 380 | /* Handle 36xx devices */ |
b0a1a6ce AG |
381 | |
382 | switch(rev) { | |
383 | case 0: /* Take care of early samples */ | |
384 | omap_revision = OMAP3630_REV_ES1_0; | |
50a01e64 | 385 | cpu_rev = "1.0"; |
b0a1a6ce AG |
386 | break; |
387 | case 1: | |
388 | omap_revision = OMAP3630_REV_ES1_1; | |
50a01e64 | 389 | cpu_rev = "1.1"; |
b0a1a6ce AG |
390 | break; |
391 | case 2: | |
51ec811a | 392 | /* FALLTHROUGH */ |
b0a1a6ce | 393 | default: |
51ec811a | 394 | omap_revision = OMAP3630_REV_ES1_2; |
50a01e64 | 395 | cpu_rev = "1.2"; |
b0a1a6ce | 396 | } |
77c0870c | 397 | break; |
01001712 | 398 | case 0xb81e: |
01001712 HP |
399 | switch (rev) { |
400 | case 0: | |
401 | omap_revision = TI8168_REV_ES1_0; | |
50a01e64 | 402 | cpu_rev = "1.0"; |
01001712 HP |
403 | break; |
404 | case 1: | |
51ec811a | 405 | /* FALLTHROUGH */ |
01001712 | 406 | default: |
51ec811a | 407 | omap_revision = TI8168_REV_ES1_1; |
50a01e64 | 408 | cpu_rev = "1.1"; |
3b32b7d6 | 409 | break; |
01001712 HP |
410 | } |
411 | break; | |
1e6cb146 AM |
412 | case 0xb944: |
413 | omap_revision = AM335X_REV_ES1_0; | |
50a01e64 | 414 | cpu_rev = "1.0"; |
c2d13554 | 415 | break; |
4390f5b2 HP |
416 | case 0xb8f2: |
417 | switch (rev) { | |
418 | case 0: | |
419 | /* FALLTHROUGH */ | |
420 | case 1: | |
421 | omap_revision = TI8148_REV_ES1_0; | |
50a01e64 | 422 | cpu_rev = "1.0"; |
4390f5b2 HP |
423 | break; |
424 | case 2: | |
425 | omap_revision = TI8148_REV_ES2_0; | |
50a01e64 | 426 | cpu_rev = "2.0"; |
4390f5b2 HP |
427 | break; |
428 | case 3: | |
429 | /* FALLTHROUGH */ | |
430 | default: | |
431 | omap_revision = TI8148_REV_ES2_1; | |
50a01e64 | 432 | cpu_rev = "2.1"; |
4390f5b2 HP |
433 | break; |
434 | } | |
1e6cb146 | 435 | break; |
2456a10f | 436 | default: |
51ec811a | 437 | /* Unknown default to latest silicon rev as default */ |
3b32b7d6 | 438 | omap_revision = OMAP3630_REV_ES1_2; |
50a01e64 | 439 | cpu_rev = "1.2"; |
51ec811a | 440 | pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n"); |
a8823143 | 441 | } |
1dbae815 TL |
442 | } |
443 | ||
4de34f35 | 444 | void __init omap4xxx_check_revision(void) |
b570e0ec SS |
445 | { |
446 | u32 idcode; | |
447 | u16 hawkeye; | |
448 | u8 rev; | |
b570e0ec SS |
449 | |
450 | /* | |
451 | * The IC rev detection is done with hawkeye and rev. | |
452 | * Note that rev does not map directly to defined processor | |
453 | * revision numbers as ES1.0 uses value 0. | |
454 | */ | |
455 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
456 | hawkeye = (idcode >> 12) & 0xffff; | |
e49c4d27 | 457 | rev = (idcode >> 28) & 0xf; |
b570e0ec | 458 | |
ed6be0ba | 459 | /* |
fa54dccd | 460 | * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0 |
ed6be0ba SS |
461 | * Use ARM register to detect the correct ES version |
462 | */ | |
ec023e46 | 463 | if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) { |
ed6be0ba SS |
464 | idcode = read_cpuid(CPUID_ID); |
465 | rev = (idcode & 0xf) - 1; | |
466 | } | |
467 | ||
468 | switch (hawkeye) { | |
469 | case 0xb852: | |
470 | switch (rev) { | |
471 | case 0: | |
472 | omap_revision = OMAP4430_REV_ES1_0; | |
ed6be0ba SS |
473 | break; |
474 | case 1: | |
e49c4d27 | 475 | default: |
ed6be0ba | 476 | omap_revision = OMAP4430_REV_ES2_0; |
e49c4d27 NK |
477 | } |
478 | break; | |
479 | case 0xb95c: | |
480 | switch (rev) { | |
481 | case 3: | |
482 | omap_revision = OMAP4430_REV_ES2_1; | |
ed6be0ba | 483 | break; |
e49c4d27 | 484 | case 4: |
e49c4d27 | 485 | omap_revision = OMAP4430_REV_ES2_2; |
55035c15 DA |
486 | break; |
487 | case 6: | |
488 | default: | |
489 | omap_revision = OMAP4430_REV_ES2_3; | |
e49c4d27 NK |
490 | } |
491 | break; | |
fa54dccd A |
492 | case 0xb94e: |
493 | switch (rev) { | |
494 | case 0: | |
fa54dccd | 495 | omap_revision = OMAP4460_REV_ES1_0; |
fa54dccd | 496 | break; |
33ee0db5 CL |
497 | case 2: |
498 | default: | |
499 | omap_revision = OMAP4460_REV_ES1_1; | |
500 | break; | |
fa54dccd A |
501 | } |
502 | break; | |
ec023e46 LI |
503 | case 0xb975: |
504 | switch (rev) { | |
505 | case 0: | |
506 | default: | |
507 | omap_revision = OMAP4470_REV_ES1_0; | |
508 | break; | |
509 | } | |
510 | break; | |
ed6be0ba | 511 | default: |
e49c4d27 | 512 | /* Unknown default to latest silicon rev as default */ |
55035c15 | 513 | omap_revision = OMAP4430_REV_ES2_3; |
b570e0ec SS |
514 | } |
515 | ||
e49c4d27 NK |
516 | pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16, |
517 | ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf)); | |
b570e0ec SS |
518 | } |
519 | ||
b13e80a8 S |
520 | void __init omap5xxx_check_revision(void) |
521 | { | |
522 | u32 idcode; | |
523 | u16 hawkeye; | |
524 | u8 rev; | |
525 | ||
526 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
527 | hawkeye = (idcode >> 12) & 0xffff; | |
528 | rev = (idcode >> 28) & 0xff; | |
529 | switch (hawkeye) { | |
530 | case 0xb942: | |
531 | switch (rev) { | |
532 | case 0: | |
533 | default: | |
534 | omap_revision = OMAP5430_REV_ES1_0; | |
535 | } | |
536 | break; | |
537 | ||
538 | case 0xb998: | |
539 | switch (rev) { | |
540 | case 0: | |
541 | default: | |
542 | omap_revision = OMAP5432_REV_ES1_0; | |
543 | } | |
544 | break; | |
545 | ||
546 | default: | |
547 | /* Unknown default to latest silicon rev as default*/ | |
548 | omap_revision = OMAP5430_REV_ES1_0; | |
549 | } | |
550 | ||
551 | pr_info("OMAP%04x ES%d.0\n", | |
552 | omap_rev() >> 16, ((omap_rev() >> 12) & 0xf)); | |
553 | } | |
554 | ||
a8823143 TL |
555 | /* |
556 | * Set up things for map_io and processor detection later on. Gets called | |
557 | * pretty much first thing from board init. For multi-omap, this gets | |
558 | * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to | |
559 | * detect the exact revision later on in omap2_detect_revision() once map_io | |
560 | * is done. | |
561 | */ | |
0e564848 TL |
562 | void __init omap2_set_globals_tap(struct omap_globals *omap2_globals) |
563 | { | |
84a34344 | 564 | omap_revision = omap2_globals->class; |
0e564848 TL |
565 | tap_base = omap2_globals->tap; |
566 | ||
a8823143 | 567 | if (cpu_is_omap34xx()) |
0e564848 TL |
568 | tap_prod_id = 0x0210; |
569 | else | |
570 | tap_prod_id = 0x0208; | |
571 | } |