[deliverable/linux.git] / arch / arm / mach-omap2 / io.c

/*
 * linux/arch/arm/mach-omap2/io.c
 *
 * OMAP2 I/O mapping code
 *
 * Copyright (C) 2005 Nokia Corporation
 * Copyright (C) 2007-2009 Texas Instruments
 *
 * Author:
 *	Juha Yrjola <juha.yrjola@nokia.com>
 *	Syed Khasim <x0khasim@ti.com>
 *
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/omapfb.h>

#include <asm/tlb.h>

#include <asm/mach/map.h>

#include <plat/mux.h>
#include <plat/sram.h>
#include <plat/sdrc.h>
#include <plat/gpmc.h>
#include <plat/serial.h>
#include <plat/vram.h>

#include "clock.h"

#include <plat/omap-pm.h>
#include <plat/powerdomain.h>
#include "powerdomains.h"

#include <plat/clockdomain.h>
#include "clockdomains.h"
#include <plat/omap_hwmod.h>
#include "omap_hwmod_2420.h"
#include "omap_hwmod_2430.h"
#include "omap_hwmod_34xx.h"

/*
 * The machine specific code may provide the extra mapping besides the
 * default mapping provided here.
 */

#ifdef CONFIG_ARCH_OMAP24XX
static struct map_desc omap24xx_io_desc[] __initdata = {
	{
		.virtual	= L3_24XX_VIRT,
		.pfn		= __phys_to_pfn(L3_24XX_PHYS),
		.length		= L3_24XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_24XX_VIRT,
		.pfn		= __phys_to_pfn(L4_24XX_PHYS),
		.length		= L4_24XX_SIZE,
		.type		= MT_DEVICE
	},
};

#ifdef CONFIG_ARCH_OMAP2420
static struct map_desc omap242x_io_desc[] __initdata = {
	{
		.virtual	= DSP_MEM_2420_VIRT,
		.pfn		= __phys_to_pfn(DSP_MEM_2420_PHYS),
		.length		= DSP_MEM_2420_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= DSP_IPI_2420_VIRT,
		.pfn		= __phys_to_pfn(DSP_IPI_2420_PHYS),
		.length		= DSP_IPI_2420_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= DSP_MMU_2420_VIRT,
		.pfn		= __phys_to_pfn(DSP_MMU_2420_PHYS),
		.length		= DSP_MMU_2420_SIZE,
		.type		= MT_DEVICE
	},
};

#endif

#ifdef CONFIG_ARCH_OMAP2430
static struct map_desc omap243x_io_desc[] __initdata = {
	{
		.virtual	= L4_WK_243X_VIRT,
		.pfn		= __phys_to_pfn(L4_WK_243X_PHYS),
		.length		= L4_WK_243X_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP243X_GPMC_VIRT,
		.pfn		= __phys_to_pfn(OMAP243X_GPMC_PHYS),
		.length		= OMAP243X_GPMC_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP243X_SDRC_VIRT,
		.pfn		= __phys_to_pfn(OMAP243X_SDRC_PHYS),
		.length		= OMAP243X_SDRC_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP243X_SMS_VIRT,
		.pfn		= __phys_to_pfn(OMAP243X_SMS_PHYS),
		.length		= OMAP243X_SMS_SIZE,
		.type		= MT_DEVICE
	},
};
#endif
#endif

#ifdef	CONFIG_ARCH_OMAP34XX
static struct map_desc omap34xx_io_desc[] __initdata = {
	{
		.virtual	= L3_34XX_VIRT,
		.pfn		= __phys_to_pfn(L3_34XX_PHYS),
		.length		= L3_34XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
		.length		= L4_34XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_WK_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_WK_34XX_PHYS),
		.length		= L4_WK_34XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP34XX_GPMC_VIRT,
		.pfn		= __phys_to_pfn(OMAP34XX_GPMC_PHYS),
		.length		= OMAP34XX_GPMC_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP343X_SMS_VIRT,
		.pfn		= __phys_to_pfn(OMAP343X_SMS_PHYS),
		.length		= OMAP343X_SMS_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP343X_SDRC_VIRT,
		.pfn		= __phys_to_pfn(OMAP343X_SDRC_PHYS),
		.length		= OMAP343X_SDRC_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_PER_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_PER_34XX_PHYS),
		.length		= L4_PER_34XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_EMU_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_EMU_34XX_PHYS),
		.length		= L4_EMU_34XX_SIZE,
		.type		= MT_DEVICE
	},
};
#endif
#ifdef	CONFIG_ARCH_OMAP4
static struct map_desc omap44xx_io_desc[] __initdata = {
	{
		.virtual	= L3_44XX_VIRT,
		.pfn		= __phys_to_pfn(L3_44XX_PHYS),
		.length		= L3_44XX_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= L4_44XX_VIRT,
		.pfn		= __phys_to_pfn(L4_44XX_PHYS),
		.length		= L4_44XX_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= L4_WK_44XX_VIRT,
		.pfn		= __phys_to_pfn(L4_WK_44XX_PHYS),
		.length		= L4_WK_44XX_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= OMAP44XX_GPMC_VIRT,
		.pfn		= __phys_to_pfn(OMAP44XX_GPMC_PHYS),
		.length		= OMAP44XX_GPMC_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= OMAP44XX_EMIF1_VIRT,
		.pfn		= __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
		.length		= OMAP44XX_EMIF1_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= OMAP44XX_EMIF2_VIRT,
		.pfn		= __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
		.length		= OMAP44XX_EMIF2_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= OMAP44XX_DMM_VIRT,
		.pfn		= __phys_to_pfn(OMAP44XX_DMM_PHYS),
		.length		= OMAP44XX_DMM_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= L4_PER_44XX_VIRT,
		.pfn		= __phys_to_pfn(L4_PER_44XX_PHYS),
		.length		= L4_PER_44XX_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= L4_EMU_44XX_VIRT,
		.pfn		= __phys_to_pfn(L4_EMU_44XX_PHYS),
		.length		= L4_EMU_44XX_SIZE,
		.type		= MT_DEVICE,
	},
};
#endif

void __init omap2_map_common_io(void)
{
#if defined(CONFIG_ARCH_OMAP2420)
	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
#endif

#if defined(CONFIG_ARCH_OMAP2430)
	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
#endif

#if defined(CONFIG_ARCH_OMAP34XX)
	iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
#endif

#if defined(CONFIG_ARCH_OMAP4)
	iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
#endif
	/* Normally devicemaps_init() would flush caches and tlb after
	 * mdesc->map_io(), but we must also do it here because of the CPU
	 * revision check below.
	 */
	local_flush_tlb_all();
	flush_cache_all();

	omap2_check_revision();
	omap_sram_init();
	omapfb_reserve_sdram();
	omap_vram_reserve_sdram();
}

/*
 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
 *
 * Sets the CORE DPLL3 M2 divider to the same value that it's at
 * currently.  This has the effect of setting the SDRC SDRAM AC timing
 * registers to the values currently defined by the kernel.  Currently
 * only defined for OMAP3; will return 0 if called on OMAP2.  Returns
 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
 * or passes along the return value of clk_set_rate().
 */
static int __init _omap2_init_reprogram_sdrc(void)
{
	struct clk *dpll3_m2_ck;
	int v = -EINVAL;
	long rate;

	if (!cpu_is_omap34xx())
		return 0;

	dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
	if (!dpll3_m2_ck)
		return -EINVAL;

	rate = clk_get_rate(dpll3_m2_ck);
	pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
	v = clk_set_rate(dpll3_m2_ck, rate);
	if (v)
		pr_err("dpll3_m2_clk rate change failed: %d\n", v);

	clk_put(dpll3_m2_ck);

	return v;
}

void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
				 struct omap_sdrc_params *sdrc_cs1)
{
	struct omap_hwmod **hwmods = NULL;

	if (cpu_is_omap2420())
		hwmods = omap2420_hwmods;
	else if (cpu_is_omap2430())
		hwmods = omap2430_hwmods;
	else if (cpu_is_omap34xx())
		hwmods = omap34xx_hwmods;

#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
	/* The OPP tables have to be registered before a clk init */
	omap_hwmod_init(hwmods);
	omap2_mux_init();
	omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
	pwrdm_init(powerdomains_omap);
	clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
#endif
	omap2_clk_init();
	omap_serial_early_init();
#ifndef CONFIG_ARCH_OMAP4
	omap_hwmod_late_init();
	omap_pm_if_init();
	omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
	_omap2_init_reprogram_sdrc();
#endif
	gpmc_init();
}
Commit	Line	Data
1dbae815 TL	1	/*
	2	* linux/arch/arm/mach-omap2/io.c
	3	*
	4	* OMAP2 I/O mapping code
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
44169075	7	* Copyright (C) 2007-2009 Texas Instruments
646e3ed1 TL	8	*
	9	* Author:
	10	* Juha Yrjola <juha.yrjola@nokia.com>
	11	* Syed Khasim <x0khasim@ti.com>
1dbae815	12	*
44169075 SS	13	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
44169075 SS	14	*
1dbae815 TL	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License version 2 as
	17	* published by the Free Software Foundation.
	18	*/
	19
1dbae815 TL	20	#include <linux/module.h>
	21	#include <linux/kernel.h>
	22	#include <linux/init.h>
fced80c7	23	#include <linux/io.h>
2f135eaf	24	#include <linux/clk.h>
91773a00	25	#include <linux/omapfb.h>
1dbae815	26
120db2cb	27	#include <asm/tlb.h>
120db2cb TL	28
	29	#include <asm/mach/map.h>
	30
ce491cf8	31	#include <plat/mux.h>
ce491cf8 TL	32	#include <plat/sram.h>
	33	#include <plat/sdrc.h>
	34	#include <plat/gpmc.h>
	35	#include <plat/serial.h>
afedec18	36	#include <plat/vram.h>
646e3ed1 TL	37
646e3ed1 TL	38	#include "clock.h"
1dbae815	39
ce491cf8 TL	40	#include <plat/omap-pm.h>
ce491cf8 TL	41	#include <plat/powerdomain.h>
9717100f	42	#include "powerdomains.h"
1dbae815	43
ce491cf8	44	#include <plat/clockdomain.h>
801954d3	45	#include "clockdomains.h"
ce491cf8	46	#include <plat/omap_hwmod.h>
02bfc030 PW	47	#include "omap_hwmod_2420.h"
	48	#include "omap_hwmod_2430.h"
	49	#include "omap_hwmod_34xx.h"
	50
1dbae815 TL	51	/*
	52	* The machine specific code may provide the extra mapping besides the
	53	* default mapping provided here.
	54	*/
cc26b3b0 SMK	55
	56	#ifdef CONFIG_ARCH_OMAP24XX
	57	static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815 TL	58	{
	59	.virtual = L3_24XX_VIRT,
	60	.pfn = __phys_to_pfn(L3_24XX_PHYS),
	61	.length = L3_24XX_SIZE,
	62	.type = MT_DEVICE
	63	},
09f21ed4	64	{
cc26b3b0 SMK	65	.virtual = L4_24XX_VIRT,
	66	.pfn = __phys_to_pfn(L4_24XX_PHYS),
	67	.length = L4_24XX_SIZE,
	68	.type = MT_DEVICE
09f21ed4	69	},
cc26b3b0 SMK	70	};
	71
	72	#ifdef CONFIG_ARCH_OMAP2420
	73	static struct map_desc omap242x_io_desc[] __initdata = {
	74	{
7adb9987 PW	75	.virtual = DSP_MEM_2420_VIRT,
	76	.pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
	77	.length = DSP_MEM_2420_SIZE,
cc26b3b0 SMK	78	.type = MT_DEVICE
	79	},
	80	{
7adb9987 PW	81	.virtual = DSP_IPI_2420_VIRT,
	82	.pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
	83	.length = DSP_IPI_2420_SIZE,
cc26b3b0	84	.type = MT_DEVICE
09f21ed4	85	},
cc26b3b0	86	{
7adb9987 PW	87	.virtual = DSP_MMU_2420_VIRT,
	88	.pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
	89	.length = DSP_MMU_2420_SIZE,
cc26b3b0 SMK	90	.type = MT_DEVICE
	91	},
	92	};
	93
	94	#endif
	95
72d0f1c3	96	#ifdef CONFIG_ARCH_OMAP2430
cc26b3b0	97	static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3 SMK	98	{
	99	.virtual = L4_WK_243X_VIRT,
	100	.pfn = __phys_to_pfn(L4_WK_243X_PHYS),
	101	.length = L4_WK_243X_SIZE,
	102	.type = MT_DEVICE
	103	},
	104	{
	105	.virtual = OMAP243X_GPMC_VIRT,
	106	.pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
	107	.length = OMAP243X_GPMC_SIZE,
	108	.type = MT_DEVICE
	109	},
cc26b3b0 SMK	110	{
	111	.virtual = OMAP243X_SDRC_VIRT,
	112	.pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
	113	.length = OMAP243X_SDRC_SIZE,
	114	.type = MT_DEVICE
	115	},
	116	{
	117	.virtual = OMAP243X_SMS_VIRT,
	118	.pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
	119	.length = OMAP243X_SMS_SIZE,
	120	.type = MT_DEVICE
	121	},
	122	};
72d0f1c3	123	#endif
72d0f1c3	124	#endif
cc26b3b0 SMK	125
	126	#ifdef CONFIG_ARCH_OMAP34XX
	127	static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815	128	{
cc26b3b0 SMK	129	.virtual = L3_34XX_VIRT,
	130	.pfn = __phys_to_pfn(L3_34XX_PHYS),
	131	.length = L3_34XX_SIZE,
c40fae95 TL	132	.type = MT_DEVICE
	133	},
	134	{
cc26b3b0 SMK	135	.virtual = L4_34XX_VIRT,
	136	.pfn = __phys_to_pfn(L4_34XX_PHYS),
	137	.length = L4_34XX_SIZE,
c40fae95 TL	138	.type = MT_DEVICE
	139	},
	140	{
cc26b3b0 SMK	141	.virtual = L4_WK_34XX_VIRT,
	142	.pfn = __phys_to_pfn(L4_WK_34XX_PHYS),
	143	.length = L4_WK_34XX_SIZE,
	144	.type = MT_DEVICE
	145	},
	146	{
	147	.virtual = OMAP34XX_GPMC_VIRT,
	148	.pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
	149	.length = OMAP34XX_GPMC_SIZE,
1dbae815	150	.type = MT_DEVICE
cc26b3b0 SMK	151	},
	152	{
	153	.virtual = OMAP343X_SMS_VIRT,
	154	.pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
	155	.length = OMAP343X_SMS_SIZE,
	156	.type = MT_DEVICE
	157	},
	158	{
	159	.virtual = OMAP343X_SDRC_VIRT,
	160	.pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
	161	.length = OMAP343X_SDRC_SIZE,
1dbae815	162	.type = MT_DEVICE
cc26b3b0 SMK	163	},
	164	{
	165	.virtual = L4_PER_34XX_VIRT,
	166	.pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
	167	.length = L4_PER_34XX_SIZE,
	168	.type = MT_DEVICE
	169	},
	170	{
	171	.virtual = L4_EMU_34XX_VIRT,
	172	.pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
	173	.length = L4_EMU_34XX_SIZE,
	174	.type = MT_DEVICE
	175	},
1dbae815	176	};
cc26b3b0	177	#endif
44169075 SS	178	#ifdef CONFIG_ARCH_OMAP4
	179	static struct map_desc omap44xx_io_desc[] __initdata = {
	180	{
	181	.virtual = L3_44XX_VIRT,
	182	.pfn = __phys_to_pfn(L3_44XX_PHYS),
	183	.length = L3_44XX_SIZE,
	184	.type = MT_DEVICE,
	185	},
	186	{
	187	.virtual = L4_44XX_VIRT,
	188	.pfn = __phys_to_pfn(L4_44XX_PHYS),
	189	.length = L4_44XX_SIZE,
	190	.type = MT_DEVICE,
	191	},
	192	{
	193	.virtual = L4_WK_44XX_VIRT,
	194	.pfn = __phys_to_pfn(L4_WK_44XX_PHYS),
	195	.length = L4_WK_44XX_SIZE,
	196	.type = MT_DEVICE,
	197	},
	198	{
	199	.virtual = OMAP44XX_GPMC_VIRT,
	200	.pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
	201	.length = OMAP44XX_GPMC_SIZE,
	202	.type = MT_DEVICE,
	203	},
f5d2d659 SS	204	{
	205	.virtual = OMAP44XX_EMIF1_VIRT,
	206	.pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
	207	.length = OMAP44XX_EMIF1_SIZE,
	208	.type = MT_DEVICE,
	209	},
	210	{
	211	.virtual = OMAP44XX_EMIF2_VIRT,
	212	.pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
	213	.length = OMAP44XX_EMIF2_SIZE,
	214	.type = MT_DEVICE,
	215	},
	216	{
	217	.virtual = OMAP44XX_DMM_VIRT,
	218	.pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
	219	.length = OMAP44XX_DMM_SIZE,
	220	.type = MT_DEVICE,
	221	},
44169075 SS	222	{
	223	.virtual = L4_PER_44XX_VIRT,
	224	.pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
	225	.length = L4_PER_44XX_SIZE,
	226	.type = MT_DEVICE,
	227	},
	228	{
	229	.virtual = L4_EMU_44XX_VIRT,
	230	.pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
	231	.length = L4_EMU_44XX_SIZE,
	232	.type = MT_DEVICE,
	233	},
	234	};
	235	#endif
1dbae815	236
120db2cb	237	void __init omap2_map_common_io(void)
1dbae815	238	{
cc26b3b0 SMK	239	#if defined(CONFIG_ARCH_OMAP2420)
	240	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	241	iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
	242	#endif
	243
	244	#if defined(CONFIG_ARCH_OMAP2430)
	245	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	246	iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
	247	#endif
	248
	249	#if defined(CONFIG_ARCH_OMAP34XX)
	250	iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
	251	#endif
120db2cb	252
44169075 SS	253	#if defined(CONFIG_ARCH_OMAP4)
	254	iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
	255	#endif
120db2cb TL	256	/* Normally devicemaps_init() would flush caches and tlb after
	257	* mdesc->map_io(), but we must also do it here because of the CPU
	258	* revision check below.
	259	*/
	260	local_flush_tlb_all();
	261	flush_cache_all();
	262
1dbae815 TL	263	omap2_check_revision();
1dbae815 TL	264	omap_sram_init();
b7cc6d46	265	omapfb_reserve_sdram();
afedec18	266	omap_vram_reserve_sdram();
120db2cb TL	267	}
120db2cb TL	268
2f135eaf PW	269	/*
	270	* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
	271	*
	272	* Sets the CORE DPLL3 M2 divider to the same value that it's at
	273	* currently. This has the effect of setting the SDRC SDRAM AC timing
	274	* registers to the values currently defined by the kernel. Currently
	275	* only defined for OMAP3; will return 0 if called on OMAP2. Returns
	276	* -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
	277	* or passes along the return value of clk_set_rate().
	278	*/
	279	static int __init _omap2_init_reprogram_sdrc(void)
	280	{
	281	struct clk *dpll3_m2_ck;
	282	int v = -EINVAL;
	283	long rate;
	284
	285	if (!cpu_is_omap34xx())
	286	return 0;
	287
	288	dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
	289	if (!dpll3_m2_ck)
	290	return -EINVAL;
	291
	292	rate = clk_get_rate(dpll3_m2_ck);
	293	pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
	294	v = clk_set_rate(dpll3_m2_ck, rate);
	295	if (v)
	296	pr_err("dpll3_m2_clk rate change failed: %d\n", v);
	297
	298	clk_put(dpll3_m2_ck);
	299
	300	return v;
	301	}
	302
58cda884 JP	303	void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
58cda884 JP	304	struct omap_sdrc_params *sdrc_cs1)
120db2cb	305	{
02bfc030 PW	306	struct omap_hwmod **hwmods = NULL;
	307
	308	if (cpu_is_omap2420())
	309	hwmods = omap2420_hwmods;
	310	else if (cpu_is_omap2430())
	311	hwmods = omap2430_hwmods;
	312	else if (cpu_is_omap34xx())
	313	hwmods = omap34xx_hwmods;
	314
44169075	315	#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
c0407a96	316	/* The OPP tables have to be registered before a clk init */
61f04ee8 TL	317	omap_hwmod_init(hwmods);
61f04ee8 TL	318	omap2_mux_init();
c0407a96	319	omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
9717100f	320	pwrdm_init(powerdomains_omap);
801954d3	321	clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
5b7815b5	322	#endif
d79b1267	323	omap2_clk_init();
b3c6df3a	324	omap_serial_early_init();
5b7815b5	325	#ifndef CONFIG_ARCH_OMAP4
02bfc030	326	omap_hwmod_late_init();
c0407a96	327	omap_pm_if_init();
58cda884	328	omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
2f135eaf	329	_omap2_init_reprogram_sdrc();
44169075	330	#endif
4bbbc1ad	331	gpmc_init();
1dbae815	332	}