Commit | Line | Data |
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1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/io.c | |
3 | * | |
4 | * OMAP2 I/O mapping code | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
44169075 | 7 | * Copyright (C) 2007-2009 Texas Instruments |
646e3ed1 TL |
8 | * |
9 | * Author: | |
10 | * Juha Yrjola <juha.yrjola@nokia.com> | |
11 | * Syed Khasim <x0khasim@ti.com> | |
1dbae815 | 12 | * |
44169075 SS |
13 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
14 | * | |
1dbae815 TL |
15 | * This program is free software; you can redistribute it and/or modify |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
19 | ||
1dbae815 TL |
20 | #include <linux/module.h> |
21 | #include <linux/kernel.h> | |
22 | #include <linux/init.h> | |
fced80c7 | 23 | #include <linux/io.h> |
2f135eaf | 24 | #include <linux/clk.h> |
91773a00 | 25 | #include <linux/omapfb.h> |
1dbae815 | 26 | |
120db2cb | 27 | #include <asm/tlb.h> |
120db2cb TL |
28 | |
29 | #include <asm/mach/map.h> | |
30 | ||
ce491cf8 TL |
31 | #include <plat/sram.h> |
32 | #include <plat/sdrc.h> | |
33 | #include <plat/gpmc.h> | |
34 | #include <plat/serial.h> | |
646e3ed1 | 35 | |
e80a9729 | 36 | #include "clock2xxx.h" |
657ebfad | 37 | #include "clock3xxx.h" |
e80a9729 | 38 | #include "clock44xx.h" |
b0a330dc | 39 | #include "io.h" |
1dbae815 | 40 | |
ce491cf8 TL |
41 | #include <plat/omap-pm.h> |
42 | #include <plat/powerdomain.h> | |
1dbae815 | 43 | |
ce491cf8 | 44 | #include <plat/clockdomain.h> |
ce491cf8 | 45 | #include <plat/omap_hwmod.h> |
5d190c40 | 46 | #include <plat/multi.h> |
02bfc030 | 47 | |
1dbae815 TL |
48 | /* |
49 | * The machine specific code may provide the extra mapping besides the | |
50 | * default mapping provided here. | |
51 | */ | |
cc26b3b0 | 52 | |
088ef950 | 53 | #ifdef CONFIG_ARCH_OMAP2 |
cc26b3b0 | 54 | static struct map_desc omap24xx_io_desc[] __initdata = { |
1dbae815 TL |
55 | { |
56 | .virtual = L3_24XX_VIRT, | |
57 | .pfn = __phys_to_pfn(L3_24XX_PHYS), | |
58 | .length = L3_24XX_SIZE, | |
59 | .type = MT_DEVICE | |
60 | }, | |
09f21ed4 | 61 | { |
cc26b3b0 SMK |
62 | .virtual = L4_24XX_VIRT, |
63 | .pfn = __phys_to_pfn(L4_24XX_PHYS), | |
64 | .length = L4_24XX_SIZE, | |
65 | .type = MT_DEVICE | |
09f21ed4 | 66 | }, |
cc26b3b0 SMK |
67 | }; |
68 | ||
69 | #ifdef CONFIG_ARCH_OMAP2420 | |
70 | static struct map_desc omap242x_io_desc[] __initdata = { | |
71 | { | |
7adb9987 PW |
72 | .virtual = DSP_MEM_2420_VIRT, |
73 | .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS), | |
74 | .length = DSP_MEM_2420_SIZE, | |
cc26b3b0 SMK |
75 | .type = MT_DEVICE |
76 | }, | |
77 | { | |
7adb9987 PW |
78 | .virtual = DSP_IPI_2420_VIRT, |
79 | .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS), | |
80 | .length = DSP_IPI_2420_SIZE, | |
cc26b3b0 | 81 | .type = MT_DEVICE |
09f21ed4 | 82 | }, |
cc26b3b0 | 83 | { |
7adb9987 PW |
84 | .virtual = DSP_MMU_2420_VIRT, |
85 | .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS), | |
86 | .length = DSP_MMU_2420_SIZE, | |
cc26b3b0 SMK |
87 | .type = MT_DEVICE |
88 | }, | |
89 | }; | |
90 | ||
91 | #endif | |
92 | ||
72d0f1c3 | 93 | #ifdef CONFIG_ARCH_OMAP2430 |
cc26b3b0 | 94 | static struct map_desc omap243x_io_desc[] __initdata = { |
72d0f1c3 SMK |
95 | { |
96 | .virtual = L4_WK_243X_VIRT, | |
97 | .pfn = __phys_to_pfn(L4_WK_243X_PHYS), | |
98 | .length = L4_WK_243X_SIZE, | |
99 | .type = MT_DEVICE | |
100 | }, | |
101 | { | |
102 | .virtual = OMAP243X_GPMC_VIRT, | |
103 | .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), | |
104 | .length = OMAP243X_GPMC_SIZE, | |
105 | .type = MT_DEVICE | |
106 | }, | |
cc26b3b0 SMK |
107 | { |
108 | .virtual = OMAP243X_SDRC_VIRT, | |
109 | .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS), | |
110 | .length = OMAP243X_SDRC_SIZE, | |
111 | .type = MT_DEVICE | |
112 | }, | |
113 | { | |
114 | .virtual = OMAP243X_SMS_VIRT, | |
115 | .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS), | |
116 | .length = OMAP243X_SMS_SIZE, | |
117 | .type = MT_DEVICE | |
118 | }, | |
119 | }; | |
72d0f1c3 | 120 | #endif |
72d0f1c3 | 121 | #endif |
cc26b3b0 | 122 | |
a8eb7ca0 | 123 | #ifdef CONFIG_ARCH_OMAP3 |
cc26b3b0 | 124 | static struct map_desc omap34xx_io_desc[] __initdata = { |
1dbae815 | 125 | { |
cc26b3b0 SMK |
126 | .virtual = L3_34XX_VIRT, |
127 | .pfn = __phys_to_pfn(L3_34XX_PHYS), | |
128 | .length = L3_34XX_SIZE, | |
c40fae95 TL |
129 | .type = MT_DEVICE |
130 | }, | |
131 | { | |
cc26b3b0 SMK |
132 | .virtual = L4_34XX_VIRT, |
133 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
134 | .length = L4_34XX_SIZE, | |
c40fae95 TL |
135 | .type = MT_DEVICE |
136 | }, | |
cc26b3b0 SMK |
137 | { |
138 | .virtual = OMAP34XX_GPMC_VIRT, | |
139 | .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), | |
140 | .length = OMAP34XX_GPMC_SIZE, | |
1dbae815 | 141 | .type = MT_DEVICE |
cc26b3b0 SMK |
142 | }, |
143 | { | |
144 | .virtual = OMAP343X_SMS_VIRT, | |
145 | .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS), | |
146 | .length = OMAP343X_SMS_SIZE, | |
147 | .type = MT_DEVICE | |
148 | }, | |
149 | { | |
150 | .virtual = OMAP343X_SDRC_VIRT, | |
151 | .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS), | |
152 | .length = OMAP343X_SDRC_SIZE, | |
1dbae815 | 153 | .type = MT_DEVICE |
cc26b3b0 SMK |
154 | }, |
155 | { | |
156 | .virtual = L4_PER_34XX_VIRT, | |
157 | .pfn = __phys_to_pfn(L4_PER_34XX_PHYS), | |
158 | .length = L4_PER_34XX_SIZE, | |
159 | .type = MT_DEVICE | |
160 | }, | |
161 | { | |
162 | .virtual = L4_EMU_34XX_VIRT, | |
163 | .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS), | |
164 | .length = L4_EMU_34XX_SIZE, | |
165 | .type = MT_DEVICE | |
166 | }, | |
a4f57b81 TL |
167 | #if defined(CONFIG_DEBUG_LL) && \ |
168 | (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3)) | |
169 | { | |
170 | .virtual = ZOOM_UART_VIRT, | |
171 | .pfn = __phys_to_pfn(ZOOM_UART_BASE), | |
172 | .length = SZ_1M, | |
173 | .type = MT_DEVICE | |
174 | }, | |
175 | #endif | |
1dbae815 | 176 | }; |
cc26b3b0 | 177 | #endif |
44169075 SS |
178 | #ifdef CONFIG_ARCH_OMAP4 |
179 | static struct map_desc omap44xx_io_desc[] __initdata = { | |
180 | { | |
181 | .virtual = L3_44XX_VIRT, | |
182 | .pfn = __phys_to_pfn(L3_44XX_PHYS), | |
183 | .length = L3_44XX_SIZE, | |
184 | .type = MT_DEVICE, | |
185 | }, | |
186 | { | |
187 | .virtual = L4_44XX_VIRT, | |
188 | .pfn = __phys_to_pfn(L4_44XX_PHYS), | |
189 | .length = L4_44XX_SIZE, | |
190 | .type = MT_DEVICE, | |
191 | }, | |
44169075 SS |
192 | { |
193 | .virtual = OMAP44XX_GPMC_VIRT, | |
194 | .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS), | |
195 | .length = OMAP44XX_GPMC_SIZE, | |
196 | .type = MT_DEVICE, | |
197 | }, | |
f5d2d659 SS |
198 | { |
199 | .virtual = OMAP44XX_EMIF1_VIRT, | |
200 | .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS), | |
201 | .length = OMAP44XX_EMIF1_SIZE, | |
202 | .type = MT_DEVICE, | |
203 | }, | |
204 | { | |
205 | .virtual = OMAP44XX_EMIF2_VIRT, | |
206 | .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS), | |
207 | .length = OMAP44XX_EMIF2_SIZE, | |
208 | .type = MT_DEVICE, | |
209 | }, | |
210 | { | |
211 | .virtual = OMAP44XX_DMM_VIRT, | |
212 | .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS), | |
213 | .length = OMAP44XX_DMM_SIZE, | |
214 | .type = MT_DEVICE, | |
215 | }, | |
44169075 SS |
216 | { |
217 | .virtual = L4_PER_44XX_VIRT, | |
218 | .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), | |
219 | .length = L4_PER_44XX_SIZE, | |
220 | .type = MT_DEVICE, | |
221 | }, | |
222 | { | |
223 | .virtual = L4_EMU_44XX_VIRT, | |
224 | .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS), | |
225 | .length = L4_EMU_44XX_SIZE, | |
226 | .type = MT_DEVICE, | |
227 | }, | |
228 | }; | |
229 | #endif | |
1dbae815 | 230 | |
6fbd55d0 TL |
231 | static void __init _omap2_map_common_io(void) |
232 | { | |
233 | /* Normally devicemaps_init() would flush caches and tlb after | |
234 | * mdesc->map_io(), but we must also do it here because of the CPU | |
235 | * revision check below. | |
236 | */ | |
237 | local_flush_tlb_all(); | |
238 | flush_cache_all(); | |
239 | ||
240 | omap2_check_revision(); | |
241 | omap_sram_init(); | |
6fbd55d0 TL |
242 | } |
243 | ||
244 | #ifdef CONFIG_ARCH_OMAP2420 | |
8185e468 | 245 | void __init omap242x_map_common_io(void) |
1dbae815 | 246 | { |
cc26b3b0 SMK |
247 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
248 | iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); | |
6fbd55d0 TL |
249 | _omap2_map_common_io(); |
250 | } | |
cc26b3b0 SMK |
251 | #endif |
252 | ||
6fbd55d0 | 253 | #ifdef CONFIG_ARCH_OMAP2430 |
8185e468 | 254 | void __init omap243x_map_common_io(void) |
6fbd55d0 | 255 | { |
cc26b3b0 SMK |
256 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
257 | iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); | |
6fbd55d0 TL |
258 | _omap2_map_common_io(); |
259 | } | |
cc26b3b0 SMK |
260 | #endif |
261 | ||
a8eb7ca0 | 262 | #ifdef CONFIG_ARCH_OMAP3 |
8185e468 | 263 | void __init omap34xx_map_common_io(void) |
6fbd55d0 | 264 | { |
cc26b3b0 | 265 | iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); |
6fbd55d0 TL |
266 | _omap2_map_common_io(); |
267 | } | |
cc26b3b0 | 268 | #endif |
120db2cb | 269 | |
6fbd55d0 | 270 | #ifdef CONFIG_ARCH_OMAP4 |
8185e468 | 271 | void __init omap44xx_map_common_io(void) |
6fbd55d0 | 272 | { |
44169075 | 273 | iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); |
6fbd55d0 | 274 | _omap2_map_common_io(); |
120db2cb | 275 | } |
6fbd55d0 | 276 | #endif |
120db2cb | 277 | |
2f135eaf PW |
278 | /* |
279 | * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters | |
280 | * | |
281 | * Sets the CORE DPLL3 M2 divider to the same value that it's at | |
282 | * currently. This has the effect of setting the SDRC SDRAM AC timing | |
283 | * registers to the values currently defined by the kernel. Currently | |
284 | * only defined for OMAP3; will return 0 if called on OMAP2. Returns | |
285 | * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, | |
286 | * or passes along the return value of clk_set_rate(). | |
287 | */ | |
288 | static int __init _omap2_init_reprogram_sdrc(void) | |
289 | { | |
290 | struct clk *dpll3_m2_ck; | |
291 | int v = -EINVAL; | |
292 | long rate; | |
293 | ||
294 | if (!cpu_is_omap34xx()) | |
295 | return 0; | |
296 | ||
297 | dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); | |
e281f7ec | 298 | if (IS_ERR(dpll3_m2_ck)) |
2f135eaf PW |
299 | return -EINVAL; |
300 | ||
301 | rate = clk_get_rate(dpll3_m2_ck); | |
302 | pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); | |
303 | v = clk_set_rate(dpll3_m2_ck, rate); | |
304 | if (v) | |
305 | pr_err("dpll3_m2_clk rate change failed: %d\n", v); | |
306 | ||
307 | clk_put(dpll3_m2_ck); | |
308 | ||
309 | return v; | |
310 | } | |
311 | ||
2092e5cc PW |
312 | static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) |
313 | { | |
314 | return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); | |
315 | } | |
316 | ||
5d190c40 TL |
317 | /* |
318 | * Initialize asm_irq_base for entry-macro.S | |
319 | */ | |
320 | static inline void omap_irq_base_init(void) | |
321 | { | |
322 | extern void __iomem *omap_irq_base; | |
323 | ||
324 | #ifdef MULTI_OMAP2 | |
df127ee3 | 325 | if (cpu_is_omap24xx()) |
5d190c40 TL |
326 | omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE); |
327 | else if (cpu_is_omap34xx()) | |
328 | omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE); | |
329 | else if (cpu_is_omap44xx()) | |
330 | omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE); | |
331 | else | |
332 | pr_err("Could not initialize omap_irq_base\n"); | |
333 | #endif | |
334 | } | |
335 | ||
4805734b | 336 | void __init omap2_init_common_infrastructure(void) |
120db2cb | 337 | { |
2092e5cc PW |
338 | u8 postsetup_state; |
339 | ||
6e01478a PW |
340 | if (cpu_is_omap242x()) { |
341 | omap2xxx_powerdomains_init(); | |
dc0b3a70 | 342 | omap2_clockdomains_init(); |
7359154e | 343 | omap2420_hwmod_init(); |
6e01478a PW |
344 | } else if (cpu_is_omap243x()) { |
345 | omap2xxx_powerdomains_init(); | |
dc0b3a70 | 346 | omap2_clockdomains_init(); |
7359154e | 347 | omap2430_hwmod_init(); |
6e01478a PW |
348 | } else if (cpu_is_omap34xx()) { |
349 | omap3xxx_powerdomains_init(); | |
dc0b3a70 | 350 | omap2_clockdomains_init(); |
7359154e | 351 | omap3xxx_hwmod_init(); |
6e01478a PW |
352 | } else if (cpu_is_omap44xx()) { |
353 | omap44xx_powerdomains_init(); | |
dc0b3a70 | 354 | omap44xx_clockdomains_init(); |
55d2cb08 | 355 | omap44xx_hwmod_init(); |
6e01478a | 356 | } else { |
2092e5cc | 357 | pr_err("Could not init hwmod data - unknown SoC\n"); |
6e01478a | 358 | } |
2092e5cc PW |
359 | |
360 | /* Set the default postsetup state for all hwmods */ | |
361 | #ifdef CONFIG_PM_RUNTIME | |
362 | postsetup_state = _HWMOD_STATE_IDLE; | |
363 | #else | |
364 | postsetup_state = _HWMOD_STATE_ENABLED; | |
365 | #endif | |
366 | omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); | |
55d2cb08 | 367 | |
ff2516fb PW |
368 | /* |
369 | * Set the default postsetup state for unusual modules (like | |
370 | * MPU WDT). | |
371 | * | |
372 | * The postsetup_state is not actually used until | |
373 | * omap_hwmod_late_init(), so boards that desire full watchdog | |
374 | * coverage of kernel initialization can reprogram the | |
375 | * postsetup_state between the calls to | |
376 | * omap2_init_common_infra() and omap2_init_common_devices(). | |
377 | * | |
378 | * XXX ideally we could detect whether the MPU WDT was currently | |
379 | * enabled here and make this conditional | |
380 | */ | |
381 | postsetup_state = _HWMOD_STATE_DISABLED; | |
382 | omap_hwmod_for_each_by_class("wd_timer", | |
383 | _set_hwmod_postsetup_state, | |
384 | &postsetup_state); | |
385 | ||
53da4ce2 | 386 | omap_pm_if_early_init(); |
e80a9729 | 387 | |
81b34fbe PW |
388 | if (cpu_is_omap2420()) |
389 | omap2420_clk_init(); | |
390 | else if (cpu_is_omap2430()) | |
391 | omap2430_clk_init(); | |
e80a9729 PW |
392 | else if (cpu_is_omap34xx()) |
393 | omap3xxx_clk_init(); | |
394 | else if (cpu_is_omap44xx()) | |
395 | omap4xxx_clk_init(); | |
396 | else | |
2092e5cc | 397 | pr_err("Could not init clock framework - unknown SoC\n"); |
4805734b PW |
398 | } |
399 | ||
4805734b PW |
400 | void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0, |
401 | struct omap_sdrc_params *sdrc_cs1) | |
402 | { | |
b3c6df3a | 403 | omap_serial_early_init(); |
97d60162 | 404 | |
2092e5cc PW |
405 | omap_hwmod_late_init(); |
406 | ||
aa4b1f6e KH |
407 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
408 | omap2_sdrc_init(sdrc_cs0, sdrc_cs1); | |
409 | _omap2_init_reprogram_sdrc(); | |
410 | } | |
4bbbc1ad | 411 | gpmc_init(); |
5d190c40 TL |
412 | |
413 | omap_irq_base_init(); | |
1dbae815 | 414 | } |
df1e9d1c TL |
415 | |
416 | /* | |
417 | * NOTE: Please use ioremap + __raw_read/write where possible instead of these | |
418 | */ | |
419 | ||
420 | u8 omap_readb(u32 pa) | |
421 | { | |
422 | return __raw_readb(OMAP2_L4_IO_ADDRESS(pa)); | |
423 | } | |
424 | EXPORT_SYMBOL(omap_readb); | |
425 | ||
426 | u16 omap_readw(u32 pa) | |
427 | { | |
428 | return __raw_readw(OMAP2_L4_IO_ADDRESS(pa)); | |
429 | } | |
430 | EXPORT_SYMBOL(omap_readw); | |
431 | ||
432 | u32 omap_readl(u32 pa) | |
433 | { | |
434 | return __raw_readl(OMAP2_L4_IO_ADDRESS(pa)); | |
435 | } | |
436 | EXPORT_SYMBOL(omap_readl); | |
437 | ||
438 | void omap_writeb(u8 v, u32 pa) | |
439 | { | |
440 | __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa)); | |
441 | } | |
442 | EXPORT_SYMBOL(omap_writeb); | |
443 | ||
444 | void omap_writew(u16 v, u32 pa) | |
445 | { | |
446 | __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa)); | |
447 | } | |
448 | EXPORT_SYMBOL(omap_writew); | |
449 | ||
450 | void omap_writel(u32 v, u32 pa) | |
451 | { | |
452 | __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa)); | |
453 | } | |
454 | EXPORT_SYMBOL(omap_writel); |