[deliverable/linux.git] / arch / arm / mach-omap2 / irq.c

/*
 * linux/arch/arm/mach-omap2/irq.c
 *
 * Interrupt handler for OMAP2 boards.
 *
 * Copyright (C) 2005 Nokia Corporation
 * Author: Paul Mundt <paul.mundt@nokia.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>

#include <asm/exception.h>
#include <asm/mach/irq.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include "soc.h"
#include "iomap.h"
#include "common.h"

/* selected INTC register offsets */

#define INTC_REVISION		0x0000
#define INTC_SYSCONFIG		0x0010
#define INTC_SYSSTATUS		0x0014
#define INTC_SIR		0x0040
#define INTC_CONTROL		0x0048
#define INTC_PROTECTION		0x004C
#define INTC_IDLE		0x0050
#define INTC_THRESHOLD		0x0068
#define INTC_MIR0		0x0084
#define INTC_MIR_CLEAR0		0x0088
#define INTC_MIR_SET0		0x008c
#define INTC_PENDING_IRQ0	0x0098
/* Number of IRQ state bits in each MIR register */
#define IRQ_BITS_PER_REG	32

#define OMAP2_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
#define OMAP3_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
#define INTCPS_SIR_IRQ_OFFSET	0x0040	/* omap2/3 active interrupt offset */
#define ACTIVEIRQ_MASK		0x7f	/* omap2/3 active interrupt bits */
#define INTCPS_NR_MIR_REGS	3
#define INTCPS_NR_IRQS		96

/*
 * OMAP2 has a number of different interrupt controllers, each interrupt
 * controller is identified as its own "bank". Register definitions are
 * fairly consistent for each bank, but not all registers are implemented
 * for each bank.. when in doubt, consult the TRM.
 */
static struct omap_irq_bank {
	void __iomem *base_reg;
	unsigned int nr_irqs;
} __attribute__ ((aligned(4))) irq_banks[] = {
	{
		/* MPU INTC */
		.nr_irqs	= 96,
	},
};

static struct irq_domain *domain;

/* Structure to save interrupt controller context */
struct omap3_intc_regs {
	u32 sysconfig;
	u32 protection;
	u32 idle;
	u32 threshold;
	u32 ilr[INTCPS_NR_IRQS];
	u32 mir[INTCPS_NR_MIR_REGS];
};

/* INTC bank register get/set */

static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
{
	__raw_writel(val, bank->base_reg + reg);
}

static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
{
	return __raw_readl(bank->base_reg + reg);
}

/* XXX: FIQ and additional INTC support (only MPU at the moment) */
static void omap_ack_irq(struct irq_data *d)
{
	intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
}

static void omap_mask_ack_irq(struct irq_data *d)
{
	irq_gc_mask_disable_reg(d);
	omap_ack_irq(d);
}

static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
{
	unsigned long tmp;

	tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
	pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
		bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);

	tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
	tmp |= 1 << 1;	/* soft reset */
	intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);

	while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
		/* Wait for reset to complete */;

	/* Enable autoidle */
	intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
}

int omap_irq_pending(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
		struct omap_irq_bank *bank = irq_banks + i;
		int irq;

		for (irq = 0; irq < bank->nr_irqs; irq += 32)
			if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
					       ((irq >> 5) << 5)))
				return 1;
	}
	return 0;
}

static __init void
omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
					handle_level_irq);
	ct = gc->chip_types;
	ct->chip.irq_ack = omap_mask_ack_irq;
	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;

	ct->regs.enable = INTC_MIR_CLEAR0;
	ct->regs.disable = INTC_MIR_SET0;
	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
				IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}

static void __init omap_init_irq(u32 base, int nr_irqs,
				 struct device_node *node)
{
	void __iomem *omap_irq_base;
	unsigned long nr_of_irqs = 0;
	unsigned int nr_banks = 0;
	int i, j, irq_base;

	omap_irq_base = ioremap(base, SZ_4K);
	if (WARN_ON(!omap_irq_base))
		return;

	irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
	if (irq_base < 0) {
		pr_warn("Couldn't allocate IRQ numbers\n");
		irq_base = 0;
	}

	domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
				       &irq_domain_simple_ops, NULL);

	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
		struct omap_irq_bank *bank = irq_banks + i;

		bank->nr_irqs = nr_irqs;

		/* Static mapping, never released */
		bank->base_reg = ioremap(base, SZ_4K);
		if (!bank->base_reg) {
			pr_err("Could not ioremap irq bank%i\n", i);
			continue;
		}

		omap_irq_bank_init_one(bank);

		for (j = 0; j < bank->nr_irqs; j += 32)
			omap_alloc_gc(bank->base_reg + j, j + irq_base, 32);

		nr_of_irqs += bank->nr_irqs;
		nr_banks++;
	}

	pr_info("Total of %ld interrupts on %d active controller%s\n",
		nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
}

void __init omap2_init_irq(void)
{
	omap_init_irq(OMAP24XX_IC_BASE, 96, NULL);
}

void __init omap3_init_irq(void)
{
	omap_init_irq(OMAP34XX_IC_BASE, 96, NULL);
}

void __init ti81xx_init_irq(void)
{
	omap_init_irq(OMAP34XX_IC_BASE, 128, NULL);
}

static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
{
	u32 irqnr;

	do {
		irqnr = readl_relaxed(base_addr + 0x98);
		if (irqnr)
			goto out;

		irqnr = readl_relaxed(base_addr + 0xb8);
		if (irqnr)
			goto out;

		irqnr = readl_relaxed(base_addr + 0xd8);
#if IS_ENABLED(CONFIG_SOC_TI81XX) || IS_ENABLED(CONFIG_SOC_AM33XX)
		if (irqnr)
			goto out;
		irqnr = readl_relaxed(base_addr + 0xf8);
#endif

out:
		if (!irqnr)
			break;

		irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
		irqnr &= ACTIVEIRQ_MASK;

		if (irqnr) {
			irqnr = irq_find_mapping(domain, irqnr);
			handle_IRQ(irqnr, regs);
		}
	} while (irqnr);
}

asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
{
	void __iomem *base_addr = OMAP2_IRQ_BASE;
	omap_intc_handle_irq(base_addr, regs);
}

int __init intc_of_init(struct device_node *node,
			     struct device_node *parent)
{
	struct resource res;
	u32 nr_irq = 96;

	if (WARN_ON(!node))
		return -ENODEV;

	if (of_address_to_resource(node, 0, &res)) {
		WARN(1, "unable to get intc registers\n");
		return -EINVAL;
	}

	if (of_property_read_u32(node, "ti,intc-size", &nr_irq))
		pr_warn("unable to get intc-size, default to %d\n", nr_irq);

	omap_init_irq(res.start, nr_irq, of_node_get(node));

	return 0;
}

static struct of_device_id irq_match[] __initdata = {
	{ .compatible = "ti,omap2-intc", .data = intc_of_init, },
	{ }
};

void __init omap_intc_of_init(void)
{
	of_irq_init(irq_match);
}

#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];

void omap_intc_save_context(void)
{
	int ind = 0, i = 0;
	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
		struct omap_irq_bank *bank = irq_banks + ind;
		intc_context[ind].sysconfig =
			intc_bank_read_reg(bank, INTC_SYSCONFIG);
		intc_context[ind].protection =
			intc_bank_read_reg(bank, INTC_PROTECTION);
		intc_context[ind].idle =
			intc_bank_read_reg(bank, INTC_IDLE);
		intc_context[ind].threshold =
			intc_bank_read_reg(bank, INTC_THRESHOLD);
		for (i = 0; i < INTCPS_NR_IRQS; i++)
			intc_context[ind].ilr[i] =
				intc_bank_read_reg(bank, (0x100 + 0x4*i));
		for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
			intc_context[ind].mir[i] =
				intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
				(0x20 * i));
	}
}

void omap_intc_restore_context(void)
{
	int ind = 0, i = 0;

	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
		struct omap_irq_bank *bank = irq_banks + ind;
		intc_bank_write_reg(intc_context[ind].sysconfig,
					bank, INTC_SYSCONFIG);
		intc_bank_write_reg(intc_context[ind].sysconfig,
					bank, INTC_SYSCONFIG);
		intc_bank_write_reg(intc_context[ind].protection,
					bank, INTC_PROTECTION);
		intc_bank_write_reg(intc_context[ind].idle,
					bank, INTC_IDLE);
		intc_bank_write_reg(intc_context[ind].threshold,
					bank, INTC_THRESHOLD);
		for (i = 0; i < INTCPS_NR_IRQS; i++)
			intc_bank_write_reg(intc_context[ind].ilr[i],
				bank, (0x100 + 0x4*i));
		for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
			intc_bank_write_reg(intc_context[ind].mir[i],
				 &irq_banks[0], INTC_MIR0 + (0x20 * i));
	}
	/* MIRs are saved and restore with other PRCM registers */
}

void omap3_intc_suspend(void)
{
	/* A pending interrupt would prevent OMAP from entering suspend */
	omap_ack_irq(NULL);
}

void omap3_intc_prepare_idle(void)
{
	/*
	 * Disable autoidle as it can stall interrupt controller,
	 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
	 */
	intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
}

void omap3_intc_resume_idle(void)
{
	/* Re-enable autoidle */
	intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
}

asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
{
	void __iomem *base_addr = OMAP3_IRQ_BASE;
	omap_intc_handle_irq(base_addr, regs);
}
#endif /* CONFIG_ARCH_OMAP3 */
Commit	Line	Data
1dbae815	1	/*
f30c2269	2	* linux/arch/arm/mach-omap2/irq.c
1dbae815 TL	3	*
	4	* Interrupt handler for OMAP2 boards.
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
	7	* Author: Paul Mundt <paul.mundt@nokia.com>
	8	*
	9	* This file is subject to the terms and conditions of the GNU General Public
	10	* License. See the file "COPYING" in the main directory of this archive
	11	* for more details.
	12	*/
	13	#include <linux/kernel.h>
52fa2120	14	#include <linux/module.h>
1dbae815	15	#include <linux/init.h>
1dbae815	16	#include <linux/interrupt.h>
2e7509e5	17	#include <linux/io.h>
ee0839c2	18
2db14997	19	#include <asm/exception.h>
1dbae815	20	#include <asm/mach/irq.h>
52fa2120 BC	21	#include <linux/irqdomain.h>
	22	#include <linux/of.h>
	23	#include <linux/of_address.h>
c4082d49	24	#include <linux/of_irq.h>
1dbae815	25
dbc04161	26	#include "soc.h"
ee0839c2	27	#include "iomap.h"
e2ed89fc	28	#include "common.h"
2e7509e5 PW	29
	30	/* selected INTC register offsets */
	31
	32	#define INTC_REVISION 0x0000
	33	#define INTC_SYSCONFIG 0x0010
	34	#define INTC_SYSSTATUS 0x0014
6ccc4c0d	35	#define INTC_SIR 0x0040
2e7509e5	36	#define INTC_CONTROL 0x0048
0addd61b RN	37	#define INTC_PROTECTION 0x004C
	38	#define INTC_IDLE 0x0050
	39	#define INTC_THRESHOLD 0x0068
	40	#define INTC_MIR0 0x0084
2e7509e5 PW	41	#define INTC_MIR_CLEAR0 0x0088
	42	#define INTC_MIR_SET0 0x008c
	43	#define INTC_PENDING_IRQ0 0x0098
2e7509e5 PW	44	/* Number of IRQ state bits in each MIR register */
2e7509e5 PW	45	#define IRQ_BITS_PER_REG 32
1dbae815	46
2db14997 MZ	47	#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
	48	#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
	49	#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */
	50	#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
3003ce3e TL	51	#define INTCPS_NR_MIR_REGS 3
3003ce3e TL	52	#define INTCPS_NR_IRQS 96
2db14997	53
1dbae815 TL	54	/*
	55	* OMAP2 has a number of different interrupt controllers, each interrupt
	56	* controller is identified as its own "bank". Register definitions are
	57	* fairly consistent for each bank, but not all registers are implemented
	58	* for each bank.. when in doubt, consult the TRM.
	59	*/
	60	static struct omap_irq_bank {
e8a91c95	61	void __iomem *base_reg;
1dbae815 TL	62	unsigned int nr_irqs;
	63	} __attribute__ ((aligned(4))) irq_banks[] = {
	64	{
	65	/* MPU INTC */
1dbae815	66	.nr_irqs = 96,
646e3ed1	67	},
1dbae815 TL	68	};
1dbae815 TL	69
52fa2120 BC	70	static struct irq_domain *domain;
52fa2120 BC	71
0addd61b RN	72	/* Structure to save interrupt controller context */
	73	struct omap3_intc_regs {
	74	u32 sysconfig;
	75	u32 protection;
	76	u32 idle;
	77	u32 threshold;
	78	u32 ilr[INTCPS_NR_IRQS];
	79	u32 mir[INTCPS_NR_MIR_REGS];
	80	};
	81
2e7509e5 PW	82	/* INTC bank register get/set */
	83
	84	static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
	85	{
	86	__raw_writel(val, bank->base_reg + reg);
	87	}
	88
	89	static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
	90	{
	91	return __raw_readl(bank->base_reg + reg);
	92	}
	93
1dbae815	94	/* XXX: FIQ and additional INTC support (only MPU at the moment) */
df303477	95	static void omap_ack_irq(struct irq_data *d)
1dbae815	96	{
2e7509e5	97	intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
1dbae815 TL	98	}
1dbae815 TL	99
df303477	100	static void omap_mask_ack_irq(struct irq_data *d)
1dbae815	101	{
667a11fa	102	irq_gc_mask_disable_reg(d);
df303477	103	omap_ack_irq(d);
1dbae815 TL	104	}
1dbae815 TL	105
1dbae815 TL	106	static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
	107	{
	108	unsigned long tmp;
	109
2e7509e5	110	tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
7852ec05 PW	111	pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
7852ec05 PW	112	bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
1dbae815	113
2e7509e5	114	tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
1dbae815	115	tmp \|= 1 << 1; /* soft reset */
2e7509e5	116	intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
1dbae815	117
2e7509e5	118	while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
1dbae815	119	/* Wait for reset to complete */;
375e12ab JY	120
375e12ab JY	121	/* Enable autoidle */
2e7509e5	122	intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
1dbae815 TL	123	}
1dbae815 TL	124
94434535 JH	125	int omap_irq_pending(void)
	126	{
	127	int i;
	128
	129	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
	130	struct omap_irq_bank *bank = irq_banks + i;
	131	int irq;
	132
	133	for (irq = 0; irq < bank->nr_irqs; irq += 32)
	134	if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
	135	((irq >> 5) << 5)))
	136	return 1;
	137	}
	138	return 0;
	139	}
	140
667a11fa TL	141	static __init void
	142	omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
	143	{
	144	struct irq_chip_generic *gc;
	145	struct irq_chip_type *ct;
	146
	147	gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
	148	handle_level_irq);
	149	ct = gc->chip_types;
	150	ct->chip.irq_ack = omap_mask_ack_irq;
	151	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	152	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
e3c83c2d	153	ct->chip.flags \|= IRQCHIP_SKIP_SET_WAKE;
667a11fa	154
667a11fa TL	155	ct->regs.enable = INTC_MIR_CLEAR0;
	156	ct->regs.disable = INTC_MIR_SET0;
	157	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
	158	IRQ_NOREQUEST \| IRQ_NOPROBE, 0);
	159	}
	160
52fa2120 BC	161	static void __init omap_init_irq(u32 base, int nr_irqs,
52fa2120 BC	162	struct device_node *node)
1dbae815	163	{
ab65be26	164	void __iomem *omap_irq_base;
4b1135a2	165	unsigned long nr_of_irqs = 0;
1dbae815	166	unsigned int nr_banks = 0;
52fa2120	167	int i, j, irq_base;
1dbae815	168
741e3a89 TL	169	omap_irq_base = ioremap(base, SZ_4K);
	170	if (WARN_ON(!omap_irq_base))
	171	return;
	172
52fa2120 BC	173	irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
	174	if (irq_base < 0) {
	175	pr_warn("Couldn't allocate IRQ numbers\n");
	176	irq_base = 0;
	177	}
	178
	179	domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
	180	&irq_domain_simple_ops, NULL);
	181
1dbae815 TL	182	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
	183	struct omap_irq_bank *bank = irq_banks + i;
	184
741e3a89	185	bank->nr_irqs = nr_irqs;
01001712	186
1b26fe86 TL	187	/* Static mapping, never released */
	188	bank->base_reg = ioremap(base, SZ_4K);
	189	if (!bank->base_reg) {
52fa2120	190	pr_err("Could not ioremap irq bank%i\n", i);
1b26fe86 TL	191	continue;
1b26fe86 TL	192	}
2e7509e5	193
1dbae815 TL	194	omap_irq_bank_init_one(bank);
1dbae815 TL	195
5c30cdfa	196	for (j = 0; j < bank->nr_irqs; j += 32)
52fa2120	197	omap_alloc_gc(bank->base_reg + j, j + irq_base, 32);
667a11fa	198
4b1135a2	199	nr_of_irqs += bank->nr_irqs;
1dbae815 TL	200	nr_banks++;
	201	}
	202
52fa2120 BC	203	pr_info("Total of %ld interrupts on %d active controller%s\n",
52fa2120 BC	204	nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
1dbae815 TL	205	}
1dbae815 TL	206
741e3a89 TL	207	void __init omap2_init_irq(void)
741e3a89 TL	208	{
52fa2120	209	omap_init_irq(OMAP24XX_IC_BASE, 96, NULL);
741e3a89 TL	210	}
	211
	212	void __init omap3_init_irq(void)
	213	{
52fa2120	214	omap_init_irq(OMAP34XX_IC_BASE, 96, NULL);
741e3a89 TL	215	}
741e3a89 TL	216
a920360f	217	void __init ti81xx_init_irq(void)
741e3a89	218	{
52fa2120	219	omap_init_irq(OMAP34XX_IC_BASE, 128, NULL);
741e3a89 TL	220	}
741e3a89 TL	221
2db14997 MZ	222	static inline void omap_intc_handle_irq(void __iomem base_addr, struct pt_regs regs)
	223	{
	224	u32 irqnr;
	225
	226	do {
	227	irqnr = readl_relaxed(base_addr + 0x98);
	228	if (irqnr)
	229	goto out;
	230
	231	irqnr = readl_relaxed(base_addr + 0xb8);
	232	if (irqnr)
	233	goto out;
	234
	235	irqnr = readl_relaxed(base_addr + 0xd8);
0bebda68	236	#if IS_ENABLED(CONFIG_SOC_TI81XX) \|\| IS_ENABLED(CONFIG_SOC_AM33XX)
2db14997 MZ	237	if (irqnr)
	238	goto out;
	239	irqnr = readl_relaxed(base_addr + 0xf8);
	240	#endif
	241
	242	out:
	243	if (!irqnr)
	244	break;
	245
	246	irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
	247	irqnr &= ACTIVEIRQ_MASK;
	248
52fa2120 BC	249	if (irqnr) {
52fa2120 BC	250	irqnr = irq_find_mapping(domain, irqnr);
2db14997	251	handle_IRQ(irqnr, regs);
52fa2120	252	}
2db14997 MZ	253	} while (irqnr);
	254	}
	255
	256	asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
	257	{
	258	void __iomem *base_addr = OMAP2_IRQ_BASE;
	259	omap_intc_handle_irq(base_addr, regs);
	260	}
	261
c4082d49	262	int __init intc_of_init(struct device_node *node,
52fa2120 BC	263	struct device_node *parent)
	264	{
	265	struct resource res;
b56f2cb7	266	u32 nr_irq = 96;
52fa2120 BC	267
	268	if (WARN_ON(!node))
	269	return -ENODEV;
	270
	271	if (of_address_to_resource(node, 0, &res)) {
	272	WARN(1, "unable to get intc registers\n");
	273	return -EINVAL;
	274	}
	275
b56f2cb7 V	276	if (of_property_read_u32(node, "ti,intc-size", &nr_irq))
b56f2cb7 V	277	pr_warn("unable to get intc-size, default to %d\n", nr_irq);
52fa2120	278
b56f2cb7	279	omap_init_irq(res.start, nr_irq, of_node_get(node));
52fa2120 BC	280
	281	return 0;
	282	}
	283
c4082d49 S	284	static struct of_device_id irq_match[] __initdata = {
	285	{ .compatible = "ti,omap2-intc", .data = intc_of_init, },
	286	{ }
	287	};
	288
	289	void __init omap_intc_of_init(void)
	290	{
	291	of_irq_init(irq_match);
	292	}
	293
08f30989	294	#if defined(CONFIG_ARCH_OMAP3) \|\| defined(CONFIG_SOC_AM33XX)
ee23b93d FB	295	static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
ee23b93d FB	296
0addd61b RN	297	void omap_intc_save_context(void)
	298	{
	299	int ind = 0, i = 0;
	300	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
	301	struct omap_irq_bank *bank = irq_banks + ind;
	302	intc_context[ind].sysconfig =
	303	intc_bank_read_reg(bank, INTC_SYSCONFIG);
	304	intc_context[ind].protection =
	305	intc_bank_read_reg(bank, INTC_PROTECTION);
	306	intc_context[ind].idle =
	307	intc_bank_read_reg(bank, INTC_IDLE);
	308	intc_context[ind].threshold =
	309	intc_bank_read_reg(bank, INTC_THRESHOLD);
	310	for (i = 0; i < INTCPS_NR_IRQS; i++)
	311	intc_context[ind].ilr[i] =
2329e7cc	312	intc_bank_read_reg(bank, (0x100 + 0x4*i));
0addd61b RN	313	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
	314	intc_context[ind].mir[i] =
	315	intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
	316	(0x20 * i));
	317	}
	318	}
	319
	320	void omap_intc_restore_context(void)
	321	{
	322	int ind = 0, i = 0;
	323
	324	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
	325	struct omap_irq_bank *bank = irq_banks + ind;
	326	intc_bank_write_reg(intc_context[ind].sysconfig,
	327	bank, INTC_SYSCONFIG);
	328	intc_bank_write_reg(intc_context[ind].sysconfig,
	329	bank, INTC_SYSCONFIG);
	330	intc_bank_write_reg(intc_context[ind].protection,
	331	bank, INTC_PROTECTION);
	332	intc_bank_write_reg(intc_context[ind].idle,
	333	bank, INTC_IDLE);
	334	intc_bank_write_reg(intc_context[ind].threshold,
	335	bank, INTC_THRESHOLD);
	336	for (i = 0; i < INTCPS_NR_IRQS; i++)
	337	intc_bank_write_reg(intc_context[ind].ilr[i],
2329e7cc	338	bank, (0x100 + 0x4*i));
0addd61b RN	339	for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
	340	intc_bank_write_reg(intc_context[ind].mir[i],
	341	&irq_banks[0], INTC_MIR0 + (0x20 * i));
	342	}
	343	/* MIRs are saved and restore with other PRCM registers */
	344	}
2bbe3af3 TK	345
	346	void omap3_intc_suspend(void)
	347	{
	348	/* A pending interrupt would prevent OMAP from entering suspend */
a7022d60	349	omap_ack_irq(NULL);
2bbe3af3	350	}
f18cc2ff TK	351
	352	void omap3_intc_prepare_idle(void)
	353	{
447b8da5 JP	354	/*
	355	* Disable autoidle as it can stall interrupt controller,
	356	* cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
	357	*/
f18cc2ff TK	358	intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
	359	}
	360
	361	void omap3_intc_resume_idle(void)
	362	{
	363	/* Re-enable autoidle */
	364	intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
	365	}
2db14997 MZ	366
	367	asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
	368	{
	369	void __iomem *base_addr = OMAP3_IRQ_BASE;
	370	omap_intc_handle_irq(base_addr, regs);
	371	}
0addd61b	372	#endif /* CONFIG_ARCH_OMAP3 */