[deliverable/linux.git] / arch / arm / mach-omap2 / mailbox.c

/*
 * Mailbox reservation modules for OMAP2/3
 *
 * Copyright (C) 2006-2009 Nokia Corporation
 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
 *        and  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <mach/mailbox.h>
#include <mach/irqs.h>

#define MAILBOX_REVISION		0x000
#define MAILBOX_SYSCONFIG		0x010
#define MAILBOX_SYSSTATUS		0x014
#define MAILBOX_MESSAGE(m)		(0x040 + 4 * (m))
#define MAILBOX_FIFOSTATUS(m)		(0x080 + 4 * (m))
#define MAILBOX_MSGSTATUS(m)		(0x0c0 + 4 * (m))
#define MAILBOX_IRQSTATUS(u)		(0x100 + 8 * (u))
#define MAILBOX_IRQENABLE(u)		(0x104 + 8 * (u))

#define MAILBOX_IRQ_NEWMSG(u)		(1 << (2 * (u)))
#define MAILBOX_IRQ_NOTFULL(u)		(1 << (2 * (u) + 1))

#define MBOX_REG_SIZE			0x120
#define MBOX_NR_REGS			(MBOX_REG_SIZE / sizeof(u32))

static void __iomem *mbox_base;

struct omap_mbox2_fifo {
	unsigned long msg;
	unsigned long fifo_stat;
	unsigned long msg_stat;
};

struct omap_mbox2_priv {
	struct omap_mbox2_fifo tx_fifo;
	struct omap_mbox2_fifo rx_fifo;
	unsigned long irqenable;
	unsigned long irqstatus;
	u32 newmsg_bit;
	u32 notfull_bit;
	u32 ctx[MBOX_NR_REGS];
};

static struct clk *mbox_ick_handle;

static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
				  omap_mbox_type_t irq);

static inline unsigned int mbox_read_reg(size_t ofs)
{
	return __raw_readl(mbox_base + ofs);
}

static inline void mbox_write_reg(u32 val, size_t ofs)
{
	__raw_writel(val, mbox_base + ofs);
}

/* Mailbox H/W preparations */
static int omap2_mbox_startup(struct omap_mbox *mbox)
{
	unsigned int l;

	mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
	if (IS_ERR(mbox_ick_handle)) {
		printk("Could not get mailboxes_ick\n");
		return -ENODEV;
	}
	clk_enable(mbox_ick_handle);

	l = mbox_read_reg(MAILBOX_REVISION);
	pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));

	/* set smart-idle & autoidle */
	l = mbox_read_reg(MAILBOX_SYSCONFIG);
	l |= 0x00000011;
	mbox_write_reg(l, MAILBOX_SYSCONFIG);

	omap2_mbox_enable_irq(mbox, IRQ_RX);

	return 0;
}

static void omap2_mbox_shutdown(struct omap_mbox *mbox)
{
	clk_disable(mbox_ick_handle);
	clk_put(mbox_ick_handle);
}

/* Mailbox FIFO handle functions */
static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	return (mbox_msg_t) mbox_read_reg(fifo->msg);
}

static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	mbox_write_reg(msg, fifo->msg);
}

static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	return (mbox_read_reg(fifo->msg_stat) == 0);
}

static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	return (mbox_read_reg(fifo->fifo_stat));
}

/* Mailbox IRQ handle functions */
static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
		omap_mbox_type_t irq)
{
	struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
	u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;

	l = mbox_read_reg(p->irqenable);
	l |= bit;
	mbox_write_reg(l, p->irqenable);
}

static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
		omap_mbox_type_t irq)
{
	struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
	u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;

	l = mbox_read_reg(p->irqenable);
	l &= ~bit;
	mbox_write_reg(l, p->irqenable);
}

static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
		omap_mbox_type_t irq)
{
	struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;

	mbox_write_reg(bit, p->irqstatus);
}

static int omap2_mbox_is_irq(struct omap_mbox *mbox,
		omap_mbox_type_t irq)
{
	struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	u32 enable = mbox_read_reg(p->irqenable);
	u32 status = mbox_read_reg(p->irqstatus);

	return (enable & status & bit);
}

static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
{
	int i;
	struct omap_mbox2_priv *p = mbox->priv;

	for (i = 0; i < MBOX_NR_REGS; i++) {
		p->ctx[i] = mbox_read_reg(i * sizeof(u32));

		dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
			i, p->ctx[i]);
	}
}

static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
{
	int i;
	struct omap_mbox2_priv *p = mbox->priv;

	for (i = 0; i < MBOX_NR_REGS; i++) {
		mbox_write_reg(p->ctx[i], i * sizeof(u32));

		dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
			i, p->ctx[i]);
	}
}

static struct omap_mbox_ops omap2_mbox_ops = {
	.type		= OMAP_MBOX_TYPE2,
	.startup	= omap2_mbox_startup,
	.shutdown	= omap2_mbox_shutdown,
	.fifo_read	= omap2_mbox_fifo_read,
	.fifo_write	= omap2_mbox_fifo_write,
	.fifo_empty	= omap2_mbox_fifo_empty,
	.fifo_full	= omap2_mbox_fifo_full,
	.enable_irq	= omap2_mbox_enable_irq,
	.disable_irq	= omap2_mbox_disable_irq,
	.ack_irq	= omap2_mbox_ack_irq,
	.is_irq		= omap2_mbox_is_irq,
	.save_ctx	= omap2_mbox_save_ctx,
	.restore_ctx	= omap2_mbox_restore_ctx,
};

/*
 * MAILBOX 0: ARM -> DSP,
 * MAILBOX 1: ARM <- DSP.
 * MAILBOX 2: ARM -> IVA,
 * MAILBOX 3: ARM <- IVA.
 */

/* FIXME: the following structs should be filled automatically by the user id */

/* DSP */
static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
	.tx_fifo = {
		.msg		= MAILBOX_MESSAGE(0),
		.fifo_stat	= MAILBOX_FIFOSTATUS(0),
	},
	.rx_fifo = {
		.msg		= MAILBOX_MESSAGE(1),
		.msg_stat	= MAILBOX_MSGSTATUS(1),
	},
	.irqenable	= MAILBOX_IRQENABLE(0),
	.irqstatus	= MAILBOX_IRQSTATUS(0),
	.notfull_bit	= MAILBOX_IRQ_NOTFULL(0),
	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(1),
};

struct omap_mbox mbox_dsp_info = {
	.name	= "dsp",
	.ops	= &omap2_mbox_ops,
	.priv	= &omap2_mbox_dsp_priv,
};
EXPORT_SYMBOL(mbox_dsp_info);

#if defined(CONFIG_ARCH_OMAP2420) /* IVA */
static struct omap_mbox2_priv omap2_mbox_iva_priv = {
	.tx_fifo = {
		.msg		= MAILBOX_MESSAGE(2),
		.fifo_stat	= MAILBOX_FIFOSTATUS(2),
	},
	.rx_fifo = {
		.msg		= MAILBOX_MESSAGE(3),
		.msg_stat	= MAILBOX_MSGSTATUS(3),
	},
	.irqenable	= MAILBOX_IRQENABLE(3),
	.irqstatus	= MAILBOX_IRQSTATUS(3),
	.notfull_bit	= MAILBOX_IRQ_NOTFULL(2),
	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(3),
};

static struct omap_mbox mbox_iva_info = {
	.name	= "iva",
	.ops	= &omap2_mbox_ops,
	.priv	= &omap2_mbox_iva_priv,
};
#endif

static int __devinit omap2_mbox_probe(struct platform_device *pdev)
{
	struct resource *res;
	int ret;

	/* MBOX base */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (unlikely(!res)) {
		dev_err(&pdev->dev, "invalid mem resource\n");
		return -ENODEV;
	}
	mbox_base = ioremap(res->start, res->end - res->start);
	if (!mbox_base)
		return -ENOMEM;

	/* DSP or IVA2 IRQ */
	mbox_dsp_info.irq = platform_get_irq(pdev, 0);
	if (mbox_dsp_info.irq < 0) {
		dev_err(&pdev->dev, "invalid irq resource\n");
		ret = -ENODEV;
		goto err_dsp;
	}

	ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info);
	if (ret)
		goto err_dsp;

#if defined(CONFIG_ARCH_OMAP2420) /* IVA */
	if (cpu_is_omap2420()) {
		/* IVA IRQ */
		res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
		if (unlikely(!res)) {
			dev_err(&pdev->dev, "invalid irq resource\n");
			ret = -ENODEV;
			goto err_iva1;
		}
		mbox_iva_info.irq = res->start;
		ret = omap_mbox_register(&pdev->dev, &mbox_iva_info);
		if (ret)
			goto err_iva1;
	}
#endif
	return 0;

err_iva1:
	omap_mbox_unregister(&mbox_dsp_info);
err_dsp:
	iounmap(mbox_base);
	return ret;
}

static int __devexit omap2_mbox_remove(struct platform_device *pdev)
{
#if defined(CONFIG_ARCH_OMAP2420)
	omap_mbox_unregister(&mbox_iva_info);
#endif
	omap_mbox_unregister(&mbox_dsp_info);
	iounmap(mbox_base);
	return 0;
}

static struct platform_driver omap2_mbox_driver = {
	.probe = omap2_mbox_probe,
	.remove = __devexit_p(omap2_mbox_remove),
	.driver = {
		.name = "omap2-mailbox",
	},
};

static int __init omap2_mbox_init(void)
{
	return platform_driver_register(&omap2_mbox_driver);
}

static void __exit omap2_mbox_exit(void)
{
	platform_driver_unregister(&omap2_mbox_driver);
}

module_init(omap2_mbox_init);
module_exit(omap2_mbox_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("omap mailbox: omap2/3 architecture specific functions");
MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, Paul Mundt");
MODULE_ALIAS("platform:omap2-mailbox");
Commit	Line	Data
340a614a	1	/*
733ecc5c	2	* Mailbox reservation modules for OMAP2/3
340a614a	3	*
733ecc5c	4	* Copyright (C) 2006-2009 Nokia Corporation
340a614a	5	* Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
733ecc5c	6	* and Paul Mundt
340a614a HD	7	*
	8	* This file is subject to the terms and conditions of the GNU General Public
	9	* License. See the file "COPYING" in the main directory of this archive
	10	* for more details.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/clk.h>
	15	#include <linux/err.h>
	16	#include <linux/platform_device.h>
fced80c7	17	#include <linux/io.h>
a09e64fb RK	18	#include <mach/mailbox.h>
a09e64fb RK	19	#include <mach/irqs.h>
340a614a	20
733ecc5c HD	21	#define MAILBOX_REVISION 0x000
	22	#define MAILBOX_SYSCONFIG 0x010
	23	#define MAILBOX_SYSSTATUS 0x014
	24	#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
	25	#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
	26	#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
	27	#define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
	28	#define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
340a614a	29
733ecc5c HD	30	#define MAILBOX_IRQ_NEWMSG(u) (1 << (2 * (u)))
733ecc5c HD	31	#define MAILBOX_IRQ_NOTFULL(u) (1 << (2 * (u) + 1))
340a614a	32
c75ee752 HD	33	#define MBOX_REG_SIZE 0x120
	34	#define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
	35
6c20a683	36	static void __iomem *mbox_base;
340a614a HD	37
	38	struct omap_mbox2_fifo {
	39	unsigned long msg;
	40	unsigned long fifo_stat;
	41	unsigned long msg_stat;
	42	};
	43
	44	struct omap_mbox2_priv {
	45	struct omap_mbox2_fifo tx_fifo;
	46	struct omap_mbox2_fifo rx_fifo;
	47	unsigned long irqenable;
	48	unsigned long irqstatus;
	49	u32 newmsg_bit;
	50	u32 notfull_bit;
c75ee752	51	u32 ctx[MBOX_NR_REGS];
340a614a HD	52	};
	53
	54	static struct clk *mbox_ick_handle;
	55
bfbdcf8a HD	56	static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
	57	omap_mbox_type_t irq);
	58
6c20a683	59	static inline unsigned int mbox_read_reg(size_t ofs)
340a614a	60	{
6c20a683	61	return __raw_readl(mbox_base + ofs);
340a614a HD	62	}
340a614a HD	63
6c20a683	64	static inline void mbox_write_reg(u32 val, size_t ofs)
340a614a	65	{
6c20a683	66	__raw_writel(val, mbox_base + ofs);
340a614a HD	67	}
	68
	69	/* Mailbox H/W preparations */
bfbdcf8a	70	static int omap2_mbox_startup(struct omap_mbox *mbox)
340a614a HD	71	{
	72	unsigned int l;
	73
	74	mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
	75	if (IS_ERR(mbox_ick_handle)) {
	76	printk("Could not get mailboxes_ick\n");
	77	return -ENODEV;
	78	}
	79	clk_enable(mbox_ick_handle);
	80
94fc58c6 HD	81	l = mbox_read_reg(MAILBOX_REVISION);
	82	pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
	83
340a614a HD	84	/* set smart-idle & autoidle */
	85	l = mbox_read_reg(MAILBOX_SYSCONFIG);
	86	l \|= 0x00000011;
	87	mbox_write_reg(l, MAILBOX_SYSCONFIG);
	88
bfbdcf8a HD	89	omap2_mbox_enable_irq(mbox, IRQ_RX);
bfbdcf8a HD	90
340a614a HD	91	return 0;
	92	}
	93
bfbdcf8a	94	static void omap2_mbox_shutdown(struct omap_mbox *mbox)
340a614a HD	95	{
	96	clk_disable(mbox_ick_handle);
	97	clk_put(mbox_ick_handle);
	98	}
	99
	100	/* Mailbox FIFO handle functions */
bfbdcf8a	101	static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
340a614a HD	102	{
	103	struct omap_mbox2_fifo *fifo =
	104	&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	105	return (mbox_msg_t) mbox_read_reg(fifo->msg);
	106	}
	107
bfbdcf8a	108	static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
340a614a HD	109	{
	110	struct omap_mbox2_fifo *fifo =
	111	&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	112	mbox_write_reg(msg, fifo->msg);
	113	}
	114
bfbdcf8a	115	static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
340a614a HD	116	{
	117	struct omap_mbox2_fifo *fifo =
	118	&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	119	return (mbox_read_reg(fifo->msg_stat) == 0);
	120	}
	121
bfbdcf8a	122	static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
340a614a HD	123	{
	124	struct omap_mbox2_fifo *fifo =
	125	&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	126	return (mbox_read_reg(fifo->fifo_stat));
	127	}
	128
	129	/* Mailbox IRQ handle functions */
bfbdcf8a	130	static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
340a614a HD	131	omap_mbox_type_t irq)
	132	{
	133	struct omap_mbox2_priv p = (struct omap_mbox2_priv )mbox->priv;
	134	u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	135
	136	l = mbox_read_reg(p->irqenable);
	137	l \|= bit;
	138	mbox_write_reg(l, p->irqenable);
	139	}
	140
bfbdcf8a	141	static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
340a614a HD	142	omap_mbox_type_t irq)
	143	{
	144	struct omap_mbox2_priv p = (struct omap_mbox2_priv )mbox->priv;
	145	u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	146
	147	l = mbox_read_reg(p->irqenable);
	148	l &= ~bit;
	149	mbox_write_reg(l, p->irqenable);
	150	}
	151
bfbdcf8a	152	static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
340a614a HD	153	omap_mbox_type_t irq)
	154	{
	155	struct omap_mbox2_priv p = (struct omap_mbox2_priv )mbox->priv;
	156	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	157
	158	mbox_write_reg(bit, p->irqstatus);
	159	}
	160
bfbdcf8a	161	static int omap2_mbox_is_irq(struct omap_mbox *mbox,
340a614a HD	162	omap_mbox_type_t irq)
	163	{
	164	struct omap_mbox2_priv p = (struct omap_mbox2_priv )mbox->priv;
	165	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	166	u32 enable = mbox_read_reg(p->irqenable);
	167	u32 status = mbox_read_reg(p->irqstatus);
	168
	169	return (enable & status & bit);
	170	}
	171
c75ee752 HD	172	static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
	173	{
	174	int i;
	175	struct omap_mbox2_priv *p = mbox->priv;
	176
	177	for (i = 0; i < MBOX_NR_REGS; i++) {
	178	p->ctx[i] = mbox_read_reg(i * sizeof(u32));
	179
	180	dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
	181	i, p->ctx[i]);
	182	}
	183	}
	184
	185	static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
	186	{
	187	int i;
	188	struct omap_mbox2_priv *p = mbox->priv;
	189
	190	for (i = 0; i < MBOX_NR_REGS; i++) {
	191	mbox_write_reg(p->ctx[i], i * sizeof(u32));
	192
	193	dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
	194	i, p->ctx[i]);
	195	}
	196	}
	197
340a614a HD	198	static struct omap_mbox_ops omap2_mbox_ops = {
	199	.type = OMAP_MBOX_TYPE2,
	200	.startup = omap2_mbox_startup,
	201	.shutdown = omap2_mbox_shutdown,
	202	.fifo_read = omap2_mbox_fifo_read,
	203	.fifo_write = omap2_mbox_fifo_write,
	204	.fifo_empty = omap2_mbox_fifo_empty,
	205	.fifo_full = omap2_mbox_fifo_full,
	206	.enable_irq = omap2_mbox_enable_irq,
	207	.disable_irq = omap2_mbox_disable_irq,
	208	.ack_irq = omap2_mbox_ack_irq,
	209	.is_irq = omap2_mbox_is_irq,
c75ee752 HD	210	.save_ctx = omap2_mbox_save_ctx,
c75ee752 HD	211	.restore_ctx = omap2_mbox_restore_ctx,
340a614a HD	212	};
	213
	214	/*
	215	* MAILBOX 0: ARM -> DSP,
	216	* MAILBOX 1: ARM <- DSP.
	217	* MAILBOX 2: ARM -> IVA,
	218	* MAILBOX 3: ARM <- IVA.
	219	*/
	220
	221	/* FIXME: the following structs should be filled automatically by the user id */
	222
	223	/* DSP */
	224	static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
	225	.tx_fifo = {
733ecc5c HD	226	.msg = MAILBOX_MESSAGE(0),
733ecc5c HD	227	.fifo_stat = MAILBOX_FIFOSTATUS(0),
340a614a HD	228	},
340a614a HD	229	.rx_fifo = {
733ecc5c HD	230	.msg = MAILBOX_MESSAGE(1),
733ecc5c HD	231	.msg_stat = MAILBOX_MSGSTATUS(1),
340a614a	232	},
733ecc5c HD	233	.irqenable = MAILBOX_IRQENABLE(0),
733ecc5c HD	234	.irqstatus = MAILBOX_IRQSTATUS(0),
340a614a HD	235	.notfull_bit = MAILBOX_IRQ_NOTFULL(0),
	236	.newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
	237	};
	238
	239	struct omap_mbox mbox_dsp_info = {
	240	.name = "dsp",
	241	.ops = &omap2_mbox_ops,
	242	.priv = &omap2_mbox_dsp_priv,
	243	};
	244	EXPORT_SYMBOL(mbox_dsp_info);
	245
6c20a683	246	#if defined(CONFIG_ARCH_OMAP2420) /* IVA */
340a614a HD	247	static struct omap_mbox2_priv omap2_mbox_iva_priv = {
340a614a HD	248	.tx_fifo = {
733ecc5c HD	249	.msg = MAILBOX_MESSAGE(2),
733ecc5c HD	250	.fifo_stat = MAILBOX_FIFOSTATUS(2),
340a614a HD	251	},
340a614a HD	252	.rx_fifo = {
733ecc5c HD	253	.msg = MAILBOX_MESSAGE(3),
733ecc5c HD	254	.msg_stat = MAILBOX_MSGSTATUS(3),
340a614a	255	},
733ecc5c HD	256	.irqenable = MAILBOX_IRQENABLE(3),
733ecc5c HD	257	.irqstatus = MAILBOX_IRQSTATUS(3),
340a614a HD	258	.notfull_bit = MAILBOX_IRQ_NOTFULL(2),
	259	.newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
	260	};
	261
	262	static struct omap_mbox mbox_iva_info = {
	263	.name = "iva",
	264	.ops = &omap2_mbox_ops,
	265	.priv = &omap2_mbox_iva_priv,
	266	};
6c20a683	267	#endif
340a614a	268
da8cfe03	269	static int __devinit omap2_mbox_probe(struct platform_device *pdev)
340a614a HD	270	{
340a614a HD	271	struct resource *res;
6c20a683	272	int ret;
340a614a HD	273
	274	/* MBOX base */
	275	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	276	if (unlikely(!res)) {
	277	dev_err(&pdev->dev, "invalid mem resource\n");
	278	return -ENODEV;
	279	}
6c20a683 HD	280	mbox_base = ioremap(res->start, res->end - res->start);
	281	if (!mbox_base)
	282	return -ENOMEM;
340a614a	283
6c20a683 HD	284	/* DSP or IVA2 IRQ */
	285	mbox_dsp_info.irq = platform_get_irq(pdev, 0);
	286	if (mbox_dsp_info.irq < 0) {
340a614a	287	dev_err(&pdev->dev, "invalid irq resource\n");
6c20a683 HD	288	ret = -ENODEV;
6c20a683 HD	289	goto err_dsp;
340a614a	290	}
340a614a	291
da8cfe03	292	ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info);
6c20a683 HD	293	if (ret)
	294	goto err_dsp;
	295
	296	#if defined(CONFIG_ARCH_OMAP2420) /* IVA */
	297	if (cpu_is_omap2420()) {
	298	/* IVA IRQ */
	299	res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
	300	if (unlikely(!res)) {
	301	dev_err(&pdev->dev, "invalid irq resource\n");
	302	ret = -ENODEV;
	303	goto err_iva1;
	304	}
	305	mbox_iva_info.irq = res->start;
da8cfe03	306	ret = omap_mbox_register(&pdev->dev, &mbox_iva_info);
6c20a683 HD	307	if (ret)
6c20a683 HD	308	goto err_iva1;
340a614a	309	}
6c20a683 HD	310	#endif
6c20a683 HD	311	return 0;
340a614a	312
6c20a683 HD	313	err_iva1:
	314	omap_mbox_unregister(&mbox_dsp_info);
	315	err_dsp:
	316	iounmap(mbox_base);
340a614a HD	317	return ret;
	318	}
	319
da8cfe03	320	static int __devexit omap2_mbox_remove(struct platform_device *pdev)
340a614a	321	{
6c20a683 HD	322	#if defined(CONFIG_ARCH_OMAP2420)
	323	omap_mbox_unregister(&mbox_iva_info);
	324	#endif
340a614a	325	omap_mbox_unregister(&mbox_dsp_info);
6c20a683	326	iounmap(mbox_base);
340a614a HD	327	return 0;
	328	}
	329
	330	static struct platform_driver omap2_mbox_driver = {
	331	.probe = omap2_mbox_probe,
da8cfe03	332	.remove = __devexit_p(omap2_mbox_remove),
340a614a	333	.driver = {
da8cfe03	334	.name = "omap2-mailbox",
340a614a HD	335	},
	336	};
	337
	338	static int __init omap2_mbox_init(void)
	339	{
	340	return platform_driver_register(&omap2_mbox_driver);
	341	}
	342
	343	static void __exit omap2_mbox_exit(void)
	344	{
	345	platform_driver_unregister(&omap2_mbox_driver);
	346	}
	347
	348	module_init(omap2_mbox_init);
	349	module_exit(omap2_mbox_exit);
	350
733ecc5c HD	351	MODULE_LICENSE("GPL v2");
	352	MODULE_DESCRIPTION("omap mailbox: omap2/3 architecture specific functions");
	353	MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, Paul Mundt");
da8cfe03	354	MODULE_ALIAS("platform:omap2-mailbox");