[deliverable/linux.git] / arch / arm / mach-omap2 / mcbsp.c

/*
 * linux/arch/arm/mach-omap2/mcbsp.c
 *
 * Copyright (C) 2008 Instituto Nokia de Tecnologia
 * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Multichannel mode not supported.
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/platform_data/asoc-ti-mcbsp.h>

#include <plat/dma.h>
#include <plat/omap_device.h>
#include <linux/pm_runtime.h>

#include "control.h"

/*
 * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
 * Sidetone needs non-gated ICLK and sidetone autoidle is broken.
 */
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"

/* McBSP1 internal signal muxing function for OMAP2/3 */
static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
				   const char *src)
{
	u32 v;

	v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);

	if (!strcmp(signal, "clkr")) {
		if (!strcmp(src, "clkr"))
			v &= ~OMAP2_MCBSP1_CLKR_MASK;
		else if (!strcmp(src, "clkx"))
			v |= OMAP2_MCBSP1_CLKR_MASK;
		else
			return -EINVAL;
	} else if (!strcmp(signal, "fsr")) {
		if (!strcmp(src, "fsr"))
			v &= ~OMAP2_MCBSP1_FSR_MASK;
		else if (!strcmp(src, "fsx"))
			v |= OMAP2_MCBSP1_FSR_MASK;
		else
			return -EINVAL;
	} else {
		return -EINVAL;
	}

	omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);

	return 0;
}

/* McBSP4 internal signal muxing function for OMAP4 */
#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX	(1 << 31)
#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX	(1 << 30)
static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal,
				   const char *src)
{
	u32 v;

	/*
	 * In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR
	 * mux) is used */
	v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);

	if (!strcmp(signal, "clkr")) {
		if (!strcmp(src, "clkr"))
			v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
		else if (!strcmp(src, "clkx"))
			v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
		else
			return -EINVAL;
	} else if (!strcmp(signal, "fsr")) {
		if (!strcmp(src, "fsr"))
			v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
		else if (!strcmp(src, "fsx"))
			v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
		else
			return -EINVAL;
	} else {
		return -EINVAL;
	}

	omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);

	return 0;
}

/* McBSP CLKS source switching function */
static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk,
				   const char *src)
{
	struct clk *fck_src;
	char *fck_src_name;
	int r;

	if (!strcmp(src, "clks_ext"))
		fck_src_name = "pad_fck";
	else if (!strcmp(src, "clks_fclk"))
		fck_src_name = "prcm_fck";
	else
		return -EINVAL;

	fck_src = clk_get(dev, fck_src_name);
	if (IS_ERR_OR_NULL(fck_src)) {
		pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks",
		       fck_src_name);
		return -EINVAL;
	}

	pm_runtime_put_sync(dev);

	r = clk_set_parent(clk, fck_src);
	if (IS_ERR_VALUE(r)) {
		pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n",
		       "clks", fck_src_name);
		clk_put(fck_src);
		return -EINVAL;
	}

	pm_runtime_get_sync(dev);

	clk_put(fck_src);

	return 0;
}

static int omap3_enable_st_clock(unsigned int id, bool enable)
{
	unsigned int w;

	/*
	 * Sidetone uses McBSP ICLK - which must not idle when sidetones
	 * are enabled or sidetones start sounding ugly.
	 */
	w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
	if (enable)
		w &= ~(1 << (id - 2));
	else
		w |= 1 << (id - 2);
	omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);

	return 0;
}

static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
{
	int id, count = 1;
	char *name = "omap-mcbsp";
	struct omap_hwmod *oh_device[2];
	struct omap_mcbsp_platform_data *pdata = NULL;
	struct platform_device *pdev;

	sscanf(oh->name, "mcbsp%d", &id);

	pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL);
	if (!pdata) {
		pr_err("%s: No memory for mcbsp\n", __func__);
		return -ENOMEM;
	}

	pdata->reg_step = 4;
	if (oh->class->rev < MCBSP_CONFIG_TYPE2) {
		pdata->reg_size = 2;
	} else {
		pdata->reg_size = 4;
		pdata->has_ccr = true;
	}
	pdata->set_clk_src = omap2_mcbsp_set_clk_src;

	/* On OMAP2/3 the McBSP1 port has 6 pin configuration */
	if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
		pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;

	/* On OMAP4 the McBSP4 port has 6 pin configuration */
	if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
		pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;

	if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
		if (id == 2)
			/* The FIFO has 1024 + 256 locations */
			pdata->buffer_size = 0x500;
		else
			/* The FIFO has 128 locations */
			pdata->buffer_size = 0x80;
	} else if (oh->class->rev == MCBSP_CONFIG_TYPE4) {
		/* The FIFO has 128 locations for all instances */
		pdata->buffer_size = 0x80;
	}

	if (oh->class->rev >= MCBSP_CONFIG_TYPE3)
		pdata->has_wakeup = true;

	oh_device[0] = oh;

	if (oh->dev_attr) {
		oh_device[1] = omap_hwmod_lookup((
		(struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
		pdata->enable_st_clock = omap3_enable_st_clock;
		count++;
	}
	pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
				sizeof(*pdata), NULL, 0, false);
	kfree(pdata);
	if (IS_ERR(pdev))  {
		pr_err("%s: Can't build omap_device for %s:%s.\n", __func__,
					name, oh->name);
		return PTR_ERR(pdev);
	}
	return 0;
}

static int __init omap2_mcbsp_init(void)
{
	omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);

	return 0;
}
arch_initcall(omap2_mcbsp_init);
Commit	Line	Data
78673bc8 EV	1	/*
	2	* linux/arch/arm/mach-omap2/mcbsp.c
	3	*
	4	* Copyright (C) 2008 Instituto Nokia de Tecnologia
	5	* Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* Multichannel mode not supported.
	12	*/
	13	#include <linux/module.h>
	14	#include <linux/init.h>
	15	#include <linux/clk.h>
	16	#include <linux/err.h>
	17	#include <linux/io.h>
	18	#include <linux/platform_device.h>
5a0e3ad6	19	#include <linux/slab.h>
2203747c	20	#include <linux/platform_data/asoc-ti-mcbsp.h>
78673bc8	21
ce491cf8	22	#include <plat/dma.h>
64bcbd33	23	#include <plat/omap_device.h>
e95496d4	24	#include <linux/pm_runtime.h>
4814ced5 PW	25
	26	#include "control.h"
	27
1743d14f JN	28	/*
	29	* FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
	30	* Sidetone needs non-gated ICLK and sidetone autoidle is broken.
	31	*/
	32	#include "cm2xxx_3xxx.h"
	33	#include "cm-regbits-34xx.h"
	34
40c0764b	35	/* McBSP1 internal signal muxing function for OMAP2/3 */
7bc0c4ba JN	36	static int omap2_mcbsp1_mux_rx_clk(struct device dev, const char signal,
7bc0c4ba JN	37	const char *src)
cf4c87ab PW	38	{
	39	u32 v;
	40
	41	v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
cf4c87ab	42
7bc0c4ba JN	43	if (!strcmp(signal, "clkr")) {
	44	if (!strcmp(src, "clkr"))
	45	v &= ~OMAP2_MCBSP1_CLKR_MASK;
	46	else if (!strcmp(src, "clkx"))
	47	v \|= OMAP2_MCBSP1_CLKR_MASK;
	48	else
	49	return -EINVAL;
	50	} else if (!strcmp(signal, "fsr")) {
	51	if (!strcmp(src, "fsr"))
	52	v &= ~OMAP2_MCBSP1_FSR_MASK;
	53	else if (!strcmp(src, "fsx"))
	54	v \|= OMAP2_MCBSP1_FSR_MASK;
	55	else
	56	return -EINVAL;
	57	} else {
	58	return -EINVAL;
	59	}
cf4c87ab	60
cf4c87ab	61	omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
7bc0c4ba JN	62
7bc0c4ba JN	63	return 0;
cf4c87ab	64	}
cf4c87ab	65
40c0764b PU	66	/* McBSP4 internal signal muxing function for OMAP4 */
	67	#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX (1 << 31)
	68	#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX (1 << 30)
	69	static int omap4_mcbsp4_mux_rx_clk(struct device dev, const char signal,
	70	const char *src)
	71	{
	72	u32 v;
	73
	74	/*
	75	* In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR
	76	* mux) is used */
	77	v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
	78
	79	if (!strcmp(signal, "clkr")) {
	80	if (!strcmp(src, "clkr"))
	81	v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
	82	else if (!strcmp(src, "clkx"))
	83	v \|= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
	84	else
	85	return -EINVAL;
	86	} else if (!strcmp(signal, "fsr")) {
	87	if (!strcmp(src, "fsr"))
	88	v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
	89	else if (!strcmp(src, "fsx"))
	90	v \|= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
	91	else
	92	return -EINVAL;
	93	} else {
	94	return -EINVAL;
	95	}
	96
	97	omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
	98
	99	return 0;
	100	}
	101
d1358657	102	/* McBSP CLKS source switching function */
09d28d2c JN	103	static int omap2_mcbsp_set_clk_src(struct device dev, struct clk clk,
09d28d2c JN	104	const char *src)
d1358657	105	{
d1358657 PW	106	struct clk *fck_src;
	107	char *fck_src_name;
	108	int r;
	109
09d28d2c	110	if (!strcmp(src, "clks_ext"))
d1358657	111	fck_src_name = "pad_fck";
09d28d2c	112	else if (!strcmp(src, "clks_fclk"))
d1358657 PW	113	fck_src_name = "prcm_fck";
	114	else
	115	return -EINVAL;
	116
09d28d2c	117	fck_src = clk_get(dev, fck_src_name);
d1358657 PW	118	if (IS_ERR_OR_NULL(fck_src)) {
	119	pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks",
	120	fck_src_name);
	121	return -EINVAL;
	122	}
	123
09d28d2c	124	pm_runtime_put_sync(dev);
d1358657	125
09d28d2c	126	r = clk_set_parent(clk, fck_src);
d1358657 PW	127	if (IS_ERR_VALUE(r)) {
	128	pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n",
	129	"clks", fck_src_name);
	130	clk_put(fck_src);
	131	return -EINVAL;
	132	}
	133
09d28d2c	134	pm_runtime_get_sync(dev);
d1358657 PW	135
	136	clk_put(fck_src);
	137
	138	return 0;
	139	}
d1358657	140
1743d14f JN	141	static int omap3_enable_st_clock(unsigned int id, bool enable)
	142	{
	143	unsigned int w;
	144
	145	/*
	146	* Sidetone uses McBSP ICLK - which must not idle when sidetones
	147	* are enabled or sidetones start sounding ugly.
	148	*/
	149	w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
	150	if (enable)
	151	w &= ~(1 << (id - 2));
	152	else
	153	w \|= 1 << (id - 2);
	154	omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
	155
	156	return 0;
	157	}
	158
9cf793f9	159	static int __init omap_init_mcbsp(struct omap_hwmod oh, void unused)
64bcbd33 KVA	160	{
	161	int id, count = 1;
	162	char *name = "omap-mcbsp";
	163	struct omap_hwmod *oh_device[2];
	164	struct omap_mcbsp_platform_data *pdata = NULL;
3528c58e	165	struct platform_device *pdev;
3cf32bba	166
64bcbd33	167	sscanf(oh->name, "mcbsp%d", &id);
78673bc8	168
64bcbd33 KVA	169	pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL);
	170	if (!pdata) {
	171	pr_err("%s: No memory for mcbsp\n", __func__);
	172	return -ENOMEM;
	173	}
3cf32bba	174
cdc71514	175	pdata->reg_step = 4;
88408230	176	if (oh->class->rev < MCBSP_CONFIG_TYPE2) {
cdc71514	177	pdata->reg_size = 2;
88408230	178	} else {
cdc71514	179	pdata->reg_size = 4;
88408230 JN	180	pdata->has_ccr = true;
88408230 JN	181	}
0c8551e5	182	pdata->set_clk_src = omap2_mcbsp_set_clk_src;
40c0764b PU	183
	184	/* On OMAP2/3 the McBSP1 port has 6 pin configuration */
	185	if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
0c8551e5	186	pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;
9504ba64	187
40c0764b PU	188	/* On OMAP4 the McBSP4 port has 6 pin configuration */
	189	if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
	190	pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;
	191
64bcbd33 KVA	192	if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
	193	if (id == 2)
	194	/* The FIFO has 1024 + 256 locations */
	195	pdata->buffer_size = 0x500;
	196	else
	197	/* The FIFO has 128 locations */
	198	pdata->buffer_size = 0x80;
da76250e PU	199	} else if (oh->class->rev == MCBSP_CONFIG_TYPE4) {
	200	/* The FIFO has 128 locations for all instances */
	201	pdata->buffer_size = 0x80;
64bcbd33	202	}
3cf32bba	203
1a645884 JN	204	if (oh->class->rev >= MCBSP_CONFIG_TYPE3)
	205	pdata->has_wakeup = true;
	206
64bcbd33	207	oh_device[0] = oh;
78673bc8	208
64bcbd33 KVA	209	if (oh->dev_attr) {
	210	oh_device[1] = omap_hwmod_lookup((
	211	(struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
1743d14f	212	pdata->enable_st_clock = omap3_enable_st_clock;
64bcbd33 KVA	213	count++;
64bcbd33 KVA	214	}
3528c58e	215	pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
f718e2c0	216	sizeof(*pdata), NULL, 0, false);
64bcbd33	217	kfree(pdata);
3528c58e	218	if (IS_ERR(pdev)) {
25985edc	219	pr_err("%s: Can't build omap_device for %s:%s.\n", __func__,
64bcbd33	220	name, oh->name);
3528c58e	221	return PTR_ERR(pdev);
64bcbd33	222	}
64bcbd33 KVA	223	return 0;
64bcbd33 KVA	224	}
a5b92cc3	225
b4b58f58	226	static int __init omap2_mcbsp_init(void)
78673bc8	227	{
64bcbd33	228	omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
b4b58f58	229
0210dc4e	230	return 0;
78673bc8 EV	231	}
78673bc8 EV	232	arch_initcall(omap2_mcbsp_init);