[deliverable/linux.git] / arch / arm / mach-omap2 / memory.c

/*
 * linux/arch/arm/mach-omap2/memory.c
 *
 * Memory timing related functions for OMAP24XX
 *
 * Copyright (C) 2005 Texas Instruments Inc.
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * Copyright (C) 2005 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/clk.h>

#include <asm/io.h>

#include <asm/arch/clock.h>
#include <asm/arch/sram.h>

#include "prm.h"

#include "memory.h"
#include "sdrc.h"

unsigned long omap2_sdrc_base;
unsigned long omap2_sms_base;

static struct memory_timings mem_timings;
static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;

u32 omap2_memory_get_slow_dll_ctrl(void)
{
	return mem_timings.slow_dll_ctrl;
}

u32 omap2_memory_get_fast_dll_ctrl(void)
{
	return mem_timings.fast_dll_ctrl;
}

u32 omap2_memory_get_type(void)
{
	return mem_timings.m_type;
}

void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
{
	unsigned long dll_cnt;
	u32 fast_dll = 0;

	mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */

	/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
	 * In the case of 2422, its ok to use CS1 instead of CS0.
	 */
	if (cpu_is_omap2422())
		mem_timings.base_cs = 1;
	else
		mem_timings.base_cs = 0;

	if (mem_timings.m_type != M_DDR)
		return;

	/* With DDR we need to determine the low frequency DLL value */
	if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
		mem_timings.dll_mode = M_UNLOCK;
	else
		mem_timings.dll_mode = M_LOCK;

	if (mem_timings.base_cs == 0) {
		fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
		dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
	} else {
		fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
		dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
	}
	if (force_lock_to_unlock_mode) {
		fast_dll &= ~0xff00;
		fast_dll |= dll_cnt;		/* Current lock mode */
	}
	/* set fast timings with DLL filter disabled */
	mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));

	/* No disruptions, DDR will be offline & C-ABI not followed */
	omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
			    mem_timings.fast_dll_ctrl,
			    mem_timings.base_cs,
			    force_lock_to_unlock_mode);
	mem_timings.slow_dll_ctrl &= 0xff00;	/* Keep lock value */

	/* Turn status into unlock ctrl */
	mem_timings.slow_dll_ctrl |=
		((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));

	/* 90 degree phase for anything below 133Mhz + disable DLL filter */
	mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
}

/* turn on smart idle modes for SDRAM scheduler and controller */
void __init omap2_init_memory(void)
{
	u32 l;

	l = sms_read_reg(SMS_SYSCONFIG);
	l &= ~(0x3 << 3);
	l |= (0x2 << 3);
	sms_write_reg(l, SMS_SYSCONFIG);

	l = sdrc_read_reg(SDRC_SYSCONFIG);
	l &= ~(0x3 << 3);
	l |= (0x2 << 3);
	sdrc_write_reg(l, SDRC_SYSCONFIG);
}
Commit	Line	Data
b824efae TL	1	/*
	2	* linux/arch/arm/mach-omap2/memory.c
	3	*
	4	* Memory timing related functions for OMAP24XX
	5	*
	6	* Copyright (C) 2005 Texas Instruments Inc.
	7	* Richard Woodruff <r-woodruff2@ti.com>
	8	*
	9	* Copyright (C) 2005 Nokia Corporation
	10	* Tony Lindgren <tony@atomide.com>
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*/
	16
b824efae TL	17	#include <linux/module.h>
	18	#include <linux/kernel.h>
	19	#include <linux/device.h>
	20	#include <linux/list.h>
	21	#include <linux/errno.h>
	22	#include <linux/delay.h>
	23	#include <linux/clk.h>
	24
	25	#include <asm/io.h>
	26
	27	#include <asm/arch/clock.h>
	28	#include <asm/arch/sram.h>
	29
44595982 PW	30	#include "prm.h"
44595982 PW	31
b824efae	32	#include "memory.h"
44595982	33	#include "sdrc.h"
b824efae	34
44595982 PW	35	unsigned long omap2_sdrc_base;
44595982 PW	36	unsigned long omap2_sms_base;
33c99075	37
b824efae	38	static struct memory_timings mem_timings;
44595982	39	static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
b824efae TL	40
	41	u32 omap2_memory_get_slow_dll_ctrl(void)
	42	{
	43	return mem_timings.slow_dll_ctrl;
	44	}
	45
	46	u32 omap2_memory_get_fast_dll_ctrl(void)
	47	{
	48	return mem_timings.fast_dll_ctrl;
	49	}
	50
	51	u32 omap2_memory_get_type(void)
	52	{
	53	return mem_timings.m_type;
	54	}
	55
	56	void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
	57	{
	58	unsigned long dll_cnt;
	59	u32 fast_dll = 0;
	60
44595982	61	mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
b824efae TL	62
	63	/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
	64	* In the case of 2422, its ok to use CS1 instead of CS0.
	65	*/
	66	if (cpu_is_omap2422())
	67	mem_timings.base_cs = 1;
	68	else
	69	mem_timings.base_cs = 0;
	70
	71	if (mem_timings.m_type != M_DDR)
	72	return;
	73
	74	/* With DDR we need to determine the low frequency DLL value */
	75	if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
	76	mem_timings.dll_mode = M_UNLOCK;
	77	else
	78	mem_timings.dll_mode = M_LOCK;
	79
	80	if (mem_timings.base_cs == 0) {
44595982 PW	81	fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
44595982 PW	82	dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
b824efae	83	} else {
44595982 PW	84	fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
44595982 PW	85	dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
b824efae TL	86	}
	87	if (force_lock_to_unlock_mode) {
	88	fast_dll &= ~0xff00;
	89	fast_dll \|= dll_cnt; /* Current lock mode */
	90	}
	91	/* set fast timings with DLL filter disabled */
	92	mem_timings.fast_dll_ctrl = (fast_dll \| (3 << 8));
	93
	94	/* No disruptions, DDR will be offline & C-ABI not followed */
	95	omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
	96	mem_timings.fast_dll_ctrl,
	97	mem_timings.base_cs,
	98	force_lock_to_unlock_mode);
	99	mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
	100
	101	/* Turn status into unlock ctrl */
	102	mem_timings.slow_dll_ctrl \|=
	103	((mem_timings.fast_dll_ctrl & 0xF) \| (1 << 2));
	104
	105	/* 90 degree phase for anything below 133Mhz + disable DLL filter */
	106	mem_timings.slow_dll_ctrl \|= ((1 << 1) \| (3 << 8));
	107	}
33c99075	108
742c53e4	109	/* turn on smart idle modes for SDRAM scheduler and controller */
33c99075 JY	110	void __init omap2_init_memory(void)
	111	{
	112	u32 l;
	113
44595982	114	l = sms_read_reg(SMS_SYSCONFIG);
33c99075 JY	115	l &= ~(0x3 << 3);
33c99075 JY	116	l \|= (0x2 << 3);
44595982	117	sms_write_reg(l, SMS_SYSCONFIG);
33c99075	118
44595982	119	l = sdrc_read_reg(SDRC_SYSCONFIG);
33c99075 JY	120	l &= ~(0x3 << 3);
33c99075 JY	121	l \|= (0x2 << 3);
44595982	122	sdrc_write_reg(l, SDRC_SYSCONFIG);
33c99075	123	}