[deliverable/linux.git] / arch / arm / mach-omap2 / omap-mpuss-lowpower.c

/*
 * OMAP MPUSS low power code
 *
 * Copyright (C) 2011 Texas Instruments, Inc.
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
 * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
 * CPU0 and CPU1 LPRM modules.
 * CPU0, CPU1 and MPUSS each have there own power domain and
 * hence multiple low power combinations of MPUSS are possible.
 *
 * The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
 * because the mode is not supported by hw constraints of dormant
 * mode. While waking up from the dormant mode, a reset  signal
 * to the Cortex-A9 processor must be asserted by the external
 * power controller.
 *
 * With architectural inputs and hardware recommendations, only
 * below modes are supported from power gain vs latency point of view.
 *
 *	CPU0		CPU1		MPUSS
 *	----------------------------------------------
 *	ON		ON		ON
 *	ON(Inactive)	OFF		ON(Inactive)
 *	OFF		OFF		CSWR
 *	OFF		OFF		OSWR
 *	OFF		OFF		OFF(Device OFF *TBD)
 *	----------------------------------------------
 *
 * Note: CPU0 is the master core and it is the last CPU to go down
 * and first to wake-up when MPUSS low power states are excercised
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/errno.h>
#include <linux/linkage.h>
#include <linux/smp.h>

#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/smp_scu.h>
#include <asm/pgalloc.h>
#include <asm/suspend.h>
#include <asm/hardware/cache-l2x0.h>

#include "soc.h"
#include "common.h"
#include "omap44xx.h"
#include "omap4-sar-layout.h"
#include "pm.h"
#include "prcm_mpu44xx.h"
#include "prcm_mpu54xx.h"
#include "prminst44xx.h"
#include "prcm44xx.h"
#include "prm44xx.h"
#include "prm-regbits-44xx.h"

static void __iomem *sar_base;

#if defined(CONFIG_PM) && defined(CONFIG_SMP)

struct omap4_cpu_pm_info {
	struct powerdomain *pwrdm;
	void __iomem *scu_sar_addr;
	void __iomem *wkup_sar_addr;
	void __iomem *l2x0_sar_addr;
};

/**
 * struct cpu_pm_ops - CPU pm operations
 * @finish_suspend:	CPU suspend finisher function pointer
 * @resume:		CPU resume function pointer
 * @scu_prepare:	CPU Snoop Control program function pointer
 * @hotplug_restart:	CPU restart function pointer
 *
 * Structure holds functions pointer for CPU low power operations like
 * suspend, resume and scu programming.
 */
struct cpu_pm_ops {
	int (*finish_suspend)(unsigned long cpu_state);
	void (*resume)(void);
	void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state);
	void (*hotplug_restart)(void);
};

static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
static struct powerdomain *mpuss_pd;
static u32 cpu_context_offset;

static int default_finish_suspend(unsigned long cpu_state)
{
	omap_do_wfi();
	return 0;
}

static void dummy_cpu_resume(void)
{}

static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state)
{}

static struct cpu_pm_ops omap_pm_ops = {
	.finish_suspend		= default_finish_suspend,
	.resume			= dummy_cpu_resume,
	.scu_prepare		= dummy_scu_prepare,
	.hotplug_restart	= dummy_cpu_resume,
};

/*
 * Program the wakeup routine address for the CPU0 and CPU1
 * used for OFF or DORMANT wakeup.
 */
static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);

	if (pm_info->wkup_sar_addr)
		writel_relaxed(addr, pm_info->wkup_sar_addr);
}

/*
 * Store the SCU power status value to scratchpad memory
 */
static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	u32 scu_pwr_st;

	switch (cpu_state) {
	case PWRDM_POWER_RET:
		scu_pwr_st = SCU_PM_DORMANT;
		break;
	case PWRDM_POWER_OFF:
		scu_pwr_st = SCU_PM_POWEROFF;
		break;
	case PWRDM_POWER_ON:
	case PWRDM_POWER_INACTIVE:
	default:
		scu_pwr_st = SCU_PM_NORMAL;
		break;
	}

	if (pm_info->scu_sar_addr)
		writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr);
}

/* Helper functions for MPUSS OSWR */
static inline void mpuss_clear_prev_logic_pwrst(void)
{
	u32 reg;

	reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
		OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
	omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION,
		OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
}

static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
{
	u32 reg;

	if (cpu_id) {
		reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
					cpu_context_offset);
		omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
					cpu_context_offset);
	} else {
		reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
					cpu_context_offset);
		omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
					cpu_context_offset);
	}
}

/*
 * Store the CPU cluster state for L2X0 low power operations.
 */
static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);

	if (pm_info->l2x0_sar_addr)
		writel_relaxed(save_state, pm_info->l2x0_sar_addr);
}

/*
 * Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
 * in every restore MPUSS OFF path.
 */
#ifdef CONFIG_CACHE_L2X0
static void __init save_l2x0_context(void)
{
	void __iomem *l2x0_base = omap4_get_l2cache_base();

	if (l2x0_base && sar_base) {
		writel_relaxed(l2x0_saved_regs.aux_ctrl,
			       sar_base + L2X0_AUXCTRL_OFFSET);
		writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
			       sar_base + L2X0_PREFETCH_CTRL_OFFSET);
	}
}
#else
static void __init save_l2x0_context(void)
{}
#endif

/**
 * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
 * The purpose of this function is to manage low power programming
 * of OMAP4 MPUSS subsystem
 * @cpu : CPU ID
 * @power_state: Low power state.
 *
 * MPUSS states for the context save:
 * save_state =
 *	0 - Nothing lost and no need to save: MPUSS INACTIVE
 *	1 - CPUx L1 and logic lost: MPUSS CSWR
 *	2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
 *	3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
 */
int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
	unsigned int save_state = 0, cpu_logic_state = PWRDM_POWER_RET;
	unsigned int wakeup_cpu;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		return -ENXIO;

	switch (power_state) {
	case PWRDM_POWER_ON:
	case PWRDM_POWER_INACTIVE:
		save_state = 0;
		break;
	case PWRDM_POWER_OFF:
		cpu_logic_state = PWRDM_POWER_OFF;
		save_state = 1;
		break;
	case PWRDM_POWER_RET:
		if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE)) {
			save_state = 0;
			break;
		}
	default:
		/*
		 * CPUx CSWR is invalid hardware state. Also CPUx OSWR
		 * doesn't make much scense, since logic is lost and $L1
		 * needs to be cleaned because of coherency. This makes
		 * CPUx OSWR equivalent to CPUX OFF and hence not supported
		 */
		WARN_ON(1);
		return -ENXIO;
	}

	pwrdm_pre_transition(NULL);

	/*
	 * Check MPUSS next state and save interrupt controller if needed.
	 * In MPUSS OSWR or device OFF, interrupt controller  contest is lost.
	 */
	mpuss_clear_prev_logic_pwrst();
	if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
		(pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
		save_state = 2;

	cpu_clear_prev_logic_pwrst(cpu);
	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
	pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state);
	set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume));
	omap_pm_ops.scu_prepare(cpu, power_state);
	l2x0_pwrst_prepare(cpu, save_state);

	/*
	 * Call low level function  with targeted low power state.
	 */
	if (save_state)
		cpu_suspend(save_state, omap_pm_ops.finish_suspend);
	else
		omap_pm_ops.finish_suspend(save_state);

	if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) && cpu)
		gic_dist_enable();

	/*
	 * Restore the CPUx power state to ON otherwise CPUx
	 * power domain can transitions to programmed low power
	 * state while doing WFI outside the low powe code. On
	 * secure devices, CPUx does WFI which can result in
	 * domain transition
	 */
	wakeup_cpu = smp_processor_id();
	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);

	pwrdm_post_transition(NULL);

	return 0;
}

/**
 * omap4_hotplug_cpu: OMAP4 CPU hotplug entry
 * @cpu : CPU ID
 * @power_state: CPU low power state.
 */
int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
{
	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
	unsigned int cpu_state = 0;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		return -ENXIO;

	/* Use the achievable power state for the domain */
	power_state = pwrdm_get_valid_lp_state(pm_info->pwrdm,
					       false, power_state);

	if (power_state == PWRDM_POWER_OFF)
		cpu_state = 1;

	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
	set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.hotplug_restart));
	omap_pm_ops.scu_prepare(cpu, power_state);

	/*
	 * CPU never retuns back if targeted power state is OFF mode.
	 * CPU ONLINE follows normal CPU ONLINE ptah via
	 * omap4_secondary_startup().
	 */
	omap_pm_ops.finish_suspend(cpu_state);

	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
	return 0;
}


/*
 * Enable Mercury Fast HG retention mode by default.
 */
static void enable_mercury_retention_mode(void)
{
	u32 reg;

	reg = omap4_prcm_mpu_read_inst_reg(OMAP54XX_PRCM_MPU_DEVICE_INST,
				  OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
	/* Enable HG_EN, HG_RAMPUP = fast mode */
	reg |= BIT(24) | BIT(25);
	omap4_prcm_mpu_write_inst_reg(reg, OMAP54XX_PRCM_MPU_DEVICE_INST,
				      OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
}

/*
 * Initialise OMAP4 MPUSS
 */
int __init omap4_mpuss_init(void)
{
	struct omap4_cpu_pm_info *pm_info;

	if (omap_rev() == OMAP4430_REV_ES1_0) {
		WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
		return -ENODEV;
	}

	/* Initilaise per CPU PM information */
	pm_info = &per_cpu(omap4_pm_info, 0x0);
	if (sar_base) {
		pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
		pm_info->wkup_sar_addr = sar_base +
					CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
		pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
	}
	pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
	if (!pm_info->pwrdm) {
		pr_err("Lookup failed for CPU0 pwrdm\n");
		return -ENODEV;
	}

	/* Clear CPU previous power domain state */
	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
	cpu_clear_prev_logic_pwrst(0);

	/* Initialise CPU0 power domain state to ON */
	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);

	pm_info = &per_cpu(omap4_pm_info, 0x1);
	if (sar_base) {
		pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
		pm_info->wkup_sar_addr = sar_base +
					CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
		pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
	}

	pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
	if (!pm_info->pwrdm) {
		pr_err("Lookup failed for CPU1 pwrdm\n");
		return -ENODEV;
	}

	/* Clear CPU previous power domain state */
	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
	cpu_clear_prev_logic_pwrst(1);

	/* Initialise CPU1 power domain state to ON */
	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);

	mpuss_pd = pwrdm_lookup("mpu_pwrdm");
	if (!mpuss_pd) {
		pr_err("Failed to lookup MPUSS power domain\n");
		return -ENODEV;
	}
	pwrdm_clear_all_prev_pwrst(mpuss_pd);
	mpuss_clear_prev_logic_pwrst();

	if (sar_base) {
		/* Save device type on scratchpad for low level code to use */
		writel_relaxed((omap_type() != OMAP2_DEVICE_TYPE_GP) ? 1 : 0,
			       sar_base + OMAP_TYPE_OFFSET);
		save_l2x0_context();
	}

	if (cpu_is_omap44xx()) {
		omap_pm_ops.finish_suspend = omap4_finish_suspend;
		omap_pm_ops.resume = omap4_cpu_resume;
		omap_pm_ops.scu_prepare = scu_pwrst_prepare;
		omap_pm_ops.hotplug_restart = omap4_secondary_startup;
		cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET;
	} else if (soc_is_omap54xx() || soc_is_dra7xx()) {
		cpu_context_offset = OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET;
		enable_mercury_retention_mode();
	}

	if (cpu_is_omap446x())
		omap_pm_ops.hotplug_restart = omap4460_secondary_startup;

	return 0;
}

#endif

/*
 * For kexec, we must set CPU1_WAKEUP_NS_PA_ADDR to point to
 * current kernel's secondary_startup() early before
 * clockdomains_init(). Otherwise clockdomain_init() can
 * wake CPU1 and cause a hang.
 */
void __init omap4_mpuss_early_init(void)
{
	unsigned long startup_pa;

	if (!cpu_is_omap44xx())
		return;

	sar_base = omap4_get_sar_ram_base();

	if (cpu_is_omap443x())
		startup_pa = virt_to_phys(omap4_secondary_startup);
	else
		startup_pa = virt_to_phys(omap4460_secondary_startup);

	writel_relaxed(startup_pa, sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
}
Commit	Line	Data
b2b9762f SS	1	/*
	2	* OMAP MPUSS low power code
	3	*
	4	* Copyright (C) 2011 Texas Instruments, Inc.
	5	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	6	*
	7	* OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
	8	* Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
	9	* CPU0 and CPU1 LPRM modules.
	10	* CPU0, CPU1 and MPUSS each have there own power domain and
	11	* hence multiple low power combinations of MPUSS are possible.
	12	*
	13	* The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
	14	* because the mode is not supported by hw constraints of dormant
	15	* mode. While waking up from the dormant mode, a reset signal
	16	* to the Cortex-A9 processor must be asserted by the external
	17	* power controller.
	18	*
	19	* With architectural inputs and hardware recommendations, only
	20	* below modes are supported from power gain vs latency point of view.
	21	*
	22	* CPU0 CPU1 MPUSS
	23	* ----------------------------------------------
	24	* ON ON ON
	25	* ON(Inactive) OFF ON(Inactive)
	26	* OFF OFF CSWR
3ba2a739 SS	27	* OFF OFF OSWR
3ba2a739 SS	28	* OFF OFF OFF(Device OFF *TBD)
b2b9762f SS	29	* ----------------------------------------------
	30	*
	31	* Note: CPU0 is the master core and it is the last CPU to go down
	32	* and first to wake-up when MPUSS low power states are excercised
	33	*
	34	*
	35	* This program is free software; you can redistribute it and/or modify
	36	* it under the terms of the GNU General Public License version 2 as
	37	* published by the Free Software Foundation.
	38	*/
	39
	40	#include <linux/kernel.h>
	41	#include <linux/io.h>
	42	#include <linux/errno.h>
	43	#include <linux/linkage.h>
	44	#include <linux/smp.h>
	45
	46	#include <asm/cacheflush.h>
	47	#include <asm/tlbflush.h>
	48	#include <asm/smp_scu.h>
b2b9762f SS	49	#include <asm/pgalloc.h>
b2b9762f SS	50	#include <asm/suspend.h>
5e94c6e3	51	#include <asm/hardware/cache-l2x0.h>
b2b9762f	52
e4c060db	53	#include "soc.h"
b2b9762f	54	#include "common.h"
c49f34bc	55	#include "omap44xx.h"
b2b9762f SS	56	#include "omap4-sar-layout.h"
b2b9762f SS	57	#include "pm.h"
3ba2a739	58	#include "prcm_mpu44xx.h"
a89726d3	59	#include "prcm_mpu54xx.h"
3ba2a739 SS	60	#include "prminst44xx.h"
	61	#include "prcm44xx.h"
	62	#include "prm44xx.h"
	63	#include "prm-regbits-44xx.h"
b2b9762f	64
0573b957 TL	65	static void __iomem *sar_base;
0573b957 TL	66
b3bf289c	67	#if defined(CONFIG_PM) && defined(CONFIG_SMP)
b2b9762f SS	68
	69	struct omap4_cpu_pm_info {
	70	struct powerdomain *pwrdm;
	71	void __iomem *scu_sar_addr;
	72	void __iomem *wkup_sar_addr;
5e94c6e3	73	void __iomem *l2x0_sar_addr;
b2b9762f SS	74	};
b2b9762f SS	75
9f192cf7 SS	76	/**
	77	* struct cpu_pm_ops - CPU pm operations
	78	* @finish_suspend: CPU suspend finisher function pointer
	79	* @resume: CPU resume function pointer
	80	* @scu_prepare: CPU Snoop Control program function pointer
e97c4eb3	81	* @hotplug_restart: CPU restart function pointer
9f192cf7 SS	82	*
	83	* Structure holds functions pointer for CPU low power operations like
	84	* suspend, resume and scu programming.
	85	*/
	86	struct cpu_pm_ops {
	87	int (*finish_suspend)(unsigned long cpu_state);
	88	void (*resume)(void);
	89	void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state);
e97c4eb3	90	void (*hotplug_restart)(void);
9f192cf7 SS	91	};
9f192cf7 SS	92
b2b9762f	93	static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
e44f9a77	94	static struct powerdomain *mpuss_pd;
a89726d3	95	static u32 cpu_context_offset;
b2b9762f	96
9f192cf7 SS	97	static int default_finish_suspend(unsigned long cpu_state)
	98	{
	99	omap_do_wfi();
	100	return 0;
	101	}
	102
	103	static void dummy_cpu_resume(void)
	104	{}
	105
	106	static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state)
	107	{}
	108
f734a9b3	109	static struct cpu_pm_ops omap_pm_ops = {
9f192cf7 SS	110	.finish_suspend = default_finish_suspend,
	111	.resume = dummy_cpu_resume,
	112	.scu_prepare = dummy_scu_prepare,
e97c4eb3	113	.hotplug_restart = dummy_cpu_resume,
9f192cf7 SS	114	};
9f192cf7 SS	115
b2b9762f SS	116	/*
	117	* Program the wakeup routine address for the CPU0 and CPU1
	118	* used for OFF or DORMANT wakeup.
	119	*/
	120	static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
	121	{
	122	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	123
325f29da RN	124	if (pm_info->wkup_sar_addr)
325f29da RN	125	writel_relaxed(addr, pm_info->wkup_sar_addr);
b2b9762f SS	126	}
b2b9762f SS	127
b2b9762f SS	128	/*
	129	* Store the SCU power status value to scratchpad memory
	130	*/
	131	static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
	132	{
	133	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	134	u32 scu_pwr_st;
	135
	136	switch (cpu_state) {
	137	case PWRDM_POWER_RET:
	138	scu_pwr_st = SCU_PM_DORMANT;
	139	break;
	140	case PWRDM_POWER_OFF:
	141	scu_pwr_st = SCU_PM_POWEROFF;
	142	break;
	143	case PWRDM_POWER_ON:
	144	case PWRDM_POWER_INACTIVE:
	145	default:
	146	scu_pwr_st = SCU_PM_NORMAL;
	147	break;
	148	}
	149
325f29da RN	150	if (pm_info->scu_sar_addr)
325f29da RN	151	writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr);
b2b9762f SS	152	}
b2b9762f SS	153
3ba2a739 SS	154	/* Helper functions for MPUSS OSWR */
	155	static inline void mpuss_clear_prev_logic_pwrst(void)
	156	{
	157	u32 reg;
	158
	159	reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
	160	OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
	161	omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION,
	162	OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
	163	}
	164
	165	static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
	166	{
	167	u32 reg;
	168
	169	if (cpu_id) {
	170	reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
a89726d3	171	cpu_context_offset);
3ba2a739	172	omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
a89726d3	173	cpu_context_offset);
3ba2a739 SS	174	} else {
3ba2a739 SS	175	reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
a89726d3	176	cpu_context_offset);
3ba2a739	177	omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
a89726d3	178	cpu_context_offset);
3ba2a739 SS	179	}
	180	}
	181
5e94c6e3 SS	182	/*
	183	* Store the CPU cluster state for L2X0 low power operations.
	184	*/
	185	static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
	186	{
	187	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
	188
325f29da RN	189	if (pm_info->l2x0_sar_addr)
325f29da RN	190	writel_relaxed(save_state, pm_info->l2x0_sar_addr);
5e94c6e3 SS	191	}
	192
	193	/*
	194	* Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
	195	* in every restore MPUSS OFF path.
	196	*/
	197	#ifdef CONFIG_CACHE_L2X0
7a09b28e	198	static void __init save_l2x0_context(void)
5e94c6e3	199	{
325f29da RN	200	void __iomem *l2x0_base = omap4_get_l2cache_base();
	201
	202	if (l2x0_base && sar_base) {
	203	writel_relaxed(l2x0_saved_regs.aux_ctrl,
	204	sar_base + L2X0_AUXCTRL_OFFSET);
	205	writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
	206	sar_base + L2X0_PREFETCH_CTRL_OFFSET);
	207	}
5e94c6e3 SS	208	}
5e94c6e3 SS	209	#else
7a09b28e	210	static void __init save_l2x0_context(void)
5e94c6e3 SS	211	{}
	212	#endif
	213
b2b9762f SS	214	/**
	215	* omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
	216	* The purpose of this function is to manage low power programming
	217	* of OMAP4 MPUSS subsystem
	218	* @cpu : CPU ID
	219	* @power_state: Low power state.
e44f9a77 SS	220	*
	221	* MPUSS states for the context save:
	222	* save_state =
	223	* 0 - Nothing lost and no need to save: MPUSS INACTIVE
	224	* 1 - CPUx L1 and logic lost: MPUSS CSWR
	225	* 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
	226	* 3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
b2b9762f SS	227	*/
	228	int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
	229	{
32d174ed	230	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
a30d81b9	231	unsigned int save_state = 0, cpu_logic_state = PWRDM_POWER_RET;
b2b9762f SS	232	unsigned int wakeup_cpu;
	233
	234	if (omap_rev() == OMAP4430_REV_ES1_0)
	235	return -ENXIO;
	236
	237	switch (power_state) {
	238	case PWRDM_POWER_ON:
	239	case PWRDM_POWER_INACTIVE:
	240	save_state = 0;
	241	break;
	242	case PWRDM_POWER_OFF:
a30d81b9	243	cpu_logic_state = PWRDM_POWER_OFF;
b2b9762f SS	244	save_state = 1;
	245	break;
	246	case PWRDM_POWER_RET:
6099dd37 RN	247	if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE)) {
	248	save_state = 0;
	249	break;
	250	}
b2b9762f SS	251	default:
	252	/*
	253	* CPUx CSWR is invalid hardware state. Also CPUx OSWR
	254	* doesn't make much scense, since logic is lost and $L1
	255	* needs to be cleaned because of coherency. This makes
	256	* CPUx OSWR equivalent to CPUX OFF and hence not supported
	257	*/
	258	WARN_ON(1);
	259	return -ENXIO;
	260	}
	261
e0555489	262	pwrdm_pre_transition(NULL);
49404dd0	263
3ba2a739 SS	264	/*
	265	* Check MPUSS next state and save interrupt controller if needed.
	266	* In MPUSS OSWR or device OFF, interrupt controller contest is lost.
	267	*/
	268	mpuss_clear_prev_logic_pwrst();
3ba2a739 SS	269	if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
	270	(pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
	271	save_state = 2;
	272
3ba2a739	273	cpu_clear_prev_logic_pwrst(cpu);
32d174ed	274	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
a30d81b9	275	pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state);
9f192cf7 SS	276	set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume));
9f192cf7 SS	277	omap_pm_ops.scu_prepare(cpu, power_state);
5e94c6e3	278	l2x0_pwrst_prepare(cpu, save_state);
b2b9762f SS	279
	280	/*
	281	* Call low level function with targeted low power state.
	282	*/
72433eba	283	if (save_state)
9f192cf7	284	cpu_suspend(save_state, omap_pm_ops.finish_suspend);
72433eba	285	else
9f192cf7	286	omap_pm_ops.finish_suspend(save_state);
b2b9762f	287
74ed7bdc SG	288	if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) && cpu)
	289	gic_dist_enable();
	290
b2b9762f SS	291	/*
	292	* Restore the CPUx power state to ON otherwise CPUx
	293	* power domain can transitions to programmed low power
	294	* state while doing WFI outside the low powe code. On
	295	* secure devices, CPUx does WFI which can result in
	296	* domain transition
	297	*/
	298	wakeup_cpu = smp_processor_id();
32d174ed	299	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
b2b9762f	300
e0555489	301	pwrdm_post_transition(NULL);
49404dd0	302
b2b9762f SS	303	return 0;
	304	}
	305
b5b4f288 SS	306	/**
	307	* omap4_hotplug_cpu: OMAP4 CPU hotplug entry
	308	* @cpu : CPU ID
	309	* @power_state: CPU low power state.
	310	*/
8bd26e3a	311	int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
b5b4f288	312	{
ff999b8a	313	struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
32d174ed	314	unsigned int cpu_state = 0;
b5b4f288 SS	315
	316	if (omap_rev() == OMAP4430_REV_ES1_0)
	317	return -ENXIO;
	318
3e6a1c94 NM	319	/* Use the achievable power state for the domain */
	320	power_state = pwrdm_get_valid_lp_state(pm_info->pwrdm,
	321	false, power_state);
	322
b5b4f288 SS	323	if (power_state == PWRDM_POWER_OFF)
	324	cpu_state = 1;
	325
32d174ed PW	326	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
32d174ed PW	327	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
e97c4eb3	328	set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.hotplug_restart));
9f192cf7	329	omap_pm_ops.scu_prepare(cpu, power_state);
b5b4f288 SS	330
b5b4f288 SS	331	/*
260db902	332	* CPU never retuns back if targeted power state is OFF mode.
b5b4f288	333	* CPU ONLINE follows normal CPU ONLINE ptah via
baf4b7d3	334	* omap4_secondary_startup().
b5b4f288	335	*/
9f192cf7	336	omap_pm_ops.finish_suspend(cpu_state);
b5b4f288	337
32d174ed	338	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
b5b4f288 SS	339	return 0;
	340	}
	341
	342
6d846c46 SS	343	/*
	344	* Enable Mercury Fast HG retention mode by default.
	345	*/
	346	static void enable_mercury_retention_mode(void)
	347	{
	348	u32 reg;
	349
	350	reg = omap4_prcm_mpu_read_inst_reg(OMAP54XX_PRCM_MPU_DEVICE_INST,
	351	OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
	352	/* Enable HG_EN, HG_RAMPUP = fast mode */
	353	reg \|= BIT(24) \| BIT(25);
	354	omap4_prcm_mpu_write_inst_reg(reg, OMAP54XX_PRCM_MPU_DEVICE_INST,
	355	OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
	356	}
	357
b2b9762f SS	358	/*
	359	* Initialise OMAP4 MPUSS
	360	*/
	361	int __init omap4_mpuss_init(void)
	362	{
	363	struct omap4_cpu_pm_info *pm_info;
b2b9762f SS	364
	365	if (omap_rev() == OMAP4430_REV_ES1_0) {
	366	WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
	367	return -ENODEV;
	368	}
	369
	370	/* Initilaise per CPU PM information */
	371	pm_info = &per_cpu(omap4_pm_info, 0x0);
325f29da RN	372	if (sar_base) {
	373	pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
	374	pm_info->wkup_sar_addr = sar_base +
	375	CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
	376	pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
	377	}
b2b9762f SS	378	pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
	379	if (!pm_info->pwrdm) {
	380	pr_err("Lookup failed for CPU0 pwrdm\n");
	381	return -ENODEV;
	382	}
	383
	384	/* Clear CPU previous power domain state */
	385	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
3ba2a739	386	cpu_clear_prev_logic_pwrst(0);
b2b9762f SS	387
	388	/* Initialise CPU0 power domain state to ON */
	389	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
	390
	391	pm_info = &per_cpu(omap4_pm_info, 0x1);
325f29da RN	392	if (sar_base) {
	393	pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
	394	pm_info->wkup_sar_addr = sar_base +
	395	CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
	396	pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
	397	}
ff999b8a	398
b2b9762f SS	399	pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
	400	if (!pm_info->pwrdm) {
	401	pr_err("Lookup failed for CPU1 pwrdm\n");
	402	return -ENODEV;
	403	}
	404
	405	/* Clear CPU previous power domain state */
	406	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
3ba2a739	407	cpu_clear_prev_logic_pwrst(1);
b2b9762f SS	408
	409	/* Initialise CPU1 power domain state to ON */
	410	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
	411
e44f9a77 SS	412	mpuss_pd = pwrdm_lookup("mpu_pwrdm");
	413	if (!mpuss_pd) {
	414	pr_err("Failed to lookup MPUSS power domain\n");
	415	return -ENODEV;
	416	}
	417	pwrdm_clear_all_prev_pwrst(mpuss_pd);
3ba2a739	418	mpuss_clear_prev_logic_pwrst();
e44f9a77	419
325f29da RN	420	if (sar_base) {
	421	/* Save device type on scratchpad for low level code to use */
	422	writel_relaxed((omap_type() != OMAP2_DEVICE_TYPE_GP) ? 1 : 0,
	423	sar_base + OMAP_TYPE_OFFSET);
	424	save_l2x0_context();
	425	}
5e94c6e3	426
9f192cf7 SS	427	if (cpu_is_omap44xx()) {
	428	omap_pm_ops.finish_suspend = omap4_finish_suspend;
	429	omap_pm_ops.resume = omap4_cpu_resume;
	430	omap_pm_ops.scu_prepare = scu_pwrst_prepare;
e97c4eb3	431	omap_pm_ops.hotplug_restart = omap4_secondary_startup;
a89726d3 SS	432	cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET;
	433	} else if (soc_is_omap54xx() \|\| soc_is_dra7xx()) {
	434	cpu_context_offset = OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET;
6d846c46	435	enable_mercury_retention_mode();
9f192cf7 SS	436	}
9f192cf7 SS	437
e97c4eb3 SS	438	if (cpu_is_omap446x())
	439	omap_pm_ops.hotplug_restart = omap4460_secondary_startup;
	440
b2b9762f SS	441	return 0;
	442	}
	443
	444	#endif
0573b957 TL	445
	446	/*
	447	* For kexec, we must set CPU1_WAKEUP_NS_PA_ADDR to point to
	448	* current kernel's secondary_startup() early before
	449	* clockdomains_init(). Otherwise clockdomain_init() can
	450	* wake CPU1 and cause a hang.
	451	*/
	452	void __init omap4_mpuss_early_init(void)
	453	{
	454	unsigned long startup_pa;
	455
	456	if (!cpu_is_omap44xx())
	457	return;
	458
	459	sar_base = omap4_get_sar_ram_base();
	460
	461	if (cpu_is_omap443x())
	462	startup_pa = virt_to_phys(omap4_secondary_startup);
	463	else
	464	startup_pa = virt_to_phys(omap4460_secondary_startup);
	465
	466	writel_relaxed(startup_pa, sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
	467	}