[deliverable/linux.git] / arch / arm / mach-omap2 / omap-smp.c

/*
 * OMAP4 SMP source file. It contains platform specific functions
 * needed for the linux smp kernel.
 *
 * Copyright (C) 2009 Texas Instruments, Inc.
 *
 * Author:
 *      Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * Platform file needed for the OMAP4 SMP. This file is based on arm
 * realview smp platform.
 * * Copyright (c) 2002 ARM Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/init.h>
#include <linux/device.h>
#include <linux/smp.h>
#include <linux/io.h>
#include <linux/irqchip/arm-gic.h>

#include <asm/smp_scu.h>

#include "omap-secure.h"
#include "omap-wakeupgen.h"
#include <asm/cputype.h>

#include "soc.h"
#include "iomap.h"
#include "common.h"
#include "clockdomain.h"
#include "pm.h"

#define CPU_MASK		0xff0ffff0
#define CPU_CORTEX_A9		0x410FC090
#define CPU_CORTEX_A15		0x410FC0F0

#define OMAP5_CORE_COUNT	0x2

u16 pm44xx_errata;

/* SCU base address */
static void __iomem *scu_base;

static DEFINE_SPINLOCK(boot_lock);

void __iomem *omap4_get_scu_base(void)
{
	return scu_base;
}

static void omap4_secondary_init(unsigned int cpu)
{
	/*
	 * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
	 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
	 * init and for CPU1, a secure PPA API provided. CPU0 must be ON
	 * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
	 * OMAP443X GP devices- SMP bit isn't accessible.
	 * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
	 */
	if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
		omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
							4, 0, 0, 0, 0, 0);

	/*
	 * Configure the CNTFRQ register for the secondary cpu's which
	 * indicates the frequency of the cpu local timers.
	 */
	if (soc_is_omap54xx() || soc_is_dra7xx())
		set_cntfreq();

	/*
	 * Synchronise with the boot thread.
	 */
	spin_lock(&boot_lock);
	spin_unlock(&boot_lock);
}

static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
	static struct clockdomain *cpu1_clkdm;
	static bool booted;
	static struct powerdomain *cpu1_pwrdm;
	void __iomem *base = omap_get_wakeupgen_base();

	/*
	 * Set synchronisation state between this boot processor
	 * and the secondary one
	 */
	spin_lock(&boot_lock);

	/*
	 * Update the AuxCoreBoot0 with boot state for secondary core.
	 * omap4_secondary_startup() routine will hold the secondary core till
	 * the AuxCoreBoot1 register is updated with cpu state
	 * A barrier is added to ensure that write buffer is drained
	 */
	if (omap_secure_apis_support())
		omap_modify_auxcoreboot0(0x200, 0xfffffdff);
	else
		__raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);

	if (!cpu1_clkdm && !cpu1_pwrdm) {
		cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
		cpu1_pwrdm = pwrdm_lookup("cpu1_pwrdm");
	}

	/*
	 * The SGI(Software Generated Interrupts) are not wakeup capable
	 * from low power states. This is known limitation on OMAP4 and
	 * needs to be worked around by using software forced clockdomain
	 * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
	 * software force wakeup. The clockdomain is then put back to
	 * hardware supervised mode.
	 * More details can be found in OMAP4430 TRM - Version J
	 * Section :
	 *	4.3.4.2 Power States of CPU0 and CPU1
	 */
	if (booted && cpu1_pwrdm && cpu1_clkdm) {
		/*
		 * GIC distributor control register has changed between
		 * CortexA9 r1pX and r2pX. The Control Register secure
		 * banked version is now composed of 2 bits:
		 * bit 0 == Secure Enable
		 * bit 1 == Non-Secure Enable
		 * The Non-Secure banked register has not changed
		 * Because the ROM Code is based on the r1pX GIC, the CPU1
		 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
		 * The workaround must be:
		 * 1) Before doing the CPU1 wakeup, CPU0 must disable
		 * the GIC distributor
		 * 2) CPU1 must re-enable the GIC distributor on
		 * it's wakeup path.
		 */
		if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
			local_irq_disable();
			gic_dist_disable();
		}

		/*
		 * Ensure that CPU power state is set to ON to avoid CPU
		 * powerdomain transition on wfi
		 */
		clkdm_wakeup(cpu1_clkdm);
		omap_set_pwrdm_state(cpu1_pwrdm, PWRDM_POWER_ON);
		clkdm_allow_idle(cpu1_clkdm);

		if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
			while (gic_dist_disabled()) {
				udelay(1);
				cpu_relax();
			}
			gic_timer_retrigger();
			local_irq_enable();
		}
	} else {
		dsb_sev();
		booted = true;
	}

	arch_send_wakeup_ipi_mask(cpumask_of(cpu));

	/*
	 * Now the secondary core is starting up let it run its
	 * calibrations, then wait for it to finish
	 */
	spin_unlock(&boot_lock);

	return 0;
}

/*
 * Initialise the CPU possible map early - this describes the CPUs
 * which may be present or become present in the system.
 */
static void __init omap4_smp_init_cpus(void)
{
	unsigned int i = 0, ncores = 1, cpu_id;

	/* Use ARM cpuid check here, as SoC detection will not work so early */
	cpu_id = read_cpuid_id() & CPU_MASK;
	if (cpu_id == CPU_CORTEX_A9) {
		/*
		 * Currently we can't call ioremap here because
		 * SoC detection won't work until after init_early.
		 */
		scu_base =  OMAP2_L4_IO_ADDRESS(scu_a9_get_base());
		BUG_ON(!scu_base);
		ncores = scu_get_core_count(scu_base);
	} else if (cpu_id == CPU_CORTEX_A15) {
		ncores = OMAP5_CORE_COUNT;
	}

	/* sanity check */
	if (ncores > nr_cpu_ids) {
		pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
			ncores, nr_cpu_ids);
		ncores = nr_cpu_ids;
	}

	for (i = 0; i < ncores; i++)
		set_cpu_possible(i, true);
}

static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
{
	void *startup_addr = omap4_secondary_startup;
	void __iomem *base = omap_get_wakeupgen_base();

	/*
	 * Initialise the SCU and wake up the secondary core using
	 * wakeup_secondary().
	 */
	if (scu_base)
		scu_enable(scu_base);

	if (cpu_is_omap446x()) {
		startup_addr = omap4460_secondary_startup;
		pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
	}

	/*
	 * Write the address of secondary startup routine into the
	 * AuxCoreBoot1 where ROM code will jump and start executing
	 * on secondary core once out of WFE
	 * A barrier is added to ensure that write buffer is drained
	 */
	if (omap_secure_apis_support())
		omap_auxcoreboot_addr(virt_to_phys(startup_addr));
	else
		__raw_writel(virt_to_phys(omap5_secondary_startup),
						base + OMAP_AUX_CORE_BOOT_1);

}

struct smp_operations omap4_smp_ops __initdata = {
	.smp_init_cpus		= omap4_smp_init_cpus,
	.smp_prepare_cpus	= omap4_smp_prepare_cpus,
	.smp_secondary_init	= omap4_secondary_init,
	.smp_boot_secondary	= omap4_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
	.cpu_die		= omap4_cpu_die,
#endif
};
Commit	Line	Data
367cd31e	1	/*
b6b24852	2	* OMAP4 SMP source file. It contains platform specific functions
367cd31e SS	3	* needed for the linux smp kernel.
	4	*
	5	* Copyright (C) 2009 Texas Instruments, Inc.
	6	*
	7	* Author:
	8	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	9	*
	10	* Platform file needed for the OMAP4 SMP. This file is based on arm
	11	* realview smp platform.
	12	* * Copyright (c) 2002 ARM Limited.
	13	*
	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License version 2 as
	16	* published by the Free Software Foundation.
	17	*/
	18	#include <linux/init.h>
	19	#include <linux/device.h>
367cd31e SS	20	#include <linux/smp.h>
367cd31e SS	21	#include <linux/io.h>
520f7bd7	22	#include <linux/irqchip/arm-gic.h>
367cd31e	23
367cd31e	24	#include <asm/smp_scu.h>
ee0839c2	25
c1db9d73	26	#include "omap-secure.h"
732231a7	27	#include "omap-wakeupgen.h"
247c445c	28	#include <asm/cputype.h>
4e65331c	29
dbc04161	30	#include "soc.h"
ee0839c2	31	#include "iomap.h"
4e65331c	32	#include "common.h"
e97ca477	33	#include "clockdomain.h"
ff999b8a	34	#include "pm.h"
e97ca477	35
283f708c SS	36	#define CPU_MASK 0xff0ffff0
	37	#define CPU_CORTEX_A9 0x410FC090
	38	#define CPU_CORTEX_A15 0x410FC0F0
	39
	40	#define OMAP5_CORE_COUNT 0x2
	41
93640735 KH	42	u16 pm44xx_errata;
93640735 KH	43
367cd31e	44	/* SCU base address */
e4e7a13a	45	static void __iomem *scu_base;
367cd31e	46
367cd31e SS	47	static DEFINE_SPINLOCK(boot_lock);
367cd31e SS	48
02afe8a7 SS	49	void __iomem *omap4_get_scu_base(void)
	50	{
	51	return scu_base;
	52	}
	53
8bd26e3a	54	static void omap4_secondary_init(unsigned int cpu)
367cd31e	55	{
b2b9762f SS	56	/*
	57	* Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
	58	* OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
	59	* init and for CPU1, a secure PPA API provided. CPU0 must be ON
	60	* while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
	61	* OMAP443X GP devices- SMP bit isn't accessible.
	62	* OMAP446X GP devices - SMP bit access is enabled on both CPUs.
	63	*/
	64	if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
	65	omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
	66	4, 0, 0, 0, 0, 0);
	67
5523e409 S	68	/*
	69	* Configure the CNTFRQ register for the secondary cpu's which
	70	* indicates the frequency of the cpu local timers.
	71	*/
	72	if (soc_is_omap54xx() \|\| soc_is_dra7xx())
	73	set_cntfreq();
	74
367cd31e SS	75	/*
	76	* Synchronise with the boot thread.
	77	*/
	78	spin_lock(&boot_lock);
	79	spin_unlock(&boot_lock);
	80	}
	81
8bd26e3a	82	static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
367cd31e	83	{
e97ca477 SS	84	static struct clockdomain *cpu1_clkdm;
e97ca477 SS	85	static bool booted;
b7806dc7	86	static struct powerdomain *cpu1_pwrdm;
247c445c SS	87	void __iomem *base = omap_get_wakeupgen_base();
247c445c SS	88
367cd31e SS	89	/*
	90	* Set synchronisation state between this boot processor
	91	* and the secondary one
	92	*/
	93	spin_lock(&boot_lock);
	94
	95	/*
942e2c9e	96	* Update the AuxCoreBoot0 with boot state for secondary core.
baf4b7d3	97	* omap4_secondary_startup() routine will hold the secondary core till
367cd31e SS	98	* the AuxCoreBoot1 register is updated with cpu state
	99	* A barrier is added to ensure that write buffer is drained
	100	*/
247c445c SS	101	if (omap_secure_apis_support())
	102	omap_modify_auxcoreboot0(0x200, 0xfffffdff);
	103	else
	104	__raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
	105
b7806dc7	106	if (!cpu1_clkdm && !cpu1_pwrdm) {
e97ca477	107	cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
b7806dc7 SS	108	cpu1_pwrdm = pwrdm_lookup("cpu1_pwrdm");
b7806dc7 SS	109	}
e97ca477 SS	110
	111	/*
	112	* The SGI(Software Generated Interrupts) are not wakeup capable
	113	* from low power states. This is known limitation on OMAP4 and
	114	* needs to be worked around by using software forced clockdomain
	115	* wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
	116	* software force wakeup. The clockdomain is then put back to
	117	* hardware supervised mode.
	118	* More details can be found in OMAP4430 TRM - Version J
	119	* Section :
	120	* 4.3.4.2 Power States of CPU0 and CPU1
	121	*/
b7806dc7	122	if (booted && cpu1_pwrdm && cpu1_clkdm) {
ff999b8a SS	123	/*
	124	* GIC distributor control register has changed between
	125	* CortexA9 r1pX and r2pX. The Control Register secure
	126	* banked version is now composed of 2 bits:
	127	* bit 0 == Secure Enable
	128	* bit 1 == Non-Secure Enable
	129	* The Non-Secure banked register has not changed
	130	* Because the ROM Code is based on the r1pX GIC, the CPU1
	131	* GIC restoration will cause a problem to CPU0 Non-Secure SW.
	132	* The workaround must be:
	133	* 1) Before doing the CPU1 wakeup, CPU0 must disable
	134	* the GIC distributor
	135	* 2) CPU1 must re-enable the GIC distributor on
	136	* it's wakeup path.
	137	*/
cd8ce159 CC	138	if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
cd8ce159 CC	139	local_irq_disable();
ff999b8a	140	gic_dist_disable();
cd8ce159	141	}
ff999b8a	142
b7806dc7 SS	143	/*
	144	* Ensure that CPU power state is set to ON to avoid CPU
	145	* powerdomain transition on wfi
	146	*/
e97ca477	147	clkdm_wakeup(cpu1_clkdm);
b7806dc7	148	omap_set_pwrdm_state(cpu1_pwrdm, PWRDM_POWER_ON);
e97ca477	149	clkdm_allow_idle(cpu1_clkdm);
cd8ce159 CC	150
	151	if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
	152	while (gic_dist_disabled()) {
	153	udelay(1);
	154	cpu_relax();
	155	}
	156	gic_timer_retrigger();
	157	local_irq_enable();
	158	}
e97ca477 SS	159	} else {
	160	dsb_sev();
	161	booted = true;
	162	}
	163
b1cffebf	164	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
367cd31e	165
367cd31e SS	166	/*
	167	* Now the secondary core is starting up let it run its
	168	* calibrations, then wait for it to finish
	169	*/
	170	spin_unlock(&boot_lock);
	171
	172	return 0;
	173	}
	174
367cd31e SS	175	/*
	176	* Initialise the CPU possible map early - this describes the CPUs
	177	* which may be present or become present in the system.
	178	*/
06915321	179	static void __init omap4_smp_init_cpus(void)
367cd31e	180	{
283f708c SS	181	unsigned int i = 0, ncores = 1, cpu_id;
	182
	183	/* Use ARM cpuid check here, as SoC detection will not work so early */
ac52e83f	184	cpu_id = read_cpuid_id() & CPU_MASK;
283f708c SS	185	if (cpu_id == CPU_CORTEX_A9) {
	186	/*
	187	* Currently we can't call ioremap here because
	188	* SoC detection won't work until after init_early.
	189	*/
80d93756	190	scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base());
283f708c SS	191	BUG_ON(!scu_base);
	192	ncores = scu_get_core_count(scu_base);
	193	} else if (cpu_id == CPU_CORTEX_A15) {
	194	ncores = OMAP5_CORE_COUNT;
	195	}
367cd31e SS	196
367cd31e SS	197	/* sanity check */
a06f916b RK	198	if (ncores > nr_cpu_ids) {
	199	pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
	200	ncores, nr_cpu_ids);
	201	ncores = nr_cpu_ids;
367cd31e	202	}
367cd31e	203
bbc3d14e RK	204	for (i = 0; i < ncores; i++)
	205	set_cpu_possible(i, true);
	206	}
	207
06915321	208	static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
bbc3d14e	209	{
baf4b7d3	210	void *startup_addr = omap4_secondary_startup;
b699ddd1	211	void __iomem *base = omap_get_wakeupgen_base();
367cd31e	212
05c74a6c RK	213	/*
	214	* Initialise the SCU and wake up the secondary core using
	215	* wakeup_secondary().
	216	*/
283f708c SS	217	if (scu_base)
283f708c SS	218	scu_enable(scu_base);
b699ddd1 SS	219
b699ddd1 SS	220	if (cpu_is_omap446x()) {
baf4b7d3	221	startup_addr = omap4460_secondary_startup;
b699ddd1 SS	222	pm44xx_errata \|= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
	223	}
	224
	225	/*
	226	* Write the address of secondary startup routine into the
	227	* AuxCoreBoot1 where ROM code will jump and start executing
	228	* on secondary core once out of WFE
	229	* A barrier is added to ensure that write buffer is drained
	230	*/
	231	if (omap_secure_apis_support())
	232	omap_auxcoreboot_addr(virt_to_phys(startup_addr));
	233	else
	234	__raw_writel(virt_to_phys(omap5_secondary_startup),
	235	base + OMAP_AUX_CORE_BOOT_1);
	236
367cd31e	237	}
06915321 MZ	238
	239	struct smp_operations omap4_smp_ops __initdata = {
	240	.smp_init_cpus = omap4_smp_init_cpus,
	241	.smp_prepare_cpus = omap4_smp_prepare_cpus,
	242	.smp_secondary_init = omap4_secondary_init,
	243	.smp_boot_secondary = omap4_boot_secondary,
	244	#ifdef CONFIG_HOTPLUG_CPU
	245	.cpu_die = omap4_cpu_die,
	246	#endif
	247	};