Commit | Line | Data |
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fbc9be10 SS |
1 | /* |
2 | * OMAP4 specific common source file. | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments, Inc. | |
5 | * Author: | |
6 | * Santosh Shilimkar <santosh.shilimkar@ti.com> | |
7 | * | |
8 | * | |
9 | * This program is free software,you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/io.h> | |
cd8ce159 | 17 | #include <linux/irq.h> |
0529e315 | 18 | #include <linux/irqchip.h> |
fbc9be10 | 19 | #include <linux/platform_device.h> |
137d105d | 20 | #include <linux/memblock.h> |
7d7e1eba TL |
21 | #include <linux/of_irq.h> |
22 | #include <linux/of_platform.h> | |
23 | #include <linux/export.h> | |
520f7bd7 | 24 | #include <linux/irqchip/arm-gic.h> |
5c61e619 | 25 | #include <linux/irqchip/irq-crossbar.h> |
fd1c0786 | 26 | #include <linux/of_address.h> |
7b6d864b | 27 | #include <linux/reboot.h> |
1306c08a | 28 | #include <linux/genalloc.h> |
fbc9be10 | 29 | |
fbc9be10 | 30 | #include <asm/hardware/cache-l2x0.h> |
137d105d | 31 | #include <asm/mach/map.h> |
716a3dc2 | 32 | #include <asm/memblock.h> |
cd8ce159 | 33 | #include <asm/smp_twd.h> |
fbc9be10 | 34 | |
732231a7 | 35 | #include "omap-wakeupgen.h" |
dbc04161 | 36 | #include "soc.h" |
b6a4226c | 37 | #include "iomap.h" |
4e65331c | 38 | #include "common.h" |
2f334a38 | 39 | #include "prminst44xx.h" |
d9a16f9a | 40 | #include "prcm_mpu44xx.h" |
501f0c75 | 41 | #include "omap4-sar-layout.h" |
f7a9b8a1 | 42 | #include "omap-secure.h" |
bb772094 | 43 | #include "sram.h" |
fbc9be10 SS |
44 | |
45 | #ifdef CONFIG_CACHE_L2X0 | |
02afe8a7 | 46 | static void __iomem *l2cache_base; |
fbc9be10 SS |
47 | #endif |
48 | ||
501f0c75 | 49 | static void __iomem *sar_ram_base; |
ff999b8a | 50 | static void __iomem *gic_dist_base_addr; |
cd8ce159 CC |
51 | static void __iomem *twd_base; |
52 | ||
53 | #define IRQ_LOCALTIMER 29 | |
501f0c75 | 54 | |
137d105d SS |
55 | #ifdef CONFIG_OMAP4_ERRATA_I688 |
56 | /* Used to implement memory barrier on DRAM path */ | |
57 | #define OMAP4_DRAM_BARRIER_VA 0xfe600000 | |
58 | ||
59 | void __iomem *dram_sync, *sram_sync; | |
60 | ||
2ec1fc4e SS |
61 | static phys_addr_t paddr; |
62 | static u32 size; | |
63 | ||
137d105d SS |
64 | void omap_bus_sync(void) |
65 | { | |
66 | if (dram_sync && sram_sync) { | |
67 | writel_relaxed(readl_relaxed(dram_sync), dram_sync); | |
68 | writel_relaxed(readl_relaxed(sram_sync), sram_sync); | |
69 | isb(); | |
70 | } | |
71 | } | |
cc4ad907 | 72 | EXPORT_SYMBOL(omap_bus_sync); |
137d105d | 73 | |
1306c08a RN |
74 | static int __init omap4_sram_init(void) |
75 | { | |
76 | struct device_node *np; | |
77 | struct gen_pool *sram_pool; | |
78 | ||
79 | np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu"); | |
80 | if (!np) | |
81 | pr_warn("%s:Unable to allocate sram needed to handle errata I688\n", | |
82 | __func__); | |
83 | sram_pool = of_get_named_gen_pool(np, "sram", 0); | |
84 | if (!sram_pool) | |
85 | pr_warn("%s:Unable to get sram pool needed to handle errata I688\n", | |
86 | __func__); | |
87 | else | |
88 | sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE); | |
89 | ||
90 | return 0; | |
91 | } | |
92 | omap_arch_initcall(omap4_sram_init); | |
93 | ||
2ec1fc4e SS |
94 | /* Steal one page physical memory for barrier implementation */ |
95 | int __init omap_barrier_reserve_memblock(void) | |
137d105d | 96 | { |
137d105d SS |
97 | |
98 | size = ALIGN(PAGE_SIZE, SZ_1M); | |
716a3dc2 RK |
99 | paddr = arm_memblock_steal(size, SZ_1M); |
100 | ||
2ec1fc4e SS |
101 | return 0; |
102 | } | |
103 | ||
104 | void __init omap_barriers_init(void) | |
105 | { | |
106 | struct map_desc dram_io_desc[1]; | |
107 | ||
137d105d SS |
108 | dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA; |
109 | dram_io_desc[0].pfn = __phys_to_pfn(paddr); | |
110 | dram_io_desc[0].length = size; | |
2e2c9de2 | 111 | dram_io_desc[0].type = MT_MEMORY_RW_SO; |
137d105d SS |
112 | iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc)); |
113 | dram_sync = (void __iomem *) dram_io_desc[0].virtual; | |
137d105d SS |
114 | |
115 | pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n", | |
116 | (long long) paddr, dram_io_desc[0].virtual); | |
117 | ||
137d105d | 118 | } |
2ec1fc4e SS |
119 | #else |
120 | void __init omap_barriers_init(void) | |
121 | {} | |
137d105d SS |
122 | #endif |
123 | ||
ff999b8a SS |
124 | void gic_dist_disable(void) |
125 | { | |
126 | if (gic_dist_base_addr) | |
edfaf05c | 127 | writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL); |
ff999b8a SS |
128 | } |
129 | ||
74ed7bdc SG |
130 | void gic_dist_enable(void) |
131 | { | |
132 | if (gic_dist_base_addr) | |
edfaf05c | 133 | writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL); |
74ed7bdc SG |
134 | } |
135 | ||
cd8ce159 CC |
136 | bool gic_dist_disabled(void) |
137 | { | |
edfaf05c | 138 | return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1); |
cd8ce159 CC |
139 | } |
140 | ||
141 | void gic_timer_retrigger(void) | |
142 | { | |
edfaf05c VK |
143 | u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT); |
144 | u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET); | |
145 | u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL); | |
cd8ce159 CC |
146 | |
147 | if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) { | |
148 | /* | |
149 | * The local timer interrupt got lost while the distributor was | |
150 | * disabled. Ack the pending interrupt, and retrigger it. | |
151 | */ | |
152 | pr_warn("%s: lost localtimer interrupt\n", __func__); | |
edfaf05c | 153 | writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT); |
cd8ce159 | 154 | if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) { |
edfaf05c | 155 | writel_relaxed(1, twd_base + TWD_TIMER_COUNTER); |
cd8ce159 | 156 | twd_ctrl |= TWD_TIMER_CONTROL_ENABLE; |
edfaf05c | 157 | writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL); |
cd8ce159 CC |
158 | } |
159 | } | |
160 | } | |
161 | ||
fbc9be10 | 162 | #ifdef CONFIG_CACHE_L2X0 |
4e803c40 | 163 | |
02afe8a7 SS |
164 | void __iomem *omap4_get_l2cache_base(void) |
165 | { | |
166 | return l2cache_base; | |
167 | } | |
168 | ||
36827edd | 169 | static void omap4_l2c310_write_sec(unsigned long val, unsigned reg) |
4e803c40 | 170 | { |
36827edd | 171 | unsigned smc_op; |
4e803c40 | 172 | |
36827edd RK |
173 | switch (reg) { |
174 | case L2X0_CTRL: | |
175 | smc_op = OMAP4_MON_L2X0_CTRL_INDEX; | |
176 | break; | |
177 | ||
178 | case L2X0_AUX_CTRL: | |
179 | smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX; | |
180 | break; | |
181 | ||
182 | case L2X0_DEBUG_CTRL: | |
183 | smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX; | |
184 | break; | |
185 | ||
186 | case L310_PREFETCH_CTRL: | |
187 | smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX; | |
188 | break; | |
189 | ||
ba394f0b SN |
190 | case L310_POWER_CTRL: |
191 | pr_info_once("OMAP L2C310: ROM does not support power control setting\n"); | |
192 | return; | |
193 | ||
36827edd RK |
194 | default: |
195 | WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg); | |
196 | return; | |
197 | } | |
198 | ||
199 | omap_smc1(smc_op, val); | |
4bdb1577 SS |
200 | } |
201 | ||
b39b14e6 | 202 | int __init omap_l2_cache_init(void) |
fbc9be10 | 203 | { |
cef3d92c | 204 | u32 aux_ctrl; |
fbc9be10 SS |
205 | |
206 | /* Static mapping, never released */ | |
207 | l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K); | |
0db1803e SS |
208 | if (WARN_ON(!l2cache_base)) |
209 | return -ENOMEM; | |
fbc9be10 | 210 | |
cef3d92c | 211 | /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */ |
d196483d | 212 | aux_ctrl = L2C_AUX_CTRL_SHARED_OVERRIDE | |
1a5a954c | 213 | L310_AUX_CTRL_DATA_PREFETCH | |
36bccb11 | 214 | L310_AUX_CTRL_INSTR_PREFETCH; |
1773e60a | 215 | |
36827edd | 216 | outer_cache.write_sec = omap4_l2c310_write_sec; |
926fd45b | 217 | if (of_have_populated_dt()) |
d196483d | 218 | l2x0_of_init(aux_ctrl, 0xcf9fffff); |
926fd45b | 219 | else |
d196483d | 220 | l2x0_init(l2cache_base, aux_ctrl, 0xcf9fffff); |
4e803c40 | 221 | |
fbc9be10 SS |
222 | return 0; |
223 | } | |
fbc9be10 | 224 | #endif |
501f0c75 SS |
225 | |
226 | void __iomem *omap4_get_sar_ram_base(void) | |
227 | { | |
228 | return sar_ram_base; | |
229 | } | |
230 | ||
231 | /* | |
232 | * SAR RAM used to save and restore the HW | |
233 | * context in low power modes | |
234 | */ | |
235 | static int __init omap4_sar_ram_init(void) | |
236 | { | |
da0e02a1 SS |
237 | unsigned long sar_base; |
238 | ||
501f0c75 SS |
239 | /* |
240 | * To avoid code running on other OMAPs in | |
241 | * multi-omap builds | |
242 | */ | |
da0e02a1 SS |
243 | if (cpu_is_omap44xx()) |
244 | sar_base = OMAP44XX_SAR_RAM_BASE; | |
245 | else if (soc_is_omap54xx()) | |
246 | sar_base = OMAP54XX_SAR_RAM_BASE; | |
247 | else | |
501f0c75 SS |
248 | return -ENOMEM; |
249 | ||
250 | /* Static mapping, never released */ | |
da0e02a1 | 251 | sar_ram_base = ioremap(sar_base, SZ_16K); |
501f0c75 SS |
252 | if (WARN_ON(!sar_ram_base)) |
253 | return -ENOMEM; | |
254 | ||
255 | return 0; | |
256 | } | |
b76c8b19 | 257 | omap_early_initcall(omap4_sar_ram_init); |
1ee47b0a | 258 | |
c4082d49 S |
259 | void __init omap_gic_of_init(void) |
260 | { | |
fd1c0786 SS |
261 | struct device_node *np; |
262 | ||
263 | /* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */ | |
264 | if (!cpu_is_omap446x()) | |
265 | goto skip_errata_init; | |
266 | ||
267 | np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); | |
268 | gic_dist_base_addr = of_iomap(np, 0); | |
269 | WARN_ON(!gic_dist_base_addr); | |
270 | ||
271 | np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer"); | |
272 | twd_base = of_iomap(np, 0); | |
273 | WARN_ON(!twd_base); | |
274 | ||
275 | skip_errata_init: | |
c4082d49 | 276 | omap_wakeupgen_init(); |
5c61e619 S |
277 | #ifdef CONFIG_IRQ_CROSSBAR |
278 | irqcrossbar_init(); | |
279 | #endif | |
0529e315 | 280 | irqchip_init(); |
c4082d49 | 281 | } |