[deliverable/linux.git] / arch / arm / mach-omap2 / omap4-common.c

/*
 * OMAP4 specific common source file.
 *
 * Copyright (C) 2010 Texas Instruments, Inc.
 * Author:
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 *
 * This program is free software,you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/memblock.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/export.h>

#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>
#include <asm/memblock.h>

#include <plat/sram.h>
#include <plat/omap-secure.h>
#include <plat/mmc.h>

#include "omap-wakeupgen.h"

#include "soc.h"
#include "common.h"
#include "hsmmc.h"
#include "omap4-sar-layout.h"

#ifdef CONFIG_CACHE_L2X0
static void __iomem *l2cache_base;
#endif

static void __iomem *sar_ram_base;

#ifdef CONFIG_OMAP4_ERRATA_I688
/* Used to implement memory barrier on DRAM path */
#define OMAP4_DRAM_BARRIER_VA			0xfe600000

void __iomem *dram_sync, *sram_sync;

static phys_addr_t paddr;
static u32 size;

void omap_bus_sync(void)
{
	if (dram_sync && sram_sync) {
		writel_relaxed(readl_relaxed(dram_sync), dram_sync);
		writel_relaxed(readl_relaxed(sram_sync), sram_sync);
		isb();
	}
}
EXPORT_SYMBOL(omap_bus_sync);

/* Steal one page physical memory for barrier implementation */
int __init omap_barrier_reserve_memblock(void)
{

	size = ALIGN(PAGE_SIZE, SZ_1M);
	paddr = arm_memblock_steal(size, SZ_1M);

	return 0;
}

void __init omap_barriers_init(void)
{
	struct map_desc dram_io_desc[1];

	dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
	dram_io_desc[0].pfn = __phys_to_pfn(paddr);
	dram_io_desc[0].length = size;
	dram_io_desc[0].type = MT_MEMORY_SO;
	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
	dram_sync = (void __iomem *) dram_io_desc[0].virtual;
	sram_sync = (void __iomem *) OMAP4_SRAM_VA;

	pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
		(long long) paddr, dram_io_desc[0].virtual);

}
#else
void __init omap_barriers_init(void)
{}
#endif

void __init gic_init_irq(void)
{
	void __iomem *omap_irq_base;
	void __iomem *gic_dist_base_addr;

	/* Static mapping, never released */
	gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
	BUG_ON(!gic_dist_base_addr);

	/* Static mapping, never released */
	omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
	BUG_ON(!omap_irq_base);

	omap_wakeupgen_init();

	gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
}

#ifdef CONFIG_CACHE_L2X0

void __iomem *omap4_get_l2cache_base(void)
{
	return l2cache_base;
}

static void omap4_l2x0_disable(void)
{
	/* Disable PL310 L2 Cache controller */
	omap_smc1(0x102, 0x0);
}

static void omap4_l2x0_set_debug(unsigned long val)
{
	/* Program PL310 L2 Cache controller debug register */
	omap_smc1(0x100, val);
}

static int __init omap_l2_cache_init(void)
{
	u32 aux_ctrl = 0;

	/*
	 * To avoid code running on other OMAPs in
	 * multi-omap builds
	 */
	if (!cpu_is_omap44xx())
		return -ENODEV;

	/* Static mapping, never released */
	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
	if (WARN_ON(!l2cache_base))
		return -ENOMEM;

	/*
	 * 16-way associativity, parity disabled
	 * Way size - 32KB (es1.0)
	 * Way size - 64KB (es2.0 +)
	 */
	aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
			(0x1 << 25) |
			(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
			(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));

	if (omap_rev() == OMAP4430_REV_ES1_0) {
		aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
	} else {
		aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
			(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
			(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
			(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
			(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
	}
	if (omap_rev() != OMAP4430_REV_ES1_0)
		omap_smc1(0x109, aux_ctrl);

	/* Enable PL310 L2 Cache controller */
	omap_smc1(0x102, 0x1);

	if (of_have_populated_dt())
		l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
	else
		l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);

	/*
	 * Override default outer_cache.disable with a OMAP4
	 * specific one
	*/
	outer_cache.disable = omap4_l2x0_disable;
	outer_cache.set_debug = omap4_l2x0_set_debug;

	return 0;
}
early_initcall(omap_l2_cache_init);
#endif

void __iomem *omap4_get_sar_ram_base(void)
{
	return sar_ram_base;
}

/*
 * SAR RAM used to save and restore the HW
 * context in low power modes
 */
static int __init omap4_sar_ram_init(void)
{
	/*
	 * To avoid code running on other OMAPs in
	 * multi-omap builds
	 */
	if (!cpu_is_omap44xx())
		return -ENOMEM;

	/* Static mapping, never released */
	sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
	if (WARN_ON(!sar_ram_base))
		return -ENOMEM;

	return 0;
}
early_initcall(omap4_sar_ram_init);

static struct of_device_id irq_match[] __initdata = {
	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
	{ .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
	{ }
};

void __init omap_gic_of_init(void)
{
	omap_wakeupgen_init();
	of_irq_init(irq_match);
}

#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
static int omap4_twl6030_hsmmc_late_init(struct device *dev)
{
	int irq = 0;
	struct platform_device *pdev = container_of(dev,
				struct platform_device, dev);
	struct omap_mmc_platform_data *pdata = dev->platform_data;

	/* Setting MMC1 Card detect Irq */
	if (pdev->id == 0) {
		irq = twl6030_mmc_card_detect_config();
		if (irq < 0) {
			dev_err(dev, "%s: Error card detect config(%d)\n",
				__func__, irq);
			return irq;
		}
		pdata->slots[0].card_detect_irq = irq;
		pdata->slots[0].card_detect = twl6030_mmc_card_detect;
	}
	return 0;
}

static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
{
	struct omap_mmc_platform_data *pdata;

	/* dev can be null if CONFIG_MMC_OMAP_HS is not set */
	if (!dev) {
		pr_err("Failed %s\n", __func__);
		return;
	}
	pdata = dev->platform_data;
	pdata->init =	omap4_twl6030_hsmmc_late_init;
}

int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
	struct omap2_hsmmc_info *c;

	omap_hsmmc_init(controllers);
	for (c = controllers; c->mmc; c++) {
		/* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
		if (!c->pdev)
			continue;
		omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
	}

	return 0;
}
#else
int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
	return 0;
}
#endif
Commit	Line	Data
fbc9be10 SS	1	/*
	2	* OMAP4 specific common source file.
	3	*
	4	* Copyright (C) 2010 Texas Instruments, Inc.
	5	* Author:
	6	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	7	*
	8	*
	9	* This program is free software,you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/io.h>
	17	#include <linux/platform_device.h>
137d105d	18	#include <linux/memblock.h>
7d7e1eba TL	19	#include <linux/of_irq.h>
	20	#include <linux/of_platform.h>
	21	#include <linux/export.h>
fbc9be10 SS	22
	23	#include <asm/hardware/gic.h>
	24	#include <asm/hardware/cache-l2x0.h>
137d105d	25	#include <asm/mach/map.h>
716a3dc2	26	#include <asm/memblock.h>
fbc9be10	27
137d105d	28	#include <plat/sram.h>
2ec1fc4e	29	#include <plat/omap-secure.h>
1ee47b0a	30	#include <plat/mmc.h>
741e3a89	31
732231a7	32	#include "omap-wakeupgen.h"
4e65331c	33
dbc04161	34	#include "soc.h"
4e65331c	35	#include "common.h"
1ee47b0a	36	#include "hsmmc.h"
501f0c75	37	#include "omap4-sar-layout.h"
fbc9be10 SS	38
fbc9be10 SS	39	#ifdef CONFIG_CACHE_L2X0
02afe8a7	40	static void __iomem *l2cache_base;
fbc9be10 SS	41	#endif
fbc9be10 SS	42
501f0c75 SS	43	static void __iomem *sar_ram_base;
501f0c75 SS	44
137d105d SS	45	#ifdef CONFIG_OMAP4_ERRATA_I688
	46	/* Used to implement memory barrier on DRAM path */
	47	#define OMAP4_DRAM_BARRIER_VA 0xfe600000
	48
	49	void __iomem dram_sync, sram_sync;
	50
2ec1fc4e SS	51	static phys_addr_t paddr;
	52	static u32 size;
	53
137d105d SS	54	void omap_bus_sync(void)
	55	{
	56	if (dram_sync && sram_sync) {
	57	writel_relaxed(readl_relaxed(dram_sync), dram_sync);
	58	writel_relaxed(readl_relaxed(sram_sync), sram_sync);
	59	isb();
	60	}
	61	}
cc4ad907	62	EXPORT_SYMBOL(omap_bus_sync);
137d105d	63
2ec1fc4e SS	64	/* Steal one page physical memory for barrier implementation */
2ec1fc4e SS	65	int __init omap_barrier_reserve_memblock(void)
137d105d	66	{
137d105d SS	67
137d105d SS	68	size = ALIGN(PAGE_SIZE, SZ_1M);
716a3dc2 RK	69	paddr = arm_memblock_steal(size, SZ_1M);
716a3dc2 RK	70
2ec1fc4e SS	71	return 0;
	72	}
	73
	74	void __init omap_barriers_init(void)
	75	{
	76	struct map_desc dram_io_desc[1];
	77
137d105d SS	78	dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
	79	dram_io_desc[0].pfn = __phys_to_pfn(paddr);
	80	dram_io_desc[0].length = size;
	81	dram_io_desc[0].type = MT_MEMORY_SO;
	82	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
	83	dram_sync = (void __iomem *) dram_io_desc[0].virtual;
	84	sram_sync = (void __iomem *) OMAP4_SRAM_VA;
	85
	86	pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
	87	(long long) paddr, dram_io_desc[0].virtual);
	88
137d105d	89	}
2ec1fc4e SS	90	#else
	91	void __init omap_barriers_init(void)
	92	{}
137d105d SS	93	#endif
137d105d SS	94
fbc9be10 SS	95	void __init gic_init_irq(void)
fbc9be10 SS	96	{
ab65be26 MZ	97	void __iomem *omap_irq_base;
	98	void __iomem *gic_dist_base_addr;
	99
fbc9be10 SS	100	/* Static mapping, never released */
	101	gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
	102	BUG_ON(!gic_dist_base_addr);
fbc9be10 SS	103
fbc9be10 SS	104	/* Static mapping, never released */
741e3a89 TL	105	omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
741e3a89 TL	106	BUG_ON(!omap_irq_base);
b580b899	107
fcf6efa3 SS	108	omap_wakeupgen_init();
fcf6efa3 SS	109
741e3a89	110	gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
fbc9be10 SS	111	}
	112
	113	#ifdef CONFIG_CACHE_L2X0
4e803c40	114
02afe8a7 SS	115	void __iomem *omap4_get_l2cache_base(void)
	116	{
	117	return l2cache_base;
	118	}
	119
4e803c40 SS	120	static void omap4_l2x0_disable(void)
	121	{
	122	/* Disable PL310 L2 Cache controller */
	123	omap_smc1(0x102, 0x0);
	124	}
	125
4bdb1577 SS	126	static void omap4_l2x0_set_debug(unsigned long val)
	127	{
	128	/* Program PL310 L2 Cache controller debug register */
	129	omap_smc1(0x100, val);
	130	}
	131
fbc9be10 SS	132	static int __init omap_l2_cache_init(void)
fbc9be10 SS	133	{
1773e60a SS	134	u32 aux_ctrl = 0;
1773e60a SS	135
fbc9be10 SS	136	/*
	137	* To avoid code running on other OMAPs in
	138	* multi-omap builds
	139	*/
	140	if (!cpu_is_omap44xx())
	141	return -ENODEV;
	142
	143	/* Static mapping, never released */
	144	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
0db1803e SS	145	if (WARN_ON(!l2cache_base))
0db1803e SS	146	return -ENOMEM;
fbc9be10	147
fbc9be10	148	/*
a777b727 SS	149	* 16-way associativity, parity disabled
	150	* Way size - 32KB (es1.0)
	151	* Way size - 64KB (es2.0 +)
fbc9be10	152	*/
1773e60a SS	153	aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) \|
	154	(0x1 << 25) \|
	155	(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) \|
	156	(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
	157
11e02640	158	if (omap_rev() == OMAP4430_REV_ES1_0) {
1773e60a	159	aux_ctrl \|= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
11e02640 MR	160	} else {
11e02640 MR	161	aux_ctrl \|= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) \|
b0f20ff9	162	(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) \|
11e02640	163	(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) \|
b89cd71a SS	164	(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) \|
b89cd71a SS	165	(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
11e02640 MR	166	}
	167	if (omap_rev() != OMAP4430_REV_ES1_0)
	168	omap_smc1(0x109, aux_ctrl);
	169
	170	/* Enable PL310 L2 Cache controller */
	171	omap_smc1(0x102, 0x1);
1773e60a	172
926fd45b SS	173	if (of_have_populated_dt())
	174	l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
	175	else
	176	l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
fbc9be10	177
4e803c40 SS	178	/*
	179	* Override default outer_cache.disable with a OMAP4
	180	* specific one
	181	*/
	182	outer_cache.disable = omap4_l2x0_disable;
4bdb1577	183	outer_cache.set_debug = omap4_l2x0_set_debug;
4e803c40	184
fbc9be10 SS	185	return 0;
	186	}
	187	early_initcall(omap_l2_cache_init);
	188	#endif
501f0c75 SS	189
	190	void __iomem *omap4_get_sar_ram_base(void)
	191	{
	192	return sar_ram_base;
	193	}
	194
	195	/*
	196	* SAR RAM used to save and restore the HW
	197	* context in low power modes
	198	*/
	199	static int __init omap4_sar_ram_init(void)
	200	{
	201	/*
	202	* To avoid code running on other OMAPs in
	203	* multi-omap builds
	204	*/
	205	if (!cpu_is_omap44xx())
	206	return -ENOMEM;
	207
	208	/* Static mapping, never released */
	209	sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
	210	if (WARN_ON(!sar_ram_base))
	211	return -ENOMEM;
	212
	213	return 0;
	214	}
	215	early_initcall(omap4_sar_ram_init);
1ee47b0a	216
c4082d49 S	217	static struct of_device_id irq_match[] __initdata = {
c4082d49 S	218	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
0c1b6fac	219	{ .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
c4082d49 S	220	{ }
	221	};
	222
	223	void __init omap_gic_of_init(void)
	224	{
	225	omap_wakeupgen_init();
	226	of_irq_init(irq_match);
	227	}
	228
1ee47b0a B	229	#if defined(CONFIG_MMC_OMAP_HS) \|\| defined(CONFIG_MMC_OMAP_HS_MODULE)
	230	static int omap4_twl6030_hsmmc_late_init(struct device *dev)
	231	{
	232	int irq = 0;
	233	struct platform_device *pdev = container_of(dev,
	234	struct platform_device, dev);
	235	struct omap_mmc_platform_data *pdata = dev->platform_data;
	236
	237	/* Setting MMC1 Card detect Irq */
	238	if (pdev->id == 0) {
	239	irq = twl6030_mmc_card_detect_config();
	240	if (irq < 0) {
	241	dev_err(dev, "%s: Error card detect config(%d)\n",
	242	__func__, irq);
	243	return irq;
	244	}
	245	pdata->slots[0].card_detect_irq = irq;
	246	pdata->slots[0].card_detect = twl6030_mmc_card_detect;
	247	}
	248	return 0;
	249	}
	250
	251	static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
	252	{
	253	struct omap_mmc_platform_data *pdata;
	254
	255	/* dev can be null if CONFIG_MMC_OMAP_HS is not set */
	256	if (!dev) {
	257	pr_err("Failed %s\n", __func__);
	258	return;
	259	}
	260	pdata = dev->platform_data;
	261	pdata->init = omap4_twl6030_hsmmc_late_init;
	262	}
	263
	264	int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
	265	{
	266	struct omap2_hsmmc_info *c;
	267
	268	omap_hsmmc_init(controllers);
	269	for (c = controllers; c->mmc; c++) {
	270	/* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
	271	if (!c->pdev)
	272	continue;
	273	omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
	274	}
	275
	276	return 0;
	277	}
	278	#else
	279	int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
	280	{
	281	return 0;
	282	}
	283	#endif