projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| d660f9a2 SS |
1 | /* |
| 2 | * OMAP44xx secure APIs file. | |
| 3 | * | |
| 4 | * Copyright (C) 2010 Texas Instruments, Inc. | |
| 5 | * Written by Santosh Shilimkar <santosh.shilimkar@ti.com> | |
| 6 | * | |
| 7 | * | |
| 8 | * This program is free software,you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License version 2 as | |
| 10 | * published by the Free Software Foundation. | |
| 11 | */ | |
| 12 | ||
| 13 | #include <linux/linkage.h> | |
| 14 | ||
| 15 | /* | |
| 16 | * This is common routine to manage secure monitor API | |
| 17 | * used to modify the PL310 secure registers. | |
| 18 | * 'r0' contains the value to be modified and 'r12' contains | |
| 19 | * the monitor API number. It uses few CPU registers | |
| 20 | * internally and hence they need be backed up including | |
| 21 | * link register "lr". | |
| 22 | * Function signature : void omap_smc1(u32 fn, u32 arg) | |
| 23 | */ | |
| 24 | ||
| 25 | ENTRY(omap_smc1) | |
| 26 | stmfd sp!, {r2-r12, lr} | |
| 27 | mov r12, r0 | |
| 28 | mov r0, r1 | |
| 29 | dsb | |
| df571c4a | 30 | smc #0 |
| d660f9a2 | 31 | ldmfd sp!, {r2-r12, pc} |
| f96bdfa0 | 32 | ENDPROC(omap_smc1) |
| 3f9eaf09 SS |
33 | |
| 34 | ENTRY(omap_modify_auxcoreboot0) | |
| 35 | stmfd sp!, {r1-r12, lr} | |
| 36 | ldr r12, =0x104 | |
| 37 | dsb | |
| 38 | smc #0 | |
| 39 | ldmfd sp!, {r1-r12, pc} | |
| f96bdfa0 | 40 | ENDPROC(omap_modify_auxcoreboot0) |
| 3f9eaf09 SS |
41 | |
| 42 | ENTRY(omap_auxcoreboot_addr) | |
| 43 | stmfd sp!, {r2-r12, lr} | |
| 44 | ldr r12, =0x105 | |
| 45 | dsb | |
| 46 | smc #0 | |
| 47 | ldmfd sp!, {r2-r12, pc} | |
| f96bdfa0 | 48 | ENDPROC(omap_auxcoreboot_addr) |
| 3f9eaf09 SS |
49 | |
| 50 | ENTRY(omap_read_auxcoreboot0) | |
| 51 | stmfd sp!, {r2-r12, lr} | |
| 52 | ldr r12, =0x103 | |
| 53 | dsb | |
| 54 | smc #0 | |
| 55 | mov r0, r0, lsr #9 | |
| 56 | ldmfd sp!, {r2-r12, pc} | |
| f96bdfa0 | 57 | ENDPROC(omap_read_auxcoreboot0) |