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63c85238 PW |
1 | /* |
2 | * omap_hwmod implementation for OMAP2/3/4 | |
3 | * | |
550c8092 | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
30e105c0 | 5 | * Copyright (C) 2011-2012 Texas Instruments, Inc. |
63c85238 | 6 | * |
4788da26 PW |
7 | * Paul Walmsley, BenoƮt Cousson, Kevin Hilman |
8 | * | |
9 | * Created in collaboration with (alphabetical order): Thara Gopinath, | |
10 | * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand | |
11 | * Sawant, Santosh Shilimkar, Richard Woodruff | |
63c85238 PW |
12 | * |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | * | |
74ff3a68 PW |
17 | * Introduction |
18 | * ------------ | |
19 | * One way to view an OMAP SoC is as a collection of largely unrelated | |
20 | * IP blocks connected by interconnects. The IP blocks include | |
21 | * devices such as ARM processors, audio serial interfaces, UARTs, | |
22 | * etc. Some of these devices, like the DSP, are created by TI; | |
23 | * others, like the SGX, largely originate from external vendors. In | |
24 | * TI's documentation, on-chip devices are referred to as "OMAP | |
25 | * modules." Some of these IP blocks are identical across several | |
26 | * OMAP versions. Others are revised frequently. | |
63c85238 | 27 | * |
74ff3a68 PW |
28 | * These OMAP modules are tied together by various interconnects. |
29 | * Most of the address and data flow between modules is via OCP-based | |
30 | * interconnects such as the L3 and L4 buses; but there are other | |
31 | * interconnects that distribute the hardware clock tree, handle idle | |
32 | * and reset signaling, supply power, and connect the modules to | |
33 | * various pads or balls on the OMAP package. | |
34 | * | |
35 | * OMAP hwmod provides a consistent way to describe the on-chip | |
36 | * hardware blocks and their integration into the rest of the chip. | |
37 | * This description can be automatically generated from the TI | |
38 | * hardware database. OMAP hwmod provides a standard, consistent API | |
39 | * to reset, enable, idle, and disable these hardware blocks. And | |
40 | * hwmod provides a way for other core code, such as the Linux device | |
41 | * code or the OMAP power management and address space mapping code, | |
42 | * to query the hardware database. | |
43 | * | |
44 | * Using hwmod | |
45 | * ----------- | |
46 | * Drivers won't call hwmod functions directly. That is done by the | |
47 | * omap_device code, and in rare occasions, by custom integration code | |
48 | * in arch/arm/ *omap*. The omap_device code includes functions to | |
49 | * build a struct platform_device using omap_hwmod data, and that is | |
50 | * currently how hwmod data is communicated to drivers and to the | |
51 | * Linux driver model. Most drivers will call omap_hwmod functions only | |
52 | * indirectly, via pm_runtime*() functions. | |
53 | * | |
54 | * From a layering perspective, here is where the OMAP hwmod code | |
55 | * fits into the kernel software stack: | |
56 | * | |
57 | * +-------------------------------+ | |
58 | * | Device driver code | | |
59 | * | (e.g., drivers/) | | |
60 | * +-------------------------------+ | |
61 | * | Linux driver model | | |
62 | * | (platform_device / | | |
63 | * | platform_driver data/code) | | |
64 | * +-------------------------------+ | |
65 | * | OMAP core-driver integration | | |
66 | * |(arch/arm/mach-omap2/devices.c)| | |
67 | * +-------------------------------+ | |
68 | * | omap_device code | | |
69 | * | (../plat-omap/omap_device.c) | | |
70 | * +-------------------------------+ | |
71 | * ----> | omap_hwmod code/data | <----- | |
72 | * | (../mach-omap2/omap_hwmod*) | | |
73 | * +-------------------------------+ | |
74 | * | OMAP clock/PRCM/register fns | | |
edfaf05c | 75 | * | ({read,write}l_relaxed, clk*) | |
74ff3a68 PW |
76 | * +-------------------------------+ |
77 | * | |
78 | * Device drivers should not contain any OMAP-specific code or data in | |
79 | * them. They should only contain code to operate the IP block that | |
80 | * the driver is responsible for. This is because these IP blocks can | |
81 | * also appear in other SoCs, either from TI (such as DaVinci) or from | |
82 | * other manufacturers; and drivers should be reusable across other | |
83 | * platforms. | |
84 | * | |
85 | * The OMAP hwmod code also will attempt to reset and idle all on-chip | |
86 | * devices upon boot. The goal here is for the kernel to be | |
87 | * completely self-reliant and independent from bootloaders. This is | |
88 | * to ensure a repeatable configuration, both to ensure consistent | |
89 | * runtime behavior, and to make it easier for others to reproduce | |
90 | * bugs. | |
91 | * | |
92 | * OMAP module activity states | |
93 | * --------------------------- | |
94 | * The hwmod code considers modules to be in one of several activity | |
95 | * states. IP blocks start out in an UNKNOWN state, then once they | |
96 | * are registered via the hwmod code, proceed to the REGISTERED state. | |
97 | * Once their clock names are resolved to clock pointers, the module | |
98 | * enters the CLKS_INITED state; and finally, once the module has been | |
99 | * reset and the integration registers programmed, the INITIALIZED state | |
100 | * is entered. The hwmod code will then place the module into either | |
101 | * the IDLE state to save power, or in the case of a critical system | |
102 | * module, the ENABLED state. | |
103 | * | |
104 | * OMAP core integration code can then call omap_hwmod*() functions | |
105 | * directly to move the module between the IDLE, ENABLED, and DISABLED | |
106 | * states, as needed. This is done during both the PM idle loop, and | |
107 | * in the OMAP core integration code's implementation of the PM runtime | |
108 | * functions. | |
109 | * | |
110 | * References | |
111 | * ---------- | |
112 | * This is a partial list. | |
63c85238 PW |
113 | * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) |
114 | * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) | |
115 | * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) | |
116 | * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) | |
117 | * - Open Core Protocol Specification 2.2 | |
118 | * | |
119 | * To do: | |
63c85238 PW |
120 | * - handle IO mapping |
121 | * - bus throughput & module latency measurement code | |
122 | * | |
123 | * XXX add tests at the beginning of each function to ensure the hwmod is | |
124 | * in the appropriate state | |
125 | * XXX error return values should be checked to ensure that they are | |
126 | * appropriate | |
127 | */ | |
128 | #undef DEBUG | |
129 | ||
130 | #include <linux/kernel.h> | |
131 | #include <linux/errno.h> | |
132 | #include <linux/io.h> | |
f5dd3bb5 | 133 | #include <linux/clk-provider.h> |
63c85238 PW |
134 | #include <linux/delay.h> |
135 | #include <linux/err.h> | |
136 | #include <linux/list.h> | |
137 | #include <linux/mutex.h> | |
dc6d1cda | 138 | #include <linux/spinlock.h> |
abc2d545 | 139 | #include <linux/slab.h> |
2221b5cd | 140 | #include <linux/bootmem.h> |
f7b861b7 | 141 | #include <linux/cpu.h> |
079abade SS |
142 | #include <linux/of.h> |
143 | #include <linux/of_address.h> | |
63c85238 | 144 | |
fa200222 PW |
145 | #include <asm/system_misc.h> |
146 | ||
a135eaae | 147 | #include "clock.h" |
2a296c8f | 148 | #include "omap_hwmod.h" |
63c85238 | 149 | |
dbc04161 TL |
150 | #include "soc.h" |
151 | #include "common.h" | |
152 | #include "clockdomain.h" | |
153 | #include "powerdomain.h" | |
ff4ae5d9 PW |
154 | #include "cm2xxx.h" |
155 | #include "cm3xxx.h" | |
1688bf19 | 156 | #include "cm33xx.h" |
b13159af | 157 | #include "prm.h" |
139563ad | 158 | #include "prm3xxx.h" |
d198b514 | 159 | #include "prm44xx.h" |
1688bf19 | 160 | #include "prm33xx.h" |
eaac329d | 161 | #include "prminst44xx.h" |
8d9af88f | 162 | #include "mux.h" |
5165882a | 163 | #include "pm.h" |
63c85238 | 164 | |
63c85238 | 165 | /* Name of the OMAP hwmod for the MPU */ |
5c2c0296 | 166 | #define MPU_INITIATOR_NAME "mpu" |
63c85238 | 167 | |
2221b5cd PW |
168 | /* |
169 | * Number of struct omap_hwmod_link records per struct | |
170 | * omap_hwmod_ocp_if record (master->slave and slave->master) | |
171 | */ | |
172 | #define LINKS_PER_OCP_IF 2 | |
173 | ||
9ebfd285 KH |
174 | /** |
175 | * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations | |
176 | * @enable_module: function to enable a module (via MODULEMODE) | |
177 | * @disable_module: function to disable a module (via MODULEMODE) | |
178 | * | |
179 | * XXX Eventually this functionality will be hidden inside the PRM/CM | |
180 | * device drivers. Until then, this should avoid huge blocks of cpu_is_*() | |
181 | * conditionals in this code. | |
182 | */ | |
183 | struct omap_hwmod_soc_ops { | |
184 | void (*enable_module)(struct omap_hwmod *oh); | |
185 | int (*disable_module)(struct omap_hwmod *oh); | |
8f6aa8ee | 186 | int (*wait_target_ready)(struct omap_hwmod *oh); |
b8249cf2 KH |
187 | int (*assert_hardreset)(struct omap_hwmod *oh, |
188 | struct omap_hwmod_rst_info *ohri); | |
189 | int (*deassert_hardreset)(struct omap_hwmod *oh, | |
190 | struct omap_hwmod_rst_info *ohri); | |
191 | int (*is_hardreset_asserted)(struct omap_hwmod *oh, | |
192 | struct omap_hwmod_rst_info *ohri); | |
0a179eaa | 193 | int (*init_clkdm)(struct omap_hwmod *oh); |
e6d3a8b0 RN |
194 | void (*update_context_lost)(struct omap_hwmod *oh); |
195 | int (*get_context_lost)(struct omap_hwmod *oh); | |
9ebfd285 KH |
196 | }; |
197 | ||
198 | /* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */ | |
199 | static struct omap_hwmod_soc_ops soc_ops; | |
200 | ||
63c85238 PW |
201 | /* omap_hwmod_list contains all registered struct omap_hwmods */ |
202 | static LIST_HEAD(omap_hwmod_list); | |
203 | ||
63c85238 PW |
204 | /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ |
205 | static struct omap_hwmod *mpu_oh; | |
206 | ||
5165882a VB |
207 | /* io_chain_lock: used to serialize reconfigurations of the I/O chain */ |
208 | static DEFINE_SPINLOCK(io_chain_lock); | |
209 | ||
2221b5cd PW |
210 | /* |
211 | * linkspace: ptr to a buffer that struct omap_hwmod_link records are | |
212 | * allocated from - used to reduce the number of small memory | |
213 | * allocations, which has a significant impact on performance | |
214 | */ | |
215 | static struct omap_hwmod_link *linkspace; | |
216 | ||
217 | /* | |
218 | * free_ls, max_ls: array indexes into linkspace; representing the | |
219 | * next free struct omap_hwmod_link index, and the maximum number of | |
220 | * struct omap_hwmod_link records allocated (respectively) | |
221 | */ | |
222 | static unsigned short free_ls, max_ls, ls_supp; | |
63c85238 | 223 | |
9ebfd285 KH |
224 | /* inited: set to true once the hwmod code is initialized */ |
225 | static bool inited; | |
226 | ||
63c85238 PW |
227 | /* Private functions */ |
228 | ||
5d95dde7 | 229 | /** |
11cd4b94 | 230 | * _fetch_next_ocp_if - return the next OCP interface in a list |
2221b5cd | 231 | * @p: ptr to a ptr to the list_head inside the ocp_if to return |
11cd4b94 PW |
232 | * @i: pointer to the index of the element pointed to by @p in the list |
233 | * | |
234 | * Return a pointer to the struct omap_hwmod_ocp_if record | |
235 | * containing the struct list_head pointed to by @p, and increment | |
236 | * @p such that a future call to this routine will return the next | |
237 | * record. | |
5d95dde7 PW |
238 | */ |
239 | static struct omap_hwmod_ocp_if *_fetch_next_ocp_if(struct list_head **p, | |
5d95dde7 PW |
240 | int *i) |
241 | { | |
242 | struct omap_hwmod_ocp_if *oi; | |
243 | ||
11cd4b94 PW |
244 | oi = list_entry(*p, struct omap_hwmod_link, node)->ocp_if; |
245 | *p = (*p)->next; | |
2221b5cd | 246 | |
5d95dde7 PW |
247 | *i = *i + 1; |
248 | ||
249 | return oi; | |
250 | } | |
251 | ||
63c85238 PW |
252 | /** |
253 | * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy | |
254 | * @oh: struct omap_hwmod * | |
255 | * | |
256 | * Load the current value of the hwmod OCP_SYSCONFIG register into the | |
257 | * struct omap_hwmod for later use. Returns -EINVAL if the hwmod has no | |
258 | * OCP_SYSCONFIG register or 0 upon success. | |
259 | */ | |
260 | static int _update_sysc_cache(struct omap_hwmod *oh) | |
261 | { | |
43b40992 PW |
262 | if (!oh->class->sysc) { |
263 | WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
264 | return -EINVAL; |
265 | } | |
266 | ||
267 | /* XXX ensure module interface clock is up */ | |
268 | ||
cc7a1d2a | 269 | oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 | 270 | |
43b40992 | 271 | if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) |
883edfdd | 272 | oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; |
63c85238 PW |
273 | |
274 | return 0; | |
275 | } | |
276 | ||
277 | /** | |
278 | * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register | |
279 | * @v: OCP_SYSCONFIG value to write | |
280 | * @oh: struct omap_hwmod * | |
281 | * | |
43b40992 PW |
282 | * Write @v into the module class' OCP_SYSCONFIG register, if it has |
283 | * one. No return value. | |
63c85238 PW |
284 | */ |
285 | static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | |
286 | { | |
43b40992 PW |
287 | if (!oh->class->sysc) { |
288 | WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
289 | return; |
290 | } | |
291 | ||
292 | /* XXX ensure module interface clock is up */ | |
293 | ||
233cbe5b RN |
294 | /* Module might have lost context, always update cache and register */ |
295 | oh->_sysc_cache = v; | |
296 | omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); | |
63c85238 PW |
297 | } |
298 | ||
299 | /** | |
300 | * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v | |
301 | * @oh: struct omap_hwmod * | |
302 | * @standbymode: MIDLEMODE field bits | |
303 | * @v: pointer to register contents to modify | |
304 | * | |
305 | * Update the master standby mode bits in @v to be @standbymode for | |
306 | * the @oh hwmod. Does not write to the hardware. Returns -EINVAL | |
307 | * upon error or 0 upon success. | |
308 | */ | |
309 | static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, | |
310 | u32 *v) | |
311 | { | |
358f0e63 TG |
312 | u32 mstandby_mask; |
313 | u8 mstandby_shift; | |
314 | ||
43b40992 PW |
315 | if (!oh->class->sysc || |
316 | !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE)) | |
63c85238 PW |
317 | return -EINVAL; |
318 | ||
43b40992 PW |
319 | if (!oh->class->sysc->sysc_fields) { |
320 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
321 | return -EINVAL; |
322 | } | |
323 | ||
43b40992 | 324 | mstandby_shift = oh->class->sysc->sysc_fields->midle_shift; |
358f0e63 TG |
325 | mstandby_mask = (0x3 << mstandby_shift); |
326 | ||
327 | *v &= ~mstandby_mask; | |
328 | *v |= __ffs(standbymode) << mstandby_shift; | |
63c85238 PW |
329 | |
330 | return 0; | |
331 | } | |
332 | ||
333 | /** | |
334 | * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v | |
335 | * @oh: struct omap_hwmod * | |
336 | * @idlemode: SIDLEMODE field bits | |
337 | * @v: pointer to register contents to modify | |
338 | * | |
339 | * Update the slave idle mode bits in @v to be @idlemode for the @oh | |
340 | * hwmod. Does not write to the hardware. Returns -EINVAL upon error | |
341 | * or 0 upon success. | |
342 | */ | |
343 | static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) | |
344 | { | |
358f0e63 TG |
345 | u32 sidle_mask; |
346 | u8 sidle_shift; | |
347 | ||
43b40992 PW |
348 | if (!oh->class->sysc || |
349 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE)) | |
63c85238 PW |
350 | return -EINVAL; |
351 | ||
43b40992 PW |
352 | if (!oh->class->sysc->sysc_fields) { |
353 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
354 | return -EINVAL; |
355 | } | |
356 | ||
43b40992 | 357 | sidle_shift = oh->class->sysc->sysc_fields->sidle_shift; |
358f0e63 TG |
358 | sidle_mask = (0x3 << sidle_shift); |
359 | ||
360 | *v &= ~sidle_mask; | |
361 | *v |= __ffs(idlemode) << sidle_shift; | |
63c85238 PW |
362 | |
363 | return 0; | |
364 | } | |
365 | ||
366 | /** | |
367 | * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
368 | * @oh: struct omap_hwmod * | |
369 | * @clockact: CLOCKACTIVITY field bits | |
370 | * @v: pointer to register contents to modify | |
371 | * | |
372 | * Update the clockactivity mode bits in @v to be @clockact for the | |
373 | * @oh hwmod. Used for additional powersaving on some modules. Does | |
374 | * not write to the hardware. Returns -EINVAL upon error or 0 upon | |
375 | * success. | |
376 | */ | |
377 | static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) | |
378 | { | |
358f0e63 TG |
379 | u32 clkact_mask; |
380 | u8 clkact_shift; | |
381 | ||
43b40992 PW |
382 | if (!oh->class->sysc || |
383 | !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) | |
63c85238 PW |
384 | return -EINVAL; |
385 | ||
43b40992 PW |
386 | if (!oh->class->sysc->sysc_fields) { |
387 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
388 | return -EINVAL; |
389 | } | |
390 | ||
43b40992 | 391 | clkact_shift = oh->class->sysc->sysc_fields->clkact_shift; |
358f0e63 TG |
392 | clkact_mask = (0x3 << clkact_shift); |
393 | ||
394 | *v &= ~clkact_mask; | |
395 | *v |= clockact << clkact_shift; | |
63c85238 PW |
396 | |
397 | return 0; | |
398 | } | |
399 | ||
400 | /** | |
313a76ee | 401 | * _set_softreset: set OCP_SYSCONFIG.SOFTRESET bit in @v |
63c85238 PW |
402 | * @oh: struct omap_hwmod * |
403 | * @v: pointer to register contents to modify | |
404 | * | |
405 | * Set the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
406 | * error or 0 upon success. | |
407 | */ | |
408 | static int _set_softreset(struct omap_hwmod *oh, u32 *v) | |
409 | { | |
358f0e63 TG |
410 | u32 softrst_mask; |
411 | ||
43b40992 PW |
412 | if (!oh->class->sysc || |
413 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
63c85238 PW |
414 | return -EINVAL; |
415 | ||
43b40992 PW |
416 | if (!oh->class->sysc->sysc_fields) { |
417 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
418 | return -EINVAL; |
419 | } | |
420 | ||
43b40992 | 421 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); |
358f0e63 TG |
422 | |
423 | *v |= softrst_mask; | |
63c85238 PW |
424 | |
425 | return 0; | |
426 | } | |
427 | ||
313a76ee RQ |
428 | /** |
429 | * _clear_softreset: clear OCP_SYSCONFIG.SOFTRESET bit in @v | |
430 | * @oh: struct omap_hwmod * | |
431 | * @v: pointer to register contents to modify | |
432 | * | |
433 | * Clear the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
434 | * error or 0 upon success. | |
435 | */ | |
436 | static int _clear_softreset(struct omap_hwmod *oh, u32 *v) | |
437 | { | |
438 | u32 softrst_mask; | |
439 | ||
440 | if (!oh->class->sysc || | |
441 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
442 | return -EINVAL; | |
443 | ||
444 | if (!oh->class->sysc->sysc_fields) { | |
445 | WARN(1, | |
446 | "omap_hwmod: %s: sysc_fields absent for sysconfig class\n", | |
447 | oh->name); | |
448 | return -EINVAL; | |
449 | } | |
450 | ||
451 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); | |
452 | ||
453 | *v &= ~softrst_mask; | |
454 | ||
455 | return 0; | |
456 | } | |
457 | ||
613ad0e9 TK |
458 | /** |
459 | * _wait_softreset_complete - wait for an OCP softreset to complete | |
460 | * @oh: struct omap_hwmod * to wait on | |
461 | * | |
462 | * Wait until the IP block represented by @oh reports that its OCP | |
463 | * softreset is complete. This can be triggered by software (see | |
464 | * _ocp_softreset()) or by hardware upon returning from off-mode (one | |
465 | * example is HSMMC). Waits for up to MAX_MODULE_SOFTRESET_WAIT | |
466 | * microseconds. Returns the number of microseconds waited. | |
467 | */ | |
468 | static int _wait_softreset_complete(struct omap_hwmod *oh) | |
469 | { | |
470 | struct omap_hwmod_class_sysconfig *sysc; | |
471 | u32 softrst_mask; | |
472 | int c = 0; | |
473 | ||
474 | sysc = oh->class->sysc; | |
475 | ||
476 | if (sysc->sysc_flags & SYSS_HAS_RESET_STATUS) | |
477 | omap_test_timeout((omap_hwmod_read(oh, sysc->syss_offs) | |
478 | & SYSS_RESETDONE_MASK), | |
479 | MAX_MODULE_SOFTRESET_WAIT, c); | |
480 | else if (sysc->sysc_flags & SYSC_HAS_RESET_STATUS) { | |
481 | softrst_mask = (0x1 << sysc->sysc_fields->srst_shift); | |
482 | omap_test_timeout(!(omap_hwmod_read(oh, sysc->sysc_offs) | |
483 | & softrst_mask), | |
484 | MAX_MODULE_SOFTRESET_WAIT, c); | |
485 | } | |
486 | ||
487 | return c; | |
488 | } | |
489 | ||
6668546f KVA |
490 | /** |
491 | * _set_dmadisable: set OCP_SYSCONFIG.DMADISABLE bit in @v | |
492 | * @oh: struct omap_hwmod * | |
493 | * | |
494 | * The DMADISABLE bit is a semi-automatic bit present in sysconfig register | |
495 | * of some modules. When the DMA must perform read/write accesses, the | |
496 | * DMADISABLE bit is cleared by the hardware. But when the DMA must stop | |
497 | * for power management, software must set the DMADISABLE bit back to 1. | |
498 | * | |
499 | * Set the DMADISABLE bit in @v for hwmod @oh. Returns -EINVAL upon | |
500 | * error or 0 upon success. | |
501 | */ | |
502 | static int _set_dmadisable(struct omap_hwmod *oh) | |
503 | { | |
504 | u32 v; | |
505 | u32 dmadisable_mask; | |
506 | ||
507 | if (!oh->class->sysc || | |
508 | !(oh->class->sysc->sysc_flags & SYSC_HAS_DMADISABLE)) | |
509 | return -EINVAL; | |
510 | ||
511 | if (!oh->class->sysc->sysc_fields) { | |
512 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
513 | return -EINVAL; | |
514 | } | |
515 | ||
516 | /* clocks must be on for this operation */ | |
517 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
518 | pr_warn("omap_hwmod: %s: dma can be disabled only from enabled state\n", oh->name); | |
519 | return -EINVAL; | |
520 | } | |
521 | ||
522 | pr_debug("omap_hwmod: %s: setting DMADISABLE\n", oh->name); | |
523 | ||
524 | v = oh->_sysc_cache; | |
525 | dmadisable_mask = | |
526 | (0x1 << oh->class->sysc->sysc_fields->dmadisable_shift); | |
527 | v |= dmadisable_mask; | |
528 | _write_sysconfig(v, oh); | |
529 | ||
530 | return 0; | |
531 | } | |
532 | ||
726072e5 PW |
533 | /** |
534 | * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v | |
535 | * @oh: struct omap_hwmod * | |
536 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
537 | * @v: pointer to register contents to modify | |
538 | * | |
539 | * Update the module autoidle bit in @v to be @autoidle for the @oh | |
540 | * hwmod. The autoidle bit controls whether the module can gate | |
541 | * internal clocks automatically when it isn't doing anything; the | |
542 | * exact function of this bit varies on a per-module basis. This | |
543 | * function does not write to the hardware. Returns -EINVAL upon | |
544 | * error or 0 upon success. | |
545 | */ | |
546 | static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | |
547 | u32 *v) | |
548 | { | |
358f0e63 TG |
549 | u32 autoidle_mask; |
550 | u8 autoidle_shift; | |
551 | ||
43b40992 PW |
552 | if (!oh->class->sysc || |
553 | !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE)) | |
726072e5 PW |
554 | return -EINVAL; |
555 | ||
43b40992 PW |
556 | if (!oh->class->sysc->sysc_fields) { |
557 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
558 | return -EINVAL; |
559 | } | |
560 | ||
43b40992 | 561 | autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift; |
8985b63d | 562 | autoidle_mask = (0x1 << autoidle_shift); |
358f0e63 TG |
563 | |
564 | *v &= ~autoidle_mask; | |
565 | *v |= autoidle << autoidle_shift; | |
726072e5 PW |
566 | |
567 | return 0; | |
568 | } | |
569 | ||
eceec009 G |
570 | /** |
571 | * _set_idle_ioring_wakeup - enable/disable IO pad wakeup on hwmod idle for mux | |
572 | * @oh: struct omap_hwmod * | |
573 | * @set_wake: bool value indicating to set (true) or clear (false) wakeup enable | |
574 | * | |
575 | * Set or clear the I/O pad wakeup flag in the mux entries for the | |
576 | * hwmod @oh. This function changes the @oh->mux->pads_dynamic array | |
577 | * in memory. If the hwmod is currently idled, and the new idle | |
578 | * values don't match the previous ones, this function will also | |
579 | * update the SCM PADCTRL registers. Otherwise, if the hwmod is not | |
580 | * currently idled, this function won't touch the hardware: the new | |
581 | * mux settings are written to the SCM PADCTRL registers when the | |
582 | * hwmod is idled. No return value. | |
583 | */ | |
584 | static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake) | |
585 | { | |
586 | struct omap_device_pad *pad; | |
587 | bool change = false; | |
588 | u16 prev_idle; | |
589 | int j; | |
590 | ||
591 | if (!oh->mux || !oh->mux->enabled) | |
592 | return; | |
593 | ||
594 | for (j = 0; j < oh->mux->nr_pads_dynamic; j++) { | |
595 | pad = oh->mux->pads_dynamic[j]; | |
596 | ||
597 | if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP)) | |
598 | continue; | |
599 | ||
600 | prev_idle = pad->idle; | |
601 | ||
602 | if (set_wake) | |
603 | pad->idle |= OMAP_WAKEUP_EN; | |
604 | else | |
605 | pad->idle &= ~OMAP_WAKEUP_EN; | |
606 | ||
607 | if (prev_idle != pad->idle) | |
608 | change = true; | |
609 | } | |
610 | ||
611 | if (change && oh->_state == _HWMOD_STATE_IDLE) | |
612 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); | |
613 | } | |
614 | ||
63c85238 PW |
615 | /** |
616 | * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
617 | * @oh: struct omap_hwmod * | |
618 | * | |
619 | * Allow the hardware module @oh to send wakeups. Returns -EINVAL | |
620 | * upon error or 0 upon success. | |
621 | */ | |
5a7ddcbd | 622 | static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 623 | { |
43b40992 | 624 | if (!oh->class->sysc || |
86009eb3 | 625 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
626 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
627 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
628 | return -EINVAL; |
629 | ||
43b40992 PW |
630 | if (!oh->class->sysc->sysc_fields) { |
631 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
632 | return -EINVAL; |
633 | } | |
634 | ||
1fe74113 BC |
635 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
636 | *v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift; | |
63c85238 | 637 | |
86009eb3 BC |
638 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
639 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
724019b0 BC |
640 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
641 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
86009eb3 | 642 | |
63c85238 PW |
643 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
644 | ||
63c85238 PW |
645 | return 0; |
646 | } | |
647 | ||
648 | /** | |
649 | * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
650 | * @oh: struct omap_hwmod * | |
651 | * | |
652 | * Prevent the hardware module @oh to send wakeups. Returns -EINVAL | |
653 | * upon error or 0 upon success. | |
654 | */ | |
5a7ddcbd | 655 | static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 656 | { |
43b40992 | 657 | if (!oh->class->sysc || |
86009eb3 | 658 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
659 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
660 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
661 | return -EINVAL; |
662 | ||
43b40992 PW |
663 | if (!oh->class->sysc->sysc_fields) { |
664 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
665 | return -EINVAL; |
666 | } | |
667 | ||
1fe74113 BC |
668 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
669 | *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift); | |
63c85238 | 670 | |
86009eb3 BC |
671 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
672 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v); | |
724019b0 | 673 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
561038f0 | 674 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART, v); |
86009eb3 | 675 | |
63c85238 PW |
676 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
677 | ||
63c85238 PW |
678 | return 0; |
679 | } | |
680 | ||
f5dd3bb5 RN |
681 | static struct clockdomain *_get_clkdm(struct omap_hwmod *oh) |
682 | { | |
c4a1ea2c RN |
683 | struct clk_hw_omap *clk; |
684 | ||
f5dd3bb5 RN |
685 | if (oh->clkdm) { |
686 | return oh->clkdm; | |
687 | } else if (oh->_clk) { | |
924f9498 TK |
688 | if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC) |
689 | return NULL; | |
f5dd3bb5 RN |
690 | clk = to_clk_hw_omap(__clk_get_hw(oh->_clk)); |
691 | return clk->clkdm; | |
f5dd3bb5 RN |
692 | } |
693 | return NULL; | |
694 | } | |
695 | ||
63c85238 PW |
696 | /** |
697 | * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active | |
698 | * @oh: struct omap_hwmod * | |
699 | * | |
700 | * Prevent the hardware module @oh from entering idle while the | |
701 | * hardare module initiator @init_oh is active. Useful when a module | |
702 | * will be accessed by a particular initiator (e.g., if a module will | |
703 | * be accessed by the IVA, there should be a sleepdep between the IVA | |
704 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
705 | * mode. If the clockdomain is marked as not needing autodeps, return |
706 | * 0 without doing anything. Otherwise, returns -EINVAL upon error or | |
707 | * passes along clkdm_add_sleepdep() value upon success. | |
63c85238 PW |
708 | */ |
709 | static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
710 | { | |
f5dd3bb5 RN |
711 | struct clockdomain *clkdm, *init_clkdm; |
712 | ||
713 | clkdm = _get_clkdm(oh); | |
714 | init_clkdm = _get_clkdm(init_oh); | |
715 | ||
716 | if (!clkdm || !init_clkdm) | |
63c85238 PW |
717 | return -EINVAL; |
718 | ||
f5dd3bb5 | 719 | if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS) |
570b54c7 PW |
720 | return 0; |
721 | ||
f5dd3bb5 | 722 | return clkdm_add_sleepdep(clkdm, init_clkdm); |
63c85238 PW |
723 | } |
724 | ||
725 | /** | |
726 | * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active | |
727 | * @oh: struct omap_hwmod * | |
728 | * | |
729 | * Allow the hardware module @oh to enter idle while the hardare | |
730 | * module initiator @init_oh is active. Useful when a module will not | |
731 | * be accessed by a particular initiator (e.g., if a module will not | |
732 | * be accessed by the IVA, there should be no sleepdep between the IVA | |
733 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
734 | * mode. If the clockdomain is marked as not needing autodeps, return |
735 | * 0 without doing anything. Returns -EINVAL upon error or passes | |
736 | * along clkdm_del_sleepdep() value upon success. | |
63c85238 PW |
737 | */ |
738 | static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
739 | { | |
f5dd3bb5 RN |
740 | struct clockdomain *clkdm, *init_clkdm; |
741 | ||
742 | clkdm = _get_clkdm(oh); | |
743 | init_clkdm = _get_clkdm(init_oh); | |
744 | ||
745 | if (!clkdm || !init_clkdm) | |
63c85238 PW |
746 | return -EINVAL; |
747 | ||
f5dd3bb5 | 748 | if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS) |
570b54c7 PW |
749 | return 0; |
750 | ||
f5dd3bb5 | 751 | return clkdm_del_sleepdep(clkdm, init_clkdm); |
63c85238 PW |
752 | } |
753 | ||
754 | /** | |
755 | * _init_main_clk - get a struct clk * for the the hwmod's main functional clk | |
756 | * @oh: struct omap_hwmod * | |
757 | * | |
758 | * Called from _init_clocks(). Populates the @oh _clk (main | |
759 | * functional clock pointer) if a main_clk is present. Returns 0 on | |
760 | * success or -EINVAL on error. | |
761 | */ | |
762 | static int _init_main_clk(struct omap_hwmod *oh) | |
763 | { | |
63c85238 PW |
764 | int ret = 0; |
765 | ||
50ebdac2 | 766 | if (!oh->main_clk) |
63c85238 PW |
767 | return 0; |
768 | ||
6ea74cb9 RN |
769 | oh->_clk = clk_get(NULL, oh->main_clk); |
770 | if (IS_ERR(oh->_clk)) { | |
3d0cb73e JP |
771 | pr_warn("omap_hwmod: %s: cannot clk_get main_clk %s\n", |
772 | oh->name, oh->main_clk); | |
63403384 | 773 | return -EINVAL; |
dc75925d | 774 | } |
4d7cb45e RN |
775 | /* |
776 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
777 | * to do something meaningful. Today its just a no-op. | |
778 | * If clk_prepare() is used at some point to do things like | |
779 | * voltage scaling etc, then this would have to be moved to | |
780 | * some point where subsystems like i2c and pmic become | |
781 | * available. | |
782 | */ | |
783 | clk_prepare(oh->_clk); | |
63c85238 | 784 | |
f5dd3bb5 | 785 | if (!_get_clkdm(oh)) |
3bb05dbf | 786 | pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n", |
5dcc3b97 | 787 | oh->name, oh->main_clk); |
81d7c6ff | 788 | |
63c85238 PW |
789 | return ret; |
790 | } | |
791 | ||
792 | /** | |
887adeac | 793 | * _init_interface_clks - get a struct clk * for the the hwmod's interface clks |
63c85238 PW |
794 | * @oh: struct omap_hwmod * |
795 | * | |
796 | * Called from _init_clocks(). Populates the @oh OCP slave interface | |
797 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
798 | */ | |
799 | static int _init_interface_clks(struct omap_hwmod *oh) | |
800 | { | |
5d95dde7 | 801 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 802 | struct list_head *p; |
63c85238 | 803 | struct clk *c; |
5d95dde7 | 804 | int i = 0; |
63c85238 PW |
805 | int ret = 0; |
806 | ||
11cd4b94 | 807 | p = oh->slave_ports.next; |
2221b5cd | 808 | |
5d95dde7 | 809 | while (i < oh->slaves_cnt) { |
11cd4b94 | 810 | os = _fetch_next_ocp_if(&p, &i); |
50ebdac2 | 811 | if (!os->clk) |
63c85238 PW |
812 | continue; |
813 | ||
6ea74cb9 RN |
814 | c = clk_get(NULL, os->clk); |
815 | if (IS_ERR(c)) { | |
3d0cb73e JP |
816 | pr_warn("omap_hwmod: %s: cannot clk_get interface_clk %s\n", |
817 | oh->name, os->clk); | |
63c85238 | 818 | ret = -EINVAL; |
0e7dc862 | 819 | continue; |
dc75925d | 820 | } |
63c85238 | 821 | os->_clk = c; |
4d7cb45e RN |
822 | /* |
823 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
824 | * to do something meaningful. Today its just a no-op. | |
825 | * If clk_prepare() is used at some point to do things like | |
826 | * voltage scaling etc, then this would have to be moved to | |
827 | * some point where subsystems like i2c and pmic become | |
828 | * available. | |
829 | */ | |
830 | clk_prepare(os->_clk); | |
63c85238 PW |
831 | } |
832 | ||
833 | return ret; | |
834 | } | |
835 | ||
836 | /** | |
837 | * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks | |
838 | * @oh: struct omap_hwmod * | |
839 | * | |
840 | * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk | |
841 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
842 | */ | |
843 | static int _init_opt_clks(struct omap_hwmod *oh) | |
844 | { | |
845 | struct omap_hwmod_opt_clk *oc; | |
846 | struct clk *c; | |
847 | int i; | |
848 | int ret = 0; | |
849 | ||
850 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { | |
6ea74cb9 RN |
851 | c = clk_get(NULL, oc->clk); |
852 | if (IS_ERR(c)) { | |
3d0cb73e JP |
853 | pr_warn("omap_hwmod: %s: cannot clk_get opt_clk %s\n", |
854 | oh->name, oc->clk); | |
63c85238 | 855 | ret = -EINVAL; |
0e7dc862 | 856 | continue; |
dc75925d | 857 | } |
63c85238 | 858 | oc->_clk = c; |
4d7cb45e RN |
859 | /* |
860 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
861 | * to do something meaningful. Today its just a no-op. | |
862 | * If clk_prepare() is used at some point to do things like | |
863 | * voltage scaling etc, then this would have to be moved to | |
864 | * some point where subsystems like i2c and pmic become | |
865 | * available. | |
866 | */ | |
867 | clk_prepare(oc->_clk); | |
63c85238 PW |
868 | } |
869 | ||
870 | return ret; | |
871 | } | |
872 | ||
873 | /** | |
874 | * _enable_clocks - enable hwmod main clock and interface clocks | |
875 | * @oh: struct omap_hwmod * | |
876 | * | |
877 | * Enables all clocks necessary for register reads and writes to succeed | |
878 | * on the hwmod @oh. Returns 0. | |
879 | */ | |
880 | static int _enable_clocks(struct omap_hwmod *oh) | |
881 | { | |
5d95dde7 | 882 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 883 | struct list_head *p; |
5d95dde7 | 884 | int i = 0; |
63c85238 PW |
885 | |
886 | pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); | |
887 | ||
4d3ae5a9 | 888 | if (oh->_clk) |
63c85238 PW |
889 | clk_enable(oh->_clk); |
890 | ||
11cd4b94 | 891 | p = oh->slave_ports.next; |
2221b5cd | 892 | |
5d95dde7 | 893 | while (i < oh->slaves_cnt) { |
11cd4b94 | 894 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 895 | |
5d95dde7 PW |
896 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) |
897 | clk_enable(os->_clk); | |
63c85238 PW |
898 | } |
899 | ||
900 | /* The opt clocks are controlled by the device driver. */ | |
901 | ||
902 | return 0; | |
903 | } | |
904 | ||
905 | /** | |
906 | * _disable_clocks - disable hwmod main clock and interface clocks | |
907 | * @oh: struct omap_hwmod * | |
908 | * | |
909 | * Disables the hwmod @oh main functional and interface clocks. Returns 0. | |
910 | */ | |
911 | static int _disable_clocks(struct omap_hwmod *oh) | |
912 | { | |
5d95dde7 | 913 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 914 | struct list_head *p; |
5d95dde7 | 915 | int i = 0; |
63c85238 PW |
916 | |
917 | pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); | |
918 | ||
4d3ae5a9 | 919 | if (oh->_clk) |
63c85238 PW |
920 | clk_disable(oh->_clk); |
921 | ||
11cd4b94 | 922 | p = oh->slave_ports.next; |
2221b5cd | 923 | |
5d95dde7 | 924 | while (i < oh->slaves_cnt) { |
11cd4b94 | 925 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 926 | |
5d95dde7 PW |
927 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) |
928 | clk_disable(os->_clk); | |
63c85238 PW |
929 | } |
930 | ||
931 | /* The opt clocks are controlled by the device driver. */ | |
932 | ||
933 | return 0; | |
934 | } | |
935 | ||
96835af9 BC |
936 | static void _enable_optional_clocks(struct omap_hwmod *oh) |
937 | { | |
938 | struct omap_hwmod_opt_clk *oc; | |
939 | int i; | |
940 | ||
941 | pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name); | |
942 | ||
943 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
944 | if (oc->_clk) { | |
945 | pr_debug("omap_hwmod: enable %s:%s\n", oc->role, | |
5dcc3b97 | 946 | __clk_get_name(oc->_clk)); |
96835af9 BC |
947 | clk_enable(oc->_clk); |
948 | } | |
949 | } | |
950 | ||
951 | static void _disable_optional_clocks(struct omap_hwmod *oh) | |
952 | { | |
953 | struct omap_hwmod_opt_clk *oc; | |
954 | int i; | |
955 | ||
956 | pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name); | |
957 | ||
958 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
959 | if (oc->_clk) { | |
960 | pr_debug("omap_hwmod: disable %s:%s\n", oc->role, | |
5dcc3b97 | 961 | __clk_get_name(oc->_clk)); |
96835af9 BC |
962 | clk_disable(oc->_clk); |
963 | } | |
964 | } | |
965 | ||
45c38252 | 966 | /** |
3d9f0327 | 967 | * _omap4_enable_module - enable CLKCTRL modulemode on OMAP4 |
45c38252 BC |
968 | * @oh: struct omap_hwmod * |
969 | * | |
970 | * Enables the PRCM module mode related to the hwmod @oh. | |
971 | * No return value. | |
972 | */ | |
3d9f0327 | 973 | static void _omap4_enable_module(struct omap_hwmod *oh) |
45c38252 | 974 | { |
45c38252 BC |
975 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) |
976 | return; | |
977 | ||
3d9f0327 KH |
978 | pr_debug("omap_hwmod: %s: %s: %d\n", |
979 | oh->name, __func__, oh->prcm.omap4.modulemode); | |
45c38252 | 980 | |
128603f0 TK |
981 | omap_cm_module_enable(oh->prcm.omap4.modulemode, |
982 | oh->clkdm->prcm_partition, | |
983 | oh->clkdm->cm_inst, oh->prcm.omap4.clkctrl_offs); | |
1688bf19 VH |
984 | } |
985 | ||
45c38252 | 986 | /** |
bfc141e3 BC |
987 | * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4 |
988 | * @oh: struct omap_hwmod * | |
989 | * | |
990 | * Wait for a module @oh to enter slave idle. Returns 0 if the module | |
991 | * does not have an IDLEST bit or if the module successfully enters | |
992 | * slave idle; otherwise, pass along the return value of the | |
993 | * appropriate *_cm*_wait_module_idle() function. | |
994 | */ | |
995 | static int _omap4_wait_target_disable(struct omap_hwmod *oh) | |
996 | { | |
2b026d13 | 997 | if (!oh) |
bfc141e3 BC |
998 | return -EINVAL; |
999 | ||
2b026d13 | 1000 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT || !oh->clkdm) |
bfc141e3 BC |
1001 | return 0; |
1002 | ||
1003 | if (oh->flags & HWMOD_NO_IDLEST) | |
1004 | return 0; | |
1005 | ||
a8ae5afa TK |
1006 | return omap_cm_wait_module_idle(oh->clkdm->prcm_partition, |
1007 | oh->clkdm->cm_inst, | |
1008 | oh->prcm.omap4.clkctrl_offs, 0); | |
1688bf19 VH |
1009 | } |
1010 | ||
212738a4 PW |
1011 | /** |
1012 | * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh | |
1013 | * @oh: struct omap_hwmod *oh | |
1014 | * | |
1015 | * Count and return the number of MPU IRQs associated with the hwmod | |
1016 | * @oh. Used to allocate struct resource data. Returns 0 if @oh is | |
1017 | * NULL. | |
1018 | */ | |
1019 | static int _count_mpu_irqs(struct omap_hwmod *oh) | |
1020 | { | |
1021 | struct omap_hwmod_irq_info *ohii; | |
1022 | int i = 0; | |
1023 | ||
1024 | if (!oh || !oh->mpu_irqs) | |
1025 | return 0; | |
1026 | ||
1027 | do { | |
1028 | ohii = &oh->mpu_irqs[i++]; | |
1029 | } while (ohii->irq != -1); | |
1030 | ||
cc1b0765 | 1031 | return i-1; |
212738a4 PW |
1032 | } |
1033 | ||
bc614958 PW |
1034 | /** |
1035 | * _count_sdma_reqs - count the number of SDMA request lines associated with @oh | |
1036 | * @oh: struct omap_hwmod *oh | |
1037 | * | |
1038 | * Count and return the number of SDMA request lines associated with | |
1039 | * the hwmod @oh. Used to allocate struct resource data. Returns 0 | |
1040 | * if @oh is NULL. | |
1041 | */ | |
1042 | static int _count_sdma_reqs(struct omap_hwmod *oh) | |
1043 | { | |
1044 | struct omap_hwmod_dma_info *ohdi; | |
1045 | int i = 0; | |
1046 | ||
1047 | if (!oh || !oh->sdma_reqs) | |
1048 | return 0; | |
1049 | ||
1050 | do { | |
1051 | ohdi = &oh->sdma_reqs[i++]; | |
1052 | } while (ohdi->dma_req != -1); | |
1053 | ||
cc1b0765 | 1054 | return i-1; |
bc614958 PW |
1055 | } |
1056 | ||
78183f3f PW |
1057 | /** |
1058 | * _count_ocp_if_addr_spaces - count the number of address space entries for @oh | |
1059 | * @oh: struct omap_hwmod *oh | |
1060 | * | |
1061 | * Count and return the number of address space ranges associated with | |
1062 | * the hwmod @oh. Used to allocate struct resource data. Returns 0 | |
1063 | * if @oh is NULL. | |
1064 | */ | |
1065 | static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os) | |
1066 | { | |
1067 | struct omap_hwmod_addr_space *mem; | |
1068 | int i = 0; | |
1069 | ||
1070 | if (!os || !os->addr) | |
1071 | return 0; | |
1072 | ||
1073 | do { | |
1074 | mem = &os->addr[i++]; | |
1075 | } while (mem->pa_start != mem->pa_end); | |
1076 | ||
cc1b0765 | 1077 | return i-1; |
78183f3f PW |
1078 | } |
1079 | ||
5e8370f1 PW |
1080 | /** |
1081 | * _get_mpu_irq_by_name - fetch MPU interrupt line number by name | |
1082 | * @oh: struct omap_hwmod * to operate on | |
1083 | * @name: pointer to the name of the MPU interrupt number to fetch (optional) | |
1084 | * @irq: pointer to an unsigned int to store the MPU IRQ number to | |
1085 | * | |
1086 | * Retrieve a MPU hardware IRQ line number named by @name associated | |
1087 | * with the IP block pointed to by @oh. The IRQ number will be filled | |
1088 | * into the address pointed to by @dma. When @name is non-null, the | |
1089 | * IRQ line number associated with the named entry will be returned. | |
1090 | * If @name is null, the first matching entry will be returned. Data | |
1091 | * order is not meaningful in hwmod data, so callers are strongly | |
1092 | * encouraged to use a non-null @name whenever possible to avoid | |
1093 | * unpredictable effects if hwmod data is later added that causes data | |
1094 | * ordering to change. Returns 0 upon success or a negative error | |
1095 | * code upon error. | |
1096 | */ | |
1097 | static int _get_mpu_irq_by_name(struct omap_hwmod *oh, const char *name, | |
1098 | unsigned int *irq) | |
1099 | { | |
1100 | int i; | |
1101 | bool found = false; | |
1102 | ||
1103 | if (!oh->mpu_irqs) | |
1104 | return -ENOENT; | |
1105 | ||
1106 | i = 0; | |
1107 | while (oh->mpu_irqs[i].irq != -1) { | |
1108 | if (name == oh->mpu_irqs[i].name || | |
1109 | !strcmp(name, oh->mpu_irqs[i].name)) { | |
1110 | found = true; | |
1111 | break; | |
1112 | } | |
1113 | i++; | |
1114 | } | |
1115 | ||
1116 | if (!found) | |
1117 | return -ENOENT; | |
1118 | ||
1119 | *irq = oh->mpu_irqs[i].irq; | |
1120 | ||
1121 | return 0; | |
1122 | } | |
1123 | ||
1124 | /** | |
1125 | * _get_sdma_req_by_name - fetch SDMA request line ID by name | |
1126 | * @oh: struct omap_hwmod * to operate on | |
1127 | * @name: pointer to the name of the SDMA request line to fetch (optional) | |
1128 | * @dma: pointer to an unsigned int to store the request line ID to | |
1129 | * | |
1130 | * Retrieve an SDMA request line ID named by @name on the IP block | |
1131 | * pointed to by @oh. The ID will be filled into the address pointed | |
1132 | * to by @dma. When @name is non-null, the request line ID associated | |
1133 | * with the named entry will be returned. If @name is null, the first | |
1134 | * matching entry will be returned. Data order is not meaningful in | |
1135 | * hwmod data, so callers are strongly encouraged to use a non-null | |
1136 | * @name whenever possible to avoid unpredictable effects if hwmod | |
1137 | * data is later added that causes data ordering to change. Returns 0 | |
1138 | * upon success or a negative error code upon error. | |
1139 | */ | |
1140 | static int _get_sdma_req_by_name(struct omap_hwmod *oh, const char *name, | |
1141 | unsigned int *dma) | |
1142 | { | |
1143 | int i; | |
1144 | bool found = false; | |
1145 | ||
1146 | if (!oh->sdma_reqs) | |
1147 | return -ENOENT; | |
1148 | ||
1149 | i = 0; | |
1150 | while (oh->sdma_reqs[i].dma_req != -1) { | |
1151 | if (name == oh->sdma_reqs[i].name || | |
1152 | !strcmp(name, oh->sdma_reqs[i].name)) { | |
1153 | found = true; | |
1154 | break; | |
1155 | } | |
1156 | i++; | |
1157 | } | |
1158 | ||
1159 | if (!found) | |
1160 | return -ENOENT; | |
1161 | ||
1162 | *dma = oh->sdma_reqs[i].dma_req; | |
1163 | ||
1164 | return 0; | |
1165 | } | |
1166 | ||
1167 | /** | |
1168 | * _get_addr_space_by_name - fetch address space start & end by name | |
1169 | * @oh: struct omap_hwmod * to operate on | |
1170 | * @name: pointer to the name of the address space to fetch (optional) | |
1171 | * @pa_start: pointer to a u32 to store the starting address to | |
1172 | * @pa_end: pointer to a u32 to store the ending address to | |
1173 | * | |
1174 | * Retrieve address space start and end addresses for the IP block | |
1175 | * pointed to by @oh. The data will be filled into the addresses | |
1176 | * pointed to by @pa_start and @pa_end. When @name is non-null, the | |
1177 | * address space data associated with the named entry will be | |
1178 | * returned. If @name is null, the first matching entry will be | |
1179 | * returned. Data order is not meaningful in hwmod data, so callers | |
1180 | * are strongly encouraged to use a non-null @name whenever possible | |
1181 | * to avoid unpredictable effects if hwmod data is later added that | |
1182 | * causes data ordering to change. Returns 0 upon success or a | |
1183 | * negative error code upon error. | |
1184 | */ | |
1185 | static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name, | |
1186 | u32 *pa_start, u32 *pa_end) | |
1187 | { | |
1188 | int i, j; | |
1189 | struct omap_hwmod_ocp_if *os; | |
2221b5cd | 1190 | struct list_head *p = NULL; |
5e8370f1 PW |
1191 | bool found = false; |
1192 | ||
11cd4b94 | 1193 | p = oh->slave_ports.next; |
2221b5cd | 1194 | |
5d95dde7 PW |
1195 | i = 0; |
1196 | while (i < oh->slaves_cnt) { | |
11cd4b94 | 1197 | os = _fetch_next_ocp_if(&p, &i); |
5e8370f1 PW |
1198 | |
1199 | if (!os->addr) | |
1200 | return -ENOENT; | |
1201 | ||
1202 | j = 0; | |
1203 | while (os->addr[j].pa_start != os->addr[j].pa_end) { | |
1204 | if (name == os->addr[j].name || | |
1205 | !strcmp(name, os->addr[j].name)) { | |
1206 | found = true; | |
1207 | break; | |
1208 | } | |
1209 | j++; | |
1210 | } | |
1211 | ||
1212 | if (found) | |
1213 | break; | |
1214 | } | |
1215 | ||
1216 | if (!found) | |
1217 | return -ENOENT; | |
1218 | ||
1219 | *pa_start = os->addr[j].pa_start; | |
1220 | *pa_end = os->addr[j].pa_end; | |
1221 | ||
1222 | return 0; | |
1223 | } | |
1224 | ||
63c85238 | 1225 | /** |
24dbc213 | 1226 | * _save_mpu_port_index - find and save the index to @oh's MPU port |
63c85238 PW |
1227 | * @oh: struct omap_hwmod * |
1228 | * | |
24dbc213 PW |
1229 | * Determines the array index of the OCP slave port that the MPU uses |
1230 | * to address the device, and saves it into the struct omap_hwmod. | |
1231 | * Intended to be called during hwmod registration only. No return | |
1232 | * value. | |
63c85238 | 1233 | */ |
24dbc213 | 1234 | static void __init _save_mpu_port_index(struct omap_hwmod *oh) |
63c85238 | 1235 | { |
24dbc213 | 1236 | struct omap_hwmod_ocp_if *os = NULL; |
11cd4b94 | 1237 | struct list_head *p; |
5d95dde7 | 1238 | int i = 0; |
63c85238 | 1239 | |
5d95dde7 | 1240 | if (!oh) |
24dbc213 PW |
1241 | return; |
1242 | ||
1243 | oh->_int_flags |= _HWMOD_NO_MPU_PORT; | |
63c85238 | 1244 | |
11cd4b94 | 1245 | p = oh->slave_ports.next; |
2221b5cd | 1246 | |
5d95dde7 | 1247 | while (i < oh->slaves_cnt) { |
11cd4b94 | 1248 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 1249 | if (os->user & OCP_USER_MPU) { |
2221b5cd | 1250 | oh->_mpu_port = os; |
24dbc213 | 1251 | oh->_int_flags &= ~_HWMOD_NO_MPU_PORT; |
63c85238 PW |
1252 | break; |
1253 | } | |
1254 | } | |
1255 | ||
24dbc213 | 1256 | return; |
63c85238 PW |
1257 | } |
1258 | ||
2d6141ba PW |
1259 | /** |
1260 | * _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU | |
1261 | * @oh: struct omap_hwmod * | |
1262 | * | |
1263 | * Given a pointer to a struct omap_hwmod record @oh, return a pointer | |
1264 | * to the struct omap_hwmod_ocp_if record that is used by the MPU to | |
1265 | * communicate with the IP block. This interface need not be directly | |
1266 | * connected to the MPU (and almost certainly is not), but is directly | |
1267 | * connected to the IP block represented by @oh. Returns a pointer | |
1268 | * to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon | |
1269 | * error or if there does not appear to be a path from the MPU to this | |
1270 | * IP block. | |
1271 | */ | |
1272 | static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh) | |
1273 | { | |
1274 | if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0) | |
1275 | return NULL; | |
1276 | ||
11cd4b94 | 1277 | return oh->_mpu_port; |
2d6141ba PW |
1278 | }; |
1279 | ||
63c85238 | 1280 | /** |
c9aafd23 | 1281 | * _find_mpu_rt_addr_space - return MPU register target address space for @oh |
63c85238 PW |
1282 | * @oh: struct omap_hwmod * |
1283 | * | |
c9aafd23 PW |
1284 | * Returns a pointer to the struct omap_hwmod_addr_space record representing |
1285 | * the register target MPU address space; or returns NULL upon error. | |
63c85238 | 1286 | */ |
c9aafd23 | 1287 | static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap_hwmod *oh) |
63c85238 PW |
1288 | { |
1289 | struct omap_hwmod_ocp_if *os; | |
1290 | struct omap_hwmod_addr_space *mem; | |
c9aafd23 | 1291 | int found = 0, i = 0; |
63c85238 | 1292 | |
2d6141ba | 1293 | os = _find_mpu_rt_port(oh); |
24dbc213 | 1294 | if (!os || !os->addr) |
78183f3f PW |
1295 | return NULL; |
1296 | ||
1297 | do { | |
1298 | mem = &os->addr[i++]; | |
1299 | if (mem->flags & ADDR_TYPE_RT) | |
63c85238 | 1300 | found = 1; |
78183f3f | 1301 | } while (!found && mem->pa_start != mem->pa_end); |
63c85238 | 1302 | |
c9aafd23 | 1303 | return (found) ? mem : NULL; |
63c85238 PW |
1304 | } |
1305 | ||
1306 | /** | |
74ff3a68 | 1307 | * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG |
63c85238 PW |
1308 | * @oh: struct omap_hwmod * |
1309 | * | |
006c7f18 PW |
1310 | * Ensure that the OCP_SYSCONFIG register for the IP block represented |
1311 | * by @oh is set to indicate to the PRCM that the IP block is active. | |
1312 | * Usually this means placing the module into smart-idle mode and | |
1313 | * smart-standby, but if there is a bug in the automatic idle handling | |
1314 | * for the IP block, it may need to be placed into the force-idle or | |
1315 | * no-idle variants of these modes. No return value. | |
63c85238 | 1316 | */ |
74ff3a68 | 1317 | static void _enable_sysc(struct omap_hwmod *oh) |
63c85238 | 1318 | { |
43b40992 | 1319 | u8 idlemode, sf; |
63c85238 | 1320 | u32 v; |
006c7f18 | 1321 | bool clkdm_act; |
f5dd3bb5 | 1322 | struct clockdomain *clkdm; |
63c85238 | 1323 | |
43b40992 | 1324 | if (!oh->class->sysc) |
63c85238 PW |
1325 | return; |
1326 | ||
613ad0e9 TK |
1327 | /* |
1328 | * Wait until reset has completed, this is needed as the IP | |
1329 | * block is reset automatically by hardware in some cases | |
1330 | * (off-mode for example), and the drivers require the | |
1331 | * IP to be ready when they access it | |
1332 | */ | |
1333 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1334 | _enable_optional_clocks(oh); | |
1335 | _wait_softreset_complete(oh); | |
1336 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1337 | _disable_optional_clocks(oh); | |
1338 | ||
63c85238 | 1339 | v = oh->_sysc_cache; |
43b40992 | 1340 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1341 | |
f5dd3bb5 | 1342 | clkdm = _get_clkdm(oh); |
43b40992 | 1343 | if (sf & SYSC_HAS_SIDLEMODE) { |
ca43ea34 RN |
1344 | if (oh->flags & HWMOD_SWSUP_SIDLE || |
1345 | oh->flags & HWMOD_SWSUP_SIDLE_ACT) { | |
35513171 RN |
1346 | idlemode = HWMOD_IDLEMODE_NO; |
1347 | } else { | |
1348 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1349 | _enable_wakeup(oh, &v); | |
1350 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) | |
1351 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1352 | else | |
1353 | idlemode = HWMOD_IDLEMODE_SMART; | |
1354 | } | |
1355 | ||
1356 | /* | |
1357 | * This is special handling for some IPs like | |
1358 | * 32k sync timer. Force them to idle! | |
1359 | */ | |
f5dd3bb5 | 1360 | clkdm_act = (clkdm && clkdm->flags & CLKDM_ACTIVE_WITH_MPU); |
006c7f18 PW |
1361 | if (clkdm_act && !(oh->class->sysc->idlemodes & |
1362 | (SIDLE_SMART | SIDLE_SMART_WKUP))) | |
1363 | idlemode = HWMOD_IDLEMODE_FORCE; | |
35513171 | 1364 | |
63c85238 PW |
1365 | _set_slave_idlemode(oh, idlemode, &v); |
1366 | } | |
1367 | ||
43b40992 | 1368 | if (sf & SYSC_HAS_MIDLEMODE) { |
092bc089 GI |
1369 | if (oh->flags & HWMOD_FORCE_MSTANDBY) { |
1370 | idlemode = HWMOD_IDLEMODE_FORCE; | |
1371 | } else if (oh->flags & HWMOD_SWSUP_MSTANDBY) { | |
724019b0 BC |
1372 | idlemode = HWMOD_IDLEMODE_NO; |
1373 | } else { | |
1374 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1375 | _enable_wakeup(oh, &v); | |
1376 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1377 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1378 | else | |
1379 | idlemode = HWMOD_IDLEMODE_SMART; | |
1380 | } | |
63c85238 PW |
1381 | _set_master_standbymode(oh, idlemode, &v); |
1382 | } | |
1383 | ||
a16b1f7f PW |
1384 | /* |
1385 | * XXX The clock framework should handle this, by | |
1386 | * calling into this code. But this must wait until the | |
1387 | * clock structures are tagged with omap_hwmod entries | |
1388 | */ | |
43b40992 PW |
1389 | if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) && |
1390 | (sf & SYSC_HAS_CLOCKACTIVITY)) | |
1391 | _set_clockactivity(oh, oh->class->sysc->clockact, &v); | |
63c85238 | 1392 | |
127500cc JH |
1393 | /* If the cached value is the same as the new value, skip the write */ |
1394 | if (oh->_sysc_cache != v) | |
1395 | _write_sysconfig(v, oh); | |
78f26e87 HH |
1396 | |
1397 | /* | |
1398 | * Set the autoidle bit only after setting the smartidle bit | |
1399 | * Setting this will not have any impact on the other modules. | |
1400 | */ | |
1401 | if (sf & SYSC_HAS_AUTOIDLE) { | |
1402 | idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? | |
1403 | 0 : 1; | |
1404 | _set_module_autoidle(oh, idlemode, &v); | |
1405 | _write_sysconfig(v, oh); | |
1406 | } | |
63c85238 PW |
1407 | } |
1408 | ||
1409 | /** | |
74ff3a68 | 1410 | * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1411 | * @oh: struct omap_hwmod * |
1412 | * | |
1413 | * If module is marked as SWSUP_SIDLE, force the module into slave | |
1414 | * idle; otherwise, configure it for smart-idle. If module is marked | |
1415 | * as SWSUP_MSUSPEND, force the module into master standby; otherwise, | |
1416 | * configure it for smart-standby. No return value. | |
1417 | */ | |
74ff3a68 | 1418 | static void _idle_sysc(struct omap_hwmod *oh) |
63c85238 | 1419 | { |
43b40992 | 1420 | u8 idlemode, sf; |
63c85238 PW |
1421 | u32 v; |
1422 | ||
43b40992 | 1423 | if (!oh->class->sysc) |
63c85238 PW |
1424 | return; |
1425 | ||
1426 | v = oh->_sysc_cache; | |
43b40992 | 1427 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1428 | |
43b40992 | 1429 | if (sf & SYSC_HAS_SIDLEMODE) { |
35513171 | 1430 | if (oh->flags & HWMOD_SWSUP_SIDLE) { |
006c7f18 | 1431 | idlemode = HWMOD_IDLEMODE_FORCE; |
35513171 RN |
1432 | } else { |
1433 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1434 | _enable_wakeup(oh, &v); | |
1435 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) | |
1436 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1437 | else | |
1438 | idlemode = HWMOD_IDLEMODE_SMART; | |
1439 | } | |
63c85238 PW |
1440 | _set_slave_idlemode(oh, idlemode, &v); |
1441 | } | |
1442 | ||
43b40992 | 1443 | if (sf & SYSC_HAS_MIDLEMODE) { |
092bc089 GI |
1444 | if ((oh->flags & HWMOD_SWSUP_MSTANDBY) || |
1445 | (oh->flags & HWMOD_FORCE_MSTANDBY)) { | |
724019b0 BC |
1446 | idlemode = HWMOD_IDLEMODE_FORCE; |
1447 | } else { | |
1448 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1449 | _enable_wakeup(oh, &v); | |
1450 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1451 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1452 | else | |
1453 | idlemode = HWMOD_IDLEMODE_SMART; | |
1454 | } | |
63c85238 PW |
1455 | _set_master_standbymode(oh, idlemode, &v); |
1456 | } | |
1457 | ||
1458 | _write_sysconfig(v, oh); | |
1459 | } | |
1460 | ||
1461 | /** | |
74ff3a68 | 1462 | * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1463 | * @oh: struct omap_hwmod * |
1464 | * | |
1465 | * Force the module into slave idle and master suspend. No return | |
1466 | * value. | |
1467 | */ | |
74ff3a68 | 1468 | static void _shutdown_sysc(struct omap_hwmod *oh) |
63c85238 PW |
1469 | { |
1470 | u32 v; | |
43b40992 | 1471 | u8 sf; |
63c85238 | 1472 | |
43b40992 | 1473 | if (!oh->class->sysc) |
63c85238 PW |
1474 | return; |
1475 | ||
1476 | v = oh->_sysc_cache; | |
43b40992 | 1477 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1478 | |
43b40992 | 1479 | if (sf & SYSC_HAS_SIDLEMODE) |
63c85238 PW |
1480 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1481 | ||
43b40992 | 1482 | if (sf & SYSC_HAS_MIDLEMODE) |
63c85238 PW |
1483 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1484 | ||
43b40992 | 1485 | if (sf & SYSC_HAS_AUTOIDLE) |
726072e5 | 1486 | _set_module_autoidle(oh, 1, &v); |
63c85238 PW |
1487 | |
1488 | _write_sysconfig(v, oh); | |
1489 | } | |
1490 | ||
1491 | /** | |
1492 | * _lookup - find an omap_hwmod by name | |
1493 | * @name: find an omap_hwmod by name | |
1494 | * | |
1495 | * Return a pointer to an omap_hwmod by name, or NULL if not found. | |
63c85238 PW |
1496 | */ |
1497 | static struct omap_hwmod *_lookup(const char *name) | |
1498 | { | |
1499 | struct omap_hwmod *oh, *temp_oh; | |
1500 | ||
1501 | oh = NULL; | |
1502 | ||
1503 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
1504 | if (!strcmp(name, temp_oh->name)) { | |
1505 | oh = temp_oh; | |
1506 | break; | |
1507 | } | |
1508 | } | |
1509 | ||
1510 | return oh; | |
1511 | } | |
868c157d | 1512 | |
6ae76997 BC |
1513 | /** |
1514 | * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod | |
1515 | * @oh: struct omap_hwmod * | |
1516 | * | |
1517 | * Convert a clockdomain name stored in a struct omap_hwmod into a | |
1518 | * clockdomain pointer, and save it into the struct omap_hwmod. | |
868c157d | 1519 | * Return -EINVAL if the clkdm_name lookup failed. |
6ae76997 BC |
1520 | */ |
1521 | static int _init_clkdm(struct omap_hwmod *oh) | |
1522 | { | |
3bb05dbf PW |
1523 | if (!oh->clkdm_name) { |
1524 | pr_debug("omap_hwmod: %s: missing clockdomain\n", oh->name); | |
6ae76997 | 1525 | return 0; |
3bb05dbf | 1526 | } |
6ae76997 | 1527 | |
6ae76997 BC |
1528 | oh->clkdm = clkdm_lookup(oh->clkdm_name); |
1529 | if (!oh->clkdm) { | |
3d0cb73e | 1530 | pr_warn("omap_hwmod: %s: could not associate to clkdm %s\n", |
6ae76997 | 1531 | oh->name, oh->clkdm_name); |
0385c582 | 1532 | return 0; |
6ae76997 BC |
1533 | } |
1534 | ||
1535 | pr_debug("omap_hwmod: %s: associated to clkdm %s\n", | |
1536 | oh->name, oh->clkdm_name); | |
1537 | ||
1538 | return 0; | |
1539 | } | |
63c85238 PW |
1540 | |
1541 | /** | |
6ae76997 BC |
1542 | * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as |
1543 | * well the clockdomain. | |
63c85238 | 1544 | * @oh: struct omap_hwmod * |
97d60162 | 1545 | * @data: not used; pass NULL |
63c85238 | 1546 | * |
a2debdbd | 1547 | * Called by omap_hwmod_setup_*() (after omap2_clk_init()). |
48d54f3f PW |
1548 | * Resolves all clock names embedded in the hwmod. Returns 0 on |
1549 | * success, or a negative error code on failure. | |
63c85238 | 1550 | */ |
97d60162 | 1551 | static int _init_clocks(struct omap_hwmod *oh, void *data) |
63c85238 PW |
1552 | { |
1553 | int ret = 0; | |
1554 | ||
48d54f3f PW |
1555 | if (oh->_state != _HWMOD_STATE_REGISTERED) |
1556 | return 0; | |
63c85238 PW |
1557 | |
1558 | pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); | |
1559 | ||
b797be1d VH |
1560 | if (soc_ops.init_clkdm) |
1561 | ret |= soc_ops.init_clkdm(oh); | |
1562 | ||
63c85238 PW |
1563 | ret |= _init_main_clk(oh); |
1564 | ret |= _init_interface_clks(oh); | |
1565 | ret |= _init_opt_clks(oh); | |
1566 | ||
f5c1f84b BC |
1567 | if (!ret) |
1568 | oh->_state = _HWMOD_STATE_CLKS_INITED; | |
6652271a | 1569 | else |
3d0cb73e | 1570 | pr_warn("omap_hwmod: %s: cannot _init_clocks\n", oh->name); |
63c85238 | 1571 | |
09c35f2f | 1572 | return ret; |
63c85238 PW |
1573 | } |
1574 | ||
5365efbe | 1575 | /** |
cc1226e7 | 1576 | * _lookup_hardreset - fill register bit info for this hwmod/reset line |
5365efbe BC |
1577 | * @oh: struct omap_hwmod * |
1578 | * @name: name of the reset line in the context of this hwmod | |
cc1226e7 | 1579 | * @ohri: struct omap_hwmod_rst_info * that this function will fill in |
5365efbe BC |
1580 | * |
1581 | * Return the bit position of the reset line that match the | |
1582 | * input name. Return -ENOENT if not found. | |
1583 | */ | |
a032d33b PW |
1584 | static int _lookup_hardreset(struct omap_hwmod *oh, const char *name, |
1585 | struct omap_hwmod_rst_info *ohri) | |
5365efbe BC |
1586 | { |
1587 | int i; | |
1588 | ||
1589 | for (i = 0; i < oh->rst_lines_cnt; i++) { | |
1590 | const char *rst_line = oh->rst_lines[i].name; | |
1591 | if (!strcmp(rst_line, name)) { | |
cc1226e7 | 1592 | ohri->rst_shift = oh->rst_lines[i].rst_shift; |
1593 | ohri->st_shift = oh->rst_lines[i].st_shift; | |
1594 | pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n", | |
1595 | oh->name, __func__, rst_line, ohri->rst_shift, | |
1596 | ohri->st_shift); | |
5365efbe | 1597 | |
cc1226e7 | 1598 | return 0; |
5365efbe BC |
1599 | } |
1600 | } | |
1601 | ||
1602 | return -ENOENT; | |
1603 | } | |
1604 | ||
1605 | /** | |
1606 | * _assert_hardreset - assert the HW reset line of submodules | |
1607 | * contained in the hwmod module. | |
1608 | * @oh: struct omap_hwmod * | |
1609 | * @name: name of the reset line to lookup and assert | |
1610 | * | |
b8249cf2 KH |
1611 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1612 | * reset line to be assert / deassert in order to enable fully the IP. | |
1613 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of | |
1614 | * asserting the hardreset line on the currently-booted SoC, or passes | |
1615 | * along the return value from _lookup_hardreset() or the SoC's | |
1616 | * assert_hardreset code. | |
5365efbe BC |
1617 | */ |
1618 | static int _assert_hardreset(struct omap_hwmod *oh, const char *name) | |
1619 | { | |
cc1226e7 | 1620 | struct omap_hwmod_rst_info ohri; |
a032d33b | 1621 | int ret = -EINVAL; |
5365efbe BC |
1622 | |
1623 | if (!oh) | |
1624 | return -EINVAL; | |
1625 | ||
b8249cf2 KH |
1626 | if (!soc_ops.assert_hardreset) |
1627 | return -ENOSYS; | |
1628 | ||
cc1226e7 | 1629 | ret = _lookup_hardreset(oh, name, &ohri); |
a032d33b | 1630 | if (ret < 0) |
cc1226e7 | 1631 | return ret; |
5365efbe | 1632 | |
b8249cf2 KH |
1633 | ret = soc_ops.assert_hardreset(oh, &ohri); |
1634 | ||
1635 | return ret; | |
5365efbe BC |
1636 | } |
1637 | ||
1638 | /** | |
1639 | * _deassert_hardreset - deassert the HW reset line of submodules contained | |
1640 | * in the hwmod module. | |
1641 | * @oh: struct omap_hwmod * | |
1642 | * @name: name of the reset line to look up and deassert | |
1643 | * | |
b8249cf2 KH |
1644 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1645 | * reset line to be assert / deassert in order to enable fully the IP. | |
1646 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of | |
1647 | * deasserting the hardreset line on the currently-booted SoC, or passes | |
1648 | * along the return value from _lookup_hardreset() or the SoC's | |
1649 | * deassert_hardreset code. | |
5365efbe BC |
1650 | */ |
1651 | static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
1652 | { | |
cc1226e7 | 1653 | struct omap_hwmod_rst_info ohri; |
b8249cf2 | 1654 | int ret = -EINVAL; |
e8e96dff | 1655 | int hwsup = 0; |
5365efbe BC |
1656 | |
1657 | if (!oh) | |
1658 | return -EINVAL; | |
1659 | ||
b8249cf2 KH |
1660 | if (!soc_ops.deassert_hardreset) |
1661 | return -ENOSYS; | |
1662 | ||
cc1226e7 | 1663 | ret = _lookup_hardreset(oh, name, &ohri); |
c48cd659 | 1664 | if (ret < 0) |
cc1226e7 | 1665 | return ret; |
5365efbe | 1666 | |
e8e96dff ORL |
1667 | if (oh->clkdm) { |
1668 | /* | |
1669 | * A clockdomain must be in SW_SUP otherwise reset | |
1670 | * might not be completed. The clockdomain can be set | |
1671 | * in HW_AUTO only when the module become ready. | |
1672 | */ | |
1673 | hwsup = clkdm_in_hwsup(oh->clkdm); | |
1674 | ret = clkdm_hwmod_enable(oh->clkdm, oh); | |
1675 | if (ret) { | |
1676 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
1677 | oh->name, oh->clkdm->name, ret); | |
1678 | return ret; | |
1679 | } | |
1680 | } | |
1681 | ||
1682 | _enable_clocks(oh); | |
1683 | if (soc_ops.enable_module) | |
1684 | soc_ops.enable_module(oh); | |
1685 | ||
b8249cf2 | 1686 | ret = soc_ops.deassert_hardreset(oh, &ohri); |
e8e96dff ORL |
1687 | |
1688 | if (soc_ops.disable_module) | |
1689 | soc_ops.disable_module(oh); | |
1690 | _disable_clocks(oh); | |
1691 | ||
cc1226e7 | 1692 | if (ret == -EBUSY) |
3d0cb73e | 1693 | pr_warn("omap_hwmod: %s: failed to hardreset\n", oh->name); |
5365efbe | 1694 | |
e8e96dff ORL |
1695 | if (!ret) { |
1696 | /* | |
1697 | * Set the clockdomain to HW_AUTO, assuming that the | |
1698 | * previous state was HW_AUTO. | |
1699 | */ | |
1700 | if (oh->clkdm && hwsup) | |
1701 | clkdm_allow_idle(oh->clkdm); | |
1702 | } else { | |
1703 | if (oh->clkdm) | |
1704 | clkdm_hwmod_disable(oh->clkdm, oh); | |
1705 | } | |
1706 | ||
cc1226e7 | 1707 | return ret; |
5365efbe BC |
1708 | } |
1709 | ||
1710 | /** | |
1711 | * _read_hardreset - read the HW reset line state of submodules | |
1712 | * contained in the hwmod module | |
1713 | * @oh: struct omap_hwmod * | |
1714 | * @name: name of the reset line to look up and read | |
1715 | * | |
b8249cf2 KH |
1716 | * Return the state of the reset line. Returns -EINVAL if @oh is |
1717 | * null, -ENOSYS if we have no way of reading the hardreset line | |
1718 | * status on the currently-booted SoC, or passes along the return | |
1719 | * value from _lookup_hardreset() or the SoC's is_hardreset_asserted | |
1720 | * code. | |
5365efbe BC |
1721 | */ |
1722 | static int _read_hardreset(struct omap_hwmod *oh, const char *name) | |
1723 | { | |
cc1226e7 | 1724 | struct omap_hwmod_rst_info ohri; |
a032d33b | 1725 | int ret = -EINVAL; |
5365efbe BC |
1726 | |
1727 | if (!oh) | |
1728 | return -EINVAL; | |
1729 | ||
b8249cf2 KH |
1730 | if (!soc_ops.is_hardreset_asserted) |
1731 | return -ENOSYS; | |
1732 | ||
cc1226e7 | 1733 | ret = _lookup_hardreset(oh, name, &ohri); |
a032d33b | 1734 | if (ret < 0) |
cc1226e7 | 1735 | return ret; |
5365efbe | 1736 | |
b8249cf2 | 1737 | return soc_ops.is_hardreset_asserted(oh, &ohri); |
5365efbe BC |
1738 | } |
1739 | ||
747834ab | 1740 | /** |
eb05f691 | 1741 | * _are_all_hardreset_lines_asserted - return true if the @oh is hard-reset |
747834ab PW |
1742 | * @oh: struct omap_hwmod * |
1743 | * | |
eb05f691 ORL |
1744 | * If all hardreset lines associated with @oh are asserted, then return true. |
1745 | * Otherwise, if part of @oh is out hardreset or if no hardreset lines | |
1746 | * associated with @oh are asserted, then return false. | |
747834ab | 1747 | * This function is used to avoid executing some parts of the IP block |
eb05f691 | 1748 | * enable/disable sequence if its hardreset line is set. |
747834ab | 1749 | */ |
eb05f691 | 1750 | static bool _are_all_hardreset_lines_asserted(struct omap_hwmod *oh) |
747834ab | 1751 | { |
eb05f691 | 1752 | int i, rst_cnt = 0; |
747834ab PW |
1753 | |
1754 | if (oh->rst_lines_cnt == 0) | |
1755 | return false; | |
1756 | ||
1757 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1758 | if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) | |
eb05f691 ORL |
1759 | rst_cnt++; |
1760 | ||
1761 | if (oh->rst_lines_cnt == rst_cnt) | |
1762 | return true; | |
747834ab PW |
1763 | |
1764 | return false; | |
1765 | } | |
1766 | ||
e9332b6e PW |
1767 | /** |
1768 | * _are_any_hardreset_lines_asserted - return true if any part of @oh is | |
1769 | * hard-reset | |
1770 | * @oh: struct omap_hwmod * | |
1771 | * | |
1772 | * If any hardreset lines associated with @oh are asserted, then | |
1773 | * return true. Otherwise, if no hardreset lines associated with @oh | |
1774 | * are asserted, or if @oh has no hardreset lines, then return false. | |
1775 | * This function is used to avoid executing some parts of the IP block | |
1776 | * enable/disable sequence if any hardreset line is set. | |
1777 | */ | |
1778 | static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh) | |
1779 | { | |
1780 | int rst_cnt = 0; | |
1781 | int i; | |
1782 | ||
1783 | for (i = 0; i < oh->rst_lines_cnt && rst_cnt == 0; i++) | |
1784 | if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) | |
1785 | rst_cnt++; | |
1786 | ||
1787 | return (rst_cnt) ? true : false; | |
1788 | } | |
1789 | ||
747834ab PW |
1790 | /** |
1791 | * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4 | |
1792 | * @oh: struct omap_hwmod * | |
1793 | * | |
1794 | * Disable the PRCM module mode related to the hwmod @oh. | |
1795 | * Return EINVAL if the modulemode is not supported and 0 in case of success. | |
1796 | */ | |
1797 | static int _omap4_disable_module(struct omap_hwmod *oh) | |
1798 | { | |
1799 | int v; | |
1800 | ||
747834ab PW |
1801 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) |
1802 | return -EINVAL; | |
1803 | ||
eb05f691 ORL |
1804 | /* |
1805 | * Since integration code might still be doing something, only | |
1806 | * disable if all lines are under hardreset. | |
1807 | */ | |
e9332b6e | 1808 | if (_are_any_hardreset_lines_asserted(oh)) |
eb05f691 ORL |
1809 | return 0; |
1810 | ||
747834ab PW |
1811 | pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); |
1812 | ||
128603f0 TK |
1813 | omap_cm_module_disable(oh->clkdm->prcm_partition, oh->clkdm->cm_inst, |
1814 | oh->prcm.omap4.clkctrl_offs); | |
747834ab | 1815 | |
747834ab PW |
1816 | v = _omap4_wait_target_disable(oh); |
1817 | if (v) | |
1818 | pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", | |
1819 | oh->name); | |
1820 | ||
1821 | return 0; | |
1822 | } | |
1823 | ||
63c85238 | 1824 | /** |
bd36179e | 1825 | * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit |
63c85238 PW |
1826 | * @oh: struct omap_hwmod * |
1827 | * | |
1828 | * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be | |
30e105c0 PW |
1829 | * enabled for this to work. Returns -ENOENT if the hwmod cannot be |
1830 | * reset this way, -EINVAL if the hwmod is in the wrong state, | |
1831 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
2cb06814 BC |
1832 | * |
1833 | * In OMAP3 a specific SYSSTATUS register is used to get the reset status. | |
bd36179e | 1834 | * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead |
2cb06814 BC |
1835 | * use the SYSCONFIG softreset bit to provide the status. |
1836 | * | |
bd36179e PW |
1837 | * Note that some IP like McBSP do have reset control but don't have |
1838 | * reset status. | |
63c85238 | 1839 | */ |
bd36179e | 1840 | static int _ocp_softreset(struct omap_hwmod *oh) |
63c85238 | 1841 | { |
613ad0e9 | 1842 | u32 v; |
6f8b7ff5 | 1843 | int c = 0; |
96835af9 | 1844 | int ret = 0; |
63c85238 | 1845 | |
43b40992 | 1846 | if (!oh->class->sysc || |
2cb06814 | 1847 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) |
30e105c0 | 1848 | return -ENOENT; |
63c85238 PW |
1849 | |
1850 | /* clocks must be on for this operation */ | |
1851 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
7852ec05 PW |
1852 | pr_warn("omap_hwmod: %s: reset can only be entered from enabled state\n", |
1853 | oh->name); | |
63c85238 PW |
1854 | return -EINVAL; |
1855 | } | |
1856 | ||
96835af9 BC |
1857 | /* For some modules, all optionnal clocks need to be enabled as well */ |
1858 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1859 | _enable_optional_clocks(oh); | |
1860 | ||
bd36179e | 1861 | pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name); |
63c85238 PW |
1862 | |
1863 | v = oh->_sysc_cache; | |
96835af9 BC |
1864 | ret = _set_softreset(oh, &v); |
1865 | if (ret) | |
1866 | goto dis_opt_clks; | |
313a76ee | 1867 | |
63c85238 PW |
1868 | _write_sysconfig(v, oh); |
1869 | ||
d99de7f5 FGL |
1870 | if (oh->class->sysc->srst_udelay) |
1871 | udelay(oh->class->sysc->srst_udelay); | |
1872 | ||
613ad0e9 | 1873 | c = _wait_softreset_complete(oh); |
01142519 | 1874 | if (c == MAX_MODULE_SOFTRESET_WAIT) { |
3d0cb73e JP |
1875 | pr_warn("omap_hwmod: %s: softreset failed (waited %d usec)\n", |
1876 | oh->name, MAX_MODULE_SOFTRESET_WAIT); | |
01142519 IS |
1877 | ret = -ETIMEDOUT; |
1878 | goto dis_opt_clks; | |
1879 | } else { | |
5365efbe | 1880 | pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); |
01142519 IS |
1881 | } |
1882 | ||
1883 | ret = _clear_softreset(oh, &v); | |
1884 | if (ret) | |
1885 | goto dis_opt_clks; | |
1886 | ||
1887 | _write_sysconfig(v, oh); | |
63c85238 PW |
1888 | |
1889 | /* | |
1890 | * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from | |
1891 | * _wait_target_ready() or _reset() | |
1892 | */ | |
1893 | ||
96835af9 BC |
1894 | dis_opt_clks: |
1895 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1896 | _disable_optional_clocks(oh); | |
1897 | ||
1898 | return ret; | |
63c85238 PW |
1899 | } |
1900 | ||
bd36179e PW |
1901 | /** |
1902 | * _reset - reset an omap_hwmod | |
1903 | * @oh: struct omap_hwmod * | |
1904 | * | |
30e105c0 PW |
1905 | * Resets an omap_hwmod @oh. If the module has a custom reset |
1906 | * function pointer defined, then call it to reset the IP block, and | |
1907 | * pass along its return value to the caller. Otherwise, if the IP | |
1908 | * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield | |
1909 | * associated with it, call a function to reset the IP block via that | |
1910 | * method, and pass along the return value to the caller. Finally, if | |
1911 | * the IP block has some hardreset lines associated with it, assert | |
1912 | * all of those, but do _not_ deassert them. (This is because driver | |
1913 | * authors have expressed an apparent requirement to control the | |
1914 | * deassertion of the hardreset lines themselves.) | |
1915 | * | |
1916 | * The default software reset mechanism for most OMAP IP blocks is | |
1917 | * triggered via the OCP_SYSCONFIG.SOFTRESET bit. However, some | |
1918 | * hwmods cannot be reset via this method. Some are not targets and | |
1919 | * therefore have no OCP header registers to access. Others (like the | |
1920 | * IVA) have idiosyncratic reset sequences. So for these relatively | |
1921 | * rare cases, custom reset code can be supplied in the struct | |
6668546f KVA |
1922 | * omap_hwmod_class .reset function pointer. |
1923 | * | |
1924 | * _set_dmadisable() is called to set the DMADISABLE bit so that it | |
1925 | * does not prevent idling of the system. This is necessary for cases | |
1926 | * where ROMCODE/BOOTLOADER uses dma and transfers control to the | |
1927 | * kernel without disabling dma. | |
1928 | * | |
1929 | * Passes along the return value from either _ocp_softreset() or the | |
1930 | * custom reset function - these must return -EINVAL if the hwmod | |
1931 | * cannot be reset this way or if the hwmod is in the wrong state, | |
1932 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
bd36179e PW |
1933 | */ |
1934 | static int _reset(struct omap_hwmod *oh) | |
1935 | { | |
30e105c0 | 1936 | int i, r; |
bd36179e PW |
1937 | |
1938 | pr_debug("omap_hwmod: %s: resetting\n", oh->name); | |
1939 | ||
30e105c0 PW |
1940 | if (oh->class->reset) { |
1941 | r = oh->class->reset(oh); | |
1942 | } else { | |
1943 | if (oh->rst_lines_cnt > 0) { | |
1944 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1945 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
1946 | return 0; | |
1947 | } else { | |
1948 | r = _ocp_softreset(oh); | |
1949 | if (r == -ENOENT) | |
1950 | r = 0; | |
1951 | } | |
1952 | } | |
1953 | ||
6668546f KVA |
1954 | _set_dmadisable(oh); |
1955 | ||
9c8b0ec7 | 1956 | /* |
30e105c0 PW |
1957 | * OCP_SYSCONFIG bits need to be reprogrammed after a |
1958 | * softreset. The _enable() function should be split to avoid | |
1959 | * the rewrite of the OCP_SYSCONFIG register. | |
9c8b0ec7 | 1960 | */ |
2800852a RN |
1961 | if (oh->class->sysc) { |
1962 | _update_sysc_cache(oh); | |
1963 | _enable_sysc(oh); | |
1964 | } | |
1965 | ||
30e105c0 | 1966 | return r; |
bd36179e PW |
1967 | } |
1968 | ||
5165882a VB |
1969 | /** |
1970 | * _reconfigure_io_chain - clear any I/O chain wakeups and reconfigure chain | |
1971 | * | |
1972 | * Call the appropriate PRM function to clear any logged I/O chain | |
1973 | * wakeups and to reconfigure the chain. This apparently needs to be | |
1974 | * done upon every mux change. Since hwmods can be concurrently | |
1975 | * enabled and idled, hold a spinlock around the I/O chain | |
1976 | * reconfiguration sequence. No return value. | |
1977 | * | |
1978 | * XXX When the PRM code is moved to drivers, this function can be removed, | |
1979 | * as the PRM infrastructure should abstract this. | |
1980 | */ | |
1981 | static void _reconfigure_io_chain(void) | |
1982 | { | |
1983 | unsigned long flags; | |
1984 | ||
1985 | spin_lock_irqsave(&io_chain_lock, flags); | |
1986 | ||
4984eeaf | 1987 | omap_prm_reconfigure_io_chain(); |
5165882a VB |
1988 | |
1989 | spin_unlock_irqrestore(&io_chain_lock, flags); | |
1990 | } | |
1991 | ||
e6d3a8b0 RN |
1992 | /** |
1993 | * _omap4_update_context_lost - increment hwmod context loss counter if | |
1994 | * hwmod context was lost, and clear hardware context loss reg | |
1995 | * @oh: hwmod to check for context loss | |
1996 | * | |
1997 | * If the PRCM indicates that the hwmod @oh lost context, increment | |
1998 | * our in-memory context loss counter, and clear the RM_*_CONTEXT | |
1999 | * bits. No return value. | |
2000 | */ | |
2001 | static void _omap4_update_context_lost(struct omap_hwmod *oh) | |
2002 | { | |
2003 | if (oh->prcm.omap4.flags & HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT) | |
2004 | return; | |
2005 | ||
2006 | if (!prm_was_any_context_lost_old(oh->clkdm->pwrdm.ptr->prcm_partition, | |
2007 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2008 | oh->prcm.omap4.context_offs)) | |
2009 | return; | |
2010 | ||
2011 | oh->prcm.omap4.context_lost_counter++; | |
2012 | prm_clear_context_loss_flags_old(oh->clkdm->pwrdm.ptr->prcm_partition, | |
2013 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2014 | oh->prcm.omap4.context_offs); | |
2015 | } | |
2016 | ||
2017 | /** | |
2018 | * _omap4_get_context_lost - get context loss counter for a hwmod | |
2019 | * @oh: hwmod to get context loss counter for | |
2020 | * | |
2021 | * Returns the in-memory context loss counter for a hwmod. | |
2022 | */ | |
2023 | static int _omap4_get_context_lost(struct omap_hwmod *oh) | |
2024 | { | |
2025 | return oh->prcm.omap4.context_lost_counter; | |
2026 | } | |
2027 | ||
6d266f63 PW |
2028 | /** |
2029 | * _enable_preprogram - Pre-program an IP block during the _enable() process | |
2030 | * @oh: struct omap_hwmod * | |
2031 | * | |
2032 | * Some IP blocks (such as AESS) require some additional programming | |
2033 | * after enable before they can enter idle. If a function pointer to | |
2034 | * do so is present in the hwmod data, then call it and pass along the | |
2035 | * return value; otherwise, return 0. | |
2036 | */ | |
0f497039 | 2037 | static int _enable_preprogram(struct omap_hwmod *oh) |
6d266f63 PW |
2038 | { |
2039 | if (!oh->class->enable_preprogram) | |
2040 | return 0; | |
2041 | ||
2042 | return oh->class->enable_preprogram(oh); | |
2043 | } | |
2044 | ||
63c85238 | 2045 | /** |
dc6d1cda | 2046 | * _enable - enable an omap_hwmod |
63c85238 PW |
2047 | * @oh: struct omap_hwmod * |
2048 | * | |
2049 | * Enables an omap_hwmod @oh such that the MPU can access the hwmod's | |
dc6d1cda PW |
2050 | * register target. Returns -EINVAL if the hwmod is in the wrong |
2051 | * state or passes along the return value of _wait_target_ready(). | |
63c85238 | 2052 | */ |
dc6d1cda | 2053 | static int _enable(struct omap_hwmod *oh) |
63c85238 | 2054 | { |
747834ab | 2055 | int r; |
665d0013 | 2056 | int hwsup = 0; |
63c85238 | 2057 | |
34617e2a BC |
2058 | pr_debug("omap_hwmod: %s: enabling\n", oh->name); |
2059 | ||
aacf0941 | 2060 | /* |
64813c3f PW |
2061 | * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled |
2062 | * state at init. Now that someone is really trying to enable | |
2063 | * them, just ensure that the hwmod mux is set. | |
aacf0941 RN |
2064 | */ |
2065 | if (oh->_int_flags & _HWMOD_SKIP_ENABLE) { | |
2066 | /* | |
2067 | * If the caller has mux data populated, do the mux'ing | |
2068 | * which wouldn't have been done as part of the _enable() | |
2069 | * done during setup. | |
2070 | */ | |
2071 | if (oh->mux) | |
2072 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); | |
2073 | ||
2074 | oh->_int_flags &= ~_HWMOD_SKIP_ENABLE; | |
2075 | return 0; | |
2076 | } | |
2077 | ||
63c85238 PW |
2078 | if (oh->_state != _HWMOD_STATE_INITIALIZED && |
2079 | oh->_state != _HWMOD_STATE_IDLE && | |
2080 | oh->_state != _HWMOD_STATE_DISABLED) { | |
4f8a428d RK |
2081 | WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n", |
2082 | oh->name); | |
63c85238 PW |
2083 | return -EINVAL; |
2084 | } | |
2085 | ||
31f62866 | 2086 | /* |
eb05f691 | 2087 | * If an IP block contains HW reset lines and all of them are |
747834ab PW |
2088 | * asserted, we let integration code associated with that |
2089 | * block handle the enable. We've received very little | |
2090 | * information on what those driver authors need, and until | |
2091 | * detailed information is provided and the driver code is | |
2092 | * posted to the public lists, this is probably the best we | |
2093 | * can do. | |
31f62866 | 2094 | */ |
eb05f691 | 2095 | if (_are_all_hardreset_lines_asserted(oh)) |
747834ab | 2096 | return 0; |
63c85238 | 2097 | |
665d0013 RN |
2098 | /* Mux pins for device runtime if populated */ |
2099 | if (oh->mux && (!oh->mux->enabled || | |
2100 | ((oh->_state == _HWMOD_STATE_IDLE) && | |
5165882a | 2101 | oh->mux->pads_dynamic))) { |
665d0013 | 2102 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); |
5165882a | 2103 | _reconfigure_io_chain(); |
6a08b11a | 2104 | } else if (oh->flags & HWMOD_RECONFIG_IO_CHAIN) { |
cc824534 | 2105 | _reconfigure_io_chain(); |
5165882a | 2106 | } |
665d0013 RN |
2107 | |
2108 | _add_initiator_dep(oh, mpu_oh); | |
34617e2a | 2109 | |
665d0013 RN |
2110 | if (oh->clkdm) { |
2111 | /* | |
2112 | * A clockdomain must be in SW_SUP before enabling | |
2113 | * completely the module. The clockdomain can be set | |
2114 | * in HW_AUTO only when the module become ready. | |
2115 | */ | |
b71c7217 PW |
2116 | hwsup = clkdm_in_hwsup(oh->clkdm) && |
2117 | !clkdm_missing_idle_reporting(oh->clkdm); | |
665d0013 RN |
2118 | r = clkdm_hwmod_enable(oh->clkdm, oh); |
2119 | if (r) { | |
2120 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
2121 | oh->name, oh->clkdm->name, r); | |
2122 | return r; | |
2123 | } | |
34617e2a | 2124 | } |
665d0013 RN |
2125 | |
2126 | _enable_clocks(oh); | |
9ebfd285 KH |
2127 | if (soc_ops.enable_module) |
2128 | soc_ops.enable_module(oh); | |
fa200222 | 2129 | if (oh->flags & HWMOD_BLOCK_WFI) |
f7b861b7 | 2130 | cpu_idle_poll_ctrl(true); |
34617e2a | 2131 | |
e6d3a8b0 RN |
2132 | if (soc_ops.update_context_lost) |
2133 | soc_ops.update_context_lost(oh); | |
2134 | ||
8f6aa8ee KH |
2135 | r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) : |
2136 | -EINVAL; | |
665d0013 RN |
2137 | if (!r) { |
2138 | /* | |
2139 | * Set the clockdomain to HW_AUTO only if the target is ready, | |
2140 | * assuming that the previous state was HW_AUTO | |
2141 | */ | |
2142 | if (oh->clkdm && hwsup) | |
2143 | clkdm_allow_idle(oh->clkdm); | |
2144 | ||
2145 | oh->_state = _HWMOD_STATE_ENABLED; | |
2146 | ||
2147 | /* Access the sysconfig only if the target is ready */ | |
2148 | if (oh->class->sysc) { | |
2149 | if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) | |
2150 | _update_sysc_cache(oh); | |
2151 | _enable_sysc(oh); | |
2152 | } | |
6d266f63 | 2153 | r = _enable_preprogram(oh); |
665d0013 | 2154 | } else { |
2577a4a6 PW |
2155 | if (soc_ops.disable_module) |
2156 | soc_ops.disable_module(oh); | |
665d0013 RN |
2157 | _disable_clocks(oh); |
2158 | pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", | |
2159 | oh->name, r); | |
34617e2a | 2160 | |
665d0013 RN |
2161 | if (oh->clkdm) |
2162 | clkdm_hwmod_disable(oh->clkdm, oh); | |
9a23dfe1 BC |
2163 | } |
2164 | ||
63c85238 PW |
2165 | return r; |
2166 | } | |
2167 | ||
2168 | /** | |
dc6d1cda | 2169 | * _idle - idle an omap_hwmod |
63c85238 PW |
2170 | * @oh: struct omap_hwmod * |
2171 | * | |
2172 | * Idles an omap_hwmod @oh. This should be called once the hwmod has | |
dc6d1cda PW |
2173 | * no further work. Returns -EINVAL if the hwmod is in the wrong |
2174 | * state or returns 0. | |
63c85238 | 2175 | */ |
dc6d1cda | 2176 | static int _idle(struct omap_hwmod *oh) |
63c85238 | 2177 | { |
34617e2a BC |
2178 | pr_debug("omap_hwmod: %s: idling\n", oh->name); |
2179 | ||
63c85238 | 2180 | if (oh->_state != _HWMOD_STATE_ENABLED) { |
4f8a428d RK |
2181 | WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n", |
2182 | oh->name); | |
63c85238 PW |
2183 | return -EINVAL; |
2184 | } | |
2185 | ||
eb05f691 | 2186 | if (_are_all_hardreset_lines_asserted(oh)) |
747834ab PW |
2187 | return 0; |
2188 | ||
43b40992 | 2189 | if (oh->class->sysc) |
74ff3a68 | 2190 | _idle_sysc(oh); |
63c85238 | 2191 | _del_initiator_dep(oh, mpu_oh); |
bfc141e3 | 2192 | |
fa200222 | 2193 | if (oh->flags & HWMOD_BLOCK_WFI) |
f7b861b7 | 2194 | cpu_idle_poll_ctrl(false); |
9ebfd285 KH |
2195 | if (soc_ops.disable_module) |
2196 | soc_ops.disable_module(oh); | |
bfc141e3 | 2197 | |
45c38252 BC |
2198 | /* |
2199 | * The module must be in idle mode before disabling any parents | |
2200 | * clocks. Otherwise, the parent clock might be disabled before | |
2201 | * the module transition is done, and thus will prevent the | |
2202 | * transition to complete properly. | |
2203 | */ | |
2204 | _disable_clocks(oh); | |
665d0013 RN |
2205 | if (oh->clkdm) |
2206 | clkdm_hwmod_disable(oh->clkdm, oh); | |
63c85238 | 2207 | |
8d9af88f | 2208 | /* Mux pins for device idle if populated */ |
5165882a | 2209 | if (oh->mux && oh->mux->pads_dynamic) { |
8d9af88f | 2210 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); |
5165882a | 2211 | _reconfigure_io_chain(); |
6a08b11a | 2212 | } else if (oh->flags & HWMOD_RECONFIG_IO_CHAIN) { |
cc824534 | 2213 | _reconfigure_io_chain(); |
5165882a | 2214 | } |
8d9af88f | 2215 | |
63c85238 PW |
2216 | oh->_state = _HWMOD_STATE_IDLE; |
2217 | ||
2218 | return 0; | |
2219 | } | |
2220 | ||
2221 | /** | |
2222 | * _shutdown - shutdown an omap_hwmod | |
2223 | * @oh: struct omap_hwmod * | |
2224 | * | |
2225 | * Shut down an omap_hwmod @oh. This should be called when the driver | |
2226 | * used for the hwmod is removed or unloaded or if the driver is not | |
2227 | * used by the system. Returns -EINVAL if the hwmod is in the wrong | |
2228 | * state or returns 0. | |
2229 | */ | |
2230 | static int _shutdown(struct omap_hwmod *oh) | |
2231 | { | |
9c8b0ec7 | 2232 | int ret, i; |
e4dc8f50 PW |
2233 | u8 prev_state; |
2234 | ||
63c85238 PW |
2235 | if (oh->_state != _HWMOD_STATE_IDLE && |
2236 | oh->_state != _HWMOD_STATE_ENABLED) { | |
4f8a428d RK |
2237 | WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n", |
2238 | oh->name); | |
63c85238 PW |
2239 | return -EINVAL; |
2240 | } | |
2241 | ||
eb05f691 | 2242 | if (_are_all_hardreset_lines_asserted(oh)) |
747834ab PW |
2243 | return 0; |
2244 | ||
63c85238 PW |
2245 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); |
2246 | ||
e4dc8f50 PW |
2247 | if (oh->class->pre_shutdown) { |
2248 | prev_state = oh->_state; | |
2249 | if (oh->_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2250 | _enable(oh); |
e4dc8f50 PW |
2251 | ret = oh->class->pre_shutdown(oh); |
2252 | if (ret) { | |
2253 | if (prev_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2254 | _idle(oh); |
e4dc8f50 PW |
2255 | return ret; |
2256 | } | |
2257 | } | |
2258 | ||
6481c73c MV |
2259 | if (oh->class->sysc) { |
2260 | if (oh->_state == _HWMOD_STATE_IDLE) | |
2261 | _enable(oh); | |
74ff3a68 | 2262 | _shutdown_sysc(oh); |
6481c73c | 2263 | } |
5365efbe | 2264 | |
3827f949 BC |
2265 | /* clocks and deps are already disabled in idle */ |
2266 | if (oh->_state == _HWMOD_STATE_ENABLED) { | |
2267 | _del_initiator_dep(oh, mpu_oh); | |
2268 | /* XXX what about the other system initiators here? dma, dsp */ | |
fa200222 | 2269 | if (oh->flags & HWMOD_BLOCK_WFI) |
f7b861b7 | 2270 | cpu_idle_poll_ctrl(false); |
9ebfd285 KH |
2271 | if (soc_ops.disable_module) |
2272 | soc_ops.disable_module(oh); | |
45c38252 | 2273 | _disable_clocks(oh); |
665d0013 RN |
2274 | if (oh->clkdm) |
2275 | clkdm_hwmod_disable(oh->clkdm, oh); | |
3827f949 | 2276 | } |
63c85238 PW |
2277 | /* XXX Should this code also force-disable the optional clocks? */ |
2278 | ||
9c8b0ec7 PW |
2279 | for (i = 0; i < oh->rst_lines_cnt; i++) |
2280 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
31f62866 | 2281 | |
8d9af88f TL |
2282 | /* Mux pins to safe mode or use populated off mode values */ |
2283 | if (oh->mux) | |
2284 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED); | |
63c85238 PW |
2285 | |
2286 | oh->_state = _HWMOD_STATE_DISABLED; | |
2287 | ||
2288 | return 0; | |
2289 | } | |
2290 | ||
5e863c56 TL |
2291 | static int of_dev_find_hwmod(struct device_node *np, |
2292 | struct omap_hwmod *oh) | |
2293 | { | |
2294 | int count, i, res; | |
2295 | const char *p; | |
2296 | ||
2297 | count = of_property_count_strings(np, "ti,hwmods"); | |
2298 | if (count < 1) | |
2299 | return -ENODEV; | |
2300 | ||
2301 | for (i = 0; i < count; i++) { | |
2302 | res = of_property_read_string_index(np, "ti,hwmods", | |
2303 | i, &p); | |
2304 | if (res) | |
2305 | continue; | |
2306 | if (!strcmp(p, oh->name)) { | |
2307 | pr_debug("omap_hwmod: dt %s[%i] uses hwmod %s\n", | |
2308 | np->name, i, oh->name); | |
2309 | return i; | |
2310 | } | |
2311 | } | |
2312 | ||
2313 | return -ENODEV; | |
2314 | } | |
2315 | ||
079abade SS |
2316 | /** |
2317 | * of_dev_hwmod_lookup - look up needed hwmod from dt blob | |
2318 | * @np: struct device_node * | |
2319 | * @oh: struct omap_hwmod * | |
5e863c56 TL |
2320 | * @index: index of the entry found |
2321 | * @found: struct device_node * found or NULL | |
079abade SS |
2322 | * |
2323 | * Parse the dt blob and find out needed hwmod. Recursive function is | |
2324 | * implemented to take care hierarchical dt blob parsing. | |
5e863c56 | 2325 | * Return: Returns 0 on success, -ENODEV when not found. |
079abade | 2326 | */ |
5e863c56 TL |
2327 | static int of_dev_hwmod_lookup(struct device_node *np, |
2328 | struct omap_hwmod *oh, | |
2329 | int *index, | |
2330 | struct device_node **found) | |
079abade | 2331 | { |
5e863c56 TL |
2332 | struct device_node *np0 = NULL; |
2333 | int res; | |
2334 | ||
2335 | res = of_dev_find_hwmod(np, oh); | |
2336 | if (res >= 0) { | |
2337 | *found = np; | |
2338 | *index = res; | |
2339 | return 0; | |
2340 | } | |
079abade SS |
2341 | |
2342 | for_each_child_of_node(np, np0) { | |
5e863c56 TL |
2343 | struct device_node *fc; |
2344 | int i; | |
2345 | ||
2346 | res = of_dev_hwmod_lookup(np0, oh, &i, &fc); | |
2347 | if (res == 0) { | |
2348 | *found = fc; | |
2349 | *index = i; | |
2350 | return 0; | |
079abade SS |
2351 | } |
2352 | } | |
5e863c56 TL |
2353 | |
2354 | *found = NULL; | |
2355 | *index = 0; | |
2356 | ||
2357 | return -ENODEV; | |
079abade SS |
2358 | } |
2359 | ||
381d033a PW |
2360 | /** |
2361 | * _init_mpu_rt_base - populate the virtual address for a hwmod | |
2362 | * @oh: struct omap_hwmod * to locate the virtual address | |
f92d9597 | 2363 | * @data: (unused, caller should pass NULL) |
5e863c56 | 2364 | * @index: index of the reg entry iospace in device tree |
f92d9597 | 2365 | * @np: struct device_node * of the IP block's device node in the DT data |
381d033a PW |
2366 | * |
2367 | * Cache the virtual address used by the MPU to access this IP block's | |
2368 | * registers. This address is needed early so the OCP registers that | |
2369 | * are part of the device's address space can be ioremapped properly. | |
6423d6df SA |
2370 | * |
2371 | * Returns 0 on success, -EINVAL if an invalid hwmod is passed, and | |
2372 | * -ENXIO on absent or invalid register target address space. | |
381d033a | 2373 | */ |
f92d9597 | 2374 | static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data, |
5e863c56 | 2375 | int index, struct device_node *np) |
381d033a | 2376 | { |
c9aafd23 | 2377 | struct omap_hwmod_addr_space *mem; |
079abade | 2378 | void __iomem *va_start = NULL; |
c9aafd23 PW |
2379 | |
2380 | if (!oh) | |
6423d6df | 2381 | return -EINVAL; |
c9aafd23 | 2382 | |
2221b5cd PW |
2383 | _save_mpu_port_index(oh); |
2384 | ||
381d033a | 2385 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) |
6423d6df | 2386 | return -ENXIO; |
381d033a | 2387 | |
c9aafd23 PW |
2388 | mem = _find_mpu_rt_addr_space(oh); |
2389 | if (!mem) { | |
2390 | pr_debug("omap_hwmod: %s: no MPU register target found\n", | |
2391 | oh->name); | |
079abade SS |
2392 | |
2393 | /* Extract the IO space from device tree blob */ | |
f92d9597 | 2394 | if (!np) |
6423d6df | 2395 | return -ENXIO; |
079abade | 2396 | |
5e863c56 | 2397 | va_start = of_iomap(np, index + oh->mpu_rt_idx); |
079abade SS |
2398 | } else { |
2399 | va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); | |
c9aafd23 PW |
2400 | } |
2401 | ||
c9aafd23 | 2402 | if (!va_start) { |
5e863c56 TL |
2403 | if (mem) |
2404 | pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); | |
2405 | else | |
2406 | pr_err("omap_hwmod: %s: Missing dt reg%i for %s\n", | |
2407 | oh->name, index, np->full_name); | |
6423d6df | 2408 | return -ENXIO; |
c9aafd23 PW |
2409 | } |
2410 | ||
2411 | pr_debug("omap_hwmod: %s: MPU register target at va %p\n", | |
2412 | oh->name, va_start); | |
2413 | ||
2414 | oh->_mpu_rt_va = va_start; | |
6423d6df | 2415 | return 0; |
381d033a PW |
2416 | } |
2417 | ||
2418 | /** | |
2419 | * _init - initialize internal data for the hwmod @oh | |
2420 | * @oh: struct omap_hwmod * | |
2421 | * @n: (unused) | |
2422 | * | |
2423 | * Look up the clocks and the address space used by the MPU to access | |
2424 | * registers belonging to the hwmod @oh. @oh must already be | |
2425 | * registered at this point. This is the first of two phases for | |
2426 | * hwmod initialization. Code called here does not touch any hardware | |
2427 | * registers, it simply prepares internal data structures. Returns 0 | |
6423d6df SA |
2428 | * upon success or if the hwmod isn't registered or if the hwmod's |
2429 | * address space is not defined, or -EINVAL upon failure. | |
381d033a PW |
2430 | */ |
2431 | static int __init _init(struct omap_hwmod *oh, void *data) | |
2432 | { | |
5e863c56 | 2433 | int r, index; |
f92d9597 | 2434 | struct device_node *np = NULL; |
381d033a PW |
2435 | |
2436 | if (oh->_state != _HWMOD_STATE_REGISTERED) | |
2437 | return 0; | |
2438 | ||
5e863c56 TL |
2439 | if (of_have_populated_dt()) { |
2440 | struct device_node *bus; | |
2441 | ||
2442 | bus = of_find_node_by_name(NULL, "ocp"); | |
2443 | if (!bus) | |
2444 | return -ENODEV; | |
2445 | ||
2446 | r = of_dev_hwmod_lookup(bus, oh, &index, &np); | |
2447 | if (r) | |
2448 | pr_debug("omap_hwmod: %s missing dt data\n", oh->name); | |
2449 | else if (np && index) | |
2450 | pr_warn("omap_hwmod: %s using broken dt data from %s\n", | |
2451 | oh->name, np->name); | |
2452 | } | |
f92d9597 | 2453 | |
6423d6df | 2454 | if (oh->class->sysc) { |
5e863c56 | 2455 | r = _init_mpu_rt_base(oh, NULL, index, np); |
6423d6df SA |
2456 | if (r < 0) { |
2457 | WARN(1, "omap_hwmod: %s: doesn't have mpu register target base\n", | |
2458 | oh->name); | |
2459 | return 0; | |
2460 | } | |
2461 | } | |
381d033a PW |
2462 | |
2463 | r = _init_clocks(oh, NULL); | |
c48cd659 | 2464 | if (r < 0) { |
381d033a PW |
2465 | WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name); |
2466 | return -EINVAL; | |
2467 | } | |
2468 | ||
3d36ad7e | 2469 | if (np) { |
f92d9597 RN |
2470 | if (of_find_property(np, "ti,no-reset-on-init", NULL)) |
2471 | oh->flags |= HWMOD_INIT_NO_RESET; | |
2472 | if (of_find_property(np, "ti,no-idle-on-init", NULL)) | |
2473 | oh->flags |= HWMOD_INIT_NO_IDLE; | |
3d36ad7e | 2474 | } |
f92d9597 | 2475 | |
381d033a PW |
2476 | oh->_state = _HWMOD_STATE_INITIALIZED; |
2477 | ||
2478 | return 0; | |
2479 | } | |
2480 | ||
63c85238 | 2481 | /** |
64813c3f | 2482 | * _setup_iclk_autoidle - configure an IP block's interface clocks |
63c85238 PW |
2483 | * @oh: struct omap_hwmod * |
2484 | * | |
64813c3f PW |
2485 | * Set up the module's interface clocks. XXX This function is still mostly |
2486 | * a stub; implementing this properly requires iclk autoidle usecounting in | |
2487 | * the clock code. No return value. | |
63c85238 | 2488 | */ |
64813c3f | 2489 | static void __init _setup_iclk_autoidle(struct omap_hwmod *oh) |
63c85238 | 2490 | { |
5d95dde7 | 2491 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 2492 | struct list_head *p; |
5d95dde7 | 2493 | int i = 0; |
381d033a | 2494 | if (oh->_state != _HWMOD_STATE_INITIALIZED) |
64813c3f | 2495 | return; |
48d54f3f | 2496 | |
11cd4b94 | 2497 | p = oh->slave_ports.next; |
63c85238 | 2498 | |
5d95dde7 | 2499 | while (i < oh->slaves_cnt) { |
11cd4b94 | 2500 | os = _fetch_next_ocp_if(&p, &i); |
5d95dde7 | 2501 | if (!os->_clk) |
64813c3f | 2502 | continue; |
63c85238 | 2503 | |
64813c3f PW |
2504 | if (os->flags & OCPIF_SWSUP_IDLE) { |
2505 | /* XXX omap_iclk_deny_idle(c); */ | |
2506 | } else { | |
2507 | /* XXX omap_iclk_allow_idle(c); */ | |
5d95dde7 | 2508 | clk_enable(os->_clk); |
63c85238 PW |
2509 | } |
2510 | } | |
2511 | ||
64813c3f PW |
2512 | return; |
2513 | } | |
2514 | ||
2515 | /** | |
2516 | * _setup_reset - reset an IP block during the setup process | |
2517 | * @oh: struct omap_hwmod * | |
2518 | * | |
2519 | * Reset the IP block corresponding to the hwmod @oh during the setup | |
2520 | * process. The IP block is first enabled so it can be successfully | |
2521 | * reset. Returns 0 upon success or a negative error code upon | |
2522 | * failure. | |
2523 | */ | |
2524 | static int __init _setup_reset(struct omap_hwmod *oh) | |
2525 | { | |
2526 | int r; | |
2527 | ||
2528 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2529 | return -EINVAL; | |
63c85238 | 2530 | |
5fb3d522 PW |
2531 | if (oh->flags & HWMOD_EXT_OPT_MAIN_CLK) |
2532 | return -EPERM; | |
2533 | ||
747834ab PW |
2534 | if (oh->rst_lines_cnt == 0) { |
2535 | r = _enable(oh); | |
2536 | if (r) { | |
3d0cb73e JP |
2537 | pr_warn("omap_hwmod: %s: cannot be enabled for reset (%d)\n", |
2538 | oh->name, oh->_state); | |
747834ab PW |
2539 | return -EINVAL; |
2540 | } | |
9a23dfe1 | 2541 | } |
63c85238 | 2542 | |
2800852a | 2543 | if (!(oh->flags & HWMOD_INIT_NO_RESET)) |
64813c3f PW |
2544 | r = _reset(oh); |
2545 | ||
2546 | return r; | |
2547 | } | |
2548 | ||
2549 | /** | |
2550 | * _setup_postsetup - transition to the appropriate state after _setup | |
2551 | * @oh: struct omap_hwmod * | |
2552 | * | |
2553 | * Place an IP block represented by @oh into a "post-setup" state -- | |
2554 | * either IDLE, ENABLED, or DISABLED. ("post-setup" simply means that | |
2555 | * this function is called at the end of _setup().) The postsetup | |
2556 | * state for an IP block can be changed by calling | |
2557 | * omap_hwmod_enter_postsetup_state() early in the boot process, | |
2558 | * before one of the omap_hwmod_setup*() functions are called for the | |
2559 | * IP block. | |
2560 | * | |
2561 | * The IP block stays in this state until a PM runtime-based driver is | |
2562 | * loaded for that IP block. A post-setup state of IDLE is | |
2563 | * appropriate for almost all IP blocks with runtime PM-enabled | |
2564 | * drivers, since those drivers are able to enable the IP block. A | |
2565 | * post-setup state of ENABLED is appropriate for kernels with PM | |
2566 | * runtime disabled. The DISABLED state is appropriate for unusual IP | |
2567 | * blocks such as the MPU WDTIMER on kernels without WDTIMER drivers | |
2568 | * included, since the WDTIMER starts running on reset and will reset | |
2569 | * the MPU if left active. | |
2570 | * | |
2571 | * This post-setup mechanism is deprecated. Once all of the OMAP | |
2572 | * drivers have been converted to use PM runtime, and all of the IP | |
2573 | * block data and interconnect data is available to the hwmod code, it | |
2574 | * should be possible to replace this mechanism with a "lazy reset" | |
2575 | * arrangement. In a "lazy reset" setup, each IP block is enabled | |
2576 | * when the driver first probes, then all remaining IP blocks without | |
2577 | * drivers are either shut down or enabled after the drivers have | |
2578 | * loaded. However, this cannot take place until the above | |
2579 | * preconditions have been met, since otherwise the late reset code | |
2580 | * has no way of knowing which IP blocks are in use by drivers, and | |
2581 | * which ones are unused. | |
2582 | * | |
2583 | * No return value. | |
2584 | */ | |
2585 | static void __init _setup_postsetup(struct omap_hwmod *oh) | |
2586 | { | |
2587 | u8 postsetup_state; | |
2588 | ||
2589 | if (oh->rst_lines_cnt > 0) | |
2590 | return; | |
76e5589e | 2591 | |
2092e5cc PW |
2592 | postsetup_state = oh->_postsetup_state; |
2593 | if (postsetup_state == _HWMOD_STATE_UNKNOWN) | |
2594 | postsetup_state = _HWMOD_STATE_ENABLED; | |
2595 | ||
2596 | /* | |
2597 | * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data - | |
2598 | * it should be set by the core code as a runtime flag during startup | |
2599 | */ | |
2600 | if ((oh->flags & HWMOD_INIT_NO_IDLE) && | |
aacf0941 RN |
2601 | (postsetup_state == _HWMOD_STATE_IDLE)) { |
2602 | oh->_int_flags |= _HWMOD_SKIP_ENABLE; | |
2092e5cc | 2603 | postsetup_state = _HWMOD_STATE_ENABLED; |
aacf0941 | 2604 | } |
2092e5cc PW |
2605 | |
2606 | if (postsetup_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2607 | _idle(oh); |
2092e5cc PW |
2608 | else if (postsetup_state == _HWMOD_STATE_DISABLED) |
2609 | _shutdown(oh); | |
2610 | else if (postsetup_state != _HWMOD_STATE_ENABLED) | |
2611 | WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", | |
2612 | oh->name, postsetup_state); | |
63c85238 | 2613 | |
64813c3f PW |
2614 | return; |
2615 | } | |
2616 | ||
2617 | /** | |
2618 | * _setup - prepare IP block hardware for use | |
2619 | * @oh: struct omap_hwmod * | |
2620 | * @n: (unused, pass NULL) | |
2621 | * | |
2622 | * Configure the IP block represented by @oh. This may include | |
2623 | * enabling the IP block, resetting it, and placing it into a | |
2624 | * post-setup state, depending on the type of IP block and applicable | |
2625 | * flags. IP blocks are reset to prevent any previous configuration | |
2626 | * by the bootloader or previous operating system from interfering | |
2627 | * with power management or other parts of the system. The reset can | |
2628 | * be avoided; see omap_hwmod_no_setup_reset(). This is the second of | |
2629 | * two phases for hwmod initialization. Code called here generally | |
2630 | * affects the IP block hardware, or system integration hardware | |
2631 | * associated with the IP block. Returns 0. | |
2632 | */ | |
2633 | static int __init _setup(struct omap_hwmod *oh, void *data) | |
2634 | { | |
2635 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2636 | return 0; | |
2637 | ||
f22d2545 TV |
2638 | if (oh->parent_hwmod) { |
2639 | int r; | |
2640 | ||
2641 | r = _enable(oh->parent_hwmod); | |
2642 | WARN(r, "hwmod: %s: setup: failed to enable parent hwmod %s\n", | |
2643 | oh->name, oh->parent_hwmod->name); | |
2644 | } | |
2645 | ||
64813c3f PW |
2646 | _setup_iclk_autoidle(oh); |
2647 | ||
2648 | if (!_setup_reset(oh)) | |
2649 | _setup_postsetup(oh); | |
2650 | ||
f22d2545 TV |
2651 | if (oh->parent_hwmod) { |
2652 | u8 postsetup_state; | |
2653 | ||
2654 | postsetup_state = oh->parent_hwmod->_postsetup_state; | |
2655 | ||
2656 | if (postsetup_state == _HWMOD_STATE_IDLE) | |
2657 | _idle(oh->parent_hwmod); | |
2658 | else if (postsetup_state == _HWMOD_STATE_DISABLED) | |
2659 | _shutdown(oh->parent_hwmod); | |
2660 | else if (postsetup_state != _HWMOD_STATE_ENABLED) | |
2661 | WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", | |
2662 | oh->parent_hwmod->name, postsetup_state); | |
2663 | } | |
2664 | ||
63c85238 PW |
2665 | return 0; |
2666 | } | |
2667 | ||
63c85238 | 2668 | /** |
0102b627 | 2669 | * _register - register a struct omap_hwmod |
63c85238 PW |
2670 | * @oh: struct omap_hwmod * |
2671 | * | |
43b40992 PW |
2672 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod |
2673 | * already has been registered by the same name; -EINVAL if the | |
2674 | * omap_hwmod is in the wrong state, if @oh is NULL, if the | |
2675 | * omap_hwmod's class field is NULL; if the omap_hwmod is missing a | |
2676 | * name, or if the omap_hwmod's class is missing a name; or 0 upon | |
2677 | * success. | |
63c85238 PW |
2678 | * |
2679 | * XXX The data should be copied into bootmem, so the original data | |
2680 | * should be marked __initdata and freed after init. This would allow | |
2681 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note | |
2682 | * that the copy process would be relatively complex due to the large number | |
2683 | * of substructures. | |
2684 | */ | |
01592df9 | 2685 | static int __init _register(struct omap_hwmod *oh) |
63c85238 | 2686 | { |
43b40992 PW |
2687 | if (!oh || !oh->name || !oh->class || !oh->class->name || |
2688 | (oh->_state != _HWMOD_STATE_UNKNOWN)) | |
63c85238 PW |
2689 | return -EINVAL; |
2690 | ||
63c85238 PW |
2691 | pr_debug("omap_hwmod: %s: registering\n", oh->name); |
2692 | ||
ce35b244 BC |
2693 | if (_lookup(oh->name)) |
2694 | return -EEXIST; | |
63c85238 | 2695 | |
63c85238 PW |
2696 | list_add_tail(&oh->node, &omap_hwmod_list); |
2697 | ||
2221b5cd PW |
2698 | INIT_LIST_HEAD(&oh->master_ports); |
2699 | INIT_LIST_HEAD(&oh->slave_ports); | |
dc6d1cda | 2700 | spin_lock_init(&oh->_lock); |
2092e5cc | 2701 | |
63c85238 PW |
2702 | oh->_state = _HWMOD_STATE_REGISTERED; |
2703 | ||
569edd70 PW |
2704 | /* |
2705 | * XXX Rather than doing a strcmp(), this should test a flag | |
2706 | * set in the hwmod data, inserted by the autogenerator code. | |
2707 | */ | |
2708 | if (!strcmp(oh->name, MPU_INITIATOR_NAME)) | |
2709 | mpu_oh = oh; | |
63c85238 | 2710 | |
569edd70 | 2711 | return 0; |
63c85238 PW |
2712 | } |
2713 | ||
2221b5cd PW |
2714 | /** |
2715 | * _alloc_links - return allocated memory for hwmod links | |
2716 | * @ml: pointer to a struct omap_hwmod_link * for the master link | |
2717 | * @sl: pointer to a struct omap_hwmod_link * for the slave link | |
2718 | * | |
2719 | * Return pointers to two struct omap_hwmod_link records, via the | |
2720 | * addresses pointed to by @ml and @sl. Will first attempt to return | |
2721 | * memory allocated as part of a large initial block, but if that has | |
2722 | * been exhausted, will allocate memory itself. Since ideally this | |
2723 | * second allocation path will never occur, the number of these | |
2724 | * 'supplemental' allocations will be logged when debugging is | |
2725 | * enabled. Returns 0. | |
2726 | */ | |
2727 | static int __init _alloc_links(struct omap_hwmod_link **ml, | |
2728 | struct omap_hwmod_link **sl) | |
2729 | { | |
2730 | unsigned int sz; | |
2731 | ||
2732 | if ((free_ls + LINKS_PER_OCP_IF) <= max_ls) { | |
2733 | *ml = &linkspace[free_ls++]; | |
2734 | *sl = &linkspace[free_ls++]; | |
2735 | return 0; | |
2736 | } | |
2737 | ||
2738 | sz = sizeof(struct omap_hwmod_link) * LINKS_PER_OCP_IF; | |
2739 | ||
2740 | *sl = NULL; | |
b6cb5bab | 2741 | *ml = memblock_virt_alloc(sz, 0); |
2221b5cd PW |
2742 | |
2743 | *sl = (void *)(*ml) + sizeof(struct omap_hwmod_link); | |
2744 | ||
2745 | ls_supp++; | |
2746 | pr_debug("omap_hwmod: supplemental link allocations needed: %d\n", | |
2747 | ls_supp * LINKS_PER_OCP_IF); | |
2748 | ||
2749 | return 0; | |
2750 | }; | |
2751 | ||
2752 | /** | |
2753 | * _add_link - add an interconnect between two IP blocks | |
2754 | * @oi: pointer to a struct omap_hwmod_ocp_if record | |
2755 | * | |
2756 | * Add struct omap_hwmod_link records connecting the master IP block | |
2757 | * specified in @oi->master to @oi, and connecting the slave IP block | |
2758 | * specified in @oi->slave to @oi. This code is assumed to run before | |
2759 | * preemption or SMP has been enabled, thus avoiding the need for | |
2760 | * locking in this code. Changes to this assumption will require | |
2761 | * additional locking. Returns 0. | |
2762 | */ | |
2763 | static int __init _add_link(struct omap_hwmod_ocp_if *oi) | |
2764 | { | |
2765 | struct omap_hwmod_link *ml, *sl; | |
2766 | ||
2767 | pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name, | |
2768 | oi->slave->name); | |
2769 | ||
2770 | _alloc_links(&ml, &sl); | |
2771 | ||
2772 | ml->ocp_if = oi; | |
2221b5cd PW |
2773 | list_add(&ml->node, &oi->master->master_ports); |
2774 | oi->master->masters_cnt++; | |
2775 | ||
2776 | sl->ocp_if = oi; | |
2221b5cd PW |
2777 | list_add(&sl->node, &oi->slave->slave_ports); |
2778 | oi->slave->slaves_cnt++; | |
2779 | ||
2780 | return 0; | |
2781 | } | |
2782 | ||
2783 | /** | |
2784 | * _register_link - register a struct omap_hwmod_ocp_if | |
2785 | * @oi: struct omap_hwmod_ocp_if * | |
2786 | * | |
2787 | * Registers the omap_hwmod_ocp_if record @oi. Returns -EEXIST if it | |
2788 | * has already been registered; -EINVAL if @oi is NULL or if the | |
2789 | * record pointed to by @oi is missing required fields; or 0 upon | |
2790 | * success. | |
2791 | * | |
2792 | * XXX The data should be copied into bootmem, so the original data | |
2793 | * should be marked __initdata and freed after init. This would allow | |
2794 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. | |
2795 | */ | |
2796 | static int __init _register_link(struct omap_hwmod_ocp_if *oi) | |
2797 | { | |
2798 | if (!oi || !oi->master || !oi->slave || !oi->user) | |
2799 | return -EINVAL; | |
2800 | ||
2801 | if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED) | |
2802 | return -EEXIST; | |
2803 | ||
2804 | pr_debug("omap_hwmod: registering link from %s to %s\n", | |
2805 | oi->master->name, oi->slave->name); | |
2806 | ||
2807 | /* | |
2808 | * Register the connected hwmods, if they haven't been | |
2809 | * registered already | |
2810 | */ | |
2811 | if (oi->master->_state != _HWMOD_STATE_REGISTERED) | |
2812 | _register(oi->master); | |
2813 | ||
2814 | if (oi->slave->_state != _HWMOD_STATE_REGISTERED) | |
2815 | _register(oi->slave); | |
2816 | ||
2817 | _add_link(oi); | |
2818 | ||
2819 | oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED; | |
2820 | ||
2821 | return 0; | |
2822 | } | |
2823 | ||
2824 | /** | |
2825 | * _alloc_linkspace - allocate large block of hwmod links | |
2826 | * @ois: pointer to an array of struct omap_hwmod_ocp_if records to count | |
2827 | * | |
2828 | * Allocate a large block of struct omap_hwmod_link records. This | |
2829 | * improves boot time significantly by avoiding the need to allocate | |
2830 | * individual records one by one. If the number of records to | |
2831 | * allocate in the block hasn't been manually specified, this function | |
2832 | * will count the number of struct omap_hwmod_ocp_if records in @ois | |
2833 | * and use that to determine the allocation size. For SoC families | |
2834 | * that require multiple list registrations, such as OMAP3xxx, this | |
2835 | * estimation process isn't optimal, so manual estimation is advised | |
2836 | * in those cases. Returns -EEXIST if the allocation has already occurred | |
2837 | * or 0 upon success. | |
2838 | */ | |
2839 | static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois) | |
2840 | { | |
2841 | unsigned int i = 0; | |
2842 | unsigned int sz; | |
2843 | ||
2844 | if (linkspace) { | |
2845 | WARN(1, "linkspace already allocated\n"); | |
2846 | return -EEXIST; | |
2847 | } | |
2848 | ||
2849 | if (max_ls == 0) | |
2850 | while (ois[i++]) | |
2851 | max_ls += LINKS_PER_OCP_IF; | |
2852 | ||
2853 | sz = sizeof(struct omap_hwmod_link) * max_ls; | |
2854 | ||
2855 | pr_debug("omap_hwmod: %s: allocating %d byte linkspace (%d links)\n", | |
2856 | __func__, sz, max_ls); | |
2857 | ||
b6cb5bab | 2858 | linkspace = memblock_virt_alloc(sz, 0); |
2221b5cd PW |
2859 | |
2860 | return 0; | |
2861 | } | |
0102b627 | 2862 | |
8f6aa8ee KH |
2863 | /* Static functions intended only for use in soc_ops field function pointers */ |
2864 | ||
2865 | /** | |
9002e921 | 2866 | * _omap2xxx_3xxx_wait_target_ready - wait for a module to leave slave idle |
8f6aa8ee KH |
2867 | * @oh: struct omap_hwmod * |
2868 | * | |
2869 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2870 | * does not have an IDLEST bit or if the module successfully leaves | |
2871 | * slave idle; otherwise, pass along the return value of the | |
2872 | * appropriate *_cm*_wait_module_ready() function. | |
2873 | */ | |
9002e921 | 2874 | static int _omap2xxx_3xxx_wait_target_ready(struct omap_hwmod *oh) |
8f6aa8ee KH |
2875 | { |
2876 | if (!oh) | |
2877 | return -EINVAL; | |
2878 | ||
2879 | if (oh->flags & HWMOD_NO_IDLEST) | |
2880 | return 0; | |
2881 | ||
2882 | if (!_find_mpu_rt_port(oh)) | |
2883 | return 0; | |
2884 | ||
2885 | /* XXX check module SIDLEMODE, hardreset status, enabled clocks */ | |
2886 | ||
021b6ff0 TK |
2887 | return omap_cm_wait_module_ready(0, oh->prcm.omap2.module_offs, |
2888 | oh->prcm.omap2.idlest_reg_id, | |
2889 | oh->prcm.omap2.idlest_idle_bit); | |
8f6aa8ee KH |
2890 | } |
2891 | ||
2892 | /** | |
2893 | * _omap4_wait_target_ready - wait for a module to leave slave idle | |
2894 | * @oh: struct omap_hwmod * | |
2895 | * | |
2896 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2897 | * does not have an IDLEST bit or if the module successfully leaves | |
2898 | * slave idle; otherwise, pass along the return value of the | |
2899 | * appropriate *_cm*_wait_module_ready() function. | |
2900 | */ | |
2901 | static int _omap4_wait_target_ready(struct omap_hwmod *oh) | |
2902 | { | |
2b026d13 | 2903 | if (!oh) |
8f6aa8ee KH |
2904 | return -EINVAL; |
2905 | ||
2b026d13 | 2906 | if (oh->flags & HWMOD_NO_IDLEST || !oh->clkdm) |
8f6aa8ee KH |
2907 | return 0; |
2908 | ||
2909 | if (!_find_mpu_rt_port(oh)) | |
2910 | return 0; | |
2911 | ||
2912 | /* XXX check module SIDLEMODE, hardreset status */ | |
2913 | ||
021b6ff0 TK |
2914 | return omap_cm_wait_module_ready(oh->clkdm->prcm_partition, |
2915 | oh->clkdm->cm_inst, | |
2916 | oh->prcm.omap4.clkctrl_offs, 0); | |
1688bf19 VH |
2917 | } |
2918 | ||
b8249cf2 KH |
2919 | /** |
2920 | * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | |
2921 | * @oh: struct omap_hwmod * to assert hardreset | |
2922 | * @ohri: hardreset line data | |
2923 | * | |
2924 | * Call omap2_prm_assert_hardreset() with parameters extracted from | |
2925 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | |
2926 | * use as an soc_ops function pointer. Passes along the return value | |
2927 | * from omap2_prm_assert_hardreset(). XXX This function is scheduled | |
2928 | * for removal when the PRM code is moved into drivers/. | |
2929 | */ | |
2930 | static int _omap2_assert_hardreset(struct omap_hwmod *oh, | |
2931 | struct omap_hwmod_rst_info *ohri) | |
2932 | { | |
efd44dc3 TK |
2933 | return omap_prm_assert_hardreset(ohri->rst_shift, 0, |
2934 | oh->prcm.omap2.module_offs, 0); | |
b8249cf2 KH |
2935 | } |
2936 | ||
2937 | /** | |
2938 | * _omap2_deassert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | |
2939 | * @oh: struct omap_hwmod * to deassert hardreset | |
2940 | * @ohri: hardreset line data | |
2941 | * | |
2942 | * Call omap2_prm_deassert_hardreset() with parameters extracted from | |
2943 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | |
2944 | * use as an soc_ops function pointer. Passes along the return value | |
2945 | * from omap2_prm_deassert_hardreset(). XXX This function is | |
2946 | * scheduled for removal when the PRM code is moved into drivers/. | |
2947 | */ | |
2948 | static int _omap2_deassert_hardreset(struct omap_hwmod *oh, | |
2949 | struct omap_hwmod_rst_info *ohri) | |
2950 | { | |
37fb59d7 TK |
2951 | return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, 0, |
2952 | oh->prcm.omap2.module_offs, 0, 0); | |
b8249cf2 KH |
2953 | } |
2954 | ||
2955 | /** | |
2956 | * _omap2_is_hardreset_asserted - call OMAP2 PRM hardreset fn with hwmod args | |
2957 | * @oh: struct omap_hwmod * to test hardreset | |
2958 | * @ohri: hardreset line data | |
2959 | * | |
2960 | * Call omap2_prm_is_hardreset_asserted() with parameters extracted | |
2961 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2962 | * intended for use as an soc_ops function pointer. Passes along the | |
2963 | * return value from omap2_prm_is_hardreset_asserted(). XXX This | |
2964 | * function is scheduled for removal when the PRM code is moved into | |
2965 | * drivers/. | |
2966 | */ | |
2967 | static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh, | |
2968 | struct omap_hwmod_rst_info *ohri) | |
2969 | { | |
1bc28b34 TK |
2970 | return omap_prm_is_hardreset_asserted(ohri->st_shift, 0, |
2971 | oh->prcm.omap2.module_offs, 0); | |
b8249cf2 KH |
2972 | } |
2973 | ||
2974 | /** | |
2975 | * _omap4_assert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | |
2976 | * @oh: struct omap_hwmod * to assert hardreset | |
2977 | * @ohri: hardreset line data | |
2978 | * | |
2979 | * Call omap4_prminst_assert_hardreset() with parameters extracted | |
2980 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2981 | * intended for use as an soc_ops function pointer. Passes along the | |
2982 | * return value from omap4_prminst_assert_hardreset(). XXX This | |
2983 | * function is scheduled for removal when the PRM code is moved into | |
2984 | * drivers/. | |
2985 | */ | |
2986 | static int _omap4_assert_hardreset(struct omap_hwmod *oh, | |
2987 | struct omap_hwmod_rst_info *ohri) | |
b8249cf2 | 2988 | { |
07b3a139 PW |
2989 | if (!oh->clkdm) |
2990 | return -EINVAL; | |
2991 | ||
efd44dc3 TK |
2992 | return omap_prm_assert_hardreset(ohri->rst_shift, |
2993 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
2994 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2995 | oh->prcm.omap4.rstctrl_offs); | |
b8249cf2 KH |
2996 | } |
2997 | ||
2998 | /** | |
2999 | * _omap4_deassert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | |
3000 | * @oh: struct omap_hwmod * to deassert hardreset | |
3001 | * @ohri: hardreset line data | |
3002 | * | |
3003 | * Call omap4_prminst_deassert_hardreset() with parameters extracted | |
3004 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
3005 | * intended for use as an soc_ops function pointer. Passes along the | |
3006 | * return value from omap4_prminst_deassert_hardreset(). XXX This | |
3007 | * function is scheduled for removal when the PRM code is moved into | |
3008 | * drivers/. | |
3009 | */ | |
3010 | static int _omap4_deassert_hardreset(struct omap_hwmod *oh, | |
3011 | struct omap_hwmod_rst_info *ohri) | |
3012 | { | |
07b3a139 PW |
3013 | if (!oh->clkdm) |
3014 | return -EINVAL; | |
3015 | ||
b8249cf2 KH |
3016 | if (ohri->st_shift) |
3017 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | |
3018 | oh->name, ohri->name); | |
37fb59d7 TK |
3019 | return omap_prm_deassert_hardreset(ohri->rst_shift, 0, |
3020 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
3021 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
3022 | oh->prcm.omap4.rstctrl_offs, 0); | |
b8249cf2 KH |
3023 | } |
3024 | ||
3025 | /** | |
3026 | * _omap4_is_hardreset_asserted - call OMAP4 PRM hardreset fn with hwmod args | |
3027 | * @oh: struct omap_hwmod * to test hardreset | |
3028 | * @ohri: hardreset line data | |
3029 | * | |
3030 | * Call omap4_prminst_is_hardreset_asserted() with parameters | |
3031 | * extracted from the hwmod @oh and the hardreset line data @ohri. | |
3032 | * Only intended for use as an soc_ops function pointer. Passes along | |
3033 | * the return value from omap4_prminst_is_hardreset_asserted(). XXX | |
3034 | * This function is scheduled for removal when the PRM code is moved | |
3035 | * into drivers/. | |
3036 | */ | |
3037 | static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh, | |
3038 | struct omap_hwmod_rst_info *ohri) | |
3039 | { | |
07b3a139 PW |
3040 | if (!oh->clkdm) |
3041 | return -EINVAL; | |
3042 | ||
1bc28b34 TK |
3043 | return omap_prm_is_hardreset_asserted(ohri->rst_shift, |
3044 | oh->clkdm->pwrdm.ptr-> | |
3045 | prcm_partition, | |
3046 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
3047 | oh->prcm.omap4.rstctrl_offs); | |
b8249cf2 KH |
3048 | } |
3049 | ||
1688bf19 VH |
3050 | /** |
3051 | * _am33xx_assert_hardreset - call AM33XX PRM hardreset fn with hwmod args | |
3052 | * @oh: struct omap_hwmod * to assert hardreset | |
3053 | * @ohri: hardreset line data | |
3054 | * | |
3055 | * Call am33xx_prminst_assert_hardreset() with parameters extracted | |
3056 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
3057 | * intended for use as an soc_ops function pointer. Passes along the | |
3058 | * return value from am33xx_prminst_assert_hardreset(). XXX This | |
3059 | * function is scheduled for removal when the PRM code is moved into | |
3060 | * drivers/. | |
3061 | */ | |
3062 | static int _am33xx_assert_hardreset(struct omap_hwmod *oh, | |
3063 | struct omap_hwmod_rst_info *ohri) | |
3064 | ||
3065 | { | |
efd44dc3 TK |
3066 | return omap_prm_assert_hardreset(ohri->rst_shift, 0, |
3067 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
3068 | oh->prcm.omap4.rstctrl_offs); | |
1688bf19 VH |
3069 | } |
3070 | ||
3071 | /** | |
3072 | * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args | |
3073 | * @oh: struct omap_hwmod * to deassert hardreset | |
3074 | * @ohri: hardreset line data | |
3075 | * | |
3076 | * Call am33xx_prminst_deassert_hardreset() with parameters extracted | |
3077 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
3078 | * intended for use as an soc_ops function pointer. Passes along the | |
3079 | * return value from am33xx_prminst_deassert_hardreset(). XXX This | |
3080 | * function is scheduled for removal when the PRM code is moved into | |
3081 | * drivers/. | |
3082 | */ | |
3083 | static int _am33xx_deassert_hardreset(struct omap_hwmod *oh, | |
3084 | struct omap_hwmod_rst_info *ohri) | |
3085 | { | |
37fb59d7 TK |
3086 | return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, 0, |
3087 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
3088 | oh->prcm.omap4.rstctrl_offs, | |
3089 | oh->prcm.omap4.rstst_offs); | |
1688bf19 VH |
3090 | } |
3091 | ||
3092 | /** | |
3093 | * _am33xx_is_hardreset_asserted - call AM33XX PRM hardreset fn with hwmod args | |
3094 | * @oh: struct omap_hwmod * to test hardreset | |
3095 | * @ohri: hardreset line data | |
3096 | * | |
3097 | * Call am33xx_prminst_is_hardreset_asserted() with parameters | |
3098 | * extracted from the hwmod @oh and the hardreset line data @ohri. | |
3099 | * Only intended for use as an soc_ops function pointer. Passes along | |
3100 | * the return value from am33xx_prminst_is_hardreset_asserted(). XXX | |
3101 | * This function is scheduled for removal when the PRM code is moved | |
3102 | * into drivers/. | |
3103 | */ | |
3104 | static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh, | |
3105 | struct omap_hwmod_rst_info *ohri) | |
3106 | { | |
1bc28b34 TK |
3107 | return omap_prm_is_hardreset_asserted(ohri->rst_shift, 0, |
3108 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
3109 | oh->prcm.omap4.rstctrl_offs); | |
1688bf19 VH |
3110 | } |
3111 | ||
0102b627 BC |
3112 | /* Public functions */ |
3113 | ||
3114 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) | |
3115 | { | |
3116 | if (oh->flags & HWMOD_16BIT_REG) | |
edfaf05c | 3117 | return readw_relaxed(oh->_mpu_rt_va + reg_offs); |
0102b627 | 3118 | else |
edfaf05c | 3119 | return readl_relaxed(oh->_mpu_rt_va + reg_offs); |
0102b627 BC |
3120 | } |
3121 | ||
3122 | void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) | |
3123 | { | |
3124 | if (oh->flags & HWMOD_16BIT_REG) | |
edfaf05c | 3125 | writew_relaxed(v, oh->_mpu_rt_va + reg_offs); |
0102b627 | 3126 | else |
edfaf05c | 3127 | writel_relaxed(v, oh->_mpu_rt_va + reg_offs); |
0102b627 BC |
3128 | } |
3129 | ||
6d3c55fd A |
3130 | /** |
3131 | * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit | |
3132 | * @oh: struct omap_hwmod * | |
3133 | * | |
3134 | * This is a public function exposed to drivers. Some drivers may need to do | |
3135 | * some settings before and after resetting the device. Those drivers after | |
3136 | * doing the necessary settings could use this function to start a reset by | |
3137 | * setting the SYSCONFIG.SOFTRESET bit. | |
3138 | */ | |
3139 | int omap_hwmod_softreset(struct omap_hwmod *oh) | |
3140 | { | |
3c55c1ba PW |
3141 | u32 v; |
3142 | int ret; | |
3143 | ||
3144 | if (!oh || !(oh->_sysc_cache)) | |
6d3c55fd A |
3145 | return -EINVAL; |
3146 | ||
3c55c1ba PW |
3147 | v = oh->_sysc_cache; |
3148 | ret = _set_softreset(oh, &v); | |
3149 | if (ret) | |
3150 | goto error; | |
3151 | _write_sysconfig(v, oh); | |
3152 | ||
313a76ee RQ |
3153 | ret = _clear_softreset(oh, &v); |
3154 | if (ret) | |
3155 | goto error; | |
3156 | _write_sysconfig(v, oh); | |
3157 | ||
3c55c1ba PW |
3158 | error: |
3159 | return ret; | |
6d3c55fd A |
3160 | } |
3161 | ||
63c85238 PW |
3162 | /** |
3163 | * omap_hwmod_lookup - look up a registered omap_hwmod by name | |
3164 | * @name: name of the omap_hwmod to look up | |
3165 | * | |
3166 | * Given a @name of an omap_hwmod, return a pointer to the registered | |
3167 | * struct omap_hwmod *, or NULL upon error. | |
3168 | */ | |
3169 | struct omap_hwmod *omap_hwmod_lookup(const char *name) | |
3170 | { | |
3171 | struct omap_hwmod *oh; | |
3172 | ||
3173 | if (!name) | |
3174 | return NULL; | |
3175 | ||
63c85238 | 3176 | oh = _lookup(name); |
63c85238 PW |
3177 | |
3178 | return oh; | |
3179 | } | |
3180 | ||
3181 | /** | |
3182 | * omap_hwmod_for_each - call function for each registered omap_hwmod | |
3183 | * @fn: pointer to a callback function | |
97d60162 | 3184 | * @data: void * data to pass to callback function |
63c85238 PW |
3185 | * |
3186 | * Call @fn for each registered omap_hwmod, passing @data to each | |
3187 | * function. @fn must return 0 for success or any other value for | |
3188 | * failure. If @fn returns non-zero, the iteration across omap_hwmods | |
3189 | * will stop and the non-zero return value will be passed to the | |
3190 | * caller of omap_hwmod_for_each(). @fn is called with | |
3191 | * omap_hwmod_for_each() held. | |
3192 | */ | |
97d60162 PW |
3193 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
3194 | void *data) | |
63c85238 PW |
3195 | { |
3196 | struct omap_hwmod *temp_oh; | |
30ebad9d | 3197 | int ret = 0; |
63c85238 PW |
3198 | |
3199 | if (!fn) | |
3200 | return -EINVAL; | |
3201 | ||
63c85238 | 3202 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
97d60162 | 3203 | ret = (*fn)(temp_oh, data); |
63c85238 PW |
3204 | if (ret) |
3205 | break; | |
3206 | } | |
63c85238 PW |
3207 | |
3208 | return ret; | |
3209 | } | |
3210 | ||
2221b5cd PW |
3211 | /** |
3212 | * omap_hwmod_register_links - register an array of hwmod links | |
3213 | * @ois: pointer to an array of omap_hwmod_ocp_if to register | |
3214 | * | |
3215 | * Intended to be called early in boot before the clock framework is | |
3216 | * initialized. If @ois is not null, will register all omap_hwmods | |
9ebfd285 KH |
3217 | * listed in @ois that are valid for this chip. Returns -EINVAL if |
3218 | * omap_hwmod_init() hasn't been called before calling this function, | |
3219 | * -ENOMEM if the link memory area can't be allocated, or 0 upon | |
3220 | * success. | |
2221b5cd PW |
3221 | */ |
3222 | int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois) | |
3223 | { | |
3224 | int r, i; | |
3225 | ||
9ebfd285 KH |
3226 | if (!inited) |
3227 | return -EINVAL; | |
3228 | ||
2221b5cd PW |
3229 | if (!ois) |
3230 | return 0; | |
3231 | ||
f7f7a29b RN |
3232 | if (ois[0] == NULL) /* Empty list */ |
3233 | return 0; | |
3234 | ||
2221b5cd PW |
3235 | if (!linkspace) { |
3236 | if (_alloc_linkspace(ois)) { | |
3237 | pr_err("omap_hwmod: could not allocate link space\n"); | |
3238 | return -ENOMEM; | |
3239 | } | |
3240 | } | |
3241 | ||
3242 | i = 0; | |
3243 | do { | |
3244 | r = _register_link(ois[i]); | |
3245 | WARN(r && r != -EEXIST, | |
3246 | "omap_hwmod: _register_link(%s -> %s) returned %d\n", | |
3247 | ois[i]->master->name, ois[i]->slave->name, r); | |
3248 | } while (ois[++i]); | |
3249 | ||
3250 | return 0; | |
3251 | } | |
3252 | ||
381d033a PW |
3253 | /** |
3254 | * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up | |
3255 | * @oh: pointer to the hwmod currently being set up (usually not the MPU) | |
3256 | * | |
3257 | * If the hwmod data corresponding to the MPU subsystem IP block | |
3258 | * hasn't been initialized and set up yet, do so now. This must be | |
3259 | * done first since sleep dependencies may be added from other hwmods | |
3260 | * to the MPU. Intended to be called only by omap_hwmod_setup*(). No | |
3261 | * return value. | |
63c85238 | 3262 | */ |
381d033a | 3263 | static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh) |
e7c7d760 | 3264 | { |
381d033a PW |
3265 | if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN) |
3266 | pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", | |
3267 | __func__, MPU_INITIATOR_NAME); | |
3268 | else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) | |
3269 | omap_hwmod_setup_one(MPU_INITIATOR_NAME); | |
e7c7d760 TL |
3270 | } |
3271 | ||
63c85238 | 3272 | /** |
a2debdbd PW |
3273 | * omap_hwmod_setup_one - set up a single hwmod |
3274 | * @oh_name: const char * name of the already-registered hwmod to set up | |
3275 | * | |
381d033a PW |
3276 | * Initialize and set up a single hwmod. Intended to be used for a |
3277 | * small number of early devices, such as the timer IP blocks used for | |
3278 | * the scheduler clock. Must be called after omap2_clk_init(). | |
3279 | * Resolves the struct clk names to struct clk pointers for each | |
3280 | * registered omap_hwmod. Also calls _setup() on each hwmod. Returns | |
3281 | * -EINVAL upon error or 0 upon success. | |
a2debdbd PW |
3282 | */ |
3283 | int __init omap_hwmod_setup_one(const char *oh_name) | |
63c85238 PW |
3284 | { |
3285 | struct omap_hwmod *oh; | |
63c85238 | 3286 | |
a2debdbd PW |
3287 | pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); |
3288 | ||
a2debdbd PW |
3289 | oh = _lookup(oh_name); |
3290 | if (!oh) { | |
3291 | WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); | |
3292 | return -EINVAL; | |
3293 | } | |
63c85238 | 3294 | |
381d033a | 3295 | _ensure_mpu_hwmod_is_setup(oh); |
63c85238 | 3296 | |
381d033a | 3297 | _init(oh, NULL); |
a2debdbd PW |
3298 | _setup(oh, NULL); |
3299 | ||
63c85238 PW |
3300 | return 0; |
3301 | } | |
3302 | ||
3303 | /** | |
381d033a | 3304 | * omap_hwmod_setup_all - set up all registered IP blocks |
63c85238 | 3305 | * |
381d033a PW |
3306 | * Initialize and set up all IP blocks registered with the hwmod code. |
3307 | * Must be called after omap2_clk_init(). Resolves the struct clk | |
3308 | * names to struct clk pointers for each registered omap_hwmod. Also | |
3309 | * calls _setup() on each hwmod. Returns 0 upon success. | |
63c85238 | 3310 | */ |
550c8092 | 3311 | static int __init omap_hwmod_setup_all(void) |
63c85238 | 3312 | { |
381d033a | 3313 | _ensure_mpu_hwmod_is_setup(NULL); |
63c85238 | 3314 | |
381d033a | 3315 | omap_hwmod_for_each(_init, NULL); |
2092e5cc | 3316 | omap_hwmod_for_each(_setup, NULL); |
63c85238 PW |
3317 | |
3318 | return 0; | |
3319 | } | |
b76c8b19 | 3320 | omap_core_initcall(omap_hwmod_setup_all); |
63c85238 | 3321 | |
63c85238 PW |
3322 | /** |
3323 | * omap_hwmod_enable - enable an omap_hwmod | |
3324 | * @oh: struct omap_hwmod * | |
3325 | * | |
74ff3a68 | 3326 | * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable(). |
63c85238 PW |
3327 | * Returns -EINVAL on error or passes along the return value from _enable(). |
3328 | */ | |
3329 | int omap_hwmod_enable(struct omap_hwmod *oh) | |
3330 | { | |
3331 | int r; | |
dc6d1cda | 3332 | unsigned long flags; |
63c85238 PW |
3333 | |
3334 | if (!oh) | |
3335 | return -EINVAL; | |
3336 | ||
dc6d1cda PW |
3337 | spin_lock_irqsave(&oh->_lock, flags); |
3338 | r = _enable(oh); | |
3339 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
3340 | |
3341 | return r; | |
3342 | } | |
3343 | ||
3344 | /** | |
3345 | * omap_hwmod_idle - idle an omap_hwmod | |
3346 | * @oh: struct omap_hwmod * | |
3347 | * | |
74ff3a68 | 3348 | * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle(). |
63c85238 PW |
3349 | * Returns -EINVAL on error or passes along the return value from _idle(). |
3350 | */ | |
3351 | int omap_hwmod_idle(struct omap_hwmod *oh) | |
3352 | { | |
dc6d1cda PW |
3353 | unsigned long flags; |
3354 | ||
63c85238 PW |
3355 | if (!oh) |
3356 | return -EINVAL; | |
3357 | ||
dc6d1cda PW |
3358 | spin_lock_irqsave(&oh->_lock, flags); |
3359 | _idle(oh); | |
3360 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
3361 | |
3362 | return 0; | |
3363 | } | |
3364 | ||
3365 | /** | |
3366 | * omap_hwmod_shutdown - shutdown an omap_hwmod | |
3367 | * @oh: struct omap_hwmod * | |
3368 | * | |
74ff3a68 | 3369 | * Shutdown an omap_hwmod @oh. Intended to be called by |
63c85238 PW |
3370 | * omap_device_shutdown(). Returns -EINVAL on error or passes along |
3371 | * the return value from _shutdown(). | |
3372 | */ | |
3373 | int omap_hwmod_shutdown(struct omap_hwmod *oh) | |
3374 | { | |
dc6d1cda PW |
3375 | unsigned long flags; |
3376 | ||
63c85238 PW |
3377 | if (!oh) |
3378 | return -EINVAL; | |
3379 | ||
dc6d1cda | 3380 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 3381 | _shutdown(oh); |
dc6d1cda | 3382 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3383 | |
3384 | return 0; | |
3385 | } | |
3386 | ||
3387 | /** | |
3388 | * omap_hwmod_enable_clocks - enable main_clk, all interface clocks | |
3389 | * @oh: struct omap_hwmod *oh | |
3390 | * | |
3391 | * Intended to be called by the omap_device code. | |
3392 | */ | |
3393 | int omap_hwmod_enable_clocks(struct omap_hwmod *oh) | |
3394 | { | |
dc6d1cda PW |
3395 | unsigned long flags; |
3396 | ||
3397 | spin_lock_irqsave(&oh->_lock, flags); | |
63c85238 | 3398 | _enable_clocks(oh); |
dc6d1cda | 3399 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3400 | |
3401 | return 0; | |
3402 | } | |
3403 | ||
3404 | /** | |
3405 | * omap_hwmod_disable_clocks - disable main_clk, all interface clocks | |
3406 | * @oh: struct omap_hwmod *oh | |
3407 | * | |
3408 | * Intended to be called by the omap_device code. | |
3409 | */ | |
3410 | int omap_hwmod_disable_clocks(struct omap_hwmod *oh) | |
3411 | { | |
dc6d1cda PW |
3412 | unsigned long flags; |
3413 | ||
3414 | spin_lock_irqsave(&oh->_lock, flags); | |
63c85238 | 3415 | _disable_clocks(oh); |
dc6d1cda | 3416 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3417 | |
3418 | return 0; | |
3419 | } | |
3420 | ||
3421 | /** | |
3422 | * omap_hwmod_ocp_barrier - wait for posted writes against the hwmod to complete | |
3423 | * @oh: struct omap_hwmod *oh | |
3424 | * | |
3425 | * Intended to be called by drivers and core code when all posted | |
3426 | * writes to a device must complete before continuing further | |
3427 | * execution (for example, after clearing some device IRQSTATUS | |
3428 | * register bits) | |
3429 | * | |
3430 | * XXX what about targets with multiple OCP threads? | |
3431 | */ | |
3432 | void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) | |
3433 | { | |
3434 | BUG_ON(!oh); | |
3435 | ||
43b40992 | 3436 | if (!oh->class->sysc || !oh->class->sysc->sysc_flags) { |
4f8a428d RK |
3437 | WARN(1, "omap_device: %s: OCP barrier impossible due to device configuration\n", |
3438 | oh->name); | |
63c85238 PW |
3439 | return; |
3440 | } | |
3441 | ||
3442 | /* | |
3443 | * Forces posted writes to complete on the OCP thread handling | |
3444 | * register writes | |
3445 | */ | |
cc7a1d2a | 3446 | omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 PW |
3447 | } |
3448 | ||
3449 | /** | |
3450 | * omap_hwmod_reset - reset the hwmod | |
3451 | * @oh: struct omap_hwmod * | |
3452 | * | |
3453 | * Under some conditions, a driver may wish to reset the entire device. | |
3454 | * Called from omap_device code. Returns -EINVAL on error or passes along | |
9b579114 | 3455 | * the return value from _reset(). |
63c85238 PW |
3456 | */ |
3457 | int omap_hwmod_reset(struct omap_hwmod *oh) | |
3458 | { | |
3459 | int r; | |
dc6d1cda | 3460 | unsigned long flags; |
63c85238 | 3461 | |
9b579114 | 3462 | if (!oh) |
63c85238 PW |
3463 | return -EINVAL; |
3464 | ||
dc6d1cda | 3465 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 3466 | r = _reset(oh); |
dc6d1cda | 3467 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3468 | |
3469 | return r; | |
3470 | } | |
3471 | ||
5e8370f1 PW |
3472 | /* |
3473 | * IP block data retrieval functions | |
3474 | */ | |
3475 | ||
63c85238 PW |
3476 | /** |
3477 | * omap_hwmod_count_resources - count number of struct resources needed by hwmod | |
3478 | * @oh: struct omap_hwmod * | |
dad4191d | 3479 | * @flags: Type of resources to include when counting (IRQ/DMA/MEM) |
63c85238 PW |
3480 | * |
3481 | * Count the number of struct resource array elements necessary to | |
3482 | * contain omap_hwmod @oh resources. Intended to be called by code | |
3483 | * that registers omap_devices. Intended to be used to determine the | |
3484 | * size of a dynamically-allocated struct resource array, before | |
3485 | * calling omap_hwmod_fill_resources(). Returns the number of struct | |
3486 | * resource array elements needed. | |
3487 | * | |
3488 | * XXX This code is not optimized. It could attempt to merge adjacent | |
3489 | * resource IDs. | |
3490 | * | |
3491 | */ | |
dad4191d | 3492 | int omap_hwmod_count_resources(struct omap_hwmod *oh, unsigned long flags) |
63c85238 | 3493 | { |
dad4191d | 3494 | int ret = 0; |
63c85238 | 3495 | |
dad4191d PU |
3496 | if (flags & IORESOURCE_IRQ) |
3497 | ret += _count_mpu_irqs(oh); | |
63c85238 | 3498 | |
dad4191d PU |
3499 | if (flags & IORESOURCE_DMA) |
3500 | ret += _count_sdma_reqs(oh); | |
2221b5cd | 3501 | |
dad4191d PU |
3502 | if (flags & IORESOURCE_MEM) { |
3503 | int i = 0; | |
3504 | struct omap_hwmod_ocp_if *os; | |
3505 | struct list_head *p = oh->slave_ports.next; | |
3506 | ||
3507 | while (i < oh->slaves_cnt) { | |
3508 | os = _fetch_next_ocp_if(&p, &i); | |
3509 | ret += _count_ocp_if_addr_spaces(os); | |
3510 | } | |
5d95dde7 | 3511 | } |
63c85238 PW |
3512 | |
3513 | return ret; | |
3514 | } | |
3515 | ||
3516 | /** | |
3517 | * omap_hwmod_fill_resources - fill struct resource array with hwmod data | |
3518 | * @oh: struct omap_hwmod * | |
3519 | * @res: pointer to the first element of an array of struct resource to fill | |
3520 | * | |
3521 | * Fill the struct resource array @res with resource data from the | |
3522 | * omap_hwmod @oh. Intended to be called by code that registers | |
3523 | * omap_devices. See also omap_hwmod_count_resources(). Returns the | |
3524 | * number of array elements filled. | |
3525 | */ | |
3526 | int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) | |
3527 | { | |
5d95dde7 | 3528 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 3529 | struct list_head *p; |
5d95dde7 | 3530 | int i, j, mpu_irqs_cnt, sdma_reqs_cnt, addr_cnt; |
63c85238 PW |
3531 | int r = 0; |
3532 | ||
3533 | /* For each IRQ, DMA, memory area, fill in array.*/ | |
3534 | ||
212738a4 PW |
3535 | mpu_irqs_cnt = _count_mpu_irqs(oh); |
3536 | for (i = 0; i < mpu_irqs_cnt; i++) { | |
0fb22a8f MZ |
3537 | unsigned int irq; |
3538 | ||
3539 | if (oh->xlate_irq) | |
3540 | irq = oh->xlate_irq((oh->mpu_irqs + i)->irq); | |
3541 | else | |
3542 | irq = (oh->mpu_irqs + i)->irq; | |
718bfd76 | 3543 | (res + r)->name = (oh->mpu_irqs + i)->name; |
0fb22a8f MZ |
3544 | (res + r)->start = irq; |
3545 | (res + r)->end = irq; | |
63c85238 PW |
3546 | (res + r)->flags = IORESOURCE_IRQ; |
3547 | r++; | |
3548 | } | |
3549 | ||
bc614958 PW |
3550 | sdma_reqs_cnt = _count_sdma_reqs(oh); |
3551 | for (i = 0; i < sdma_reqs_cnt; i++) { | |
9ee9fff9 BC |
3552 | (res + r)->name = (oh->sdma_reqs + i)->name; |
3553 | (res + r)->start = (oh->sdma_reqs + i)->dma_req; | |
3554 | (res + r)->end = (oh->sdma_reqs + i)->dma_req; | |
63c85238 PW |
3555 | (res + r)->flags = IORESOURCE_DMA; |
3556 | r++; | |
3557 | } | |
3558 | ||
11cd4b94 | 3559 | p = oh->slave_ports.next; |
2221b5cd | 3560 | |
5d95dde7 PW |
3561 | i = 0; |
3562 | while (i < oh->slaves_cnt) { | |
11cd4b94 | 3563 | os = _fetch_next_ocp_if(&p, &i); |
78183f3f | 3564 | addr_cnt = _count_ocp_if_addr_spaces(os); |
63c85238 | 3565 | |
78183f3f | 3566 | for (j = 0; j < addr_cnt; j++) { |
cd503802 | 3567 | (res + r)->name = (os->addr + j)->name; |
63c85238 PW |
3568 | (res + r)->start = (os->addr + j)->pa_start; |
3569 | (res + r)->end = (os->addr + j)->pa_end; | |
3570 | (res + r)->flags = IORESOURCE_MEM; | |
3571 | r++; | |
3572 | } | |
3573 | } | |
3574 | ||
3575 | return r; | |
3576 | } | |
3577 | ||
b82b04e8 VH |
3578 | /** |
3579 | * omap_hwmod_fill_dma_resources - fill struct resource array with dma data | |
3580 | * @oh: struct omap_hwmod * | |
3581 | * @res: pointer to the array of struct resource to fill | |
3582 | * | |
3583 | * Fill the struct resource array @res with dma resource data from the | |
3584 | * omap_hwmod @oh. Intended to be called by code that registers | |
3585 | * omap_devices. See also omap_hwmod_count_resources(). Returns the | |
3586 | * number of array elements filled. | |
3587 | */ | |
3588 | int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res) | |
3589 | { | |
3590 | int i, sdma_reqs_cnt; | |
3591 | int r = 0; | |
3592 | ||
3593 | sdma_reqs_cnt = _count_sdma_reqs(oh); | |
3594 | for (i = 0; i < sdma_reqs_cnt; i++) { | |
3595 | (res + r)->name = (oh->sdma_reqs + i)->name; | |
3596 | (res + r)->start = (oh->sdma_reqs + i)->dma_req; | |
3597 | (res + r)->end = (oh->sdma_reqs + i)->dma_req; | |
3598 | (res + r)->flags = IORESOURCE_DMA; | |
3599 | r++; | |
3600 | } | |
3601 | ||
3602 | return r; | |
3603 | } | |
3604 | ||
5e8370f1 PW |
3605 | /** |
3606 | * omap_hwmod_get_resource_byname - fetch IP block integration data by name | |
3607 | * @oh: struct omap_hwmod * to operate on | |
3608 | * @type: one of the IORESOURCE_* constants from include/linux/ioport.h | |
3609 | * @name: pointer to the name of the data to fetch (optional) | |
3610 | * @rsrc: pointer to a struct resource, allocated by the caller | |
3611 | * | |
3612 | * Retrieve MPU IRQ, SDMA request line, or address space start/end | |
3613 | * data for the IP block pointed to by @oh. The data will be filled | |
3614 | * into a struct resource record pointed to by @rsrc. The struct | |
3615 | * resource must be allocated by the caller. When @name is non-null, | |
3616 | * the data associated with the matching entry in the IRQ/SDMA/address | |
3617 | * space hwmod data arrays will be returned. If @name is null, the | |
3618 | * first array entry will be returned. Data order is not meaningful | |
3619 | * in hwmod data, so callers are strongly encouraged to use a non-null | |
3620 | * @name whenever possible to avoid unpredictable effects if hwmod | |
3621 | * data is later added that causes data ordering to change. This | |
3622 | * function is only intended for use by OMAP core code. Device | |
3623 | * drivers should not call this function - the appropriate bus-related | |
3624 | * data accessor functions should be used instead. Returns 0 upon | |
3625 | * success or a negative error code upon error. | |
3626 | */ | |
3627 | int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, | |
3628 | const char *name, struct resource *rsrc) | |
3629 | { | |
3630 | int r; | |
3631 | unsigned int irq, dma; | |
3632 | u32 pa_start, pa_end; | |
3633 | ||
3634 | if (!oh || !rsrc) | |
3635 | return -EINVAL; | |
3636 | ||
3637 | if (type == IORESOURCE_IRQ) { | |
3638 | r = _get_mpu_irq_by_name(oh, name, &irq); | |
3639 | if (r) | |
3640 | return r; | |
3641 | ||
3642 | rsrc->start = irq; | |
3643 | rsrc->end = irq; | |
3644 | } else if (type == IORESOURCE_DMA) { | |
3645 | r = _get_sdma_req_by_name(oh, name, &dma); | |
3646 | if (r) | |
3647 | return r; | |
3648 | ||
3649 | rsrc->start = dma; | |
3650 | rsrc->end = dma; | |
3651 | } else if (type == IORESOURCE_MEM) { | |
3652 | r = _get_addr_space_by_name(oh, name, &pa_start, &pa_end); | |
3653 | if (r) | |
3654 | return r; | |
3655 | ||
3656 | rsrc->start = pa_start; | |
3657 | rsrc->end = pa_end; | |
3658 | } else { | |
3659 | return -EINVAL; | |
3660 | } | |
3661 | ||
3662 | rsrc->flags = type; | |
3663 | rsrc->name = name; | |
3664 | ||
3665 | return 0; | |
3666 | } | |
3667 | ||
63c85238 PW |
3668 | /** |
3669 | * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain | |
3670 | * @oh: struct omap_hwmod * | |
3671 | * | |
3672 | * Return the powerdomain pointer associated with the OMAP module | |
3673 | * @oh's main clock. If @oh does not have a main clk, return the | |
3674 | * powerdomain associated with the interface clock associated with the | |
3675 | * module's MPU port. (XXX Perhaps this should use the SDMA port | |
3676 | * instead?) Returns NULL on error, or a struct powerdomain * on | |
3677 | * success. | |
3678 | */ | |
3679 | struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) | |
3680 | { | |
3681 | struct clk *c; | |
2d6141ba | 3682 | struct omap_hwmod_ocp_if *oi; |
f5dd3bb5 | 3683 | struct clockdomain *clkdm; |
f5dd3bb5 | 3684 | struct clk_hw_omap *clk; |
63c85238 PW |
3685 | |
3686 | if (!oh) | |
3687 | return NULL; | |
3688 | ||
f5dd3bb5 RN |
3689 | if (oh->clkdm) |
3690 | return oh->clkdm->pwrdm.ptr; | |
3691 | ||
63c85238 PW |
3692 | if (oh->_clk) { |
3693 | c = oh->_clk; | |
3694 | } else { | |
2d6141ba PW |
3695 | oi = _find_mpu_rt_port(oh); |
3696 | if (!oi) | |
63c85238 | 3697 | return NULL; |
2d6141ba | 3698 | c = oi->_clk; |
63c85238 PW |
3699 | } |
3700 | ||
f5dd3bb5 RN |
3701 | clk = to_clk_hw_omap(__clk_get_hw(c)); |
3702 | clkdm = clk->clkdm; | |
f5dd3bb5 | 3703 | if (!clkdm) |
d5647c18 TG |
3704 | return NULL; |
3705 | ||
f5dd3bb5 | 3706 | return clkdm->pwrdm.ptr; |
63c85238 PW |
3707 | } |
3708 | ||
db2a60bf PW |
3709 | /** |
3710 | * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU) | |
3711 | * @oh: struct omap_hwmod * | |
3712 | * | |
3713 | * Returns the virtual address corresponding to the beginning of the | |
3714 | * module's register target, in the address range that is intended to | |
3715 | * be used by the MPU. Returns the virtual address upon success or NULL | |
3716 | * upon error. | |
3717 | */ | |
3718 | void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh) | |
3719 | { | |
3720 | if (!oh) | |
3721 | return NULL; | |
3722 | ||
3723 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
3724 | return NULL; | |
3725 | ||
3726 | if (oh->_state == _HWMOD_STATE_UNKNOWN) | |
3727 | return NULL; | |
3728 | ||
3729 | return oh->_mpu_rt_va; | |
3730 | } | |
3731 | ||
63c85238 PW |
3732 | /** |
3733 | * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh | |
3734 | * @oh: struct omap_hwmod * | |
3735 | * @init_oh: struct omap_hwmod * (initiator) | |
3736 | * | |
3737 | * Add a sleep dependency between the initiator @init_oh and @oh. | |
3738 | * Intended to be called by DSP/Bridge code via platform_data for the | |
3739 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
3740 | * code needs to add/del initiator dependencies dynamically | |
3741 | * before/after accessing a device. Returns the return value from | |
3742 | * _add_initiator_dep(). | |
3743 | * | |
3744 | * XXX Keep a usecount in the clockdomain code | |
3745 | */ | |
3746 | int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, | |
3747 | struct omap_hwmod *init_oh) | |
3748 | { | |
3749 | return _add_initiator_dep(oh, init_oh); | |
3750 | } | |
3751 | ||
3752 | /* | |
3753 | * XXX what about functions for drivers to save/restore ocp_sysconfig | |
3754 | * for context save/restore operations? | |
3755 | */ | |
3756 | ||
3757 | /** | |
3758 | * omap_hwmod_del_initiator_dep - remove sleepdep from @init_oh to @oh | |
3759 | * @oh: struct omap_hwmod * | |
3760 | * @init_oh: struct omap_hwmod * (initiator) | |
3761 | * | |
3762 | * Remove a sleep dependency between the initiator @init_oh and @oh. | |
3763 | * Intended to be called by DSP/Bridge code via platform_data for the | |
3764 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
3765 | * code needs to add/del initiator dependencies dynamically | |
3766 | * before/after accessing a device. Returns the return value from | |
3767 | * _del_initiator_dep(). | |
3768 | * | |
3769 | * XXX Keep a usecount in the clockdomain code | |
3770 | */ | |
3771 | int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, | |
3772 | struct omap_hwmod *init_oh) | |
3773 | { | |
3774 | return _del_initiator_dep(oh, init_oh); | |
3775 | } | |
3776 | ||
63c85238 PW |
3777 | /** |
3778 | * omap_hwmod_enable_wakeup - allow device to wake up the system | |
3779 | * @oh: struct omap_hwmod * | |
3780 | * | |
3781 | * Sets the module OCP socket ENAWAKEUP bit to allow the module to | |
2a1cc144 G |
3782 | * send wakeups to the PRCM, and enable I/O ring wakeup events for |
3783 | * this IP block if it has dynamic mux entries. Eventually this | |
3784 | * should set PRCM wakeup registers to cause the PRCM to receive | |
3785 | * wakeup events from the module. Does not set any wakeup routing | |
3786 | * registers beyond this point - if the module is to wake up any other | |
3787 | * module or subsystem, that must be set separately. Called by | |
3788 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
3789 | */ |
3790 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | |
3791 | { | |
dc6d1cda | 3792 | unsigned long flags; |
5a7ddcbd | 3793 | u32 v; |
dc6d1cda | 3794 | |
dc6d1cda | 3795 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
3796 | |
3797 | if (oh->class->sysc && | |
3798 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
3799 | v = oh->_sysc_cache; | |
3800 | _enable_wakeup(oh, &v); | |
3801 | _write_sysconfig(v, oh); | |
3802 | } | |
3803 | ||
eceec009 | 3804 | _set_idle_ioring_wakeup(oh, true); |
dc6d1cda | 3805 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3806 | |
3807 | return 0; | |
3808 | } | |
3809 | ||
3810 | /** | |
3811 | * omap_hwmod_disable_wakeup - prevent device from waking the system | |
3812 | * @oh: struct omap_hwmod * | |
3813 | * | |
3814 | * Clears the module OCP socket ENAWAKEUP bit to prevent the module | |
2a1cc144 G |
3815 | * from sending wakeups to the PRCM, and disable I/O ring wakeup |
3816 | * events for this IP block if it has dynamic mux entries. Eventually | |
3817 | * this should clear PRCM wakeup registers to cause the PRCM to ignore | |
3818 | * wakeup events from the module. Does not set any wakeup routing | |
3819 | * registers beyond this point - if the module is to wake up any other | |
3820 | * module or subsystem, that must be set separately. Called by | |
3821 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
3822 | */ |
3823 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | |
3824 | { | |
dc6d1cda | 3825 | unsigned long flags; |
5a7ddcbd | 3826 | u32 v; |
dc6d1cda | 3827 | |
dc6d1cda | 3828 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
3829 | |
3830 | if (oh->class->sysc && | |
3831 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
3832 | v = oh->_sysc_cache; | |
3833 | _disable_wakeup(oh, &v); | |
3834 | _write_sysconfig(v, oh); | |
3835 | } | |
3836 | ||
eceec009 | 3837 | _set_idle_ioring_wakeup(oh, false); |
dc6d1cda | 3838 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3839 | |
3840 | return 0; | |
3841 | } | |
43b40992 | 3842 | |
aee48e3c PW |
3843 | /** |
3844 | * omap_hwmod_assert_hardreset - assert the HW reset line of submodules | |
3845 | * contained in the hwmod module. | |
3846 | * @oh: struct omap_hwmod * | |
3847 | * @name: name of the reset line to lookup and assert | |
3848 | * | |
3849 | * Some IP like dsp, ipu or iva contain processor that require | |
3850 | * an HW reset line to be assert / deassert in order to enable fully | |
3851 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
3852 | * yet supported on this OMAP; otherwise, passes along the return value | |
3853 | * from _assert_hardreset(). | |
3854 | */ | |
3855 | int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) | |
3856 | { | |
3857 | int ret; | |
dc6d1cda | 3858 | unsigned long flags; |
aee48e3c PW |
3859 | |
3860 | if (!oh) | |
3861 | return -EINVAL; | |
3862 | ||
dc6d1cda | 3863 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3864 | ret = _assert_hardreset(oh, name); |
dc6d1cda | 3865 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3866 | |
3867 | return ret; | |
3868 | } | |
3869 | ||
3870 | /** | |
3871 | * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules | |
3872 | * contained in the hwmod module. | |
3873 | * @oh: struct omap_hwmod * | |
3874 | * @name: name of the reset line to look up and deassert | |
3875 | * | |
3876 | * Some IP like dsp, ipu or iva contain processor that require | |
3877 | * an HW reset line to be assert / deassert in order to enable fully | |
3878 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
3879 | * yet supported on this OMAP; otherwise, passes along the return value | |
3880 | * from _deassert_hardreset(). | |
3881 | */ | |
3882 | int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
3883 | { | |
3884 | int ret; | |
dc6d1cda | 3885 | unsigned long flags; |
aee48e3c PW |
3886 | |
3887 | if (!oh) | |
3888 | return -EINVAL; | |
3889 | ||
dc6d1cda | 3890 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3891 | ret = _deassert_hardreset(oh, name); |
dc6d1cda | 3892 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3893 | |
3894 | return ret; | |
3895 | } | |
3896 | ||
3897 | /** | |
3898 | * omap_hwmod_read_hardreset - read the HW reset line state of submodules | |
3899 | * contained in the hwmod module | |
3900 | * @oh: struct omap_hwmod * | |
3901 | * @name: name of the reset line to look up and read | |
3902 | * | |
3903 | * Return the current state of the hwmod @oh's reset line named @name: | |
3904 | * returns -EINVAL upon parameter error or if this operation | |
3905 | * is unsupported on the current OMAP; otherwise, passes along the return | |
3906 | * value from _read_hardreset(). | |
3907 | */ | |
3908 | int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name) | |
3909 | { | |
3910 | int ret; | |
dc6d1cda | 3911 | unsigned long flags; |
aee48e3c PW |
3912 | |
3913 | if (!oh) | |
3914 | return -EINVAL; | |
3915 | ||
dc6d1cda | 3916 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3917 | ret = _read_hardreset(oh, name); |
dc6d1cda | 3918 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3919 | |
3920 | return ret; | |
3921 | } | |
3922 | ||
3923 | ||
43b40992 PW |
3924 | /** |
3925 | * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname | |
3926 | * @classname: struct omap_hwmod_class name to search for | |
3927 | * @fn: callback function pointer to call for each hwmod in class @classname | |
3928 | * @user: arbitrary context data to pass to the callback function | |
3929 | * | |
ce35b244 BC |
3930 | * For each omap_hwmod of class @classname, call @fn. |
3931 | * If the callback function returns something other than | |
43b40992 PW |
3932 | * zero, the iterator is terminated, and the callback function's return |
3933 | * value is passed back to the caller. Returns 0 upon success, -EINVAL | |
3934 | * if @classname or @fn are NULL, or passes back the error code from @fn. | |
3935 | */ | |
3936 | int omap_hwmod_for_each_by_class(const char *classname, | |
3937 | int (*fn)(struct omap_hwmod *oh, | |
3938 | void *user), | |
3939 | void *user) | |
3940 | { | |
3941 | struct omap_hwmod *temp_oh; | |
3942 | int ret = 0; | |
3943 | ||
3944 | if (!classname || !fn) | |
3945 | return -EINVAL; | |
3946 | ||
3947 | pr_debug("omap_hwmod: %s: looking for modules of class %s\n", | |
3948 | __func__, classname); | |
3949 | ||
43b40992 PW |
3950 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
3951 | if (!strcmp(temp_oh->class->name, classname)) { | |
3952 | pr_debug("omap_hwmod: %s: %s: calling callback fn\n", | |
3953 | __func__, temp_oh->name); | |
3954 | ret = (*fn)(temp_oh, user); | |
3955 | if (ret) | |
3956 | break; | |
3957 | } | |
3958 | } | |
3959 | ||
43b40992 PW |
3960 | if (ret) |
3961 | pr_debug("omap_hwmod: %s: iterator terminated early: %d\n", | |
3962 | __func__, ret); | |
3963 | ||
3964 | return ret; | |
3965 | } | |
3966 | ||
2092e5cc PW |
3967 | /** |
3968 | * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod | |
3969 | * @oh: struct omap_hwmod * | |
3970 | * @state: state that _setup() should leave the hwmod in | |
3971 | * | |
550c8092 | 3972 | * Sets the hwmod state that @oh will enter at the end of _setup() |
64813c3f PW |
3973 | * (called by omap_hwmod_setup_*()). See also the documentation |
3974 | * for _setup_postsetup(), above. Returns 0 upon success or | |
3975 | * -EINVAL if there is a problem with the arguments or if the hwmod is | |
3976 | * in the wrong state. | |
2092e5cc PW |
3977 | */ |
3978 | int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) | |
3979 | { | |
3980 | int ret; | |
dc6d1cda | 3981 | unsigned long flags; |
2092e5cc PW |
3982 | |
3983 | if (!oh) | |
3984 | return -EINVAL; | |
3985 | ||
3986 | if (state != _HWMOD_STATE_DISABLED && | |
3987 | state != _HWMOD_STATE_ENABLED && | |
3988 | state != _HWMOD_STATE_IDLE) | |
3989 | return -EINVAL; | |
3990 | ||
dc6d1cda | 3991 | spin_lock_irqsave(&oh->_lock, flags); |
2092e5cc PW |
3992 | |
3993 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
3994 | ret = -EINVAL; | |
3995 | goto ohsps_unlock; | |
3996 | } | |
3997 | ||
3998 | oh->_postsetup_state = state; | |
3999 | ret = 0; | |
4000 | ||
4001 | ohsps_unlock: | |
dc6d1cda | 4002 | spin_unlock_irqrestore(&oh->_lock, flags); |
2092e5cc PW |
4003 | |
4004 | return ret; | |
4005 | } | |
c80705aa KH |
4006 | |
4007 | /** | |
4008 | * omap_hwmod_get_context_loss_count - get lost context count | |
4009 | * @oh: struct omap_hwmod * | |
4010 | * | |
e6d3a8b0 RN |
4011 | * Returns the context loss count of associated @oh |
4012 | * upon success, or zero if no context loss data is available. | |
c80705aa | 4013 | * |
e6d3a8b0 RN |
4014 | * On OMAP4, this queries the per-hwmod context loss register, |
4015 | * assuming one exists. If not, or on OMAP2/3, this queries the | |
4016 | * enclosing powerdomain context loss count. | |
c80705aa | 4017 | */ |
fc013873 | 4018 | int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh) |
c80705aa KH |
4019 | { |
4020 | struct powerdomain *pwrdm; | |
4021 | int ret = 0; | |
4022 | ||
e6d3a8b0 RN |
4023 | if (soc_ops.get_context_lost) |
4024 | return soc_ops.get_context_lost(oh); | |
4025 | ||
c80705aa KH |
4026 | pwrdm = omap_hwmod_get_pwrdm(oh); |
4027 | if (pwrdm) | |
4028 | ret = pwrdm_get_context_loss_count(pwrdm); | |
4029 | ||
4030 | return ret; | |
4031 | } | |
43b01643 PW |
4032 | |
4033 | /** | |
4034 | * omap_hwmod_no_setup_reset - prevent a hwmod from being reset upon setup | |
4035 | * @oh: struct omap_hwmod * | |
4036 | * | |
4037 | * Prevent the hwmod @oh from being reset during the setup process. | |
4038 | * Intended for use by board-*.c files on boards with devices that | |
4039 | * cannot tolerate being reset. Must be called before the hwmod has | |
4040 | * been set up. Returns 0 upon success or negative error code upon | |
4041 | * failure. | |
4042 | */ | |
4043 | int omap_hwmod_no_setup_reset(struct omap_hwmod *oh) | |
4044 | { | |
4045 | if (!oh) | |
4046 | return -EINVAL; | |
4047 | ||
4048 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
4049 | pr_err("omap_hwmod: %s: cannot prevent setup reset; in wrong state\n", | |
4050 | oh->name); | |
4051 | return -EINVAL; | |
4052 | } | |
4053 | ||
4054 | oh->flags |= HWMOD_INIT_NO_RESET; | |
4055 | ||
4056 | return 0; | |
4057 | } | |
abc2d545 TK |
4058 | |
4059 | /** | |
4060 | * omap_hwmod_pad_route_irq - route an I/O pad wakeup to a particular MPU IRQ | |
4061 | * @oh: struct omap_hwmod * containing hwmod mux entries | |
4062 | * @pad_idx: array index in oh->mux of the hwmod mux entry to route wakeup | |
4063 | * @irq_idx: the hwmod mpu_irqs array index of the IRQ to trigger on wakeup | |
4064 | * | |
4065 | * When an I/O pad wakeup arrives for the dynamic or wakeup hwmod mux | |
4066 | * entry number @pad_idx for the hwmod @oh, trigger the interrupt | |
4067 | * service routine for the hwmod's mpu_irqs array index @irq_idx. If | |
4068 | * this function is not called for a given pad_idx, then the ISR | |
4069 | * associated with @oh's first MPU IRQ will be triggered when an I/O | |
4070 | * pad wakeup occurs on that pad. Note that @pad_idx is the index of | |
4071 | * the _dynamic or wakeup_ entry: if there are other entries not | |
4072 | * marked with OMAP_DEVICE_PAD_WAKEUP or OMAP_DEVICE_PAD_REMUX, these | |
4073 | * entries are NOT COUNTED in the dynamic pad index. This function | |
4074 | * must be called separately for each pad that requires its interrupt | |
4075 | * to be re-routed this way. Returns -EINVAL if there is an argument | |
4076 | * problem or if @oh does not have hwmod mux entries or MPU IRQs; | |
4077 | * returns -ENOMEM if memory cannot be allocated; or 0 upon success. | |
4078 | * | |
4079 | * XXX This function interface is fragile. Rather than using array | |
4080 | * indexes, which are subject to unpredictable change, it should be | |
4081 | * using hwmod IRQ names, and some other stable key for the hwmod mux | |
4082 | * pad records. | |
4083 | */ | |
4084 | int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx) | |
4085 | { | |
4086 | int nr_irqs; | |
4087 | ||
4088 | might_sleep(); | |
4089 | ||
4090 | if (!oh || !oh->mux || !oh->mpu_irqs || pad_idx < 0 || | |
4091 | pad_idx >= oh->mux->nr_pads_dynamic) | |
4092 | return -EINVAL; | |
4093 | ||
4094 | /* Check the number of available mpu_irqs */ | |
4095 | for (nr_irqs = 0; oh->mpu_irqs[nr_irqs].irq >= 0; nr_irqs++) | |
4096 | ; | |
4097 | ||
4098 | if (irq_idx >= nr_irqs) | |
4099 | return -EINVAL; | |
4100 | ||
4101 | if (!oh->mux->irqs) { | |
4102 | /* XXX What frees this? */ | |
4103 | oh->mux->irqs = kzalloc(sizeof(int) * oh->mux->nr_pads_dynamic, | |
4104 | GFP_KERNEL); | |
4105 | if (!oh->mux->irqs) | |
4106 | return -ENOMEM; | |
4107 | } | |
4108 | oh->mux->irqs[pad_idx] = irq_idx; | |
4109 | ||
4110 | return 0; | |
4111 | } | |
9ebfd285 KH |
4112 | |
4113 | /** | |
4114 | * omap_hwmod_init - initialize the hwmod code | |
4115 | * | |
4116 | * Sets up some function pointers needed by the hwmod code to operate on the | |
4117 | * currently-booted SoC. Intended to be called once during kernel init | |
4118 | * before any hwmods are registered. No return value. | |
4119 | */ | |
4120 | void __init omap_hwmod_init(void) | |
4121 | { | |
ff4ae5d9 | 4122 | if (cpu_is_omap24xx()) { |
9002e921 | 4123 | soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready; |
ff4ae5d9 PW |
4124 | soc_ops.assert_hardreset = _omap2_assert_hardreset; |
4125 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | |
4126 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | |
4127 | } else if (cpu_is_omap34xx()) { | |
9002e921 | 4128 | soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready; |
b8249cf2 KH |
4129 | soc_ops.assert_hardreset = _omap2_assert_hardreset; |
4130 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | |
4131 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | |
0385c582 | 4132 | soc_ops.init_clkdm = _init_clkdm; |
debcd1f8 | 4133 | } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) { |
9ebfd285 KH |
4134 | soc_ops.enable_module = _omap4_enable_module; |
4135 | soc_ops.disable_module = _omap4_disable_module; | |
8f6aa8ee | 4136 | soc_ops.wait_target_ready = _omap4_wait_target_ready; |
b8249cf2 KH |
4137 | soc_ops.assert_hardreset = _omap4_assert_hardreset; |
4138 | soc_ops.deassert_hardreset = _omap4_deassert_hardreset; | |
4139 | soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; | |
0a179eaa | 4140 | soc_ops.init_clkdm = _init_clkdm; |
e6d3a8b0 RN |
4141 | soc_ops.update_context_lost = _omap4_update_context_lost; |
4142 | soc_ops.get_context_lost = _omap4_get_context_lost; | |
c8b428a5 AM |
4143 | } else if (soc_is_am43xx()) { |
4144 | soc_ops.enable_module = _omap4_enable_module; | |
4145 | soc_ops.disable_module = _omap4_disable_module; | |
4146 | soc_ops.wait_target_ready = _omap4_wait_target_ready; | |
409d7063 TK |
4147 | soc_ops.assert_hardreset = _omap4_assert_hardreset; |
4148 | soc_ops.deassert_hardreset = _omap4_deassert_hardreset; | |
4149 | soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; | |
c8b428a5 | 4150 | soc_ops.init_clkdm = _init_clkdm; |
1688bf19 | 4151 | } else if (soc_is_am33xx()) { |
05d2b093 TK |
4152 | soc_ops.enable_module = _omap4_enable_module; |
4153 | soc_ops.disable_module = _omap4_disable_module; | |
4154 | soc_ops.wait_target_ready = _omap4_wait_target_ready; | |
1688bf19 VH |
4155 | soc_ops.assert_hardreset = _am33xx_assert_hardreset; |
4156 | soc_ops.deassert_hardreset = _am33xx_deassert_hardreset; | |
4157 | soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted; | |
4158 | soc_ops.init_clkdm = _init_clkdm; | |
8f6aa8ee KH |
4159 | } else { |
4160 | WARN(1, "omap_hwmod: unknown SoC type\n"); | |
9ebfd285 KH |
4161 | } |
4162 | ||
4163 | inited = true; | |
4164 | } | |
68c9a95e TL |
4165 | |
4166 | /** | |
4167 | * omap_hwmod_get_main_clk - get pointer to main clock name | |
4168 | * @oh: struct omap_hwmod * | |
4169 | * | |
4170 | * Returns the main clock name assocated with @oh upon success, | |
4171 | * or NULL if @oh is NULL. | |
4172 | */ | |
4173 | const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh) | |
4174 | { | |
4175 | if (!oh) | |
4176 | return NULL; | |
4177 | ||
4178 | return oh->main_clk; | |
4179 | } |