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63c85238 PW |
1 | /* |
2 | * omap_hwmod implementation for OMAP2/3/4 | |
3 | * | |
550c8092 | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
30e105c0 | 5 | * Copyright (C) 2011-2012 Texas Instruments, Inc. |
63c85238 | 6 | * |
4788da26 PW |
7 | * Paul Walmsley, BenoƮt Cousson, Kevin Hilman |
8 | * | |
9 | * Created in collaboration with (alphabetical order): Thara Gopinath, | |
10 | * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand | |
11 | * Sawant, Santosh Shilimkar, Richard Woodruff | |
63c85238 PW |
12 | * |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | * | |
74ff3a68 PW |
17 | * Introduction |
18 | * ------------ | |
19 | * One way to view an OMAP SoC is as a collection of largely unrelated | |
20 | * IP blocks connected by interconnects. The IP blocks include | |
21 | * devices such as ARM processors, audio serial interfaces, UARTs, | |
22 | * etc. Some of these devices, like the DSP, are created by TI; | |
23 | * others, like the SGX, largely originate from external vendors. In | |
24 | * TI's documentation, on-chip devices are referred to as "OMAP | |
25 | * modules." Some of these IP blocks are identical across several | |
26 | * OMAP versions. Others are revised frequently. | |
63c85238 | 27 | * |
74ff3a68 PW |
28 | * These OMAP modules are tied together by various interconnects. |
29 | * Most of the address and data flow between modules is via OCP-based | |
30 | * interconnects such as the L3 and L4 buses; but there are other | |
31 | * interconnects that distribute the hardware clock tree, handle idle | |
32 | * and reset signaling, supply power, and connect the modules to | |
33 | * various pads or balls on the OMAP package. | |
34 | * | |
35 | * OMAP hwmod provides a consistent way to describe the on-chip | |
36 | * hardware blocks and their integration into the rest of the chip. | |
37 | * This description can be automatically generated from the TI | |
38 | * hardware database. OMAP hwmod provides a standard, consistent API | |
39 | * to reset, enable, idle, and disable these hardware blocks. And | |
40 | * hwmod provides a way for other core code, such as the Linux device | |
41 | * code or the OMAP power management and address space mapping code, | |
42 | * to query the hardware database. | |
43 | * | |
44 | * Using hwmod | |
45 | * ----------- | |
46 | * Drivers won't call hwmod functions directly. That is done by the | |
47 | * omap_device code, and in rare occasions, by custom integration code | |
48 | * in arch/arm/ *omap*. The omap_device code includes functions to | |
49 | * build a struct platform_device using omap_hwmod data, and that is | |
50 | * currently how hwmod data is communicated to drivers and to the | |
51 | * Linux driver model. Most drivers will call omap_hwmod functions only | |
52 | * indirectly, via pm_runtime*() functions. | |
53 | * | |
54 | * From a layering perspective, here is where the OMAP hwmod code | |
55 | * fits into the kernel software stack: | |
56 | * | |
57 | * +-------------------------------+ | |
58 | * | Device driver code | | |
59 | * | (e.g., drivers/) | | |
60 | * +-------------------------------+ | |
61 | * | Linux driver model | | |
62 | * | (platform_device / | | |
63 | * | platform_driver data/code) | | |
64 | * +-------------------------------+ | |
65 | * | OMAP core-driver integration | | |
66 | * |(arch/arm/mach-omap2/devices.c)| | |
67 | * +-------------------------------+ | |
68 | * | omap_device code | | |
69 | * | (../plat-omap/omap_device.c) | | |
70 | * +-------------------------------+ | |
71 | * ----> | omap_hwmod code/data | <----- | |
72 | * | (../mach-omap2/omap_hwmod*) | | |
73 | * +-------------------------------+ | |
74 | * | OMAP clock/PRCM/register fns | | |
edfaf05c | 75 | * | ({read,write}l_relaxed, clk*) | |
74ff3a68 PW |
76 | * +-------------------------------+ |
77 | * | |
78 | * Device drivers should not contain any OMAP-specific code or data in | |
79 | * them. They should only contain code to operate the IP block that | |
80 | * the driver is responsible for. This is because these IP blocks can | |
81 | * also appear in other SoCs, either from TI (such as DaVinci) or from | |
82 | * other manufacturers; and drivers should be reusable across other | |
83 | * platforms. | |
84 | * | |
85 | * The OMAP hwmod code also will attempt to reset and idle all on-chip | |
86 | * devices upon boot. The goal here is for the kernel to be | |
87 | * completely self-reliant and independent from bootloaders. This is | |
88 | * to ensure a repeatable configuration, both to ensure consistent | |
89 | * runtime behavior, and to make it easier for others to reproduce | |
90 | * bugs. | |
91 | * | |
92 | * OMAP module activity states | |
93 | * --------------------------- | |
94 | * The hwmod code considers modules to be in one of several activity | |
95 | * states. IP blocks start out in an UNKNOWN state, then once they | |
96 | * are registered via the hwmod code, proceed to the REGISTERED state. | |
97 | * Once their clock names are resolved to clock pointers, the module | |
98 | * enters the CLKS_INITED state; and finally, once the module has been | |
99 | * reset and the integration registers programmed, the INITIALIZED state | |
100 | * is entered. The hwmod code will then place the module into either | |
101 | * the IDLE state to save power, or in the case of a critical system | |
102 | * module, the ENABLED state. | |
103 | * | |
104 | * OMAP core integration code can then call omap_hwmod*() functions | |
105 | * directly to move the module between the IDLE, ENABLED, and DISABLED | |
106 | * states, as needed. This is done during both the PM idle loop, and | |
107 | * in the OMAP core integration code's implementation of the PM runtime | |
108 | * functions. | |
109 | * | |
110 | * References | |
111 | * ---------- | |
112 | * This is a partial list. | |
63c85238 PW |
113 | * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) |
114 | * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) | |
115 | * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) | |
116 | * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) | |
117 | * - Open Core Protocol Specification 2.2 | |
118 | * | |
119 | * To do: | |
63c85238 PW |
120 | * - handle IO mapping |
121 | * - bus throughput & module latency measurement code | |
122 | * | |
123 | * XXX add tests at the beginning of each function to ensure the hwmod is | |
124 | * in the appropriate state | |
125 | * XXX error return values should be checked to ensure that they are | |
126 | * appropriate | |
127 | */ | |
128 | #undef DEBUG | |
129 | ||
130 | #include <linux/kernel.h> | |
131 | #include <linux/errno.h> | |
132 | #include <linux/io.h> | |
f5b00f6f | 133 | #include <linux/clk.h> |
f5dd3bb5 | 134 | #include <linux/clk-provider.h> |
63c85238 PW |
135 | #include <linux/delay.h> |
136 | #include <linux/err.h> | |
137 | #include <linux/list.h> | |
138 | #include <linux/mutex.h> | |
dc6d1cda | 139 | #include <linux/spinlock.h> |
abc2d545 | 140 | #include <linux/slab.h> |
2221b5cd | 141 | #include <linux/bootmem.h> |
f7b861b7 | 142 | #include <linux/cpu.h> |
079abade SS |
143 | #include <linux/of.h> |
144 | #include <linux/of_address.h> | |
63c85238 | 145 | |
fa200222 PW |
146 | #include <asm/system_misc.h> |
147 | ||
a135eaae | 148 | #include "clock.h" |
2a296c8f | 149 | #include "omap_hwmod.h" |
63c85238 | 150 | |
dbc04161 TL |
151 | #include "soc.h" |
152 | #include "common.h" | |
153 | #include "clockdomain.h" | |
154 | #include "powerdomain.h" | |
ff4ae5d9 PW |
155 | #include "cm2xxx.h" |
156 | #include "cm3xxx.h" | |
1688bf19 | 157 | #include "cm33xx.h" |
b13159af | 158 | #include "prm.h" |
139563ad | 159 | #include "prm3xxx.h" |
d198b514 | 160 | #include "prm44xx.h" |
1688bf19 | 161 | #include "prm33xx.h" |
eaac329d | 162 | #include "prminst44xx.h" |
8d9af88f | 163 | #include "mux.h" |
5165882a | 164 | #include "pm.h" |
63c85238 | 165 | |
63c85238 | 166 | /* Name of the OMAP hwmod for the MPU */ |
5c2c0296 | 167 | #define MPU_INITIATOR_NAME "mpu" |
63c85238 | 168 | |
2221b5cd PW |
169 | /* |
170 | * Number of struct omap_hwmod_link records per struct | |
171 | * omap_hwmod_ocp_if record (master->slave and slave->master) | |
172 | */ | |
173 | #define LINKS_PER_OCP_IF 2 | |
174 | ||
4ebf5b28 TK |
175 | /* |
176 | * Address offset (in bytes) between the reset control and the reset | |
177 | * status registers: 4 bytes on OMAP4 | |
178 | */ | |
179 | #define OMAP4_RST_CTRL_ST_OFFSET 4 | |
180 | ||
9ebfd285 KH |
181 | /** |
182 | * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations | |
183 | * @enable_module: function to enable a module (via MODULEMODE) | |
184 | * @disable_module: function to disable a module (via MODULEMODE) | |
185 | * | |
186 | * XXX Eventually this functionality will be hidden inside the PRM/CM | |
187 | * device drivers. Until then, this should avoid huge blocks of cpu_is_*() | |
188 | * conditionals in this code. | |
189 | */ | |
190 | struct omap_hwmod_soc_ops { | |
191 | void (*enable_module)(struct omap_hwmod *oh); | |
192 | int (*disable_module)(struct omap_hwmod *oh); | |
8f6aa8ee | 193 | int (*wait_target_ready)(struct omap_hwmod *oh); |
b8249cf2 KH |
194 | int (*assert_hardreset)(struct omap_hwmod *oh, |
195 | struct omap_hwmod_rst_info *ohri); | |
196 | int (*deassert_hardreset)(struct omap_hwmod *oh, | |
197 | struct omap_hwmod_rst_info *ohri); | |
198 | int (*is_hardreset_asserted)(struct omap_hwmod *oh, | |
199 | struct omap_hwmod_rst_info *ohri); | |
0a179eaa | 200 | int (*init_clkdm)(struct omap_hwmod *oh); |
e6d3a8b0 RN |
201 | void (*update_context_lost)(struct omap_hwmod *oh); |
202 | int (*get_context_lost)(struct omap_hwmod *oh); | |
9ebfd285 KH |
203 | }; |
204 | ||
205 | /* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */ | |
206 | static struct omap_hwmod_soc_ops soc_ops; | |
207 | ||
63c85238 PW |
208 | /* omap_hwmod_list contains all registered struct omap_hwmods */ |
209 | static LIST_HEAD(omap_hwmod_list); | |
210 | ||
63c85238 PW |
211 | /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ |
212 | static struct omap_hwmod *mpu_oh; | |
213 | ||
5165882a VB |
214 | /* io_chain_lock: used to serialize reconfigurations of the I/O chain */ |
215 | static DEFINE_SPINLOCK(io_chain_lock); | |
216 | ||
2221b5cd PW |
217 | /* |
218 | * linkspace: ptr to a buffer that struct omap_hwmod_link records are | |
219 | * allocated from - used to reduce the number of small memory | |
220 | * allocations, which has a significant impact on performance | |
221 | */ | |
222 | static struct omap_hwmod_link *linkspace; | |
223 | ||
224 | /* | |
225 | * free_ls, max_ls: array indexes into linkspace; representing the | |
226 | * next free struct omap_hwmod_link index, and the maximum number of | |
227 | * struct omap_hwmod_link records allocated (respectively) | |
228 | */ | |
229 | static unsigned short free_ls, max_ls, ls_supp; | |
63c85238 | 230 | |
9ebfd285 KH |
231 | /* inited: set to true once the hwmod code is initialized */ |
232 | static bool inited; | |
233 | ||
63c85238 PW |
234 | /* Private functions */ |
235 | ||
5d95dde7 | 236 | /** |
11cd4b94 | 237 | * _fetch_next_ocp_if - return the next OCP interface in a list |
2221b5cd | 238 | * @p: ptr to a ptr to the list_head inside the ocp_if to return |
11cd4b94 PW |
239 | * @i: pointer to the index of the element pointed to by @p in the list |
240 | * | |
241 | * Return a pointer to the struct omap_hwmod_ocp_if record | |
242 | * containing the struct list_head pointed to by @p, and increment | |
243 | * @p such that a future call to this routine will return the next | |
244 | * record. | |
5d95dde7 PW |
245 | */ |
246 | static struct omap_hwmod_ocp_if *_fetch_next_ocp_if(struct list_head **p, | |
5d95dde7 PW |
247 | int *i) |
248 | { | |
249 | struct omap_hwmod_ocp_if *oi; | |
250 | ||
11cd4b94 PW |
251 | oi = list_entry(*p, struct omap_hwmod_link, node)->ocp_if; |
252 | *p = (*p)->next; | |
2221b5cd | 253 | |
5d95dde7 PW |
254 | *i = *i + 1; |
255 | ||
256 | return oi; | |
257 | } | |
258 | ||
63c85238 PW |
259 | /** |
260 | * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy | |
261 | * @oh: struct omap_hwmod * | |
262 | * | |
263 | * Load the current value of the hwmod OCP_SYSCONFIG register into the | |
264 | * struct omap_hwmod for later use. Returns -EINVAL if the hwmod has no | |
265 | * OCP_SYSCONFIG register or 0 upon success. | |
266 | */ | |
267 | static int _update_sysc_cache(struct omap_hwmod *oh) | |
268 | { | |
43b40992 PW |
269 | if (!oh->class->sysc) { |
270 | WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
271 | return -EINVAL; |
272 | } | |
273 | ||
274 | /* XXX ensure module interface clock is up */ | |
275 | ||
cc7a1d2a | 276 | oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 | 277 | |
43b40992 | 278 | if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) |
883edfdd | 279 | oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; |
63c85238 PW |
280 | |
281 | return 0; | |
282 | } | |
283 | ||
284 | /** | |
285 | * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register | |
286 | * @v: OCP_SYSCONFIG value to write | |
287 | * @oh: struct omap_hwmod * | |
288 | * | |
43b40992 PW |
289 | * Write @v into the module class' OCP_SYSCONFIG register, if it has |
290 | * one. No return value. | |
63c85238 PW |
291 | */ |
292 | static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | |
293 | { | |
43b40992 PW |
294 | if (!oh->class->sysc) { |
295 | WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
296 | return; |
297 | } | |
298 | ||
299 | /* XXX ensure module interface clock is up */ | |
300 | ||
233cbe5b RN |
301 | /* Module might have lost context, always update cache and register */ |
302 | oh->_sysc_cache = v; | |
aaf2c0fb LV |
303 | |
304 | /* | |
305 | * Some IP blocks (such as RTC) require unlocking of IP before | |
306 | * accessing its registers. If a function pointer is present | |
307 | * to unlock, then call it before accessing sysconfig and | |
308 | * call lock after writing sysconfig. | |
309 | */ | |
310 | if (oh->class->unlock) | |
311 | oh->class->unlock(oh); | |
312 | ||
233cbe5b | 313 | omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); |
aaf2c0fb LV |
314 | |
315 | if (oh->class->lock) | |
316 | oh->class->lock(oh); | |
63c85238 PW |
317 | } |
318 | ||
319 | /** | |
320 | * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v | |
321 | * @oh: struct omap_hwmod * | |
322 | * @standbymode: MIDLEMODE field bits | |
323 | * @v: pointer to register contents to modify | |
324 | * | |
325 | * Update the master standby mode bits in @v to be @standbymode for | |
326 | * the @oh hwmod. Does not write to the hardware. Returns -EINVAL | |
327 | * upon error or 0 upon success. | |
328 | */ | |
329 | static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, | |
330 | u32 *v) | |
331 | { | |
358f0e63 TG |
332 | u32 mstandby_mask; |
333 | u8 mstandby_shift; | |
334 | ||
43b40992 PW |
335 | if (!oh->class->sysc || |
336 | !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE)) | |
63c85238 PW |
337 | return -EINVAL; |
338 | ||
43b40992 PW |
339 | if (!oh->class->sysc->sysc_fields) { |
340 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
341 | return -EINVAL; |
342 | } | |
343 | ||
43b40992 | 344 | mstandby_shift = oh->class->sysc->sysc_fields->midle_shift; |
358f0e63 TG |
345 | mstandby_mask = (0x3 << mstandby_shift); |
346 | ||
347 | *v &= ~mstandby_mask; | |
348 | *v |= __ffs(standbymode) << mstandby_shift; | |
63c85238 PW |
349 | |
350 | return 0; | |
351 | } | |
352 | ||
353 | /** | |
354 | * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v | |
355 | * @oh: struct omap_hwmod * | |
356 | * @idlemode: SIDLEMODE field bits | |
357 | * @v: pointer to register contents to modify | |
358 | * | |
359 | * Update the slave idle mode bits in @v to be @idlemode for the @oh | |
360 | * hwmod. Does not write to the hardware. Returns -EINVAL upon error | |
361 | * or 0 upon success. | |
362 | */ | |
363 | static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) | |
364 | { | |
358f0e63 TG |
365 | u32 sidle_mask; |
366 | u8 sidle_shift; | |
367 | ||
43b40992 PW |
368 | if (!oh->class->sysc || |
369 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE)) | |
63c85238 PW |
370 | return -EINVAL; |
371 | ||
43b40992 PW |
372 | if (!oh->class->sysc->sysc_fields) { |
373 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
374 | return -EINVAL; |
375 | } | |
376 | ||
43b40992 | 377 | sidle_shift = oh->class->sysc->sysc_fields->sidle_shift; |
358f0e63 TG |
378 | sidle_mask = (0x3 << sidle_shift); |
379 | ||
380 | *v &= ~sidle_mask; | |
381 | *v |= __ffs(idlemode) << sidle_shift; | |
63c85238 PW |
382 | |
383 | return 0; | |
384 | } | |
385 | ||
386 | /** | |
387 | * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
388 | * @oh: struct omap_hwmod * | |
389 | * @clockact: CLOCKACTIVITY field bits | |
390 | * @v: pointer to register contents to modify | |
391 | * | |
392 | * Update the clockactivity mode bits in @v to be @clockact for the | |
393 | * @oh hwmod. Used for additional powersaving on some modules. Does | |
394 | * not write to the hardware. Returns -EINVAL upon error or 0 upon | |
395 | * success. | |
396 | */ | |
397 | static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) | |
398 | { | |
358f0e63 TG |
399 | u32 clkact_mask; |
400 | u8 clkact_shift; | |
401 | ||
43b40992 PW |
402 | if (!oh->class->sysc || |
403 | !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) | |
63c85238 PW |
404 | return -EINVAL; |
405 | ||
43b40992 PW |
406 | if (!oh->class->sysc->sysc_fields) { |
407 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
408 | return -EINVAL; |
409 | } | |
410 | ||
43b40992 | 411 | clkact_shift = oh->class->sysc->sysc_fields->clkact_shift; |
358f0e63 TG |
412 | clkact_mask = (0x3 << clkact_shift); |
413 | ||
414 | *v &= ~clkact_mask; | |
415 | *v |= clockact << clkact_shift; | |
63c85238 PW |
416 | |
417 | return 0; | |
418 | } | |
419 | ||
420 | /** | |
313a76ee | 421 | * _set_softreset: set OCP_SYSCONFIG.SOFTRESET bit in @v |
63c85238 PW |
422 | * @oh: struct omap_hwmod * |
423 | * @v: pointer to register contents to modify | |
424 | * | |
425 | * Set the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
426 | * error or 0 upon success. | |
427 | */ | |
428 | static int _set_softreset(struct omap_hwmod *oh, u32 *v) | |
429 | { | |
358f0e63 TG |
430 | u32 softrst_mask; |
431 | ||
43b40992 PW |
432 | if (!oh->class->sysc || |
433 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
63c85238 PW |
434 | return -EINVAL; |
435 | ||
43b40992 PW |
436 | if (!oh->class->sysc->sysc_fields) { |
437 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
438 | return -EINVAL; |
439 | } | |
440 | ||
43b40992 | 441 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); |
358f0e63 TG |
442 | |
443 | *v |= softrst_mask; | |
63c85238 PW |
444 | |
445 | return 0; | |
446 | } | |
447 | ||
313a76ee RQ |
448 | /** |
449 | * _clear_softreset: clear OCP_SYSCONFIG.SOFTRESET bit in @v | |
450 | * @oh: struct omap_hwmod * | |
451 | * @v: pointer to register contents to modify | |
452 | * | |
453 | * Clear the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
454 | * error or 0 upon success. | |
455 | */ | |
456 | static int _clear_softreset(struct omap_hwmod *oh, u32 *v) | |
457 | { | |
458 | u32 softrst_mask; | |
459 | ||
460 | if (!oh->class->sysc || | |
461 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
462 | return -EINVAL; | |
463 | ||
464 | if (!oh->class->sysc->sysc_fields) { | |
465 | WARN(1, | |
466 | "omap_hwmod: %s: sysc_fields absent for sysconfig class\n", | |
467 | oh->name); | |
468 | return -EINVAL; | |
469 | } | |
470 | ||
471 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); | |
472 | ||
473 | *v &= ~softrst_mask; | |
474 | ||
475 | return 0; | |
476 | } | |
477 | ||
613ad0e9 TK |
478 | /** |
479 | * _wait_softreset_complete - wait for an OCP softreset to complete | |
480 | * @oh: struct omap_hwmod * to wait on | |
481 | * | |
482 | * Wait until the IP block represented by @oh reports that its OCP | |
483 | * softreset is complete. This can be triggered by software (see | |
484 | * _ocp_softreset()) or by hardware upon returning from off-mode (one | |
485 | * example is HSMMC). Waits for up to MAX_MODULE_SOFTRESET_WAIT | |
486 | * microseconds. Returns the number of microseconds waited. | |
487 | */ | |
488 | static int _wait_softreset_complete(struct omap_hwmod *oh) | |
489 | { | |
490 | struct omap_hwmod_class_sysconfig *sysc; | |
491 | u32 softrst_mask; | |
492 | int c = 0; | |
493 | ||
494 | sysc = oh->class->sysc; | |
495 | ||
496 | if (sysc->sysc_flags & SYSS_HAS_RESET_STATUS) | |
497 | omap_test_timeout((omap_hwmod_read(oh, sysc->syss_offs) | |
498 | & SYSS_RESETDONE_MASK), | |
499 | MAX_MODULE_SOFTRESET_WAIT, c); | |
500 | else if (sysc->sysc_flags & SYSC_HAS_RESET_STATUS) { | |
501 | softrst_mask = (0x1 << sysc->sysc_fields->srst_shift); | |
502 | omap_test_timeout(!(omap_hwmod_read(oh, sysc->sysc_offs) | |
503 | & softrst_mask), | |
504 | MAX_MODULE_SOFTRESET_WAIT, c); | |
505 | } | |
506 | ||
507 | return c; | |
508 | } | |
509 | ||
6668546f KVA |
510 | /** |
511 | * _set_dmadisable: set OCP_SYSCONFIG.DMADISABLE bit in @v | |
512 | * @oh: struct omap_hwmod * | |
513 | * | |
514 | * The DMADISABLE bit is a semi-automatic bit present in sysconfig register | |
515 | * of some modules. When the DMA must perform read/write accesses, the | |
516 | * DMADISABLE bit is cleared by the hardware. But when the DMA must stop | |
517 | * for power management, software must set the DMADISABLE bit back to 1. | |
518 | * | |
519 | * Set the DMADISABLE bit in @v for hwmod @oh. Returns -EINVAL upon | |
520 | * error or 0 upon success. | |
521 | */ | |
522 | static int _set_dmadisable(struct omap_hwmod *oh) | |
523 | { | |
524 | u32 v; | |
525 | u32 dmadisable_mask; | |
526 | ||
527 | if (!oh->class->sysc || | |
528 | !(oh->class->sysc->sysc_flags & SYSC_HAS_DMADISABLE)) | |
529 | return -EINVAL; | |
530 | ||
531 | if (!oh->class->sysc->sysc_fields) { | |
532 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
533 | return -EINVAL; | |
534 | } | |
535 | ||
536 | /* clocks must be on for this operation */ | |
537 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
538 | pr_warn("omap_hwmod: %s: dma can be disabled only from enabled state\n", oh->name); | |
539 | return -EINVAL; | |
540 | } | |
541 | ||
542 | pr_debug("omap_hwmod: %s: setting DMADISABLE\n", oh->name); | |
543 | ||
544 | v = oh->_sysc_cache; | |
545 | dmadisable_mask = | |
546 | (0x1 << oh->class->sysc->sysc_fields->dmadisable_shift); | |
547 | v |= dmadisable_mask; | |
548 | _write_sysconfig(v, oh); | |
549 | ||
550 | return 0; | |
551 | } | |
552 | ||
726072e5 PW |
553 | /** |
554 | * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v | |
555 | * @oh: struct omap_hwmod * | |
556 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
557 | * @v: pointer to register contents to modify | |
558 | * | |
559 | * Update the module autoidle bit in @v to be @autoidle for the @oh | |
560 | * hwmod. The autoidle bit controls whether the module can gate | |
561 | * internal clocks automatically when it isn't doing anything; the | |
562 | * exact function of this bit varies on a per-module basis. This | |
563 | * function does not write to the hardware. Returns -EINVAL upon | |
564 | * error or 0 upon success. | |
565 | */ | |
566 | static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | |
567 | u32 *v) | |
568 | { | |
358f0e63 TG |
569 | u32 autoidle_mask; |
570 | u8 autoidle_shift; | |
571 | ||
43b40992 PW |
572 | if (!oh->class->sysc || |
573 | !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE)) | |
726072e5 PW |
574 | return -EINVAL; |
575 | ||
43b40992 PW |
576 | if (!oh->class->sysc->sysc_fields) { |
577 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
578 | return -EINVAL; |
579 | } | |
580 | ||
43b40992 | 581 | autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift; |
8985b63d | 582 | autoidle_mask = (0x1 << autoidle_shift); |
358f0e63 TG |
583 | |
584 | *v &= ~autoidle_mask; | |
585 | *v |= autoidle << autoidle_shift; | |
726072e5 PW |
586 | |
587 | return 0; | |
588 | } | |
589 | ||
eceec009 G |
590 | /** |
591 | * _set_idle_ioring_wakeup - enable/disable IO pad wakeup on hwmod idle for mux | |
592 | * @oh: struct omap_hwmod * | |
593 | * @set_wake: bool value indicating to set (true) or clear (false) wakeup enable | |
594 | * | |
595 | * Set or clear the I/O pad wakeup flag in the mux entries for the | |
596 | * hwmod @oh. This function changes the @oh->mux->pads_dynamic array | |
597 | * in memory. If the hwmod is currently idled, and the new idle | |
598 | * values don't match the previous ones, this function will also | |
599 | * update the SCM PADCTRL registers. Otherwise, if the hwmod is not | |
600 | * currently idled, this function won't touch the hardware: the new | |
601 | * mux settings are written to the SCM PADCTRL registers when the | |
602 | * hwmod is idled. No return value. | |
603 | */ | |
604 | static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake) | |
605 | { | |
606 | struct omap_device_pad *pad; | |
607 | bool change = false; | |
608 | u16 prev_idle; | |
609 | int j; | |
610 | ||
611 | if (!oh->mux || !oh->mux->enabled) | |
612 | return; | |
613 | ||
614 | for (j = 0; j < oh->mux->nr_pads_dynamic; j++) { | |
615 | pad = oh->mux->pads_dynamic[j]; | |
616 | ||
617 | if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP)) | |
618 | continue; | |
619 | ||
620 | prev_idle = pad->idle; | |
621 | ||
622 | if (set_wake) | |
623 | pad->idle |= OMAP_WAKEUP_EN; | |
624 | else | |
625 | pad->idle &= ~OMAP_WAKEUP_EN; | |
626 | ||
627 | if (prev_idle != pad->idle) | |
628 | change = true; | |
629 | } | |
630 | ||
631 | if (change && oh->_state == _HWMOD_STATE_IDLE) | |
632 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); | |
633 | } | |
634 | ||
63c85238 PW |
635 | /** |
636 | * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
637 | * @oh: struct omap_hwmod * | |
638 | * | |
639 | * Allow the hardware module @oh to send wakeups. Returns -EINVAL | |
640 | * upon error or 0 upon success. | |
641 | */ | |
5a7ddcbd | 642 | static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 643 | { |
43b40992 | 644 | if (!oh->class->sysc || |
86009eb3 | 645 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
646 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
647 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
648 | return -EINVAL; |
649 | ||
43b40992 PW |
650 | if (!oh->class->sysc->sysc_fields) { |
651 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
652 | return -EINVAL; |
653 | } | |
654 | ||
1fe74113 BC |
655 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
656 | *v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift; | |
63c85238 | 657 | |
86009eb3 BC |
658 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
659 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
724019b0 BC |
660 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
661 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
86009eb3 | 662 | |
63c85238 PW |
663 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
664 | ||
63c85238 PW |
665 | return 0; |
666 | } | |
667 | ||
668 | /** | |
669 | * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
670 | * @oh: struct omap_hwmod * | |
671 | * | |
672 | * Prevent the hardware module @oh to send wakeups. Returns -EINVAL | |
673 | * upon error or 0 upon success. | |
674 | */ | |
5a7ddcbd | 675 | static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 676 | { |
43b40992 | 677 | if (!oh->class->sysc || |
86009eb3 | 678 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
679 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
680 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
681 | return -EINVAL; |
682 | ||
43b40992 PW |
683 | if (!oh->class->sysc->sysc_fields) { |
684 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
685 | return -EINVAL; |
686 | } | |
687 | ||
1fe74113 BC |
688 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
689 | *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift); | |
63c85238 | 690 | |
86009eb3 BC |
691 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
692 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v); | |
724019b0 | 693 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
561038f0 | 694 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART, v); |
86009eb3 | 695 | |
63c85238 PW |
696 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
697 | ||
63c85238 PW |
698 | return 0; |
699 | } | |
700 | ||
f5dd3bb5 RN |
701 | static struct clockdomain *_get_clkdm(struct omap_hwmod *oh) |
702 | { | |
c4a1ea2c RN |
703 | struct clk_hw_omap *clk; |
704 | ||
f5dd3bb5 RN |
705 | if (oh->clkdm) { |
706 | return oh->clkdm; | |
707 | } else if (oh->_clk) { | |
924f9498 TK |
708 | if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC) |
709 | return NULL; | |
f5dd3bb5 RN |
710 | clk = to_clk_hw_omap(__clk_get_hw(oh->_clk)); |
711 | return clk->clkdm; | |
f5dd3bb5 RN |
712 | } |
713 | return NULL; | |
714 | } | |
715 | ||
63c85238 PW |
716 | /** |
717 | * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active | |
718 | * @oh: struct omap_hwmod * | |
719 | * | |
720 | * Prevent the hardware module @oh from entering idle while the | |
721 | * hardare module initiator @init_oh is active. Useful when a module | |
722 | * will be accessed by a particular initiator (e.g., if a module will | |
723 | * be accessed by the IVA, there should be a sleepdep between the IVA | |
724 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
725 | * mode. If the clockdomain is marked as not needing autodeps, return |
726 | * 0 without doing anything. Otherwise, returns -EINVAL upon error or | |
727 | * passes along clkdm_add_sleepdep() value upon success. | |
63c85238 PW |
728 | */ |
729 | static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
730 | { | |
f5dd3bb5 RN |
731 | struct clockdomain *clkdm, *init_clkdm; |
732 | ||
733 | clkdm = _get_clkdm(oh); | |
734 | init_clkdm = _get_clkdm(init_oh); | |
735 | ||
736 | if (!clkdm || !init_clkdm) | |
63c85238 PW |
737 | return -EINVAL; |
738 | ||
f5dd3bb5 | 739 | if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS) |
570b54c7 PW |
740 | return 0; |
741 | ||
f5dd3bb5 | 742 | return clkdm_add_sleepdep(clkdm, init_clkdm); |
63c85238 PW |
743 | } |
744 | ||
745 | /** | |
746 | * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active | |
747 | * @oh: struct omap_hwmod * | |
748 | * | |
749 | * Allow the hardware module @oh to enter idle while the hardare | |
750 | * module initiator @init_oh is active. Useful when a module will not | |
751 | * be accessed by a particular initiator (e.g., if a module will not | |
752 | * be accessed by the IVA, there should be no sleepdep between the IVA | |
753 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
754 | * mode. If the clockdomain is marked as not needing autodeps, return |
755 | * 0 without doing anything. Returns -EINVAL upon error or passes | |
756 | * along clkdm_del_sleepdep() value upon success. | |
63c85238 PW |
757 | */ |
758 | static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
759 | { | |
f5dd3bb5 RN |
760 | struct clockdomain *clkdm, *init_clkdm; |
761 | ||
762 | clkdm = _get_clkdm(oh); | |
763 | init_clkdm = _get_clkdm(init_oh); | |
764 | ||
765 | if (!clkdm || !init_clkdm) | |
63c85238 PW |
766 | return -EINVAL; |
767 | ||
f5dd3bb5 | 768 | if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS) |
570b54c7 PW |
769 | return 0; |
770 | ||
f5dd3bb5 | 771 | return clkdm_del_sleepdep(clkdm, init_clkdm); |
63c85238 PW |
772 | } |
773 | ||
774 | /** | |
775 | * _init_main_clk - get a struct clk * for the the hwmod's main functional clk | |
776 | * @oh: struct omap_hwmod * | |
777 | * | |
778 | * Called from _init_clocks(). Populates the @oh _clk (main | |
779 | * functional clock pointer) if a main_clk is present. Returns 0 on | |
780 | * success or -EINVAL on error. | |
781 | */ | |
782 | static int _init_main_clk(struct omap_hwmod *oh) | |
783 | { | |
63c85238 PW |
784 | int ret = 0; |
785 | ||
50ebdac2 | 786 | if (!oh->main_clk) |
63c85238 PW |
787 | return 0; |
788 | ||
6ea74cb9 RN |
789 | oh->_clk = clk_get(NULL, oh->main_clk); |
790 | if (IS_ERR(oh->_clk)) { | |
3d0cb73e JP |
791 | pr_warn("omap_hwmod: %s: cannot clk_get main_clk %s\n", |
792 | oh->name, oh->main_clk); | |
63403384 | 793 | return -EINVAL; |
dc75925d | 794 | } |
4d7cb45e RN |
795 | /* |
796 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
797 | * to do something meaningful. Today its just a no-op. | |
798 | * If clk_prepare() is used at some point to do things like | |
799 | * voltage scaling etc, then this would have to be moved to | |
800 | * some point where subsystems like i2c and pmic become | |
801 | * available. | |
802 | */ | |
803 | clk_prepare(oh->_clk); | |
63c85238 | 804 | |
f5dd3bb5 | 805 | if (!_get_clkdm(oh)) |
3bb05dbf | 806 | pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n", |
5dcc3b97 | 807 | oh->name, oh->main_clk); |
81d7c6ff | 808 | |
63c85238 PW |
809 | return ret; |
810 | } | |
811 | ||
812 | /** | |
887adeac | 813 | * _init_interface_clks - get a struct clk * for the the hwmod's interface clks |
63c85238 PW |
814 | * @oh: struct omap_hwmod * |
815 | * | |
816 | * Called from _init_clocks(). Populates the @oh OCP slave interface | |
817 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
818 | */ | |
819 | static int _init_interface_clks(struct omap_hwmod *oh) | |
820 | { | |
5d95dde7 | 821 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 822 | struct list_head *p; |
63c85238 | 823 | struct clk *c; |
5d95dde7 | 824 | int i = 0; |
63c85238 PW |
825 | int ret = 0; |
826 | ||
11cd4b94 | 827 | p = oh->slave_ports.next; |
2221b5cd | 828 | |
5d95dde7 | 829 | while (i < oh->slaves_cnt) { |
11cd4b94 | 830 | os = _fetch_next_ocp_if(&p, &i); |
50ebdac2 | 831 | if (!os->clk) |
63c85238 PW |
832 | continue; |
833 | ||
6ea74cb9 RN |
834 | c = clk_get(NULL, os->clk); |
835 | if (IS_ERR(c)) { | |
3d0cb73e JP |
836 | pr_warn("omap_hwmod: %s: cannot clk_get interface_clk %s\n", |
837 | oh->name, os->clk); | |
63c85238 | 838 | ret = -EINVAL; |
0e7dc862 | 839 | continue; |
dc75925d | 840 | } |
63c85238 | 841 | os->_clk = c; |
4d7cb45e RN |
842 | /* |
843 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
844 | * to do something meaningful. Today its just a no-op. | |
845 | * If clk_prepare() is used at some point to do things like | |
846 | * voltage scaling etc, then this would have to be moved to | |
847 | * some point where subsystems like i2c and pmic become | |
848 | * available. | |
849 | */ | |
850 | clk_prepare(os->_clk); | |
63c85238 PW |
851 | } |
852 | ||
853 | return ret; | |
854 | } | |
855 | ||
856 | /** | |
857 | * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks | |
858 | * @oh: struct omap_hwmod * | |
859 | * | |
860 | * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk | |
861 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
862 | */ | |
863 | static int _init_opt_clks(struct omap_hwmod *oh) | |
864 | { | |
865 | struct omap_hwmod_opt_clk *oc; | |
866 | struct clk *c; | |
867 | int i; | |
868 | int ret = 0; | |
869 | ||
870 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { | |
6ea74cb9 RN |
871 | c = clk_get(NULL, oc->clk); |
872 | if (IS_ERR(c)) { | |
3d0cb73e JP |
873 | pr_warn("omap_hwmod: %s: cannot clk_get opt_clk %s\n", |
874 | oh->name, oc->clk); | |
63c85238 | 875 | ret = -EINVAL; |
0e7dc862 | 876 | continue; |
dc75925d | 877 | } |
63c85238 | 878 | oc->_clk = c; |
4d7cb45e RN |
879 | /* |
880 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
881 | * to do something meaningful. Today its just a no-op. | |
882 | * If clk_prepare() is used at some point to do things like | |
883 | * voltage scaling etc, then this would have to be moved to | |
884 | * some point where subsystems like i2c and pmic become | |
885 | * available. | |
886 | */ | |
887 | clk_prepare(oc->_clk); | |
63c85238 PW |
888 | } |
889 | ||
890 | return ret; | |
891 | } | |
892 | ||
c12ba8ce PU |
893 | static void _enable_optional_clocks(struct omap_hwmod *oh) |
894 | { | |
895 | struct omap_hwmod_opt_clk *oc; | |
896 | int i; | |
897 | ||
898 | pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name); | |
899 | ||
900 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
901 | if (oc->_clk) { | |
902 | pr_debug("omap_hwmod: enable %s:%s\n", oc->role, | |
903 | __clk_get_name(oc->_clk)); | |
904 | clk_enable(oc->_clk); | |
905 | } | |
906 | } | |
907 | ||
908 | static void _disable_optional_clocks(struct omap_hwmod *oh) | |
909 | { | |
910 | struct omap_hwmod_opt_clk *oc; | |
911 | int i; | |
912 | ||
913 | pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name); | |
914 | ||
915 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
916 | if (oc->_clk) { | |
917 | pr_debug("omap_hwmod: disable %s:%s\n", oc->role, | |
918 | __clk_get_name(oc->_clk)); | |
919 | clk_disable(oc->_clk); | |
920 | } | |
921 | } | |
922 | ||
63c85238 PW |
923 | /** |
924 | * _enable_clocks - enable hwmod main clock and interface clocks | |
925 | * @oh: struct omap_hwmod * | |
926 | * | |
927 | * Enables all clocks necessary for register reads and writes to succeed | |
928 | * on the hwmod @oh. Returns 0. | |
929 | */ | |
930 | static int _enable_clocks(struct omap_hwmod *oh) | |
931 | { | |
5d95dde7 | 932 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 933 | struct list_head *p; |
5d95dde7 | 934 | int i = 0; |
63c85238 PW |
935 | |
936 | pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); | |
937 | ||
4d3ae5a9 | 938 | if (oh->_clk) |
63c85238 PW |
939 | clk_enable(oh->_clk); |
940 | ||
11cd4b94 | 941 | p = oh->slave_ports.next; |
2221b5cd | 942 | |
5d95dde7 | 943 | while (i < oh->slaves_cnt) { |
11cd4b94 | 944 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 945 | |
5d95dde7 PW |
946 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) |
947 | clk_enable(os->_clk); | |
63c85238 PW |
948 | } |
949 | ||
c12ba8ce PU |
950 | if (oh->flags & HWMOD_OPT_CLKS_NEEDED) |
951 | _enable_optional_clocks(oh); | |
952 | ||
63c85238 PW |
953 | /* The opt clocks are controlled by the device driver. */ |
954 | ||
955 | return 0; | |
956 | } | |
957 | ||
958 | /** | |
959 | * _disable_clocks - disable hwmod main clock and interface clocks | |
960 | * @oh: struct omap_hwmod * | |
961 | * | |
962 | * Disables the hwmod @oh main functional and interface clocks. Returns 0. | |
963 | */ | |
964 | static int _disable_clocks(struct omap_hwmod *oh) | |
965 | { | |
5d95dde7 | 966 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 967 | struct list_head *p; |
5d95dde7 | 968 | int i = 0; |
63c85238 PW |
969 | |
970 | pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); | |
971 | ||
4d3ae5a9 | 972 | if (oh->_clk) |
63c85238 PW |
973 | clk_disable(oh->_clk); |
974 | ||
11cd4b94 | 975 | p = oh->slave_ports.next; |
2221b5cd | 976 | |
5d95dde7 | 977 | while (i < oh->slaves_cnt) { |
11cd4b94 | 978 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 979 | |
5d95dde7 PW |
980 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) |
981 | clk_disable(os->_clk); | |
63c85238 PW |
982 | } |
983 | ||
c12ba8ce PU |
984 | if (oh->flags & HWMOD_OPT_CLKS_NEEDED) |
985 | _disable_optional_clocks(oh); | |
986 | ||
63c85238 PW |
987 | /* The opt clocks are controlled by the device driver. */ |
988 | ||
989 | return 0; | |
990 | } | |
991 | ||
45c38252 | 992 | /** |
3d9f0327 | 993 | * _omap4_enable_module - enable CLKCTRL modulemode on OMAP4 |
45c38252 BC |
994 | * @oh: struct omap_hwmod * |
995 | * | |
996 | * Enables the PRCM module mode related to the hwmod @oh. | |
997 | * No return value. | |
998 | */ | |
3d9f0327 | 999 | static void _omap4_enable_module(struct omap_hwmod *oh) |
45c38252 | 1000 | { |
45c38252 BC |
1001 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) |
1002 | return; | |
1003 | ||
3d9f0327 KH |
1004 | pr_debug("omap_hwmod: %s: %s: %d\n", |
1005 | oh->name, __func__, oh->prcm.omap4.modulemode); | |
45c38252 | 1006 | |
128603f0 TK |
1007 | omap_cm_module_enable(oh->prcm.omap4.modulemode, |
1008 | oh->clkdm->prcm_partition, | |
1009 | oh->clkdm->cm_inst, oh->prcm.omap4.clkctrl_offs); | |
1688bf19 VH |
1010 | } |
1011 | ||
45c38252 | 1012 | /** |
bfc141e3 BC |
1013 | * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4 |
1014 | * @oh: struct omap_hwmod * | |
1015 | * | |
1016 | * Wait for a module @oh to enter slave idle. Returns 0 if the module | |
1017 | * does not have an IDLEST bit or if the module successfully enters | |
1018 | * slave idle; otherwise, pass along the return value of the | |
1019 | * appropriate *_cm*_wait_module_idle() function. | |
1020 | */ | |
1021 | static int _omap4_wait_target_disable(struct omap_hwmod *oh) | |
1022 | { | |
2b026d13 | 1023 | if (!oh) |
bfc141e3 BC |
1024 | return -EINVAL; |
1025 | ||
2b026d13 | 1026 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT || !oh->clkdm) |
bfc141e3 BC |
1027 | return 0; |
1028 | ||
1029 | if (oh->flags & HWMOD_NO_IDLEST) | |
1030 | return 0; | |
1031 | ||
a8ae5afa TK |
1032 | return omap_cm_wait_module_idle(oh->clkdm->prcm_partition, |
1033 | oh->clkdm->cm_inst, | |
1034 | oh->prcm.omap4.clkctrl_offs, 0); | |
1688bf19 VH |
1035 | } |
1036 | ||
212738a4 PW |
1037 | /** |
1038 | * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh | |
1039 | * @oh: struct omap_hwmod *oh | |
1040 | * | |
1041 | * Count and return the number of MPU IRQs associated with the hwmod | |
1042 | * @oh. Used to allocate struct resource data. Returns 0 if @oh is | |
1043 | * NULL. | |
1044 | */ | |
1045 | static int _count_mpu_irqs(struct omap_hwmod *oh) | |
1046 | { | |
1047 | struct omap_hwmod_irq_info *ohii; | |
1048 | int i = 0; | |
1049 | ||
1050 | if (!oh || !oh->mpu_irqs) | |
1051 | return 0; | |
1052 | ||
1053 | do { | |
1054 | ohii = &oh->mpu_irqs[i++]; | |
1055 | } while (ohii->irq != -1); | |
1056 | ||
cc1b0765 | 1057 | return i-1; |
212738a4 PW |
1058 | } |
1059 | ||
bc614958 PW |
1060 | /** |
1061 | * _count_sdma_reqs - count the number of SDMA request lines associated with @oh | |
1062 | * @oh: struct omap_hwmod *oh | |
1063 | * | |
1064 | * Count and return the number of SDMA request lines associated with | |
1065 | * the hwmod @oh. Used to allocate struct resource data. Returns 0 | |
1066 | * if @oh is NULL. | |
1067 | */ | |
1068 | static int _count_sdma_reqs(struct omap_hwmod *oh) | |
1069 | { | |
1070 | struct omap_hwmod_dma_info *ohdi; | |
1071 | int i = 0; | |
1072 | ||
1073 | if (!oh || !oh->sdma_reqs) | |
1074 | return 0; | |
1075 | ||
1076 | do { | |
1077 | ohdi = &oh->sdma_reqs[i++]; | |
1078 | } while (ohdi->dma_req != -1); | |
1079 | ||
cc1b0765 | 1080 | return i-1; |
bc614958 PW |
1081 | } |
1082 | ||
78183f3f PW |
1083 | /** |
1084 | * _count_ocp_if_addr_spaces - count the number of address space entries for @oh | |
1085 | * @oh: struct omap_hwmod *oh | |
1086 | * | |
1087 | * Count and return the number of address space ranges associated with | |
1088 | * the hwmod @oh. Used to allocate struct resource data. Returns 0 | |
1089 | * if @oh is NULL. | |
1090 | */ | |
1091 | static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os) | |
1092 | { | |
1093 | struct omap_hwmod_addr_space *mem; | |
1094 | int i = 0; | |
1095 | ||
1096 | if (!os || !os->addr) | |
1097 | return 0; | |
1098 | ||
1099 | do { | |
1100 | mem = &os->addr[i++]; | |
1101 | } while (mem->pa_start != mem->pa_end); | |
1102 | ||
cc1b0765 | 1103 | return i-1; |
78183f3f PW |
1104 | } |
1105 | ||
5e8370f1 PW |
1106 | /** |
1107 | * _get_mpu_irq_by_name - fetch MPU interrupt line number by name | |
1108 | * @oh: struct omap_hwmod * to operate on | |
1109 | * @name: pointer to the name of the MPU interrupt number to fetch (optional) | |
1110 | * @irq: pointer to an unsigned int to store the MPU IRQ number to | |
1111 | * | |
1112 | * Retrieve a MPU hardware IRQ line number named by @name associated | |
1113 | * with the IP block pointed to by @oh. The IRQ number will be filled | |
1114 | * into the address pointed to by @dma. When @name is non-null, the | |
1115 | * IRQ line number associated with the named entry will be returned. | |
1116 | * If @name is null, the first matching entry will be returned. Data | |
1117 | * order is not meaningful in hwmod data, so callers are strongly | |
1118 | * encouraged to use a non-null @name whenever possible to avoid | |
1119 | * unpredictable effects if hwmod data is later added that causes data | |
1120 | * ordering to change. Returns 0 upon success or a negative error | |
1121 | * code upon error. | |
1122 | */ | |
1123 | static int _get_mpu_irq_by_name(struct omap_hwmod *oh, const char *name, | |
1124 | unsigned int *irq) | |
1125 | { | |
1126 | int i; | |
1127 | bool found = false; | |
1128 | ||
1129 | if (!oh->mpu_irqs) | |
1130 | return -ENOENT; | |
1131 | ||
1132 | i = 0; | |
1133 | while (oh->mpu_irqs[i].irq != -1) { | |
1134 | if (name == oh->mpu_irqs[i].name || | |
1135 | !strcmp(name, oh->mpu_irqs[i].name)) { | |
1136 | found = true; | |
1137 | break; | |
1138 | } | |
1139 | i++; | |
1140 | } | |
1141 | ||
1142 | if (!found) | |
1143 | return -ENOENT; | |
1144 | ||
1145 | *irq = oh->mpu_irqs[i].irq; | |
1146 | ||
1147 | return 0; | |
1148 | } | |
1149 | ||
1150 | /** | |
1151 | * _get_sdma_req_by_name - fetch SDMA request line ID by name | |
1152 | * @oh: struct omap_hwmod * to operate on | |
1153 | * @name: pointer to the name of the SDMA request line to fetch (optional) | |
1154 | * @dma: pointer to an unsigned int to store the request line ID to | |
1155 | * | |
1156 | * Retrieve an SDMA request line ID named by @name on the IP block | |
1157 | * pointed to by @oh. The ID will be filled into the address pointed | |
1158 | * to by @dma. When @name is non-null, the request line ID associated | |
1159 | * with the named entry will be returned. If @name is null, the first | |
1160 | * matching entry will be returned. Data order is not meaningful in | |
1161 | * hwmod data, so callers are strongly encouraged to use a non-null | |
1162 | * @name whenever possible to avoid unpredictable effects if hwmod | |
1163 | * data is later added that causes data ordering to change. Returns 0 | |
1164 | * upon success or a negative error code upon error. | |
1165 | */ | |
1166 | static int _get_sdma_req_by_name(struct omap_hwmod *oh, const char *name, | |
1167 | unsigned int *dma) | |
1168 | { | |
1169 | int i; | |
1170 | bool found = false; | |
1171 | ||
1172 | if (!oh->sdma_reqs) | |
1173 | return -ENOENT; | |
1174 | ||
1175 | i = 0; | |
1176 | while (oh->sdma_reqs[i].dma_req != -1) { | |
1177 | if (name == oh->sdma_reqs[i].name || | |
1178 | !strcmp(name, oh->sdma_reqs[i].name)) { | |
1179 | found = true; | |
1180 | break; | |
1181 | } | |
1182 | i++; | |
1183 | } | |
1184 | ||
1185 | if (!found) | |
1186 | return -ENOENT; | |
1187 | ||
1188 | *dma = oh->sdma_reqs[i].dma_req; | |
1189 | ||
1190 | return 0; | |
1191 | } | |
1192 | ||
1193 | /** | |
1194 | * _get_addr_space_by_name - fetch address space start & end by name | |
1195 | * @oh: struct omap_hwmod * to operate on | |
1196 | * @name: pointer to the name of the address space to fetch (optional) | |
1197 | * @pa_start: pointer to a u32 to store the starting address to | |
1198 | * @pa_end: pointer to a u32 to store the ending address to | |
1199 | * | |
1200 | * Retrieve address space start and end addresses for the IP block | |
1201 | * pointed to by @oh. The data will be filled into the addresses | |
1202 | * pointed to by @pa_start and @pa_end. When @name is non-null, the | |
1203 | * address space data associated with the named entry will be | |
1204 | * returned. If @name is null, the first matching entry will be | |
1205 | * returned. Data order is not meaningful in hwmod data, so callers | |
1206 | * are strongly encouraged to use a non-null @name whenever possible | |
1207 | * to avoid unpredictable effects if hwmod data is later added that | |
1208 | * causes data ordering to change. Returns 0 upon success or a | |
1209 | * negative error code upon error. | |
1210 | */ | |
1211 | static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name, | |
1212 | u32 *pa_start, u32 *pa_end) | |
1213 | { | |
1214 | int i, j; | |
1215 | struct omap_hwmod_ocp_if *os; | |
2221b5cd | 1216 | struct list_head *p = NULL; |
5e8370f1 PW |
1217 | bool found = false; |
1218 | ||
11cd4b94 | 1219 | p = oh->slave_ports.next; |
2221b5cd | 1220 | |
5d95dde7 PW |
1221 | i = 0; |
1222 | while (i < oh->slaves_cnt) { | |
11cd4b94 | 1223 | os = _fetch_next_ocp_if(&p, &i); |
5e8370f1 PW |
1224 | |
1225 | if (!os->addr) | |
1226 | return -ENOENT; | |
1227 | ||
1228 | j = 0; | |
1229 | while (os->addr[j].pa_start != os->addr[j].pa_end) { | |
1230 | if (name == os->addr[j].name || | |
1231 | !strcmp(name, os->addr[j].name)) { | |
1232 | found = true; | |
1233 | break; | |
1234 | } | |
1235 | j++; | |
1236 | } | |
1237 | ||
1238 | if (found) | |
1239 | break; | |
1240 | } | |
1241 | ||
1242 | if (!found) | |
1243 | return -ENOENT; | |
1244 | ||
1245 | *pa_start = os->addr[j].pa_start; | |
1246 | *pa_end = os->addr[j].pa_end; | |
1247 | ||
1248 | return 0; | |
1249 | } | |
1250 | ||
63c85238 | 1251 | /** |
24dbc213 | 1252 | * _save_mpu_port_index - find and save the index to @oh's MPU port |
63c85238 PW |
1253 | * @oh: struct omap_hwmod * |
1254 | * | |
24dbc213 PW |
1255 | * Determines the array index of the OCP slave port that the MPU uses |
1256 | * to address the device, and saves it into the struct omap_hwmod. | |
1257 | * Intended to be called during hwmod registration only. No return | |
1258 | * value. | |
63c85238 | 1259 | */ |
24dbc213 | 1260 | static void __init _save_mpu_port_index(struct omap_hwmod *oh) |
63c85238 | 1261 | { |
24dbc213 | 1262 | struct omap_hwmod_ocp_if *os = NULL; |
11cd4b94 | 1263 | struct list_head *p; |
5d95dde7 | 1264 | int i = 0; |
63c85238 | 1265 | |
5d95dde7 | 1266 | if (!oh) |
24dbc213 PW |
1267 | return; |
1268 | ||
1269 | oh->_int_flags |= _HWMOD_NO_MPU_PORT; | |
63c85238 | 1270 | |
11cd4b94 | 1271 | p = oh->slave_ports.next; |
2221b5cd | 1272 | |
5d95dde7 | 1273 | while (i < oh->slaves_cnt) { |
11cd4b94 | 1274 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 1275 | if (os->user & OCP_USER_MPU) { |
2221b5cd | 1276 | oh->_mpu_port = os; |
24dbc213 | 1277 | oh->_int_flags &= ~_HWMOD_NO_MPU_PORT; |
63c85238 PW |
1278 | break; |
1279 | } | |
1280 | } | |
1281 | ||
24dbc213 | 1282 | return; |
63c85238 PW |
1283 | } |
1284 | ||
2d6141ba PW |
1285 | /** |
1286 | * _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU | |
1287 | * @oh: struct omap_hwmod * | |
1288 | * | |
1289 | * Given a pointer to a struct omap_hwmod record @oh, return a pointer | |
1290 | * to the struct omap_hwmod_ocp_if record that is used by the MPU to | |
1291 | * communicate with the IP block. This interface need not be directly | |
1292 | * connected to the MPU (and almost certainly is not), but is directly | |
1293 | * connected to the IP block represented by @oh. Returns a pointer | |
1294 | * to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon | |
1295 | * error or if there does not appear to be a path from the MPU to this | |
1296 | * IP block. | |
1297 | */ | |
1298 | static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh) | |
1299 | { | |
1300 | if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0) | |
1301 | return NULL; | |
1302 | ||
11cd4b94 | 1303 | return oh->_mpu_port; |
2d6141ba PW |
1304 | }; |
1305 | ||
63c85238 | 1306 | /** |
c9aafd23 | 1307 | * _find_mpu_rt_addr_space - return MPU register target address space for @oh |
63c85238 PW |
1308 | * @oh: struct omap_hwmod * |
1309 | * | |
c9aafd23 PW |
1310 | * Returns a pointer to the struct omap_hwmod_addr_space record representing |
1311 | * the register target MPU address space; or returns NULL upon error. | |
63c85238 | 1312 | */ |
c9aafd23 | 1313 | static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap_hwmod *oh) |
63c85238 PW |
1314 | { |
1315 | struct omap_hwmod_ocp_if *os; | |
1316 | struct omap_hwmod_addr_space *mem; | |
c9aafd23 | 1317 | int found = 0, i = 0; |
63c85238 | 1318 | |
2d6141ba | 1319 | os = _find_mpu_rt_port(oh); |
24dbc213 | 1320 | if (!os || !os->addr) |
78183f3f PW |
1321 | return NULL; |
1322 | ||
1323 | do { | |
1324 | mem = &os->addr[i++]; | |
1325 | if (mem->flags & ADDR_TYPE_RT) | |
63c85238 | 1326 | found = 1; |
78183f3f | 1327 | } while (!found && mem->pa_start != mem->pa_end); |
63c85238 | 1328 | |
c9aafd23 | 1329 | return (found) ? mem : NULL; |
63c85238 PW |
1330 | } |
1331 | ||
1332 | /** | |
74ff3a68 | 1333 | * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG |
63c85238 PW |
1334 | * @oh: struct omap_hwmod * |
1335 | * | |
006c7f18 PW |
1336 | * Ensure that the OCP_SYSCONFIG register for the IP block represented |
1337 | * by @oh is set to indicate to the PRCM that the IP block is active. | |
1338 | * Usually this means placing the module into smart-idle mode and | |
1339 | * smart-standby, but if there is a bug in the automatic idle handling | |
1340 | * for the IP block, it may need to be placed into the force-idle or | |
1341 | * no-idle variants of these modes. No return value. | |
63c85238 | 1342 | */ |
74ff3a68 | 1343 | static void _enable_sysc(struct omap_hwmod *oh) |
63c85238 | 1344 | { |
43b40992 | 1345 | u8 idlemode, sf; |
63c85238 | 1346 | u32 v; |
006c7f18 | 1347 | bool clkdm_act; |
f5dd3bb5 | 1348 | struct clockdomain *clkdm; |
63c85238 | 1349 | |
43b40992 | 1350 | if (!oh->class->sysc) |
63c85238 PW |
1351 | return; |
1352 | ||
613ad0e9 TK |
1353 | /* |
1354 | * Wait until reset has completed, this is needed as the IP | |
1355 | * block is reset automatically by hardware in some cases | |
1356 | * (off-mode for example), and the drivers require the | |
1357 | * IP to be ready when they access it | |
1358 | */ | |
1359 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1360 | _enable_optional_clocks(oh); | |
1361 | _wait_softreset_complete(oh); | |
1362 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1363 | _disable_optional_clocks(oh); | |
1364 | ||
63c85238 | 1365 | v = oh->_sysc_cache; |
43b40992 | 1366 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1367 | |
f5dd3bb5 | 1368 | clkdm = _get_clkdm(oh); |
43b40992 | 1369 | if (sf & SYSC_HAS_SIDLEMODE) { |
ca43ea34 RN |
1370 | if (oh->flags & HWMOD_SWSUP_SIDLE || |
1371 | oh->flags & HWMOD_SWSUP_SIDLE_ACT) { | |
35513171 RN |
1372 | idlemode = HWMOD_IDLEMODE_NO; |
1373 | } else { | |
1374 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1375 | _enable_wakeup(oh, &v); | |
1376 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) | |
1377 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1378 | else | |
1379 | idlemode = HWMOD_IDLEMODE_SMART; | |
1380 | } | |
1381 | ||
1382 | /* | |
1383 | * This is special handling for some IPs like | |
1384 | * 32k sync timer. Force them to idle! | |
1385 | */ | |
f5dd3bb5 | 1386 | clkdm_act = (clkdm && clkdm->flags & CLKDM_ACTIVE_WITH_MPU); |
006c7f18 PW |
1387 | if (clkdm_act && !(oh->class->sysc->idlemodes & |
1388 | (SIDLE_SMART | SIDLE_SMART_WKUP))) | |
1389 | idlemode = HWMOD_IDLEMODE_FORCE; | |
35513171 | 1390 | |
63c85238 PW |
1391 | _set_slave_idlemode(oh, idlemode, &v); |
1392 | } | |
1393 | ||
43b40992 | 1394 | if (sf & SYSC_HAS_MIDLEMODE) { |
092bc089 GI |
1395 | if (oh->flags & HWMOD_FORCE_MSTANDBY) { |
1396 | idlemode = HWMOD_IDLEMODE_FORCE; | |
1397 | } else if (oh->flags & HWMOD_SWSUP_MSTANDBY) { | |
724019b0 BC |
1398 | idlemode = HWMOD_IDLEMODE_NO; |
1399 | } else { | |
1400 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1401 | _enable_wakeup(oh, &v); | |
1402 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1403 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1404 | else | |
1405 | idlemode = HWMOD_IDLEMODE_SMART; | |
1406 | } | |
63c85238 PW |
1407 | _set_master_standbymode(oh, idlemode, &v); |
1408 | } | |
1409 | ||
a16b1f7f PW |
1410 | /* |
1411 | * XXX The clock framework should handle this, by | |
1412 | * calling into this code. But this must wait until the | |
1413 | * clock structures are tagged with omap_hwmod entries | |
1414 | */ | |
43b40992 PW |
1415 | if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) && |
1416 | (sf & SYSC_HAS_CLOCKACTIVITY)) | |
1417 | _set_clockactivity(oh, oh->class->sysc->clockact, &v); | |
63c85238 | 1418 | |
3ca4a238 | 1419 | _write_sysconfig(v, oh); |
78f26e87 HH |
1420 | |
1421 | /* | |
1422 | * Set the autoidle bit only after setting the smartidle bit | |
1423 | * Setting this will not have any impact on the other modules. | |
1424 | */ | |
1425 | if (sf & SYSC_HAS_AUTOIDLE) { | |
1426 | idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? | |
1427 | 0 : 1; | |
1428 | _set_module_autoidle(oh, idlemode, &v); | |
1429 | _write_sysconfig(v, oh); | |
1430 | } | |
63c85238 PW |
1431 | } |
1432 | ||
1433 | /** | |
74ff3a68 | 1434 | * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1435 | * @oh: struct omap_hwmod * |
1436 | * | |
1437 | * If module is marked as SWSUP_SIDLE, force the module into slave | |
1438 | * idle; otherwise, configure it for smart-idle. If module is marked | |
1439 | * as SWSUP_MSUSPEND, force the module into master standby; otherwise, | |
1440 | * configure it for smart-standby. No return value. | |
1441 | */ | |
74ff3a68 | 1442 | static void _idle_sysc(struct omap_hwmod *oh) |
63c85238 | 1443 | { |
43b40992 | 1444 | u8 idlemode, sf; |
63c85238 PW |
1445 | u32 v; |
1446 | ||
43b40992 | 1447 | if (!oh->class->sysc) |
63c85238 PW |
1448 | return; |
1449 | ||
1450 | v = oh->_sysc_cache; | |
43b40992 | 1451 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1452 | |
43b40992 | 1453 | if (sf & SYSC_HAS_SIDLEMODE) { |
35513171 | 1454 | if (oh->flags & HWMOD_SWSUP_SIDLE) { |
006c7f18 | 1455 | idlemode = HWMOD_IDLEMODE_FORCE; |
35513171 RN |
1456 | } else { |
1457 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1458 | _enable_wakeup(oh, &v); | |
1459 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) | |
1460 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1461 | else | |
1462 | idlemode = HWMOD_IDLEMODE_SMART; | |
1463 | } | |
63c85238 PW |
1464 | _set_slave_idlemode(oh, idlemode, &v); |
1465 | } | |
1466 | ||
43b40992 | 1467 | if (sf & SYSC_HAS_MIDLEMODE) { |
092bc089 GI |
1468 | if ((oh->flags & HWMOD_SWSUP_MSTANDBY) || |
1469 | (oh->flags & HWMOD_FORCE_MSTANDBY)) { | |
724019b0 BC |
1470 | idlemode = HWMOD_IDLEMODE_FORCE; |
1471 | } else { | |
1472 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1473 | _enable_wakeup(oh, &v); | |
1474 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1475 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1476 | else | |
1477 | idlemode = HWMOD_IDLEMODE_SMART; | |
1478 | } | |
63c85238 PW |
1479 | _set_master_standbymode(oh, idlemode, &v); |
1480 | } | |
1481 | ||
3ca4a238 LV |
1482 | /* If the cached value is the same as the new value, skip the write */ |
1483 | if (oh->_sysc_cache != v) | |
1484 | _write_sysconfig(v, oh); | |
63c85238 PW |
1485 | } |
1486 | ||
1487 | /** | |
74ff3a68 | 1488 | * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1489 | * @oh: struct omap_hwmod * |
1490 | * | |
1491 | * Force the module into slave idle and master suspend. No return | |
1492 | * value. | |
1493 | */ | |
74ff3a68 | 1494 | static void _shutdown_sysc(struct omap_hwmod *oh) |
63c85238 PW |
1495 | { |
1496 | u32 v; | |
43b40992 | 1497 | u8 sf; |
63c85238 | 1498 | |
43b40992 | 1499 | if (!oh->class->sysc) |
63c85238 PW |
1500 | return; |
1501 | ||
1502 | v = oh->_sysc_cache; | |
43b40992 | 1503 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1504 | |
43b40992 | 1505 | if (sf & SYSC_HAS_SIDLEMODE) |
63c85238 PW |
1506 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1507 | ||
43b40992 | 1508 | if (sf & SYSC_HAS_MIDLEMODE) |
63c85238 PW |
1509 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1510 | ||
43b40992 | 1511 | if (sf & SYSC_HAS_AUTOIDLE) |
726072e5 | 1512 | _set_module_autoidle(oh, 1, &v); |
63c85238 PW |
1513 | |
1514 | _write_sysconfig(v, oh); | |
1515 | } | |
1516 | ||
1517 | /** | |
1518 | * _lookup - find an omap_hwmod by name | |
1519 | * @name: find an omap_hwmod by name | |
1520 | * | |
1521 | * Return a pointer to an omap_hwmod by name, or NULL if not found. | |
63c85238 PW |
1522 | */ |
1523 | static struct omap_hwmod *_lookup(const char *name) | |
1524 | { | |
1525 | struct omap_hwmod *oh, *temp_oh; | |
1526 | ||
1527 | oh = NULL; | |
1528 | ||
1529 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
1530 | if (!strcmp(name, temp_oh->name)) { | |
1531 | oh = temp_oh; | |
1532 | break; | |
1533 | } | |
1534 | } | |
1535 | ||
1536 | return oh; | |
1537 | } | |
868c157d | 1538 | |
6ae76997 BC |
1539 | /** |
1540 | * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod | |
1541 | * @oh: struct omap_hwmod * | |
1542 | * | |
1543 | * Convert a clockdomain name stored in a struct omap_hwmod into a | |
1544 | * clockdomain pointer, and save it into the struct omap_hwmod. | |
868c157d | 1545 | * Return -EINVAL if the clkdm_name lookup failed. |
6ae76997 BC |
1546 | */ |
1547 | static int _init_clkdm(struct omap_hwmod *oh) | |
1548 | { | |
3bb05dbf PW |
1549 | if (!oh->clkdm_name) { |
1550 | pr_debug("omap_hwmod: %s: missing clockdomain\n", oh->name); | |
6ae76997 | 1551 | return 0; |
3bb05dbf | 1552 | } |
6ae76997 | 1553 | |
6ae76997 BC |
1554 | oh->clkdm = clkdm_lookup(oh->clkdm_name); |
1555 | if (!oh->clkdm) { | |
3d0cb73e | 1556 | pr_warn("omap_hwmod: %s: could not associate to clkdm %s\n", |
6ae76997 | 1557 | oh->name, oh->clkdm_name); |
0385c582 | 1558 | return 0; |
6ae76997 BC |
1559 | } |
1560 | ||
1561 | pr_debug("omap_hwmod: %s: associated to clkdm %s\n", | |
1562 | oh->name, oh->clkdm_name); | |
1563 | ||
1564 | return 0; | |
1565 | } | |
63c85238 PW |
1566 | |
1567 | /** | |
6ae76997 BC |
1568 | * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as |
1569 | * well the clockdomain. | |
63c85238 | 1570 | * @oh: struct omap_hwmod * |
97d60162 | 1571 | * @data: not used; pass NULL |
63c85238 | 1572 | * |
a2debdbd | 1573 | * Called by omap_hwmod_setup_*() (after omap2_clk_init()). |
48d54f3f PW |
1574 | * Resolves all clock names embedded in the hwmod. Returns 0 on |
1575 | * success, or a negative error code on failure. | |
63c85238 | 1576 | */ |
97d60162 | 1577 | static int _init_clocks(struct omap_hwmod *oh, void *data) |
63c85238 PW |
1578 | { |
1579 | int ret = 0; | |
1580 | ||
48d54f3f PW |
1581 | if (oh->_state != _HWMOD_STATE_REGISTERED) |
1582 | return 0; | |
63c85238 PW |
1583 | |
1584 | pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); | |
1585 | ||
b797be1d VH |
1586 | if (soc_ops.init_clkdm) |
1587 | ret |= soc_ops.init_clkdm(oh); | |
1588 | ||
63c85238 PW |
1589 | ret |= _init_main_clk(oh); |
1590 | ret |= _init_interface_clks(oh); | |
1591 | ret |= _init_opt_clks(oh); | |
1592 | ||
f5c1f84b BC |
1593 | if (!ret) |
1594 | oh->_state = _HWMOD_STATE_CLKS_INITED; | |
6652271a | 1595 | else |
3d0cb73e | 1596 | pr_warn("omap_hwmod: %s: cannot _init_clocks\n", oh->name); |
63c85238 | 1597 | |
09c35f2f | 1598 | return ret; |
63c85238 PW |
1599 | } |
1600 | ||
5365efbe | 1601 | /** |
cc1226e7 | 1602 | * _lookup_hardreset - fill register bit info for this hwmod/reset line |
5365efbe BC |
1603 | * @oh: struct omap_hwmod * |
1604 | * @name: name of the reset line in the context of this hwmod | |
cc1226e7 | 1605 | * @ohri: struct omap_hwmod_rst_info * that this function will fill in |
5365efbe BC |
1606 | * |
1607 | * Return the bit position of the reset line that match the | |
1608 | * input name. Return -ENOENT if not found. | |
1609 | */ | |
a032d33b PW |
1610 | static int _lookup_hardreset(struct omap_hwmod *oh, const char *name, |
1611 | struct omap_hwmod_rst_info *ohri) | |
5365efbe BC |
1612 | { |
1613 | int i; | |
1614 | ||
1615 | for (i = 0; i < oh->rst_lines_cnt; i++) { | |
1616 | const char *rst_line = oh->rst_lines[i].name; | |
1617 | if (!strcmp(rst_line, name)) { | |
cc1226e7 | 1618 | ohri->rst_shift = oh->rst_lines[i].rst_shift; |
1619 | ohri->st_shift = oh->rst_lines[i].st_shift; | |
1620 | pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n", | |
1621 | oh->name, __func__, rst_line, ohri->rst_shift, | |
1622 | ohri->st_shift); | |
5365efbe | 1623 | |
cc1226e7 | 1624 | return 0; |
5365efbe BC |
1625 | } |
1626 | } | |
1627 | ||
1628 | return -ENOENT; | |
1629 | } | |
1630 | ||
1631 | /** | |
1632 | * _assert_hardreset - assert the HW reset line of submodules | |
1633 | * contained in the hwmod module. | |
1634 | * @oh: struct omap_hwmod * | |
1635 | * @name: name of the reset line to lookup and assert | |
1636 | * | |
b8249cf2 KH |
1637 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1638 | * reset line to be assert / deassert in order to enable fully the IP. | |
1639 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of | |
1640 | * asserting the hardreset line on the currently-booted SoC, or passes | |
1641 | * along the return value from _lookup_hardreset() or the SoC's | |
1642 | * assert_hardreset code. | |
5365efbe BC |
1643 | */ |
1644 | static int _assert_hardreset(struct omap_hwmod *oh, const char *name) | |
1645 | { | |
cc1226e7 | 1646 | struct omap_hwmod_rst_info ohri; |
a032d33b | 1647 | int ret = -EINVAL; |
5365efbe BC |
1648 | |
1649 | if (!oh) | |
1650 | return -EINVAL; | |
1651 | ||
b8249cf2 KH |
1652 | if (!soc_ops.assert_hardreset) |
1653 | return -ENOSYS; | |
1654 | ||
cc1226e7 | 1655 | ret = _lookup_hardreset(oh, name, &ohri); |
a032d33b | 1656 | if (ret < 0) |
cc1226e7 | 1657 | return ret; |
5365efbe | 1658 | |
b8249cf2 KH |
1659 | ret = soc_ops.assert_hardreset(oh, &ohri); |
1660 | ||
1661 | return ret; | |
5365efbe BC |
1662 | } |
1663 | ||
1664 | /** | |
1665 | * _deassert_hardreset - deassert the HW reset line of submodules contained | |
1666 | * in the hwmod module. | |
1667 | * @oh: struct omap_hwmod * | |
1668 | * @name: name of the reset line to look up and deassert | |
1669 | * | |
b8249cf2 KH |
1670 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1671 | * reset line to be assert / deassert in order to enable fully the IP. | |
1672 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of | |
1673 | * deasserting the hardreset line on the currently-booted SoC, or passes | |
1674 | * along the return value from _lookup_hardreset() or the SoC's | |
1675 | * deassert_hardreset code. | |
5365efbe BC |
1676 | */ |
1677 | static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
1678 | { | |
cc1226e7 | 1679 | struct omap_hwmod_rst_info ohri; |
b8249cf2 | 1680 | int ret = -EINVAL; |
e8e96dff | 1681 | int hwsup = 0; |
5365efbe BC |
1682 | |
1683 | if (!oh) | |
1684 | return -EINVAL; | |
1685 | ||
b8249cf2 KH |
1686 | if (!soc_ops.deassert_hardreset) |
1687 | return -ENOSYS; | |
1688 | ||
cc1226e7 | 1689 | ret = _lookup_hardreset(oh, name, &ohri); |
c48cd659 | 1690 | if (ret < 0) |
cc1226e7 | 1691 | return ret; |
5365efbe | 1692 | |
e8e96dff ORL |
1693 | if (oh->clkdm) { |
1694 | /* | |
1695 | * A clockdomain must be in SW_SUP otherwise reset | |
1696 | * might not be completed. The clockdomain can be set | |
1697 | * in HW_AUTO only when the module become ready. | |
1698 | */ | |
1699 | hwsup = clkdm_in_hwsup(oh->clkdm); | |
1700 | ret = clkdm_hwmod_enable(oh->clkdm, oh); | |
1701 | if (ret) { | |
1702 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
1703 | oh->name, oh->clkdm->name, ret); | |
1704 | return ret; | |
1705 | } | |
1706 | } | |
1707 | ||
1708 | _enable_clocks(oh); | |
1709 | if (soc_ops.enable_module) | |
1710 | soc_ops.enable_module(oh); | |
1711 | ||
b8249cf2 | 1712 | ret = soc_ops.deassert_hardreset(oh, &ohri); |
e8e96dff ORL |
1713 | |
1714 | if (soc_ops.disable_module) | |
1715 | soc_ops.disable_module(oh); | |
1716 | _disable_clocks(oh); | |
1717 | ||
cc1226e7 | 1718 | if (ret == -EBUSY) |
3d0cb73e | 1719 | pr_warn("omap_hwmod: %s: failed to hardreset\n", oh->name); |
5365efbe | 1720 | |
80d2518d | 1721 | if (oh->clkdm) { |
e8e96dff ORL |
1722 | /* |
1723 | * Set the clockdomain to HW_AUTO, assuming that the | |
1724 | * previous state was HW_AUTO. | |
1725 | */ | |
80d2518d | 1726 | if (hwsup) |
e8e96dff | 1727 | clkdm_allow_idle(oh->clkdm); |
80d2518d TK |
1728 | |
1729 | clkdm_hwmod_disable(oh->clkdm, oh); | |
e8e96dff ORL |
1730 | } |
1731 | ||
cc1226e7 | 1732 | return ret; |
5365efbe BC |
1733 | } |
1734 | ||
1735 | /** | |
1736 | * _read_hardreset - read the HW reset line state of submodules | |
1737 | * contained in the hwmod module | |
1738 | * @oh: struct omap_hwmod * | |
1739 | * @name: name of the reset line to look up and read | |
1740 | * | |
b8249cf2 KH |
1741 | * Return the state of the reset line. Returns -EINVAL if @oh is |
1742 | * null, -ENOSYS if we have no way of reading the hardreset line | |
1743 | * status on the currently-booted SoC, or passes along the return | |
1744 | * value from _lookup_hardreset() or the SoC's is_hardreset_asserted | |
1745 | * code. | |
5365efbe BC |
1746 | */ |
1747 | static int _read_hardreset(struct omap_hwmod *oh, const char *name) | |
1748 | { | |
cc1226e7 | 1749 | struct omap_hwmod_rst_info ohri; |
a032d33b | 1750 | int ret = -EINVAL; |
5365efbe BC |
1751 | |
1752 | if (!oh) | |
1753 | return -EINVAL; | |
1754 | ||
b8249cf2 KH |
1755 | if (!soc_ops.is_hardreset_asserted) |
1756 | return -ENOSYS; | |
1757 | ||
cc1226e7 | 1758 | ret = _lookup_hardreset(oh, name, &ohri); |
a032d33b | 1759 | if (ret < 0) |
cc1226e7 | 1760 | return ret; |
5365efbe | 1761 | |
b8249cf2 | 1762 | return soc_ops.is_hardreset_asserted(oh, &ohri); |
5365efbe BC |
1763 | } |
1764 | ||
747834ab | 1765 | /** |
eb05f691 | 1766 | * _are_all_hardreset_lines_asserted - return true if the @oh is hard-reset |
747834ab PW |
1767 | * @oh: struct omap_hwmod * |
1768 | * | |
eb05f691 ORL |
1769 | * If all hardreset lines associated with @oh are asserted, then return true. |
1770 | * Otherwise, if part of @oh is out hardreset or if no hardreset lines | |
1771 | * associated with @oh are asserted, then return false. | |
747834ab | 1772 | * This function is used to avoid executing some parts of the IP block |
eb05f691 | 1773 | * enable/disable sequence if its hardreset line is set. |
747834ab | 1774 | */ |
eb05f691 | 1775 | static bool _are_all_hardreset_lines_asserted(struct omap_hwmod *oh) |
747834ab | 1776 | { |
eb05f691 | 1777 | int i, rst_cnt = 0; |
747834ab PW |
1778 | |
1779 | if (oh->rst_lines_cnt == 0) | |
1780 | return false; | |
1781 | ||
1782 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1783 | if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) | |
eb05f691 ORL |
1784 | rst_cnt++; |
1785 | ||
1786 | if (oh->rst_lines_cnt == rst_cnt) | |
1787 | return true; | |
747834ab PW |
1788 | |
1789 | return false; | |
1790 | } | |
1791 | ||
e9332b6e PW |
1792 | /** |
1793 | * _are_any_hardreset_lines_asserted - return true if any part of @oh is | |
1794 | * hard-reset | |
1795 | * @oh: struct omap_hwmod * | |
1796 | * | |
1797 | * If any hardreset lines associated with @oh are asserted, then | |
1798 | * return true. Otherwise, if no hardreset lines associated with @oh | |
1799 | * are asserted, or if @oh has no hardreset lines, then return false. | |
1800 | * This function is used to avoid executing some parts of the IP block | |
1801 | * enable/disable sequence if any hardreset line is set. | |
1802 | */ | |
1803 | static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh) | |
1804 | { | |
1805 | int rst_cnt = 0; | |
1806 | int i; | |
1807 | ||
1808 | for (i = 0; i < oh->rst_lines_cnt && rst_cnt == 0; i++) | |
1809 | if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) | |
1810 | rst_cnt++; | |
1811 | ||
1812 | return (rst_cnt) ? true : false; | |
1813 | } | |
1814 | ||
747834ab PW |
1815 | /** |
1816 | * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4 | |
1817 | * @oh: struct omap_hwmod * | |
1818 | * | |
1819 | * Disable the PRCM module mode related to the hwmod @oh. | |
1820 | * Return EINVAL if the modulemode is not supported and 0 in case of success. | |
1821 | */ | |
1822 | static int _omap4_disable_module(struct omap_hwmod *oh) | |
1823 | { | |
1824 | int v; | |
1825 | ||
747834ab PW |
1826 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) |
1827 | return -EINVAL; | |
1828 | ||
eb05f691 ORL |
1829 | /* |
1830 | * Since integration code might still be doing something, only | |
1831 | * disable if all lines are under hardreset. | |
1832 | */ | |
e9332b6e | 1833 | if (_are_any_hardreset_lines_asserted(oh)) |
eb05f691 ORL |
1834 | return 0; |
1835 | ||
747834ab PW |
1836 | pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); |
1837 | ||
128603f0 TK |
1838 | omap_cm_module_disable(oh->clkdm->prcm_partition, oh->clkdm->cm_inst, |
1839 | oh->prcm.omap4.clkctrl_offs); | |
747834ab | 1840 | |
747834ab PW |
1841 | v = _omap4_wait_target_disable(oh); |
1842 | if (v) | |
1843 | pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", | |
1844 | oh->name); | |
1845 | ||
1846 | return 0; | |
1847 | } | |
1848 | ||
63c85238 | 1849 | /** |
bd36179e | 1850 | * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit |
63c85238 PW |
1851 | * @oh: struct omap_hwmod * |
1852 | * | |
1853 | * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be | |
30e105c0 PW |
1854 | * enabled for this to work. Returns -ENOENT if the hwmod cannot be |
1855 | * reset this way, -EINVAL if the hwmod is in the wrong state, | |
1856 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
2cb06814 BC |
1857 | * |
1858 | * In OMAP3 a specific SYSSTATUS register is used to get the reset status. | |
bd36179e | 1859 | * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead |
2cb06814 BC |
1860 | * use the SYSCONFIG softreset bit to provide the status. |
1861 | * | |
bd36179e PW |
1862 | * Note that some IP like McBSP do have reset control but don't have |
1863 | * reset status. | |
63c85238 | 1864 | */ |
bd36179e | 1865 | static int _ocp_softreset(struct omap_hwmod *oh) |
63c85238 | 1866 | { |
613ad0e9 | 1867 | u32 v; |
6f8b7ff5 | 1868 | int c = 0; |
96835af9 | 1869 | int ret = 0; |
63c85238 | 1870 | |
43b40992 | 1871 | if (!oh->class->sysc || |
2cb06814 | 1872 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) |
30e105c0 | 1873 | return -ENOENT; |
63c85238 PW |
1874 | |
1875 | /* clocks must be on for this operation */ | |
1876 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
7852ec05 PW |
1877 | pr_warn("omap_hwmod: %s: reset can only be entered from enabled state\n", |
1878 | oh->name); | |
63c85238 PW |
1879 | return -EINVAL; |
1880 | } | |
1881 | ||
96835af9 BC |
1882 | /* For some modules, all optionnal clocks need to be enabled as well */ |
1883 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1884 | _enable_optional_clocks(oh); | |
1885 | ||
bd36179e | 1886 | pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name); |
63c85238 PW |
1887 | |
1888 | v = oh->_sysc_cache; | |
96835af9 BC |
1889 | ret = _set_softreset(oh, &v); |
1890 | if (ret) | |
1891 | goto dis_opt_clks; | |
313a76ee | 1892 | |
63c85238 PW |
1893 | _write_sysconfig(v, oh); |
1894 | ||
d99de7f5 FGL |
1895 | if (oh->class->sysc->srst_udelay) |
1896 | udelay(oh->class->sysc->srst_udelay); | |
1897 | ||
613ad0e9 | 1898 | c = _wait_softreset_complete(oh); |
01142519 | 1899 | if (c == MAX_MODULE_SOFTRESET_WAIT) { |
3d0cb73e JP |
1900 | pr_warn("omap_hwmod: %s: softreset failed (waited %d usec)\n", |
1901 | oh->name, MAX_MODULE_SOFTRESET_WAIT); | |
01142519 IS |
1902 | ret = -ETIMEDOUT; |
1903 | goto dis_opt_clks; | |
1904 | } else { | |
5365efbe | 1905 | pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); |
01142519 IS |
1906 | } |
1907 | ||
1908 | ret = _clear_softreset(oh, &v); | |
1909 | if (ret) | |
1910 | goto dis_opt_clks; | |
1911 | ||
1912 | _write_sysconfig(v, oh); | |
63c85238 PW |
1913 | |
1914 | /* | |
1915 | * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from | |
1916 | * _wait_target_ready() or _reset() | |
1917 | */ | |
1918 | ||
96835af9 BC |
1919 | dis_opt_clks: |
1920 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1921 | _disable_optional_clocks(oh); | |
1922 | ||
1923 | return ret; | |
63c85238 PW |
1924 | } |
1925 | ||
bd36179e PW |
1926 | /** |
1927 | * _reset - reset an omap_hwmod | |
1928 | * @oh: struct omap_hwmod * | |
1929 | * | |
30e105c0 PW |
1930 | * Resets an omap_hwmod @oh. If the module has a custom reset |
1931 | * function pointer defined, then call it to reset the IP block, and | |
1932 | * pass along its return value to the caller. Otherwise, if the IP | |
1933 | * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield | |
1934 | * associated with it, call a function to reset the IP block via that | |
1935 | * method, and pass along the return value to the caller. Finally, if | |
1936 | * the IP block has some hardreset lines associated with it, assert | |
1937 | * all of those, but do _not_ deassert them. (This is because driver | |
1938 | * authors have expressed an apparent requirement to control the | |
1939 | * deassertion of the hardreset lines themselves.) | |
1940 | * | |
1941 | * The default software reset mechanism for most OMAP IP blocks is | |
1942 | * triggered via the OCP_SYSCONFIG.SOFTRESET bit. However, some | |
1943 | * hwmods cannot be reset via this method. Some are not targets and | |
1944 | * therefore have no OCP header registers to access. Others (like the | |
1945 | * IVA) have idiosyncratic reset sequences. So for these relatively | |
1946 | * rare cases, custom reset code can be supplied in the struct | |
6668546f KVA |
1947 | * omap_hwmod_class .reset function pointer. |
1948 | * | |
1949 | * _set_dmadisable() is called to set the DMADISABLE bit so that it | |
1950 | * does not prevent idling of the system. This is necessary for cases | |
1951 | * where ROMCODE/BOOTLOADER uses dma and transfers control to the | |
1952 | * kernel without disabling dma. | |
1953 | * | |
1954 | * Passes along the return value from either _ocp_softreset() or the | |
1955 | * custom reset function - these must return -EINVAL if the hwmod | |
1956 | * cannot be reset this way or if the hwmod is in the wrong state, | |
1957 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
bd36179e PW |
1958 | */ |
1959 | static int _reset(struct omap_hwmod *oh) | |
1960 | { | |
30e105c0 | 1961 | int i, r; |
bd36179e PW |
1962 | |
1963 | pr_debug("omap_hwmod: %s: resetting\n", oh->name); | |
1964 | ||
30e105c0 PW |
1965 | if (oh->class->reset) { |
1966 | r = oh->class->reset(oh); | |
1967 | } else { | |
1968 | if (oh->rst_lines_cnt > 0) { | |
1969 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1970 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
1971 | return 0; | |
1972 | } else { | |
1973 | r = _ocp_softreset(oh); | |
1974 | if (r == -ENOENT) | |
1975 | r = 0; | |
1976 | } | |
1977 | } | |
1978 | ||
6668546f KVA |
1979 | _set_dmadisable(oh); |
1980 | ||
9c8b0ec7 | 1981 | /* |
30e105c0 PW |
1982 | * OCP_SYSCONFIG bits need to be reprogrammed after a |
1983 | * softreset. The _enable() function should be split to avoid | |
1984 | * the rewrite of the OCP_SYSCONFIG register. | |
9c8b0ec7 | 1985 | */ |
2800852a RN |
1986 | if (oh->class->sysc) { |
1987 | _update_sysc_cache(oh); | |
1988 | _enable_sysc(oh); | |
1989 | } | |
1990 | ||
30e105c0 | 1991 | return r; |
bd36179e PW |
1992 | } |
1993 | ||
5165882a VB |
1994 | /** |
1995 | * _reconfigure_io_chain - clear any I/O chain wakeups and reconfigure chain | |
1996 | * | |
1997 | * Call the appropriate PRM function to clear any logged I/O chain | |
1998 | * wakeups and to reconfigure the chain. This apparently needs to be | |
1999 | * done upon every mux change. Since hwmods can be concurrently | |
2000 | * enabled and idled, hold a spinlock around the I/O chain | |
2001 | * reconfiguration sequence. No return value. | |
2002 | * | |
2003 | * XXX When the PRM code is moved to drivers, this function can be removed, | |
2004 | * as the PRM infrastructure should abstract this. | |
2005 | */ | |
2006 | static void _reconfigure_io_chain(void) | |
2007 | { | |
2008 | unsigned long flags; | |
2009 | ||
2010 | spin_lock_irqsave(&io_chain_lock, flags); | |
2011 | ||
4984eeaf | 2012 | omap_prm_reconfigure_io_chain(); |
5165882a VB |
2013 | |
2014 | spin_unlock_irqrestore(&io_chain_lock, flags); | |
2015 | } | |
2016 | ||
e6d3a8b0 RN |
2017 | /** |
2018 | * _omap4_update_context_lost - increment hwmod context loss counter if | |
2019 | * hwmod context was lost, and clear hardware context loss reg | |
2020 | * @oh: hwmod to check for context loss | |
2021 | * | |
2022 | * If the PRCM indicates that the hwmod @oh lost context, increment | |
2023 | * our in-memory context loss counter, and clear the RM_*_CONTEXT | |
2024 | * bits. No return value. | |
2025 | */ | |
2026 | static void _omap4_update_context_lost(struct omap_hwmod *oh) | |
2027 | { | |
2028 | if (oh->prcm.omap4.flags & HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT) | |
2029 | return; | |
2030 | ||
2031 | if (!prm_was_any_context_lost_old(oh->clkdm->pwrdm.ptr->prcm_partition, | |
2032 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2033 | oh->prcm.omap4.context_offs)) | |
2034 | return; | |
2035 | ||
2036 | oh->prcm.omap4.context_lost_counter++; | |
2037 | prm_clear_context_loss_flags_old(oh->clkdm->pwrdm.ptr->prcm_partition, | |
2038 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2039 | oh->prcm.omap4.context_offs); | |
2040 | } | |
2041 | ||
2042 | /** | |
2043 | * _omap4_get_context_lost - get context loss counter for a hwmod | |
2044 | * @oh: hwmod to get context loss counter for | |
2045 | * | |
2046 | * Returns the in-memory context loss counter for a hwmod. | |
2047 | */ | |
2048 | static int _omap4_get_context_lost(struct omap_hwmod *oh) | |
2049 | { | |
2050 | return oh->prcm.omap4.context_lost_counter; | |
2051 | } | |
2052 | ||
6d266f63 PW |
2053 | /** |
2054 | * _enable_preprogram - Pre-program an IP block during the _enable() process | |
2055 | * @oh: struct omap_hwmod * | |
2056 | * | |
2057 | * Some IP blocks (such as AESS) require some additional programming | |
2058 | * after enable before they can enter idle. If a function pointer to | |
2059 | * do so is present in the hwmod data, then call it and pass along the | |
2060 | * return value; otherwise, return 0. | |
2061 | */ | |
0f497039 | 2062 | static int _enable_preprogram(struct omap_hwmod *oh) |
6d266f63 PW |
2063 | { |
2064 | if (!oh->class->enable_preprogram) | |
2065 | return 0; | |
2066 | ||
2067 | return oh->class->enable_preprogram(oh); | |
2068 | } | |
2069 | ||
63c85238 | 2070 | /** |
dc6d1cda | 2071 | * _enable - enable an omap_hwmod |
63c85238 PW |
2072 | * @oh: struct omap_hwmod * |
2073 | * | |
2074 | * Enables an omap_hwmod @oh such that the MPU can access the hwmod's | |
dc6d1cda PW |
2075 | * register target. Returns -EINVAL if the hwmod is in the wrong |
2076 | * state or passes along the return value of _wait_target_ready(). | |
63c85238 | 2077 | */ |
dc6d1cda | 2078 | static int _enable(struct omap_hwmod *oh) |
63c85238 | 2079 | { |
747834ab | 2080 | int r; |
665d0013 | 2081 | int hwsup = 0; |
63c85238 | 2082 | |
34617e2a BC |
2083 | pr_debug("omap_hwmod: %s: enabling\n", oh->name); |
2084 | ||
aacf0941 | 2085 | /* |
64813c3f PW |
2086 | * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled |
2087 | * state at init. Now that someone is really trying to enable | |
2088 | * them, just ensure that the hwmod mux is set. | |
aacf0941 RN |
2089 | */ |
2090 | if (oh->_int_flags & _HWMOD_SKIP_ENABLE) { | |
2091 | /* | |
2092 | * If the caller has mux data populated, do the mux'ing | |
2093 | * which wouldn't have been done as part of the _enable() | |
2094 | * done during setup. | |
2095 | */ | |
2096 | if (oh->mux) | |
2097 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); | |
2098 | ||
2099 | oh->_int_flags &= ~_HWMOD_SKIP_ENABLE; | |
2100 | return 0; | |
2101 | } | |
2102 | ||
63c85238 PW |
2103 | if (oh->_state != _HWMOD_STATE_INITIALIZED && |
2104 | oh->_state != _HWMOD_STATE_IDLE && | |
2105 | oh->_state != _HWMOD_STATE_DISABLED) { | |
4f8a428d RK |
2106 | WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n", |
2107 | oh->name); | |
63c85238 PW |
2108 | return -EINVAL; |
2109 | } | |
2110 | ||
31f62866 | 2111 | /* |
eb05f691 | 2112 | * If an IP block contains HW reset lines and all of them are |
747834ab PW |
2113 | * asserted, we let integration code associated with that |
2114 | * block handle the enable. We've received very little | |
2115 | * information on what those driver authors need, and until | |
2116 | * detailed information is provided and the driver code is | |
2117 | * posted to the public lists, this is probably the best we | |
2118 | * can do. | |
31f62866 | 2119 | */ |
eb05f691 | 2120 | if (_are_all_hardreset_lines_asserted(oh)) |
747834ab | 2121 | return 0; |
63c85238 | 2122 | |
665d0013 RN |
2123 | /* Mux pins for device runtime if populated */ |
2124 | if (oh->mux && (!oh->mux->enabled || | |
2125 | ((oh->_state == _HWMOD_STATE_IDLE) && | |
5165882a | 2126 | oh->mux->pads_dynamic))) { |
665d0013 | 2127 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); |
5165882a | 2128 | _reconfigure_io_chain(); |
6a08b11a | 2129 | } else if (oh->flags & HWMOD_RECONFIG_IO_CHAIN) { |
cc824534 | 2130 | _reconfigure_io_chain(); |
5165882a | 2131 | } |
665d0013 RN |
2132 | |
2133 | _add_initiator_dep(oh, mpu_oh); | |
34617e2a | 2134 | |
665d0013 RN |
2135 | if (oh->clkdm) { |
2136 | /* | |
2137 | * A clockdomain must be in SW_SUP before enabling | |
2138 | * completely the module. The clockdomain can be set | |
2139 | * in HW_AUTO only when the module become ready. | |
2140 | */ | |
b71c7217 PW |
2141 | hwsup = clkdm_in_hwsup(oh->clkdm) && |
2142 | !clkdm_missing_idle_reporting(oh->clkdm); | |
665d0013 RN |
2143 | r = clkdm_hwmod_enable(oh->clkdm, oh); |
2144 | if (r) { | |
2145 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
2146 | oh->name, oh->clkdm->name, r); | |
2147 | return r; | |
2148 | } | |
34617e2a | 2149 | } |
665d0013 RN |
2150 | |
2151 | _enable_clocks(oh); | |
9ebfd285 KH |
2152 | if (soc_ops.enable_module) |
2153 | soc_ops.enable_module(oh); | |
fa200222 | 2154 | if (oh->flags & HWMOD_BLOCK_WFI) |
f7b861b7 | 2155 | cpu_idle_poll_ctrl(true); |
34617e2a | 2156 | |
e6d3a8b0 RN |
2157 | if (soc_ops.update_context_lost) |
2158 | soc_ops.update_context_lost(oh); | |
2159 | ||
8f6aa8ee KH |
2160 | r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) : |
2161 | -EINVAL; | |
665d0013 RN |
2162 | if (!r) { |
2163 | /* | |
2164 | * Set the clockdomain to HW_AUTO only if the target is ready, | |
2165 | * assuming that the previous state was HW_AUTO | |
2166 | */ | |
2167 | if (oh->clkdm && hwsup) | |
2168 | clkdm_allow_idle(oh->clkdm); | |
2169 | ||
2170 | oh->_state = _HWMOD_STATE_ENABLED; | |
2171 | ||
2172 | /* Access the sysconfig only if the target is ready */ | |
2173 | if (oh->class->sysc) { | |
2174 | if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) | |
2175 | _update_sysc_cache(oh); | |
2176 | _enable_sysc(oh); | |
2177 | } | |
6d266f63 | 2178 | r = _enable_preprogram(oh); |
665d0013 | 2179 | } else { |
2577a4a6 PW |
2180 | if (soc_ops.disable_module) |
2181 | soc_ops.disable_module(oh); | |
665d0013 | 2182 | _disable_clocks(oh); |
812ce9d2 LV |
2183 | pr_err("omap_hwmod: %s: _wait_target_ready failed: %d\n", |
2184 | oh->name, r); | |
34617e2a | 2185 | |
665d0013 RN |
2186 | if (oh->clkdm) |
2187 | clkdm_hwmod_disable(oh->clkdm, oh); | |
9a23dfe1 BC |
2188 | } |
2189 | ||
63c85238 PW |
2190 | return r; |
2191 | } | |
2192 | ||
2193 | /** | |
dc6d1cda | 2194 | * _idle - idle an omap_hwmod |
63c85238 PW |
2195 | * @oh: struct omap_hwmod * |
2196 | * | |
2197 | * Idles an omap_hwmod @oh. This should be called once the hwmod has | |
dc6d1cda PW |
2198 | * no further work. Returns -EINVAL if the hwmod is in the wrong |
2199 | * state or returns 0. | |
63c85238 | 2200 | */ |
dc6d1cda | 2201 | static int _idle(struct omap_hwmod *oh) |
63c85238 | 2202 | { |
2e18f5a1 LV |
2203 | if (oh->flags & HWMOD_NO_IDLE) { |
2204 | oh->_int_flags |= _HWMOD_SKIP_ENABLE; | |
2205 | return 0; | |
2206 | } | |
2207 | ||
34617e2a BC |
2208 | pr_debug("omap_hwmod: %s: idling\n", oh->name); |
2209 | ||
c20c8f75 SA |
2210 | if (_are_all_hardreset_lines_asserted(oh)) |
2211 | return 0; | |
2212 | ||
63c85238 | 2213 | if (oh->_state != _HWMOD_STATE_ENABLED) { |
4f8a428d RK |
2214 | WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n", |
2215 | oh->name); | |
63c85238 PW |
2216 | return -EINVAL; |
2217 | } | |
2218 | ||
43b40992 | 2219 | if (oh->class->sysc) |
74ff3a68 | 2220 | _idle_sysc(oh); |
63c85238 | 2221 | _del_initiator_dep(oh, mpu_oh); |
bfc141e3 | 2222 | |
fa200222 | 2223 | if (oh->flags & HWMOD_BLOCK_WFI) |
f7b861b7 | 2224 | cpu_idle_poll_ctrl(false); |
9ebfd285 KH |
2225 | if (soc_ops.disable_module) |
2226 | soc_ops.disable_module(oh); | |
bfc141e3 | 2227 | |
45c38252 BC |
2228 | /* |
2229 | * The module must be in idle mode before disabling any parents | |
2230 | * clocks. Otherwise, the parent clock might be disabled before | |
2231 | * the module transition is done, and thus will prevent the | |
2232 | * transition to complete properly. | |
2233 | */ | |
2234 | _disable_clocks(oh); | |
665d0013 RN |
2235 | if (oh->clkdm) |
2236 | clkdm_hwmod_disable(oh->clkdm, oh); | |
63c85238 | 2237 | |
8d9af88f | 2238 | /* Mux pins for device idle if populated */ |
5165882a | 2239 | if (oh->mux && oh->mux->pads_dynamic) { |
8d9af88f | 2240 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); |
5165882a | 2241 | _reconfigure_io_chain(); |
6a08b11a | 2242 | } else if (oh->flags & HWMOD_RECONFIG_IO_CHAIN) { |
cc824534 | 2243 | _reconfigure_io_chain(); |
5165882a | 2244 | } |
8d9af88f | 2245 | |
63c85238 PW |
2246 | oh->_state = _HWMOD_STATE_IDLE; |
2247 | ||
2248 | return 0; | |
2249 | } | |
2250 | ||
2251 | /** | |
2252 | * _shutdown - shutdown an omap_hwmod | |
2253 | * @oh: struct omap_hwmod * | |
2254 | * | |
2255 | * Shut down an omap_hwmod @oh. This should be called when the driver | |
2256 | * used for the hwmod is removed or unloaded or if the driver is not | |
2257 | * used by the system. Returns -EINVAL if the hwmod is in the wrong | |
2258 | * state or returns 0. | |
2259 | */ | |
2260 | static int _shutdown(struct omap_hwmod *oh) | |
2261 | { | |
9c8b0ec7 | 2262 | int ret, i; |
e4dc8f50 PW |
2263 | u8 prev_state; |
2264 | ||
c20c8f75 SA |
2265 | if (_are_all_hardreset_lines_asserted(oh)) |
2266 | return 0; | |
2267 | ||
63c85238 PW |
2268 | if (oh->_state != _HWMOD_STATE_IDLE && |
2269 | oh->_state != _HWMOD_STATE_ENABLED) { | |
4f8a428d RK |
2270 | WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n", |
2271 | oh->name); | |
63c85238 PW |
2272 | return -EINVAL; |
2273 | } | |
2274 | ||
2275 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); | |
2276 | ||
e4dc8f50 PW |
2277 | if (oh->class->pre_shutdown) { |
2278 | prev_state = oh->_state; | |
2279 | if (oh->_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2280 | _enable(oh); |
e4dc8f50 PW |
2281 | ret = oh->class->pre_shutdown(oh); |
2282 | if (ret) { | |
2283 | if (prev_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2284 | _idle(oh); |
e4dc8f50 PW |
2285 | return ret; |
2286 | } | |
2287 | } | |
2288 | ||
6481c73c MV |
2289 | if (oh->class->sysc) { |
2290 | if (oh->_state == _HWMOD_STATE_IDLE) | |
2291 | _enable(oh); | |
74ff3a68 | 2292 | _shutdown_sysc(oh); |
6481c73c | 2293 | } |
5365efbe | 2294 | |
3827f949 BC |
2295 | /* clocks and deps are already disabled in idle */ |
2296 | if (oh->_state == _HWMOD_STATE_ENABLED) { | |
2297 | _del_initiator_dep(oh, mpu_oh); | |
2298 | /* XXX what about the other system initiators here? dma, dsp */ | |
fa200222 | 2299 | if (oh->flags & HWMOD_BLOCK_WFI) |
f7b861b7 | 2300 | cpu_idle_poll_ctrl(false); |
9ebfd285 KH |
2301 | if (soc_ops.disable_module) |
2302 | soc_ops.disable_module(oh); | |
45c38252 | 2303 | _disable_clocks(oh); |
665d0013 RN |
2304 | if (oh->clkdm) |
2305 | clkdm_hwmod_disable(oh->clkdm, oh); | |
3827f949 | 2306 | } |
63c85238 PW |
2307 | /* XXX Should this code also force-disable the optional clocks? */ |
2308 | ||
9c8b0ec7 PW |
2309 | for (i = 0; i < oh->rst_lines_cnt; i++) |
2310 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
31f62866 | 2311 | |
8d9af88f TL |
2312 | /* Mux pins to safe mode or use populated off mode values */ |
2313 | if (oh->mux) | |
2314 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED); | |
63c85238 PW |
2315 | |
2316 | oh->_state = _HWMOD_STATE_DISABLED; | |
2317 | ||
2318 | return 0; | |
2319 | } | |
2320 | ||
5e863c56 TL |
2321 | static int of_dev_find_hwmod(struct device_node *np, |
2322 | struct omap_hwmod *oh) | |
2323 | { | |
2324 | int count, i, res; | |
2325 | const char *p; | |
2326 | ||
2327 | count = of_property_count_strings(np, "ti,hwmods"); | |
2328 | if (count < 1) | |
2329 | return -ENODEV; | |
2330 | ||
2331 | for (i = 0; i < count; i++) { | |
2332 | res = of_property_read_string_index(np, "ti,hwmods", | |
2333 | i, &p); | |
2334 | if (res) | |
2335 | continue; | |
2336 | if (!strcmp(p, oh->name)) { | |
2337 | pr_debug("omap_hwmod: dt %s[%i] uses hwmod %s\n", | |
2338 | np->name, i, oh->name); | |
2339 | return i; | |
2340 | } | |
2341 | } | |
2342 | ||
2343 | return -ENODEV; | |
2344 | } | |
2345 | ||
079abade SS |
2346 | /** |
2347 | * of_dev_hwmod_lookup - look up needed hwmod from dt blob | |
2348 | * @np: struct device_node * | |
2349 | * @oh: struct omap_hwmod * | |
5e863c56 TL |
2350 | * @index: index of the entry found |
2351 | * @found: struct device_node * found or NULL | |
079abade SS |
2352 | * |
2353 | * Parse the dt blob and find out needed hwmod. Recursive function is | |
2354 | * implemented to take care hierarchical dt blob parsing. | |
5e863c56 | 2355 | * Return: Returns 0 on success, -ENODEV when not found. |
079abade | 2356 | */ |
5e863c56 TL |
2357 | static int of_dev_hwmod_lookup(struct device_node *np, |
2358 | struct omap_hwmod *oh, | |
2359 | int *index, | |
2360 | struct device_node **found) | |
079abade | 2361 | { |
5e863c56 TL |
2362 | struct device_node *np0 = NULL; |
2363 | int res; | |
2364 | ||
2365 | res = of_dev_find_hwmod(np, oh); | |
2366 | if (res >= 0) { | |
2367 | *found = np; | |
2368 | *index = res; | |
2369 | return 0; | |
2370 | } | |
079abade SS |
2371 | |
2372 | for_each_child_of_node(np, np0) { | |
5e863c56 TL |
2373 | struct device_node *fc; |
2374 | int i; | |
2375 | ||
2376 | res = of_dev_hwmod_lookup(np0, oh, &i, &fc); | |
2377 | if (res == 0) { | |
2378 | *found = fc; | |
2379 | *index = i; | |
2380 | return 0; | |
079abade SS |
2381 | } |
2382 | } | |
5e863c56 TL |
2383 | |
2384 | *found = NULL; | |
2385 | *index = 0; | |
2386 | ||
2387 | return -ENODEV; | |
079abade SS |
2388 | } |
2389 | ||
381d033a PW |
2390 | /** |
2391 | * _init_mpu_rt_base - populate the virtual address for a hwmod | |
2392 | * @oh: struct omap_hwmod * to locate the virtual address | |
f92d9597 | 2393 | * @data: (unused, caller should pass NULL) |
5e863c56 | 2394 | * @index: index of the reg entry iospace in device tree |
f92d9597 | 2395 | * @np: struct device_node * of the IP block's device node in the DT data |
381d033a PW |
2396 | * |
2397 | * Cache the virtual address used by the MPU to access this IP block's | |
2398 | * registers. This address is needed early so the OCP registers that | |
2399 | * are part of the device's address space can be ioremapped properly. | |
6423d6df | 2400 | * |
9a258afa RQ |
2401 | * If SYSC access is not needed, the registers will not be remapped |
2402 | * and non-availability of MPU access is not treated as an error. | |
2403 | * | |
6423d6df SA |
2404 | * Returns 0 on success, -EINVAL if an invalid hwmod is passed, and |
2405 | * -ENXIO on absent or invalid register target address space. | |
381d033a | 2406 | */ |
f92d9597 | 2407 | static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data, |
5e863c56 | 2408 | int index, struct device_node *np) |
381d033a | 2409 | { |
c9aafd23 | 2410 | struct omap_hwmod_addr_space *mem; |
079abade | 2411 | void __iomem *va_start = NULL; |
c9aafd23 PW |
2412 | |
2413 | if (!oh) | |
6423d6df | 2414 | return -EINVAL; |
c9aafd23 | 2415 | |
2221b5cd PW |
2416 | _save_mpu_port_index(oh); |
2417 | ||
9a258afa RQ |
2418 | /* if we don't need sysc access we don't need to ioremap */ |
2419 | if (!oh->class->sysc) | |
2420 | return 0; | |
2421 | ||
2422 | /* we can't continue without MPU PORT if we need sysc access */ | |
381d033a | 2423 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) |
6423d6df | 2424 | return -ENXIO; |
381d033a | 2425 | |
c9aafd23 PW |
2426 | mem = _find_mpu_rt_addr_space(oh); |
2427 | if (!mem) { | |
2428 | pr_debug("omap_hwmod: %s: no MPU register target found\n", | |
2429 | oh->name); | |
079abade SS |
2430 | |
2431 | /* Extract the IO space from device tree blob */ | |
9a258afa RQ |
2432 | if (!np) { |
2433 | pr_err("omap_hwmod: %s: no dt node\n", oh->name); | |
6423d6df | 2434 | return -ENXIO; |
9a258afa | 2435 | } |
079abade | 2436 | |
5e863c56 | 2437 | va_start = of_iomap(np, index + oh->mpu_rt_idx); |
079abade SS |
2438 | } else { |
2439 | va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); | |
c9aafd23 PW |
2440 | } |
2441 | ||
c9aafd23 | 2442 | if (!va_start) { |
5e863c56 TL |
2443 | if (mem) |
2444 | pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); | |
2445 | else | |
2446 | pr_err("omap_hwmod: %s: Missing dt reg%i for %s\n", | |
2447 | oh->name, index, np->full_name); | |
6423d6df | 2448 | return -ENXIO; |
c9aafd23 PW |
2449 | } |
2450 | ||
2451 | pr_debug("omap_hwmod: %s: MPU register target at va %p\n", | |
2452 | oh->name, va_start); | |
2453 | ||
2454 | oh->_mpu_rt_va = va_start; | |
6423d6df | 2455 | return 0; |
381d033a PW |
2456 | } |
2457 | ||
2458 | /** | |
2459 | * _init - initialize internal data for the hwmod @oh | |
2460 | * @oh: struct omap_hwmod * | |
2461 | * @n: (unused) | |
2462 | * | |
2463 | * Look up the clocks and the address space used by the MPU to access | |
2464 | * registers belonging to the hwmod @oh. @oh must already be | |
2465 | * registered at this point. This is the first of two phases for | |
2466 | * hwmod initialization. Code called here does not touch any hardware | |
2467 | * registers, it simply prepares internal data structures. Returns 0 | |
6423d6df SA |
2468 | * upon success or if the hwmod isn't registered or if the hwmod's |
2469 | * address space is not defined, or -EINVAL upon failure. | |
381d033a PW |
2470 | */ |
2471 | static int __init _init(struct omap_hwmod *oh, void *data) | |
2472 | { | |
5e863c56 | 2473 | int r, index; |
f92d9597 | 2474 | struct device_node *np = NULL; |
381d033a PW |
2475 | |
2476 | if (oh->_state != _HWMOD_STATE_REGISTERED) | |
2477 | return 0; | |
2478 | ||
5e863c56 TL |
2479 | if (of_have_populated_dt()) { |
2480 | struct device_node *bus; | |
2481 | ||
2482 | bus = of_find_node_by_name(NULL, "ocp"); | |
2483 | if (!bus) | |
2484 | return -ENODEV; | |
2485 | ||
2486 | r = of_dev_hwmod_lookup(bus, oh, &index, &np); | |
2487 | if (r) | |
2488 | pr_debug("omap_hwmod: %s missing dt data\n", oh->name); | |
2489 | else if (np && index) | |
2490 | pr_warn("omap_hwmod: %s using broken dt data from %s\n", | |
2491 | oh->name, np->name); | |
2492 | } | |
f92d9597 | 2493 | |
9a258afa RQ |
2494 | r = _init_mpu_rt_base(oh, NULL, index, np); |
2495 | if (r < 0) { | |
2496 | WARN(1, "omap_hwmod: %s: doesn't have mpu register target base\n", | |
2497 | oh->name); | |
2498 | return 0; | |
6423d6df | 2499 | } |
381d033a PW |
2500 | |
2501 | r = _init_clocks(oh, NULL); | |
c48cd659 | 2502 | if (r < 0) { |
381d033a PW |
2503 | WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name); |
2504 | return -EINVAL; | |
2505 | } | |
2506 | ||
3d36ad7e | 2507 | if (np) { |
f92d9597 RN |
2508 | if (of_find_property(np, "ti,no-reset-on-init", NULL)) |
2509 | oh->flags |= HWMOD_INIT_NO_RESET; | |
2510 | if (of_find_property(np, "ti,no-idle-on-init", NULL)) | |
2511 | oh->flags |= HWMOD_INIT_NO_IDLE; | |
2e18f5a1 LV |
2512 | if (of_find_property(np, "ti,no-idle", NULL)) |
2513 | oh->flags |= HWMOD_NO_IDLE; | |
3d36ad7e | 2514 | } |
f92d9597 | 2515 | |
381d033a PW |
2516 | oh->_state = _HWMOD_STATE_INITIALIZED; |
2517 | ||
2518 | return 0; | |
2519 | } | |
2520 | ||
63c85238 | 2521 | /** |
64813c3f | 2522 | * _setup_iclk_autoidle - configure an IP block's interface clocks |
63c85238 PW |
2523 | * @oh: struct omap_hwmod * |
2524 | * | |
64813c3f PW |
2525 | * Set up the module's interface clocks. XXX This function is still mostly |
2526 | * a stub; implementing this properly requires iclk autoidle usecounting in | |
2527 | * the clock code. No return value. | |
63c85238 | 2528 | */ |
64813c3f | 2529 | static void __init _setup_iclk_autoidle(struct omap_hwmod *oh) |
63c85238 | 2530 | { |
5d95dde7 | 2531 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 2532 | struct list_head *p; |
5d95dde7 | 2533 | int i = 0; |
381d033a | 2534 | if (oh->_state != _HWMOD_STATE_INITIALIZED) |
64813c3f | 2535 | return; |
48d54f3f | 2536 | |
11cd4b94 | 2537 | p = oh->slave_ports.next; |
63c85238 | 2538 | |
5d95dde7 | 2539 | while (i < oh->slaves_cnt) { |
11cd4b94 | 2540 | os = _fetch_next_ocp_if(&p, &i); |
5d95dde7 | 2541 | if (!os->_clk) |
64813c3f | 2542 | continue; |
63c85238 | 2543 | |
64813c3f PW |
2544 | if (os->flags & OCPIF_SWSUP_IDLE) { |
2545 | /* XXX omap_iclk_deny_idle(c); */ | |
2546 | } else { | |
2547 | /* XXX omap_iclk_allow_idle(c); */ | |
5d95dde7 | 2548 | clk_enable(os->_clk); |
63c85238 PW |
2549 | } |
2550 | } | |
2551 | ||
64813c3f PW |
2552 | return; |
2553 | } | |
2554 | ||
2555 | /** | |
2556 | * _setup_reset - reset an IP block during the setup process | |
2557 | * @oh: struct omap_hwmod * | |
2558 | * | |
2559 | * Reset the IP block corresponding to the hwmod @oh during the setup | |
2560 | * process. The IP block is first enabled so it can be successfully | |
2561 | * reset. Returns 0 upon success or a negative error code upon | |
2562 | * failure. | |
2563 | */ | |
2564 | static int __init _setup_reset(struct omap_hwmod *oh) | |
2565 | { | |
2566 | int r; | |
2567 | ||
2568 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2569 | return -EINVAL; | |
63c85238 | 2570 | |
5fb3d522 PW |
2571 | if (oh->flags & HWMOD_EXT_OPT_MAIN_CLK) |
2572 | return -EPERM; | |
2573 | ||
747834ab PW |
2574 | if (oh->rst_lines_cnt == 0) { |
2575 | r = _enable(oh); | |
2576 | if (r) { | |
3d0cb73e JP |
2577 | pr_warn("omap_hwmod: %s: cannot be enabled for reset (%d)\n", |
2578 | oh->name, oh->_state); | |
747834ab PW |
2579 | return -EINVAL; |
2580 | } | |
9a23dfe1 | 2581 | } |
63c85238 | 2582 | |
2800852a | 2583 | if (!(oh->flags & HWMOD_INIT_NO_RESET)) |
64813c3f PW |
2584 | r = _reset(oh); |
2585 | ||
2586 | return r; | |
2587 | } | |
2588 | ||
2589 | /** | |
2590 | * _setup_postsetup - transition to the appropriate state after _setup | |
2591 | * @oh: struct omap_hwmod * | |
2592 | * | |
2593 | * Place an IP block represented by @oh into a "post-setup" state -- | |
2594 | * either IDLE, ENABLED, or DISABLED. ("post-setup" simply means that | |
2595 | * this function is called at the end of _setup().) The postsetup | |
2596 | * state for an IP block can be changed by calling | |
2597 | * omap_hwmod_enter_postsetup_state() early in the boot process, | |
2598 | * before one of the omap_hwmod_setup*() functions are called for the | |
2599 | * IP block. | |
2600 | * | |
2601 | * The IP block stays in this state until a PM runtime-based driver is | |
2602 | * loaded for that IP block. A post-setup state of IDLE is | |
2603 | * appropriate for almost all IP blocks with runtime PM-enabled | |
2604 | * drivers, since those drivers are able to enable the IP block. A | |
2605 | * post-setup state of ENABLED is appropriate for kernels with PM | |
2606 | * runtime disabled. The DISABLED state is appropriate for unusual IP | |
2607 | * blocks such as the MPU WDTIMER on kernels without WDTIMER drivers | |
2608 | * included, since the WDTIMER starts running on reset and will reset | |
2609 | * the MPU if left active. | |
2610 | * | |
2611 | * This post-setup mechanism is deprecated. Once all of the OMAP | |
2612 | * drivers have been converted to use PM runtime, and all of the IP | |
2613 | * block data and interconnect data is available to the hwmod code, it | |
2614 | * should be possible to replace this mechanism with a "lazy reset" | |
2615 | * arrangement. In a "lazy reset" setup, each IP block is enabled | |
2616 | * when the driver first probes, then all remaining IP blocks without | |
2617 | * drivers are either shut down or enabled after the drivers have | |
2618 | * loaded. However, this cannot take place until the above | |
2619 | * preconditions have been met, since otherwise the late reset code | |
2620 | * has no way of knowing which IP blocks are in use by drivers, and | |
2621 | * which ones are unused. | |
2622 | * | |
2623 | * No return value. | |
2624 | */ | |
2625 | static void __init _setup_postsetup(struct omap_hwmod *oh) | |
2626 | { | |
2627 | u8 postsetup_state; | |
2628 | ||
2629 | if (oh->rst_lines_cnt > 0) | |
2630 | return; | |
76e5589e | 2631 | |
2092e5cc PW |
2632 | postsetup_state = oh->_postsetup_state; |
2633 | if (postsetup_state == _HWMOD_STATE_UNKNOWN) | |
2634 | postsetup_state = _HWMOD_STATE_ENABLED; | |
2635 | ||
2636 | /* | |
2637 | * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data - | |
2638 | * it should be set by the core code as a runtime flag during startup | |
2639 | */ | |
2e18f5a1 | 2640 | if ((oh->flags & (HWMOD_INIT_NO_IDLE | HWMOD_NO_IDLE)) && |
aacf0941 RN |
2641 | (postsetup_state == _HWMOD_STATE_IDLE)) { |
2642 | oh->_int_flags |= _HWMOD_SKIP_ENABLE; | |
2092e5cc | 2643 | postsetup_state = _HWMOD_STATE_ENABLED; |
aacf0941 | 2644 | } |
2092e5cc PW |
2645 | |
2646 | if (postsetup_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2647 | _idle(oh); |
2092e5cc PW |
2648 | else if (postsetup_state == _HWMOD_STATE_DISABLED) |
2649 | _shutdown(oh); | |
2650 | else if (postsetup_state != _HWMOD_STATE_ENABLED) | |
2651 | WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", | |
2652 | oh->name, postsetup_state); | |
63c85238 | 2653 | |
64813c3f PW |
2654 | return; |
2655 | } | |
2656 | ||
2657 | /** | |
2658 | * _setup - prepare IP block hardware for use | |
2659 | * @oh: struct omap_hwmod * | |
2660 | * @n: (unused, pass NULL) | |
2661 | * | |
2662 | * Configure the IP block represented by @oh. This may include | |
2663 | * enabling the IP block, resetting it, and placing it into a | |
2664 | * post-setup state, depending on the type of IP block and applicable | |
2665 | * flags. IP blocks are reset to prevent any previous configuration | |
2666 | * by the bootloader or previous operating system from interfering | |
2667 | * with power management or other parts of the system. The reset can | |
2668 | * be avoided; see omap_hwmod_no_setup_reset(). This is the second of | |
2669 | * two phases for hwmod initialization. Code called here generally | |
2670 | * affects the IP block hardware, or system integration hardware | |
2671 | * associated with the IP block. Returns 0. | |
2672 | */ | |
2673 | static int __init _setup(struct omap_hwmod *oh, void *data) | |
2674 | { | |
2675 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2676 | return 0; | |
2677 | ||
f22d2545 TV |
2678 | if (oh->parent_hwmod) { |
2679 | int r; | |
2680 | ||
2681 | r = _enable(oh->parent_hwmod); | |
2682 | WARN(r, "hwmod: %s: setup: failed to enable parent hwmod %s\n", | |
2683 | oh->name, oh->parent_hwmod->name); | |
2684 | } | |
2685 | ||
64813c3f PW |
2686 | _setup_iclk_autoidle(oh); |
2687 | ||
2688 | if (!_setup_reset(oh)) | |
2689 | _setup_postsetup(oh); | |
2690 | ||
f22d2545 TV |
2691 | if (oh->parent_hwmod) { |
2692 | u8 postsetup_state; | |
2693 | ||
2694 | postsetup_state = oh->parent_hwmod->_postsetup_state; | |
2695 | ||
2696 | if (postsetup_state == _HWMOD_STATE_IDLE) | |
2697 | _idle(oh->parent_hwmod); | |
2698 | else if (postsetup_state == _HWMOD_STATE_DISABLED) | |
2699 | _shutdown(oh->parent_hwmod); | |
2700 | else if (postsetup_state != _HWMOD_STATE_ENABLED) | |
2701 | WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", | |
2702 | oh->parent_hwmod->name, postsetup_state); | |
2703 | } | |
2704 | ||
63c85238 PW |
2705 | return 0; |
2706 | } | |
2707 | ||
63c85238 | 2708 | /** |
0102b627 | 2709 | * _register - register a struct omap_hwmod |
63c85238 PW |
2710 | * @oh: struct omap_hwmod * |
2711 | * | |
43b40992 PW |
2712 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod |
2713 | * already has been registered by the same name; -EINVAL if the | |
2714 | * omap_hwmod is in the wrong state, if @oh is NULL, if the | |
2715 | * omap_hwmod's class field is NULL; if the omap_hwmod is missing a | |
2716 | * name, or if the omap_hwmod's class is missing a name; or 0 upon | |
2717 | * success. | |
63c85238 PW |
2718 | * |
2719 | * XXX The data should be copied into bootmem, so the original data | |
2720 | * should be marked __initdata and freed after init. This would allow | |
2721 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note | |
2722 | * that the copy process would be relatively complex due to the large number | |
2723 | * of substructures. | |
2724 | */ | |
01592df9 | 2725 | static int __init _register(struct omap_hwmod *oh) |
63c85238 | 2726 | { |
43b40992 PW |
2727 | if (!oh || !oh->name || !oh->class || !oh->class->name || |
2728 | (oh->_state != _HWMOD_STATE_UNKNOWN)) | |
63c85238 PW |
2729 | return -EINVAL; |
2730 | ||
63c85238 PW |
2731 | pr_debug("omap_hwmod: %s: registering\n", oh->name); |
2732 | ||
ce35b244 BC |
2733 | if (_lookup(oh->name)) |
2734 | return -EEXIST; | |
63c85238 | 2735 | |
63c85238 PW |
2736 | list_add_tail(&oh->node, &omap_hwmod_list); |
2737 | ||
2221b5cd PW |
2738 | INIT_LIST_HEAD(&oh->master_ports); |
2739 | INIT_LIST_HEAD(&oh->slave_ports); | |
dc6d1cda | 2740 | spin_lock_init(&oh->_lock); |
69317952 | 2741 | lockdep_set_class(&oh->_lock, &oh->hwmod_key); |
2092e5cc | 2742 | |
63c85238 PW |
2743 | oh->_state = _HWMOD_STATE_REGISTERED; |
2744 | ||
569edd70 PW |
2745 | /* |
2746 | * XXX Rather than doing a strcmp(), this should test a flag | |
2747 | * set in the hwmod data, inserted by the autogenerator code. | |
2748 | */ | |
2749 | if (!strcmp(oh->name, MPU_INITIATOR_NAME)) | |
2750 | mpu_oh = oh; | |
63c85238 | 2751 | |
569edd70 | 2752 | return 0; |
63c85238 PW |
2753 | } |
2754 | ||
2221b5cd PW |
2755 | /** |
2756 | * _alloc_links - return allocated memory for hwmod links | |
2757 | * @ml: pointer to a struct omap_hwmod_link * for the master link | |
2758 | * @sl: pointer to a struct omap_hwmod_link * for the slave link | |
2759 | * | |
2760 | * Return pointers to two struct omap_hwmod_link records, via the | |
2761 | * addresses pointed to by @ml and @sl. Will first attempt to return | |
2762 | * memory allocated as part of a large initial block, but if that has | |
2763 | * been exhausted, will allocate memory itself. Since ideally this | |
2764 | * second allocation path will never occur, the number of these | |
2765 | * 'supplemental' allocations will be logged when debugging is | |
2766 | * enabled. Returns 0. | |
2767 | */ | |
2768 | static int __init _alloc_links(struct omap_hwmod_link **ml, | |
2769 | struct omap_hwmod_link **sl) | |
2770 | { | |
2771 | unsigned int sz; | |
2772 | ||
2773 | if ((free_ls + LINKS_PER_OCP_IF) <= max_ls) { | |
2774 | *ml = &linkspace[free_ls++]; | |
2775 | *sl = &linkspace[free_ls++]; | |
2776 | return 0; | |
2777 | } | |
2778 | ||
2779 | sz = sizeof(struct omap_hwmod_link) * LINKS_PER_OCP_IF; | |
2780 | ||
2781 | *sl = NULL; | |
b6cb5bab | 2782 | *ml = memblock_virt_alloc(sz, 0); |
2221b5cd PW |
2783 | |
2784 | *sl = (void *)(*ml) + sizeof(struct omap_hwmod_link); | |
2785 | ||
2786 | ls_supp++; | |
2787 | pr_debug("omap_hwmod: supplemental link allocations needed: %d\n", | |
2788 | ls_supp * LINKS_PER_OCP_IF); | |
2789 | ||
2790 | return 0; | |
2791 | }; | |
2792 | ||
2793 | /** | |
2794 | * _add_link - add an interconnect between two IP blocks | |
2795 | * @oi: pointer to a struct omap_hwmod_ocp_if record | |
2796 | * | |
2797 | * Add struct omap_hwmod_link records connecting the master IP block | |
2798 | * specified in @oi->master to @oi, and connecting the slave IP block | |
2799 | * specified in @oi->slave to @oi. This code is assumed to run before | |
2800 | * preemption or SMP has been enabled, thus avoiding the need for | |
2801 | * locking in this code. Changes to this assumption will require | |
2802 | * additional locking. Returns 0. | |
2803 | */ | |
2804 | static int __init _add_link(struct omap_hwmod_ocp_if *oi) | |
2805 | { | |
2806 | struct omap_hwmod_link *ml, *sl; | |
2807 | ||
2808 | pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name, | |
2809 | oi->slave->name); | |
2810 | ||
2811 | _alloc_links(&ml, &sl); | |
2812 | ||
2813 | ml->ocp_if = oi; | |
2221b5cd PW |
2814 | list_add(&ml->node, &oi->master->master_ports); |
2815 | oi->master->masters_cnt++; | |
2816 | ||
2817 | sl->ocp_if = oi; | |
2221b5cd PW |
2818 | list_add(&sl->node, &oi->slave->slave_ports); |
2819 | oi->slave->slaves_cnt++; | |
2820 | ||
2821 | return 0; | |
2822 | } | |
2823 | ||
2824 | /** | |
2825 | * _register_link - register a struct omap_hwmod_ocp_if | |
2826 | * @oi: struct omap_hwmod_ocp_if * | |
2827 | * | |
2828 | * Registers the omap_hwmod_ocp_if record @oi. Returns -EEXIST if it | |
2829 | * has already been registered; -EINVAL if @oi is NULL or if the | |
2830 | * record pointed to by @oi is missing required fields; or 0 upon | |
2831 | * success. | |
2832 | * | |
2833 | * XXX The data should be copied into bootmem, so the original data | |
2834 | * should be marked __initdata and freed after init. This would allow | |
2835 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. | |
2836 | */ | |
2837 | static int __init _register_link(struct omap_hwmod_ocp_if *oi) | |
2838 | { | |
2839 | if (!oi || !oi->master || !oi->slave || !oi->user) | |
2840 | return -EINVAL; | |
2841 | ||
2842 | if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED) | |
2843 | return -EEXIST; | |
2844 | ||
2845 | pr_debug("omap_hwmod: registering link from %s to %s\n", | |
2846 | oi->master->name, oi->slave->name); | |
2847 | ||
2848 | /* | |
2849 | * Register the connected hwmods, if they haven't been | |
2850 | * registered already | |
2851 | */ | |
2852 | if (oi->master->_state != _HWMOD_STATE_REGISTERED) | |
2853 | _register(oi->master); | |
2854 | ||
2855 | if (oi->slave->_state != _HWMOD_STATE_REGISTERED) | |
2856 | _register(oi->slave); | |
2857 | ||
2858 | _add_link(oi); | |
2859 | ||
2860 | oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED; | |
2861 | ||
2862 | return 0; | |
2863 | } | |
2864 | ||
2865 | /** | |
2866 | * _alloc_linkspace - allocate large block of hwmod links | |
2867 | * @ois: pointer to an array of struct omap_hwmod_ocp_if records to count | |
2868 | * | |
2869 | * Allocate a large block of struct omap_hwmod_link records. This | |
2870 | * improves boot time significantly by avoiding the need to allocate | |
2871 | * individual records one by one. If the number of records to | |
2872 | * allocate in the block hasn't been manually specified, this function | |
2873 | * will count the number of struct omap_hwmod_ocp_if records in @ois | |
2874 | * and use that to determine the allocation size. For SoC families | |
2875 | * that require multiple list registrations, such as OMAP3xxx, this | |
2876 | * estimation process isn't optimal, so manual estimation is advised | |
2877 | * in those cases. Returns -EEXIST if the allocation has already occurred | |
2878 | * or 0 upon success. | |
2879 | */ | |
2880 | static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois) | |
2881 | { | |
2882 | unsigned int i = 0; | |
2883 | unsigned int sz; | |
2884 | ||
2885 | if (linkspace) { | |
2886 | WARN(1, "linkspace already allocated\n"); | |
2887 | return -EEXIST; | |
2888 | } | |
2889 | ||
2890 | if (max_ls == 0) | |
2891 | while (ois[i++]) | |
2892 | max_ls += LINKS_PER_OCP_IF; | |
2893 | ||
2894 | sz = sizeof(struct omap_hwmod_link) * max_ls; | |
2895 | ||
2896 | pr_debug("omap_hwmod: %s: allocating %d byte linkspace (%d links)\n", | |
2897 | __func__, sz, max_ls); | |
2898 | ||
b6cb5bab | 2899 | linkspace = memblock_virt_alloc(sz, 0); |
2221b5cd PW |
2900 | |
2901 | return 0; | |
2902 | } | |
0102b627 | 2903 | |
8f6aa8ee KH |
2904 | /* Static functions intended only for use in soc_ops field function pointers */ |
2905 | ||
2906 | /** | |
9002e921 | 2907 | * _omap2xxx_3xxx_wait_target_ready - wait for a module to leave slave idle |
8f6aa8ee KH |
2908 | * @oh: struct omap_hwmod * |
2909 | * | |
2910 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2911 | * does not have an IDLEST bit or if the module successfully leaves | |
2912 | * slave idle; otherwise, pass along the return value of the | |
2913 | * appropriate *_cm*_wait_module_ready() function. | |
2914 | */ | |
9002e921 | 2915 | static int _omap2xxx_3xxx_wait_target_ready(struct omap_hwmod *oh) |
8f6aa8ee KH |
2916 | { |
2917 | if (!oh) | |
2918 | return -EINVAL; | |
2919 | ||
2920 | if (oh->flags & HWMOD_NO_IDLEST) | |
2921 | return 0; | |
2922 | ||
2923 | if (!_find_mpu_rt_port(oh)) | |
2924 | return 0; | |
2925 | ||
2926 | /* XXX check module SIDLEMODE, hardreset status, enabled clocks */ | |
2927 | ||
021b6ff0 TK |
2928 | return omap_cm_wait_module_ready(0, oh->prcm.omap2.module_offs, |
2929 | oh->prcm.omap2.idlest_reg_id, | |
2930 | oh->prcm.omap2.idlest_idle_bit); | |
8f6aa8ee KH |
2931 | } |
2932 | ||
2933 | /** | |
2934 | * _omap4_wait_target_ready - wait for a module to leave slave idle | |
2935 | * @oh: struct omap_hwmod * | |
2936 | * | |
2937 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2938 | * does not have an IDLEST bit or if the module successfully leaves | |
2939 | * slave idle; otherwise, pass along the return value of the | |
2940 | * appropriate *_cm*_wait_module_ready() function. | |
2941 | */ | |
2942 | static int _omap4_wait_target_ready(struct omap_hwmod *oh) | |
2943 | { | |
2b026d13 | 2944 | if (!oh) |
8f6aa8ee KH |
2945 | return -EINVAL; |
2946 | ||
2b026d13 | 2947 | if (oh->flags & HWMOD_NO_IDLEST || !oh->clkdm) |
8f6aa8ee KH |
2948 | return 0; |
2949 | ||
2950 | if (!_find_mpu_rt_port(oh)) | |
2951 | return 0; | |
2952 | ||
2953 | /* XXX check module SIDLEMODE, hardreset status */ | |
2954 | ||
021b6ff0 TK |
2955 | return omap_cm_wait_module_ready(oh->clkdm->prcm_partition, |
2956 | oh->clkdm->cm_inst, | |
2957 | oh->prcm.omap4.clkctrl_offs, 0); | |
1688bf19 VH |
2958 | } |
2959 | ||
b8249cf2 KH |
2960 | /** |
2961 | * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | |
2962 | * @oh: struct omap_hwmod * to assert hardreset | |
2963 | * @ohri: hardreset line data | |
2964 | * | |
2965 | * Call omap2_prm_assert_hardreset() with parameters extracted from | |
2966 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | |
2967 | * use as an soc_ops function pointer. Passes along the return value | |
2968 | * from omap2_prm_assert_hardreset(). XXX This function is scheduled | |
2969 | * for removal when the PRM code is moved into drivers/. | |
2970 | */ | |
2971 | static int _omap2_assert_hardreset(struct omap_hwmod *oh, | |
2972 | struct omap_hwmod_rst_info *ohri) | |
2973 | { | |
efd44dc3 TK |
2974 | return omap_prm_assert_hardreset(ohri->rst_shift, 0, |
2975 | oh->prcm.omap2.module_offs, 0); | |
b8249cf2 KH |
2976 | } |
2977 | ||
2978 | /** | |
2979 | * _omap2_deassert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | |
2980 | * @oh: struct omap_hwmod * to deassert hardreset | |
2981 | * @ohri: hardreset line data | |
2982 | * | |
2983 | * Call omap2_prm_deassert_hardreset() with parameters extracted from | |
2984 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | |
2985 | * use as an soc_ops function pointer. Passes along the return value | |
2986 | * from omap2_prm_deassert_hardreset(). XXX This function is | |
2987 | * scheduled for removal when the PRM code is moved into drivers/. | |
2988 | */ | |
2989 | static int _omap2_deassert_hardreset(struct omap_hwmod *oh, | |
2990 | struct omap_hwmod_rst_info *ohri) | |
2991 | { | |
37fb59d7 TK |
2992 | return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, 0, |
2993 | oh->prcm.omap2.module_offs, 0, 0); | |
b8249cf2 KH |
2994 | } |
2995 | ||
2996 | /** | |
2997 | * _omap2_is_hardreset_asserted - call OMAP2 PRM hardreset fn with hwmod args | |
2998 | * @oh: struct omap_hwmod * to test hardreset | |
2999 | * @ohri: hardreset line data | |
3000 | * | |
3001 | * Call omap2_prm_is_hardreset_asserted() with parameters extracted | |
3002 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
3003 | * intended for use as an soc_ops function pointer. Passes along the | |
3004 | * return value from omap2_prm_is_hardreset_asserted(). XXX This | |
3005 | * function is scheduled for removal when the PRM code is moved into | |
3006 | * drivers/. | |
3007 | */ | |
3008 | static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh, | |
3009 | struct omap_hwmod_rst_info *ohri) | |
3010 | { | |
1bc28b34 TK |
3011 | return omap_prm_is_hardreset_asserted(ohri->st_shift, 0, |
3012 | oh->prcm.omap2.module_offs, 0); | |
b8249cf2 KH |
3013 | } |
3014 | ||
3015 | /** | |
3016 | * _omap4_assert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | |
3017 | * @oh: struct omap_hwmod * to assert hardreset | |
3018 | * @ohri: hardreset line data | |
3019 | * | |
3020 | * Call omap4_prminst_assert_hardreset() with parameters extracted | |
3021 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
3022 | * intended for use as an soc_ops function pointer. Passes along the | |
3023 | * return value from omap4_prminst_assert_hardreset(). XXX This | |
3024 | * function is scheduled for removal when the PRM code is moved into | |
3025 | * drivers/. | |
3026 | */ | |
3027 | static int _omap4_assert_hardreset(struct omap_hwmod *oh, | |
3028 | struct omap_hwmod_rst_info *ohri) | |
b8249cf2 | 3029 | { |
07b3a139 PW |
3030 | if (!oh->clkdm) |
3031 | return -EINVAL; | |
3032 | ||
efd44dc3 TK |
3033 | return omap_prm_assert_hardreset(ohri->rst_shift, |
3034 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
3035 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
3036 | oh->prcm.omap4.rstctrl_offs); | |
b8249cf2 KH |
3037 | } |
3038 | ||
3039 | /** | |
3040 | * _omap4_deassert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | |
3041 | * @oh: struct omap_hwmod * to deassert hardreset | |
3042 | * @ohri: hardreset line data | |
3043 | * | |
3044 | * Call omap4_prminst_deassert_hardreset() with parameters extracted | |
3045 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
3046 | * intended for use as an soc_ops function pointer. Passes along the | |
3047 | * return value from omap4_prminst_deassert_hardreset(). XXX This | |
3048 | * function is scheduled for removal when the PRM code is moved into | |
3049 | * drivers/. | |
3050 | */ | |
3051 | static int _omap4_deassert_hardreset(struct omap_hwmod *oh, | |
3052 | struct omap_hwmod_rst_info *ohri) | |
3053 | { | |
07b3a139 PW |
3054 | if (!oh->clkdm) |
3055 | return -EINVAL; | |
3056 | ||
b8249cf2 KH |
3057 | if (ohri->st_shift) |
3058 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | |
3059 | oh->name, ohri->name); | |
4ebf5b28 | 3060 | return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->rst_shift, |
37fb59d7 TK |
3061 | oh->clkdm->pwrdm.ptr->prcm_partition, |
3062 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
4ebf5b28 TK |
3063 | oh->prcm.omap4.rstctrl_offs, |
3064 | oh->prcm.omap4.rstctrl_offs + | |
3065 | OMAP4_RST_CTRL_ST_OFFSET); | |
b8249cf2 KH |
3066 | } |
3067 | ||
3068 | /** | |
3069 | * _omap4_is_hardreset_asserted - call OMAP4 PRM hardreset fn with hwmod args | |
3070 | * @oh: struct omap_hwmod * to test hardreset | |
3071 | * @ohri: hardreset line data | |
3072 | * | |
3073 | * Call omap4_prminst_is_hardreset_asserted() with parameters | |
3074 | * extracted from the hwmod @oh and the hardreset line data @ohri. | |
3075 | * Only intended for use as an soc_ops function pointer. Passes along | |
3076 | * the return value from omap4_prminst_is_hardreset_asserted(). XXX | |
3077 | * This function is scheduled for removal when the PRM code is moved | |
3078 | * into drivers/. | |
3079 | */ | |
3080 | static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh, | |
3081 | struct omap_hwmod_rst_info *ohri) | |
3082 | { | |
07b3a139 PW |
3083 | if (!oh->clkdm) |
3084 | return -EINVAL; | |
3085 | ||
1bc28b34 TK |
3086 | return omap_prm_is_hardreset_asserted(ohri->rst_shift, |
3087 | oh->clkdm->pwrdm.ptr-> | |
3088 | prcm_partition, | |
3089 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
3090 | oh->prcm.omap4.rstctrl_offs); | |
b8249cf2 KH |
3091 | } |
3092 | ||
1688bf19 VH |
3093 | /** |
3094 | * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args | |
3095 | * @oh: struct omap_hwmod * to deassert hardreset | |
3096 | * @ohri: hardreset line data | |
3097 | * | |
3098 | * Call am33xx_prminst_deassert_hardreset() with parameters extracted | |
3099 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
3100 | * intended for use as an soc_ops function pointer. Passes along the | |
3101 | * return value from am33xx_prminst_deassert_hardreset(). XXX This | |
3102 | * function is scheduled for removal when the PRM code is moved into | |
3103 | * drivers/. | |
3104 | */ | |
3105 | static int _am33xx_deassert_hardreset(struct omap_hwmod *oh, | |
3106 | struct omap_hwmod_rst_info *ohri) | |
3107 | { | |
a5bf00cd TK |
3108 | return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, |
3109 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
37fb59d7 TK |
3110 | oh->clkdm->pwrdm.ptr->prcm_offs, |
3111 | oh->prcm.omap4.rstctrl_offs, | |
3112 | oh->prcm.omap4.rstst_offs); | |
1688bf19 VH |
3113 | } |
3114 | ||
0102b627 BC |
3115 | /* Public functions */ |
3116 | ||
3117 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) | |
3118 | { | |
3119 | if (oh->flags & HWMOD_16BIT_REG) | |
edfaf05c | 3120 | return readw_relaxed(oh->_mpu_rt_va + reg_offs); |
0102b627 | 3121 | else |
edfaf05c | 3122 | return readl_relaxed(oh->_mpu_rt_va + reg_offs); |
0102b627 BC |
3123 | } |
3124 | ||
3125 | void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) | |
3126 | { | |
3127 | if (oh->flags & HWMOD_16BIT_REG) | |
edfaf05c | 3128 | writew_relaxed(v, oh->_mpu_rt_va + reg_offs); |
0102b627 | 3129 | else |
edfaf05c | 3130 | writel_relaxed(v, oh->_mpu_rt_va + reg_offs); |
0102b627 BC |
3131 | } |
3132 | ||
6d3c55fd A |
3133 | /** |
3134 | * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit | |
3135 | * @oh: struct omap_hwmod * | |
3136 | * | |
3137 | * This is a public function exposed to drivers. Some drivers may need to do | |
3138 | * some settings before and after resetting the device. Those drivers after | |
3139 | * doing the necessary settings could use this function to start a reset by | |
3140 | * setting the SYSCONFIG.SOFTRESET bit. | |
3141 | */ | |
3142 | int omap_hwmod_softreset(struct omap_hwmod *oh) | |
3143 | { | |
3c55c1ba PW |
3144 | u32 v; |
3145 | int ret; | |
3146 | ||
3147 | if (!oh || !(oh->_sysc_cache)) | |
6d3c55fd A |
3148 | return -EINVAL; |
3149 | ||
3c55c1ba PW |
3150 | v = oh->_sysc_cache; |
3151 | ret = _set_softreset(oh, &v); | |
3152 | if (ret) | |
3153 | goto error; | |
3154 | _write_sysconfig(v, oh); | |
3155 | ||
313a76ee RQ |
3156 | ret = _clear_softreset(oh, &v); |
3157 | if (ret) | |
3158 | goto error; | |
3159 | _write_sysconfig(v, oh); | |
3160 | ||
3c55c1ba PW |
3161 | error: |
3162 | return ret; | |
6d3c55fd A |
3163 | } |
3164 | ||
63c85238 PW |
3165 | /** |
3166 | * omap_hwmod_lookup - look up a registered omap_hwmod by name | |
3167 | * @name: name of the omap_hwmod to look up | |
3168 | * | |
3169 | * Given a @name of an omap_hwmod, return a pointer to the registered | |
3170 | * struct omap_hwmod *, or NULL upon error. | |
3171 | */ | |
3172 | struct omap_hwmod *omap_hwmod_lookup(const char *name) | |
3173 | { | |
3174 | struct omap_hwmod *oh; | |
3175 | ||
3176 | if (!name) | |
3177 | return NULL; | |
3178 | ||
63c85238 | 3179 | oh = _lookup(name); |
63c85238 PW |
3180 | |
3181 | return oh; | |
3182 | } | |
3183 | ||
3184 | /** | |
3185 | * omap_hwmod_for_each - call function for each registered omap_hwmod | |
3186 | * @fn: pointer to a callback function | |
97d60162 | 3187 | * @data: void * data to pass to callback function |
63c85238 PW |
3188 | * |
3189 | * Call @fn for each registered omap_hwmod, passing @data to each | |
3190 | * function. @fn must return 0 for success or any other value for | |
3191 | * failure. If @fn returns non-zero, the iteration across omap_hwmods | |
3192 | * will stop and the non-zero return value will be passed to the | |
3193 | * caller of omap_hwmod_for_each(). @fn is called with | |
3194 | * omap_hwmod_for_each() held. | |
3195 | */ | |
97d60162 PW |
3196 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
3197 | void *data) | |
63c85238 PW |
3198 | { |
3199 | struct omap_hwmod *temp_oh; | |
30ebad9d | 3200 | int ret = 0; |
63c85238 PW |
3201 | |
3202 | if (!fn) | |
3203 | return -EINVAL; | |
3204 | ||
63c85238 | 3205 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
97d60162 | 3206 | ret = (*fn)(temp_oh, data); |
63c85238 PW |
3207 | if (ret) |
3208 | break; | |
3209 | } | |
63c85238 PW |
3210 | |
3211 | return ret; | |
3212 | } | |
3213 | ||
2221b5cd PW |
3214 | /** |
3215 | * omap_hwmod_register_links - register an array of hwmod links | |
3216 | * @ois: pointer to an array of omap_hwmod_ocp_if to register | |
3217 | * | |
3218 | * Intended to be called early in boot before the clock framework is | |
3219 | * initialized. If @ois is not null, will register all omap_hwmods | |
9ebfd285 KH |
3220 | * listed in @ois that are valid for this chip. Returns -EINVAL if |
3221 | * omap_hwmod_init() hasn't been called before calling this function, | |
3222 | * -ENOMEM if the link memory area can't be allocated, or 0 upon | |
3223 | * success. | |
2221b5cd PW |
3224 | */ |
3225 | int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois) | |
3226 | { | |
3227 | int r, i; | |
3228 | ||
9ebfd285 KH |
3229 | if (!inited) |
3230 | return -EINVAL; | |
3231 | ||
2221b5cd PW |
3232 | if (!ois) |
3233 | return 0; | |
3234 | ||
f7f7a29b RN |
3235 | if (ois[0] == NULL) /* Empty list */ |
3236 | return 0; | |
3237 | ||
2221b5cd PW |
3238 | if (!linkspace) { |
3239 | if (_alloc_linkspace(ois)) { | |
3240 | pr_err("omap_hwmod: could not allocate link space\n"); | |
3241 | return -ENOMEM; | |
3242 | } | |
3243 | } | |
3244 | ||
3245 | i = 0; | |
3246 | do { | |
3247 | r = _register_link(ois[i]); | |
3248 | WARN(r && r != -EEXIST, | |
3249 | "omap_hwmod: _register_link(%s -> %s) returned %d\n", | |
3250 | ois[i]->master->name, ois[i]->slave->name, r); | |
3251 | } while (ois[++i]); | |
3252 | ||
3253 | return 0; | |
3254 | } | |
3255 | ||
381d033a PW |
3256 | /** |
3257 | * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up | |
3258 | * @oh: pointer to the hwmod currently being set up (usually not the MPU) | |
3259 | * | |
3260 | * If the hwmod data corresponding to the MPU subsystem IP block | |
3261 | * hasn't been initialized and set up yet, do so now. This must be | |
3262 | * done first since sleep dependencies may be added from other hwmods | |
3263 | * to the MPU. Intended to be called only by omap_hwmod_setup*(). No | |
3264 | * return value. | |
63c85238 | 3265 | */ |
381d033a | 3266 | static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh) |
e7c7d760 | 3267 | { |
381d033a PW |
3268 | if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN) |
3269 | pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", | |
3270 | __func__, MPU_INITIATOR_NAME); | |
3271 | else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) | |
3272 | omap_hwmod_setup_one(MPU_INITIATOR_NAME); | |
e7c7d760 TL |
3273 | } |
3274 | ||
63c85238 | 3275 | /** |
a2debdbd PW |
3276 | * omap_hwmod_setup_one - set up a single hwmod |
3277 | * @oh_name: const char * name of the already-registered hwmod to set up | |
3278 | * | |
381d033a PW |
3279 | * Initialize and set up a single hwmod. Intended to be used for a |
3280 | * small number of early devices, such as the timer IP blocks used for | |
3281 | * the scheduler clock. Must be called after omap2_clk_init(). | |
3282 | * Resolves the struct clk names to struct clk pointers for each | |
3283 | * registered omap_hwmod. Also calls _setup() on each hwmod. Returns | |
3284 | * -EINVAL upon error or 0 upon success. | |
a2debdbd PW |
3285 | */ |
3286 | int __init omap_hwmod_setup_one(const char *oh_name) | |
63c85238 PW |
3287 | { |
3288 | struct omap_hwmod *oh; | |
63c85238 | 3289 | |
a2debdbd PW |
3290 | pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); |
3291 | ||
a2debdbd PW |
3292 | oh = _lookup(oh_name); |
3293 | if (!oh) { | |
3294 | WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); | |
3295 | return -EINVAL; | |
3296 | } | |
63c85238 | 3297 | |
381d033a | 3298 | _ensure_mpu_hwmod_is_setup(oh); |
63c85238 | 3299 | |
381d033a | 3300 | _init(oh, NULL); |
a2debdbd PW |
3301 | _setup(oh, NULL); |
3302 | ||
63c85238 PW |
3303 | return 0; |
3304 | } | |
3305 | ||
3306 | /** | |
381d033a | 3307 | * omap_hwmod_setup_all - set up all registered IP blocks |
63c85238 | 3308 | * |
381d033a PW |
3309 | * Initialize and set up all IP blocks registered with the hwmod code. |
3310 | * Must be called after omap2_clk_init(). Resolves the struct clk | |
3311 | * names to struct clk pointers for each registered omap_hwmod. Also | |
3312 | * calls _setup() on each hwmod. Returns 0 upon success. | |
63c85238 | 3313 | */ |
550c8092 | 3314 | static int __init omap_hwmod_setup_all(void) |
63c85238 | 3315 | { |
381d033a | 3316 | _ensure_mpu_hwmod_is_setup(NULL); |
63c85238 | 3317 | |
381d033a | 3318 | omap_hwmod_for_each(_init, NULL); |
2092e5cc | 3319 | omap_hwmod_for_each(_setup, NULL); |
63c85238 PW |
3320 | |
3321 | return 0; | |
3322 | } | |
8dd5ea72 | 3323 | omap_postcore_initcall(omap_hwmod_setup_all); |
63c85238 | 3324 | |
63c85238 PW |
3325 | /** |
3326 | * omap_hwmod_enable - enable an omap_hwmod | |
3327 | * @oh: struct omap_hwmod * | |
3328 | * | |
74ff3a68 | 3329 | * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable(). |
63c85238 PW |
3330 | * Returns -EINVAL on error or passes along the return value from _enable(). |
3331 | */ | |
3332 | int omap_hwmod_enable(struct omap_hwmod *oh) | |
3333 | { | |
3334 | int r; | |
dc6d1cda | 3335 | unsigned long flags; |
63c85238 PW |
3336 | |
3337 | if (!oh) | |
3338 | return -EINVAL; | |
3339 | ||
dc6d1cda PW |
3340 | spin_lock_irqsave(&oh->_lock, flags); |
3341 | r = _enable(oh); | |
3342 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
3343 | |
3344 | return r; | |
3345 | } | |
3346 | ||
3347 | /** | |
3348 | * omap_hwmod_idle - idle an omap_hwmod | |
3349 | * @oh: struct omap_hwmod * | |
3350 | * | |
74ff3a68 | 3351 | * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle(). |
63c85238 PW |
3352 | * Returns -EINVAL on error or passes along the return value from _idle(). |
3353 | */ | |
3354 | int omap_hwmod_idle(struct omap_hwmod *oh) | |
3355 | { | |
6da23358 | 3356 | int r; |
dc6d1cda PW |
3357 | unsigned long flags; |
3358 | ||
63c85238 PW |
3359 | if (!oh) |
3360 | return -EINVAL; | |
3361 | ||
dc6d1cda | 3362 | spin_lock_irqsave(&oh->_lock, flags); |
6da23358 | 3363 | r = _idle(oh); |
dc6d1cda | 3364 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 | 3365 | |
6da23358 | 3366 | return r; |
63c85238 PW |
3367 | } |
3368 | ||
3369 | /** | |
3370 | * omap_hwmod_shutdown - shutdown an omap_hwmod | |
3371 | * @oh: struct omap_hwmod * | |
3372 | * | |
74ff3a68 | 3373 | * Shutdown an omap_hwmod @oh. Intended to be called by |
63c85238 PW |
3374 | * omap_device_shutdown(). Returns -EINVAL on error or passes along |
3375 | * the return value from _shutdown(). | |
3376 | */ | |
3377 | int omap_hwmod_shutdown(struct omap_hwmod *oh) | |
3378 | { | |
6da23358 | 3379 | int r; |
dc6d1cda PW |
3380 | unsigned long flags; |
3381 | ||
63c85238 PW |
3382 | if (!oh) |
3383 | return -EINVAL; | |
3384 | ||
dc6d1cda | 3385 | spin_lock_irqsave(&oh->_lock, flags); |
6da23358 | 3386 | r = _shutdown(oh); |
dc6d1cda | 3387 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 | 3388 | |
6da23358 | 3389 | return r; |
63c85238 PW |
3390 | } |
3391 | ||
5e8370f1 PW |
3392 | /* |
3393 | * IP block data retrieval functions | |
3394 | */ | |
3395 | ||
63c85238 PW |
3396 | /** |
3397 | * omap_hwmod_count_resources - count number of struct resources needed by hwmod | |
3398 | * @oh: struct omap_hwmod * | |
dad4191d | 3399 | * @flags: Type of resources to include when counting (IRQ/DMA/MEM) |
63c85238 PW |
3400 | * |
3401 | * Count the number of struct resource array elements necessary to | |
3402 | * contain omap_hwmod @oh resources. Intended to be called by code | |
3403 | * that registers omap_devices. Intended to be used to determine the | |
3404 | * size of a dynamically-allocated struct resource array, before | |
3405 | * calling omap_hwmod_fill_resources(). Returns the number of struct | |
3406 | * resource array elements needed. | |
3407 | * | |
3408 | * XXX This code is not optimized. It could attempt to merge adjacent | |
3409 | * resource IDs. | |
3410 | * | |
3411 | */ | |
dad4191d | 3412 | int omap_hwmod_count_resources(struct omap_hwmod *oh, unsigned long flags) |
63c85238 | 3413 | { |
dad4191d | 3414 | int ret = 0; |
63c85238 | 3415 | |
dad4191d PU |
3416 | if (flags & IORESOURCE_IRQ) |
3417 | ret += _count_mpu_irqs(oh); | |
63c85238 | 3418 | |
dad4191d PU |
3419 | if (flags & IORESOURCE_DMA) |
3420 | ret += _count_sdma_reqs(oh); | |
2221b5cd | 3421 | |
dad4191d PU |
3422 | if (flags & IORESOURCE_MEM) { |
3423 | int i = 0; | |
3424 | struct omap_hwmod_ocp_if *os; | |
3425 | struct list_head *p = oh->slave_ports.next; | |
3426 | ||
3427 | while (i < oh->slaves_cnt) { | |
3428 | os = _fetch_next_ocp_if(&p, &i); | |
3429 | ret += _count_ocp_if_addr_spaces(os); | |
3430 | } | |
5d95dde7 | 3431 | } |
63c85238 PW |
3432 | |
3433 | return ret; | |
3434 | } | |
3435 | ||
3436 | /** | |
3437 | * omap_hwmod_fill_resources - fill struct resource array with hwmod data | |
3438 | * @oh: struct omap_hwmod * | |
3439 | * @res: pointer to the first element of an array of struct resource to fill | |
3440 | * | |
3441 | * Fill the struct resource array @res with resource data from the | |
3442 | * omap_hwmod @oh. Intended to be called by code that registers | |
3443 | * omap_devices. See also omap_hwmod_count_resources(). Returns the | |
3444 | * number of array elements filled. | |
3445 | */ | |
3446 | int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) | |
3447 | { | |
5d95dde7 | 3448 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 3449 | struct list_head *p; |
5d95dde7 | 3450 | int i, j, mpu_irqs_cnt, sdma_reqs_cnt, addr_cnt; |
63c85238 PW |
3451 | int r = 0; |
3452 | ||
3453 | /* For each IRQ, DMA, memory area, fill in array.*/ | |
3454 | ||
212738a4 PW |
3455 | mpu_irqs_cnt = _count_mpu_irqs(oh); |
3456 | for (i = 0; i < mpu_irqs_cnt; i++) { | |
0fb22a8f MZ |
3457 | unsigned int irq; |
3458 | ||
3459 | if (oh->xlate_irq) | |
3460 | irq = oh->xlate_irq((oh->mpu_irqs + i)->irq); | |
3461 | else | |
3462 | irq = (oh->mpu_irqs + i)->irq; | |
718bfd76 | 3463 | (res + r)->name = (oh->mpu_irqs + i)->name; |
0fb22a8f MZ |
3464 | (res + r)->start = irq; |
3465 | (res + r)->end = irq; | |
63c85238 PW |
3466 | (res + r)->flags = IORESOURCE_IRQ; |
3467 | r++; | |
3468 | } | |
3469 | ||
bc614958 PW |
3470 | sdma_reqs_cnt = _count_sdma_reqs(oh); |
3471 | for (i = 0; i < sdma_reqs_cnt; i++) { | |
9ee9fff9 BC |
3472 | (res + r)->name = (oh->sdma_reqs + i)->name; |
3473 | (res + r)->start = (oh->sdma_reqs + i)->dma_req; | |
3474 | (res + r)->end = (oh->sdma_reqs + i)->dma_req; | |
63c85238 PW |
3475 | (res + r)->flags = IORESOURCE_DMA; |
3476 | r++; | |
3477 | } | |
3478 | ||
11cd4b94 | 3479 | p = oh->slave_ports.next; |
2221b5cd | 3480 | |
5d95dde7 PW |
3481 | i = 0; |
3482 | while (i < oh->slaves_cnt) { | |
11cd4b94 | 3483 | os = _fetch_next_ocp_if(&p, &i); |
78183f3f | 3484 | addr_cnt = _count_ocp_if_addr_spaces(os); |
63c85238 | 3485 | |
78183f3f | 3486 | for (j = 0; j < addr_cnt; j++) { |
cd503802 | 3487 | (res + r)->name = (os->addr + j)->name; |
63c85238 PW |
3488 | (res + r)->start = (os->addr + j)->pa_start; |
3489 | (res + r)->end = (os->addr + j)->pa_end; | |
3490 | (res + r)->flags = IORESOURCE_MEM; | |
3491 | r++; | |
3492 | } | |
3493 | } | |
3494 | ||
3495 | return r; | |
3496 | } | |
3497 | ||
b82b04e8 VH |
3498 | /** |
3499 | * omap_hwmod_fill_dma_resources - fill struct resource array with dma data | |
3500 | * @oh: struct omap_hwmod * | |
3501 | * @res: pointer to the array of struct resource to fill | |
3502 | * | |
3503 | * Fill the struct resource array @res with dma resource data from the | |
3504 | * omap_hwmod @oh. Intended to be called by code that registers | |
3505 | * omap_devices. See also omap_hwmod_count_resources(). Returns the | |
3506 | * number of array elements filled. | |
3507 | */ | |
3508 | int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res) | |
3509 | { | |
3510 | int i, sdma_reqs_cnt; | |
3511 | int r = 0; | |
3512 | ||
3513 | sdma_reqs_cnt = _count_sdma_reqs(oh); | |
3514 | for (i = 0; i < sdma_reqs_cnt; i++) { | |
3515 | (res + r)->name = (oh->sdma_reqs + i)->name; | |
3516 | (res + r)->start = (oh->sdma_reqs + i)->dma_req; | |
3517 | (res + r)->end = (oh->sdma_reqs + i)->dma_req; | |
3518 | (res + r)->flags = IORESOURCE_DMA; | |
3519 | r++; | |
3520 | } | |
3521 | ||
3522 | return r; | |
3523 | } | |
3524 | ||
5e8370f1 PW |
3525 | /** |
3526 | * omap_hwmod_get_resource_byname - fetch IP block integration data by name | |
3527 | * @oh: struct omap_hwmod * to operate on | |
3528 | * @type: one of the IORESOURCE_* constants from include/linux/ioport.h | |
3529 | * @name: pointer to the name of the data to fetch (optional) | |
3530 | * @rsrc: pointer to a struct resource, allocated by the caller | |
3531 | * | |
3532 | * Retrieve MPU IRQ, SDMA request line, or address space start/end | |
3533 | * data for the IP block pointed to by @oh. The data will be filled | |
3534 | * into a struct resource record pointed to by @rsrc. The struct | |
3535 | * resource must be allocated by the caller. When @name is non-null, | |
3536 | * the data associated with the matching entry in the IRQ/SDMA/address | |
3537 | * space hwmod data arrays will be returned. If @name is null, the | |
3538 | * first array entry will be returned. Data order is not meaningful | |
3539 | * in hwmod data, so callers are strongly encouraged to use a non-null | |
3540 | * @name whenever possible to avoid unpredictable effects if hwmod | |
3541 | * data is later added that causes data ordering to change. This | |
3542 | * function is only intended for use by OMAP core code. Device | |
3543 | * drivers should not call this function - the appropriate bus-related | |
3544 | * data accessor functions should be used instead. Returns 0 upon | |
3545 | * success or a negative error code upon error. | |
3546 | */ | |
3547 | int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, | |
3548 | const char *name, struct resource *rsrc) | |
3549 | { | |
3550 | int r; | |
3551 | unsigned int irq, dma; | |
3552 | u32 pa_start, pa_end; | |
3553 | ||
3554 | if (!oh || !rsrc) | |
3555 | return -EINVAL; | |
3556 | ||
3557 | if (type == IORESOURCE_IRQ) { | |
3558 | r = _get_mpu_irq_by_name(oh, name, &irq); | |
3559 | if (r) | |
3560 | return r; | |
3561 | ||
3562 | rsrc->start = irq; | |
3563 | rsrc->end = irq; | |
3564 | } else if (type == IORESOURCE_DMA) { | |
3565 | r = _get_sdma_req_by_name(oh, name, &dma); | |
3566 | if (r) | |
3567 | return r; | |
3568 | ||
3569 | rsrc->start = dma; | |
3570 | rsrc->end = dma; | |
3571 | } else if (type == IORESOURCE_MEM) { | |
3572 | r = _get_addr_space_by_name(oh, name, &pa_start, &pa_end); | |
3573 | if (r) | |
3574 | return r; | |
3575 | ||
3576 | rsrc->start = pa_start; | |
3577 | rsrc->end = pa_end; | |
3578 | } else { | |
3579 | return -EINVAL; | |
3580 | } | |
3581 | ||
3582 | rsrc->flags = type; | |
3583 | rsrc->name = name; | |
3584 | ||
3585 | return 0; | |
3586 | } | |
3587 | ||
63c85238 PW |
3588 | /** |
3589 | * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain | |
3590 | * @oh: struct omap_hwmod * | |
3591 | * | |
3592 | * Return the powerdomain pointer associated with the OMAP module | |
3593 | * @oh's main clock. If @oh does not have a main clk, return the | |
3594 | * powerdomain associated with the interface clock associated with the | |
3595 | * module's MPU port. (XXX Perhaps this should use the SDMA port | |
3596 | * instead?) Returns NULL on error, or a struct powerdomain * on | |
3597 | * success. | |
3598 | */ | |
3599 | struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) | |
3600 | { | |
3601 | struct clk *c; | |
2d6141ba | 3602 | struct omap_hwmod_ocp_if *oi; |
f5dd3bb5 | 3603 | struct clockdomain *clkdm; |
f5dd3bb5 | 3604 | struct clk_hw_omap *clk; |
63c85238 PW |
3605 | |
3606 | if (!oh) | |
3607 | return NULL; | |
3608 | ||
f5dd3bb5 RN |
3609 | if (oh->clkdm) |
3610 | return oh->clkdm->pwrdm.ptr; | |
3611 | ||
63c85238 PW |
3612 | if (oh->_clk) { |
3613 | c = oh->_clk; | |
3614 | } else { | |
2d6141ba PW |
3615 | oi = _find_mpu_rt_port(oh); |
3616 | if (!oi) | |
63c85238 | 3617 | return NULL; |
2d6141ba | 3618 | c = oi->_clk; |
63c85238 PW |
3619 | } |
3620 | ||
f5dd3bb5 RN |
3621 | clk = to_clk_hw_omap(__clk_get_hw(c)); |
3622 | clkdm = clk->clkdm; | |
f5dd3bb5 | 3623 | if (!clkdm) |
d5647c18 TG |
3624 | return NULL; |
3625 | ||
f5dd3bb5 | 3626 | return clkdm->pwrdm.ptr; |
63c85238 PW |
3627 | } |
3628 | ||
db2a60bf PW |
3629 | /** |
3630 | * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU) | |
3631 | * @oh: struct omap_hwmod * | |
3632 | * | |
3633 | * Returns the virtual address corresponding to the beginning of the | |
3634 | * module's register target, in the address range that is intended to | |
3635 | * be used by the MPU. Returns the virtual address upon success or NULL | |
3636 | * upon error. | |
3637 | */ | |
3638 | void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh) | |
3639 | { | |
3640 | if (!oh) | |
3641 | return NULL; | |
3642 | ||
3643 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
3644 | return NULL; | |
3645 | ||
3646 | if (oh->_state == _HWMOD_STATE_UNKNOWN) | |
3647 | return NULL; | |
3648 | ||
3649 | return oh->_mpu_rt_va; | |
3650 | } | |
3651 | ||
63c85238 PW |
3652 | /* |
3653 | * XXX what about functions for drivers to save/restore ocp_sysconfig | |
3654 | * for context save/restore operations? | |
3655 | */ | |
3656 | ||
63c85238 PW |
3657 | /** |
3658 | * omap_hwmod_enable_wakeup - allow device to wake up the system | |
3659 | * @oh: struct omap_hwmod * | |
3660 | * | |
3661 | * Sets the module OCP socket ENAWAKEUP bit to allow the module to | |
2a1cc144 G |
3662 | * send wakeups to the PRCM, and enable I/O ring wakeup events for |
3663 | * this IP block if it has dynamic mux entries. Eventually this | |
3664 | * should set PRCM wakeup registers to cause the PRCM to receive | |
3665 | * wakeup events from the module. Does not set any wakeup routing | |
3666 | * registers beyond this point - if the module is to wake up any other | |
3667 | * module or subsystem, that must be set separately. Called by | |
3668 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
3669 | */ |
3670 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | |
3671 | { | |
dc6d1cda | 3672 | unsigned long flags; |
5a7ddcbd | 3673 | u32 v; |
dc6d1cda | 3674 | |
dc6d1cda | 3675 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
3676 | |
3677 | if (oh->class->sysc && | |
3678 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
3679 | v = oh->_sysc_cache; | |
3680 | _enable_wakeup(oh, &v); | |
3681 | _write_sysconfig(v, oh); | |
3682 | } | |
3683 | ||
eceec009 | 3684 | _set_idle_ioring_wakeup(oh, true); |
dc6d1cda | 3685 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3686 | |
3687 | return 0; | |
3688 | } | |
3689 | ||
3690 | /** | |
3691 | * omap_hwmod_disable_wakeup - prevent device from waking the system | |
3692 | * @oh: struct omap_hwmod * | |
3693 | * | |
3694 | * Clears the module OCP socket ENAWAKEUP bit to prevent the module | |
2a1cc144 G |
3695 | * from sending wakeups to the PRCM, and disable I/O ring wakeup |
3696 | * events for this IP block if it has dynamic mux entries. Eventually | |
3697 | * this should clear PRCM wakeup registers to cause the PRCM to ignore | |
3698 | * wakeup events from the module. Does not set any wakeup routing | |
3699 | * registers beyond this point - if the module is to wake up any other | |
3700 | * module or subsystem, that must be set separately. Called by | |
3701 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
3702 | */ |
3703 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | |
3704 | { | |
dc6d1cda | 3705 | unsigned long flags; |
5a7ddcbd | 3706 | u32 v; |
dc6d1cda | 3707 | |
dc6d1cda | 3708 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
3709 | |
3710 | if (oh->class->sysc && | |
3711 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
3712 | v = oh->_sysc_cache; | |
3713 | _disable_wakeup(oh, &v); | |
3714 | _write_sysconfig(v, oh); | |
3715 | } | |
3716 | ||
eceec009 | 3717 | _set_idle_ioring_wakeup(oh, false); |
dc6d1cda | 3718 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3719 | |
3720 | return 0; | |
3721 | } | |
43b40992 | 3722 | |
aee48e3c PW |
3723 | /** |
3724 | * omap_hwmod_assert_hardreset - assert the HW reset line of submodules | |
3725 | * contained in the hwmod module. | |
3726 | * @oh: struct omap_hwmod * | |
3727 | * @name: name of the reset line to lookup and assert | |
3728 | * | |
3729 | * Some IP like dsp, ipu or iva contain processor that require | |
3730 | * an HW reset line to be assert / deassert in order to enable fully | |
3731 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
3732 | * yet supported on this OMAP; otherwise, passes along the return value | |
3733 | * from _assert_hardreset(). | |
3734 | */ | |
3735 | int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) | |
3736 | { | |
3737 | int ret; | |
dc6d1cda | 3738 | unsigned long flags; |
aee48e3c PW |
3739 | |
3740 | if (!oh) | |
3741 | return -EINVAL; | |
3742 | ||
dc6d1cda | 3743 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3744 | ret = _assert_hardreset(oh, name); |
dc6d1cda | 3745 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3746 | |
3747 | return ret; | |
3748 | } | |
3749 | ||
3750 | /** | |
3751 | * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules | |
3752 | * contained in the hwmod module. | |
3753 | * @oh: struct omap_hwmod * | |
3754 | * @name: name of the reset line to look up and deassert | |
3755 | * | |
3756 | * Some IP like dsp, ipu or iva contain processor that require | |
3757 | * an HW reset line to be assert / deassert in order to enable fully | |
3758 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
3759 | * yet supported on this OMAP; otherwise, passes along the return value | |
3760 | * from _deassert_hardreset(). | |
3761 | */ | |
3762 | int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
3763 | { | |
3764 | int ret; | |
dc6d1cda | 3765 | unsigned long flags; |
aee48e3c PW |
3766 | |
3767 | if (!oh) | |
3768 | return -EINVAL; | |
3769 | ||
dc6d1cda | 3770 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3771 | ret = _deassert_hardreset(oh, name); |
dc6d1cda | 3772 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3773 | |
3774 | return ret; | |
3775 | } | |
3776 | ||
43b40992 PW |
3777 | /** |
3778 | * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname | |
3779 | * @classname: struct omap_hwmod_class name to search for | |
3780 | * @fn: callback function pointer to call for each hwmod in class @classname | |
3781 | * @user: arbitrary context data to pass to the callback function | |
3782 | * | |
ce35b244 BC |
3783 | * For each omap_hwmod of class @classname, call @fn. |
3784 | * If the callback function returns something other than | |
43b40992 PW |
3785 | * zero, the iterator is terminated, and the callback function's return |
3786 | * value is passed back to the caller. Returns 0 upon success, -EINVAL | |
3787 | * if @classname or @fn are NULL, or passes back the error code from @fn. | |
3788 | */ | |
3789 | int omap_hwmod_for_each_by_class(const char *classname, | |
3790 | int (*fn)(struct omap_hwmod *oh, | |
3791 | void *user), | |
3792 | void *user) | |
3793 | { | |
3794 | struct omap_hwmod *temp_oh; | |
3795 | int ret = 0; | |
3796 | ||
3797 | if (!classname || !fn) | |
3798 | return -EINVAL; | |
3799 | ||
3800 | pr_debug("omap_hwmod: %s: looking for modules of class %s\n", | |
3801 | __func__, classname); | |
3802 | ||
43b40992 PW |
3803 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
3804 | if (!strcmp(temp_oh->class->name, classname)) { | |
3805 | pr_debug("omap_hwmod: %s: %s: calling callback fn\n", | |
3806 | __func__, temp_oh->name); | |
3807 | ret = (*fn)(temp_oh, user); | |
3808 | if (ret) | |
3809 | break; | |
3810 | } | |
3811 | } | |
3812 | ||
43b40992 PW |
3813 | if (ret) |
3814 | pr_debug("omap_hwmod: %s: iterator terminated early: %d\n", | |
3815 | __func__, ret); | |
3816 | ||
3817 | return ret; | |
3818 | } | |
3819 | ||
2092e5cc PW |
3820 | /** |
3821 | * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod | |
3822 | * @oh: struct omap_hwmod * | |
3823 | * @state: state that _setup() should leave the hwmod in | |
3824 | * | |
550c8092 | 3825 | * Sets the hwmod state that @oh will enter at the end of _setup() |
64813c3f PW |
3826 | * (called by omap_hwmod_setup_*()). See also the documentation |
3827 | * for _setup_postsetup(), above. Returns 0 upon success or | |
3828 | * -EINVAL if there is a problem with the arguments or if the hwmod is | |
3829 | * in the wrong state. | |
2092e5cc PW |
3830 | */ |
3831 | int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) | |
3832 | { | |
3833 | int ret; | |
dc6d1cda | 3834 | unsigned long flags; |
2092e5cc PW |
3835 | |
3836 | if (!oh) | |
3837 | return -EINVAL; | |
3838 | ||
3839 | if (state != _HWMOD_STATE_DISABLED && | |
3840 | state != _HWMOD_STATE_ENABLED && | |
3841 | state != _HWMOD_STATE_IDLE) | |
3842 | return -EINVAL; | |
3843 | ||
dc6d1cda | 3844 | spin_lock_irqsave(&oh->_lock, flags); |
2092e5cc PW |
3845 | |
3846 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
3847 | ret = -EINVAL; | |
3848 | goto ohsps_unlock; | |
3849 | } | |
3850 | ||
3851 | oh->_postsetup_state = state; | |
3852 | ret = 0; | |
3853 | ||
3854 | ohsps_unlock: | |
dc6d1cda | 3855 | spin_unlock_irqrestore(&oh->_lock, flags); |
2092e5cc PW |
3856 | |
3857 | return ret; | |
3858 | } | |
c80705aa KH |
3859 | |
3860 | /** | |
3861 | * omap_hwmod_get_context_loss_count - get lost context count | |
3862 | * @oh: struct omap_hwmod * | |
3863 | * | |
e6d3a8b0 RN |
3864 | * Returns the context loss count of associated @oh |
3865 | * upon success, or zero if no context loss data is available. | |
c80705aa | 3866 | * |
e6d3a8b0 RN |
3867 | * On OMAP4, this queries the per-hwmod context loss register, |
3868 | * assuming one exists. If not, or on OMAP2/3, this queries the | |
3869 | * enclosing powerdomain context loss count. | |
c80705aa | 3870 | */ |
fc013873 | 3871 | int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh) |
c80705aa KH |
3872 | { |
3873 | struct powerdomain *pwrdm; | |
3874 | int ret = 0; | |
3875 | ||
e6d3a8b0 RN |
3876 | if (soc_ops.get_context_lost) |
3877 | return soc_ops.get_context_lost(oh); | |
3878 | ||
c80705aa KH |
3879 | pwrdm = omap_hwmod_get_pwrdm(oh); |
3880 | if (pwrdm) | |
3881 | ret = pwrdm_get_context_loss_count(pwrdm); | |
3882 | ||
3883 | return ret; | |
3884 | } | |
43b01643 | 3885 | |
9ebfd285 KH |
3886 | /** |
3887 | * omap_hwmod_init - initialize the hwmod code | |
3888 | * | |
3889 | * Sets up some function pointers needed by the hwmod code to operate on the | |
3890 | * currently-booted SoC. Intended to be called once during kernel init | |
3891 | * before any hwmods are registered. No return value. | |
3892 | */ | |
3893 | void __init omap_hwmod_init(void) | |
3894 | { | |
ff4ae5d9 | 3895 | if (cpu_is_omap24xx()) { |
9002e921 | 3896 | soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready; |
ff4ae5d9 PW |
3897 | soc_ops.assert_hardreset = _omap2_assert_hardreset; |
3898 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | |
3899 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | |
3900 | } else if (cpu_is_omap34xx()) { | |
9002e921 | 3901 | soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready; |
b8249cf2 KH |
3902 | soc_ops.assert_hardreset = _omap2_assert_hardreset; |
3903 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | |
3904 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | |
0385c582 | 3905 | soc_ops.init_clkdm = _init_clkdm; |
debcd1f8 | 3906 | } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) { |
9ebfd285 KH |
3907 | soc_ops.enable_module = _omap4_enable_module; |
3908 | soc_ops.disable_module = _omap4_disable_module; | |
8f6aa8ee | 3909 | soc_ops.wait_target_ready = _omap4_wait_target_ready; |
b8249cf2 KH |
3910 | soc_ops.assert_hardreset = _omap4_assert_hardreset; |
3911 | soc_ops.deassert_hardreset = _omap4_deassert_hardreset; | |
3912 | soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; | |
0a179eaa | 3913 | soc_ops.init_clkdm = _init_clkdm; |
e6d3a8b0 RN |
3914 | soc_ops.update_context_lost = _omap4_update_context_lost; |
3915 | soc_ops.get_context_lost = _omap4_get_context_lost; | |
0f3ccb24 TL |
3916 | } else if (cpu_is_ti814x() || cpu_is_ti816x() || soc_is_am33xx() || |
3917 | soc_is_am43xx()) { | |
c8b428a5 AM |
3918 | soc_ops.enable_module = _omap4_enable_module; |
3919 | soc_ops.disable_module = _omap4_disable_module; | |
3920 | soc_ops.wait_target_ready = _omap4_wait_target_ready; | |
409d7063 | 3921 | soc_ops.assert_hardreset = _omap4_assert_hardreset; |
1688bf19 | 3922 | soc_ops.deassert_hardreset = _am33xx_deassert_hardreset; |
a5bf00cd | 3923 | soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; |
1688bf19 | 3924 | soc_ops.init_clkdm = _init_clkdm; |
8f6aa8ee KH |
3925 | } else { |
3926 | WARN(1, "omap_hwmod: unknown SoC type\n"); | |
9ebfd285 KH |
3927 | } |
3928 | ||
3929 | inited = true; | |
3930 | } | |
68c9a95e TL |
3931 | |
3932 | /** | |
3933 | * omap_hwmod_get_main_clk - get pointer to main clock name | |
3934 | * @oh: struct omap_hwmod * | |
3935 | * | |
3936 | * Returns the main clock name assocated with @oh upon success, | |
3937 | * or NULL if @oh is NULL. | |
3938 | */ | |
3939 | const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh) | |
3940 | { | |
3941 | if (!oh) | |
3942 | return NULL; | |
3943 | ||
3944 | return oh->main_clk; | |
3945 | } |