Commit | Line | Data |
---|---|---|
02bfc030 | 1 | /* |
7359154e | 2 | * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips |
02bfc030 | 3 | * |
78183f3f | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
0a78c5c5 | 5 | * Copyright (C) 2012 Texas Instruments, Inc. |
02bfc030 PW |
6 | * Paul Walmsley |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * XXX handle crossbar/shared link difference for L3? | |
7359154e | 13 | * XXX these should be marked initdata for multi-OMAP kernels |
02bfc030 | 14 | */ |
3a8761c0 TL |
15 | |
16 | #include <linux/i2c-omap.h> | |
2203747c AB |
17 | #include <linux/platform_data/spi-omap2-mcspi.h> |
18 | ||
ce491cf8 | 19 | #include <plat/omap_hwmod.h> |
2b6c4e73 | 20 | #include <plat-omap/dma-omap.h> |
eddb1262 | 21 | #include <plat/dmtimer.h> |
1e0f51a9 | 22 | #include "l3_2xxx.h" |
70606b1c | 23 | #include "l4_2xxx.h" |
02bfc030 | 24 | |
43b40992 PW |
25 | #include "omap_hwmod_common_data.h" |
26 | ||
a714b9cf | 27 | #include "cm-regbits-24xx.h" |
2004290f | 28 | #include "prm-regbits-24xx.h" |
3a8761c0 | 29 | #include "i2c.h" |
68f39e74 | 30 | #include "mmc.h" |
ff2516fb | 31 | #include "wd_timer.h" |
02bfc030 | 32 | |
7359154e PW |
33 | /* |
34 | * OMAP2420 hardware module integration data | |
35 | * | |
844a3b63 | 36 | * All of the data in this section should be autogeneratable from the |
7359154e PW |
37 | * TI hardware database or other technical documentation. Data that |
38 | * is driver-specific or driver-kernel integration-specific belongs | |
39 | * elsewhere. | |
40 | */ | |
41 | ||
844a3b63 PW |
42 | /* |
43 | * IP blocks | |
44 | */ | |
996746ca | 45 | |
3af35fbc PW |
46 | /* IVA1 (IVA1) */ |
47 | static struct omap_hwmod_class iva1_hwmod_class = { | |
48 | .name = "iva1", | |
49 | }; | |
50 | ||
51 | static struct omap_hwmod_rst_info omap2420_iva_resets[] = { | |
52 | { .name = "iva", .rst_shift = 8 }, | |
53 | }; | |
54 | ||
08072acf PW |
55 | static struct omap_hwmod omap2420_iva_hwmod = { |
56 | .name = "iva", | |
3af35fbc PW |
57 | .class = &iva1_hwmod_class, |
58 | .clkdm_name = "iva1_clkdm", | |
59 | .rst_lines = omap2420_iva_resets, | |
60 | .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets), | |
61 | .main_clk = "iva1_ifck", | |
62 | }; | |
63 | ||
64 | /* DSP */ | |
65 | static struct omap_hwmod_class dsp_hwmod_class = { | |
66 | .name = "dsp", | |
67 | }; | |
68 | ||
69 | static struct omap_hwmod_rst_info omap2420_dsp_resets[] = { | |
70 | { .name = "logic", .rst_shift = 0 }, | |
71 | { .name = "mmu", .rst_shift = 1 }, | |
72 | }; | |
73 | ||
74 | static struct omap_hwmod omap2420_dsp_hwmod = { | |
75 | .name = "dsp", | |
76 | .class = &dsp_hwmod_class, | |
77 | .clkdm_name = "dsp_clkdm", | |
78 | .rst_lines = omap2420_dsp_resets, | |
79 | .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets), | |
80 | .main_clk = "dsp_fck", | |
08072acf PW |
81 | }; |
82 | ||
2004290f PW |
83 | /* I2C common */ |
84 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
85 | .rev_offs = 0x00, | |
86 | .sysc_offs = 0x20, | |
87 | .syss_offs = 0x10, | |
d73d65fa | 88 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
2004290f PW |
89 | .sysc_fields = &omap_hwmod_sysc_type1, |
90 | }; | |
91 | ||
92 | static struct omap_hwmod_class i2c_class = { | |
93 | .name = "i2c", | |
94 | .sysc = &i2c_sysc, | |
db791a75 | 95 | .rev = OMAP_I2C_IP_VERSION_1, |
6d3c55fd | 96 | .reset = &omap_i2c_reset, |
2004290f PW |
97 | }; |
98 | ||
4d4441a6 AG |
99 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
100 | .flags = OMAP_I2C_FLAG_NO_FIFO | | |
101 | OMAP_I2C_FLAG_SIMPLE_CLOCK | | |
102 | OMAP_I2C_FLAG_16BIT_DATA_REG | | |
103 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
104 | }; | |
2004290f PW |
105 | |
106 | /* I2C1 */ | |
2004290f PW |
107 | static struct omap_hwmod omap2420_i2c1_hwmod = { |
108 | .name = "i2c1", | |
0d619a89 | 109 | .mpu_irqs = omap2_i2c1_mpu_irqs, |
d826ebfa | 110 | .sdma_reqs = omap2_i2c1_sdma_reqs, |
2004290f PW |
111 | .main_clk = "i2c1_fck", |
112 | .prcm = { | |
113 | .omap2 = { | |
114 | .module_offs = CORE_MOD, | |
115 | .prcm_reg_id = 1, | |
116 | .module_bit = OMAP2420_EN_I2C1_SHIFT, | |
117 | .idlest_reg_id = 1, | |
118 | .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, | |
119 | }, | |
120 | }, | |
2004290f PW |
121 | .class = &i2c_class, |
122 | .dev_attr = &i2c_dev_attr, | |
2004290f PW |
123 | .flags = HWMOD_16BIT_REG, |
124 | }; | |
125 | ||
126 | /* I2C2 */ | |
2004290f PW |
127 | static struct omap_hwmod omap2420_i2c2_hwmod = { |
128 | .name = "i2c2", | |
0d619a89 | 129 | .mpu_irqs = omap2_i2c2_mpu_irqs, |
d826ebfa | 130 | .sdma_reqs = omap2_i2c2_sdma_reqs, |
2004290f PW |
131 | .main_clk = "i2c2_fck", |
132 | .prcm = { | |
133 | .omap2 = { | |
134 | .module_offs = CORE_MOD, | |
135 | .prcm_reg_id = 1, | |
136 | .module_bit = OMAP2420_EN_I2C2_SHIFT, | |
137 | .idlest_reg_id = 1, | |
138 | .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, | |
139 | }, | |
140 | }, | |
2004290f PW |
141 | .class = &i2c_class, |
142 | .dev_attr = &i2c_dev_attr, | |
2004290f PW |
143 | .flags = HWMOD_16BIT_REG, |
144 | }; | |
145 | ||
745685df MK |
146 | /* dma attributes */ |
147 | static struct omap_dma_dev_attr dma_dev_attr = { | |
148 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
149 | IS_CSSA_32 | IS_CDSA_32, | |
150 | .lch_count = 32, | |
151 | }; | |
152 | ||
745685df MK |
153 | static struct omap_hwmod omap2420_dma_system_hwmod = { |
154 | .name = "dma", | |
273b9465 | 155 | .class = &omap2xxx_dma_hwmod_class, |
0d619a89 | 156 | .mpu_irqs = omap2_dma_system_irqs, |
745685df | 157 | .main_clk = "core_l3_ck", |
745685df | 158 | .dev_attr = &dma_dev_attr, |
745685df MK |
159 | .flags = HWMOD_NO_IDLEST, |
160 | }; | |
161 | ||
fca1ab55 | 162 | /* mailbox */ |
fca1ab55 | 163 | static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { |
7d7e1eba TL |
164 | { .name = "dsp", .irq = 26 + OMAP_INTC_START, }, |
165 | { .name = "iva", .irq = 34 + OMAP_INTC_START, }, | |
166 | { .irq = -1 }, | |
fca1ab55 ORL |
167 | }; |
168 | ||
fca1ab55 ORL |
169 | static struct omap_hwmod omap2420_mailbox_hwmod = { |
170 | .name = "mailbox", | |
273b9465 | 171 | .class = &omap2xxx_mailbox_hwmod_class, |
fca1ab55 | 172 | .mpu_irqs = omap2420_mailbox_irqs, |
fca1ab55 ORL |
173 | .main_clk = "mailboxes_ick", |
174 | .prcm = { | |
175 | .omap2 = { | |
176 | .prcm_reg_id = 1, | |
177 | .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | |
178 | .module_offs = CORE_MOD, | |
179 | .idlest_reg_id = 1, | |
180 | .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, | |
181 | }, | |
182 | }, | |
fca1ab55 ORL |
183 | }; |
184 | ||
3cb72fa4 C |
185 | /* |
186 | * 'mcbsp' class | |
187 | * multi channel buffered serial port controller | |
188 | */ | |
189 | ||
190 | static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { | |
191 | .name = "mcbsp", | |
192 | }; | |
193 | ||
b3153100 PU |
194 | static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { |
195 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | |
196 | { .role = "prcm_fck", .clk = "func_96m_ck" }, | |
197 | }; | |
198 | ||
3cb72fa4 C |
199 | /* mcbsp1 */ |
200 | static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { | |
7d7e1eba TL |
201 | { .name = "tx", .irq = 59 + OMAP_INTC_START, }, |
202 | { .name = "rx", .irq = 60 + OMAP_INTC_START, }, | |
203 | { .irq = -1 }, | |
3cb72fa4 C |
204 | }; |
205 | ||
3cb72fa4 C |
206 | static struct omap_hwmod omap2420_mcbsp1_hwmod = { |
207 | .name = "mcbsp1", | |
208 | .class = &omap2420_mcbsp_hwmod_class, | |
209 | .mpu_irqs = omap2420_mcbsp1_irqs, | |
d826ebfa | 210 | .sdma_reqs = omap2_mcbsp1_sdma_reqs, |
3cb72fa4 C |
211 | .main_clk = "mcbsp1_fck", |
212 | .prcm = { | |
213 | .omap2 = { | |
214 | .prcm_reg_id = 1, | |
215 | .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, | |
216 | .module_offs = CORE_MOD, | |
217 | .idlest_reg_id = 1, | |
218 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, | |
219 | }, | |
220 | }, | |
b3153100 PU |
221 | .opt_clks = mcbsp_opt_clks, |
222 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | |
3cb72fa4 C |
223 | }; |
224 | ||
225 | /* mcbsp2 */ | |
226 | static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { | |
7d7e1eba TL |
227 | { .name = "tx", .irq = 62 + OMAP_INTC_START, }, |
228 | { .name = "rx", .irq = 63 + OMAP_INTC_START, }, | |
229 | { .irq = -1 }, | |
3cb72fa4 C |
230 | }; |
231 | ||
3cb72fa4 C |
232 | static struct omap_hwmod omap2420_mcbsp2_hwmod = { |
233 | .name = "mcbsp2", | |
234 | .class = &omap2420_mcbsp_hwmod_class, | |
235 | .mpu_irqs = omap2420_mcbsp2_irqs, | |
d826ebfa | 236 | .sdma_reqs = omap2_mcbsp2_sdma_reqs, |
3cb72fa4 C |
237 | .main_clk = "mcbsp2_fck", |
238 | .prcm = { | |
239 | .omap2 = { | |
240 | .prcm_reg_id = 1, | |
241 | .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, | |
242 | .module_offs = CORE_MOD, | |
243 | .idlest_reg_id = 1, | |
244 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, | |
245 | }, | |
246 | }, | |
b3153100 PU |
247 | .opt_clks = mcbsp_opt_clks, |
248 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | |
0a78c5c5 PW |
249 | }; |
250 | ||
ad1b6662 TL |
251 | static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = { |
252 | .rev_offs = 0x3c, | |
253 | .sysc_offs = 0x64, | |
254 | .syss_offs = 0x68, | |
255 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
256 | .sysc_fields = &omap_hwmod_sysc_type1, | |
257 | }; | |
258 | ||
259 | static struct omap_hwmod_class omap2420_msdi_hwmod_class = { | |
260 | .name = "msdi", | |
261 | .sysc = &omap2420_msdi_sysc, | |
262 | .reset = &omap_msdi_reset, | |
263 | }; | |
264 | ||
265 | /* msdi1 */ | |
266 | static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = { | |
7d7e1eba TL |
267 | { .irq = 83 + OMAP_INTC_START, }, |
268 | { .irq = -1 }, | |
ad1b6662 TL |
269 | }; |
270 | ||
271 | static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = { | |
272 | { .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */ | |
273 | { .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */ | |
274 | { .dma_req = -1 } | |
275 | }; | |
276 | ||
277 | static struct omap_hwmod omap2420_msdi1_hwmod = { | |
278 | .name = "msdi1", | |
279 | .class = &omap2420_msdi_hwmod_class, | |
280 | .mpu_irqs = omap2420_msdi1_irqs, | |
281 | .sdma_reqs = omap2420_msdi1_sdma_reqs, | |
282 | .main_clk = "mmc_fck", | |
283 | .prcm = { | |
284 | .omap2 = { | |
285 | .prcm_reg_id = 1, | |
286 | .module_bit = OMAP2420_EN_MMC_SHIFT, | |
287 | .module_offs = CORE_MOD, | |
288 | .idlest_reg_id = 1, | |
289 | .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT, | |
290 | }, | |
291 | }, | |
292 | .flags = HWMOD_16BIT_REG, | |
293 | }; | |
294 | ||
f32bd778 PW |
295 | /* HDQ1W/1-wire */ |
296 | static struct omap_hwmod omap2420_hdq1w_hwmod = { | |
297 | .name = "hdq1w", | |
298 | .mpu_irqs = omap2_hdq1w_mpu_irqs, | |
299 | .main_clk = "hdq_fck", | |
300 | .prcm = { | |
301 | .omap2 = { | |
302 | .module_offs = CORE_MOD, | |
303 | .prcm_reg_id = 1, | |
304 | .module_bit = OMAP24XX_EN_HDQ_SHIFT, | |
305 | .idlest_reg_id = 1, | |
306 | .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT, | |
307 | }, | |
308 | }, | |
309 | .class = &omap2_hdq1w_class, | |
310 | }; | |
311 | ||
844a3b63 PW |
312 | /* |
313 | * interfaces | |
314 | */ | |
315 | ||
844a3b63 PW |
316 | /* L4 CORE -> I2C1 interface */ |
317 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { | |
cb48427e | 318 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
319 | .slave = &omap2420_i2c1_hwmod, |
320 | .clk = "i2c1_ick", | |
321 | .addr = omap2_i2c1_addr_space, | |
322 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
323 | }; | |
324 | ||
325 | /* L4 CORE -> I2C2 interface */ | |
326 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { | |
cb48427e | 327 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
328 | .slave = &omap2420_i2c2_hwmod, |
329 | .clk = "i2c2_ick", | |
330 | .addr = omap2_i2c2_addr_space, | |
331 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
332 | }; | |
333 | ||
334 | /* IVA <- L3 interface */ | |
335 | static struct omap_hwmod_ocp_if omap2420_l3__iva = { | |
cb48427e | 336 | .master = &omap2xxx_l3_main_hwmod, |
844a3b63 | 337 | .slave = &omap2420_iva_hwmod, |
3af35fbc PW |
338 | .clk = "core_l3_ck", |
339 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
340 | }; | |
341 | ||
342 | /* DSP <- L3 interface */ | |
343 | static struct omap_hwmod_ocp_if omap2420_l3__dsp = { | |
344 | .master = &omap2xxx_l3_main_hwmod, | |
345 | .slave = &omap2420_dsp_hwmod, | |
346 | .clk = "dsp_ick", | |
844a3b63 PW |
347 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
348 | }; | |
349 | ||
350 | static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { | |
351 | { | |
352 | .pa_start = 0x48028000, | |
353 | .pa_end = 0x48028000 + SZ_1K - 1, | |
354 | .flags = ADDR_TYPE_RT | |
355 | }, | |
356 | { } | |
357 | }; | |
358 | ||
359 | /* l4_wkup -> timer1 */ | |
360 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { | |
cb48427e PW |
361 | .master = &omap2xxx_l4_wkup_hwmod, |
362 | .slave = &omap2xxx_timer1_hwmod, | |
844a3b63 PW |
363 | .clk = "gpt1_ick", |
364 | .addr = omap2420_timer1_addrs, | |
365 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
366 | }; | |
367 | ||
844a3b63 PW |
368 | /* l4_wkup -> wd_timer2 */ |
369 | static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { | |
370 | { | |
371 | .pa_start = 0x48022000, | |
372 | .pa_end = 0x4802207f, | |
373 | .flags = ADDR_TYPE_RT | |
374 | }, | |
375 | { } | |
376 | }; | |
377 | ||
378 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { | |
cb48427e PW |
379 | .master = &omap2xxx_l4_wkup_hwmod, |
380 | .slave = &omap2xxx_wd_timer2_hwmod, | |
844a3b63 PW |
381 | .clk = "mpu_wdt_ick", |
382 | .addr = omap2420_wd_timer2_addrs, | |
383 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
384 | }; | |
385 | ||
844a3b63 PW |
386 | /* l4_wkup -> gpio1 */ |
387 | static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { | |
388 | { | |
389 | .pa_start = 0x48018000, | |
390 | .pa_end = 0x480181ff, | |
391 | .flags = ADDR_TYPE_RT | |
392 | }, | |
393 | { } | |
394 | }; | |
395 | ||
396 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { | |
cb48427e PW |
397 | .master = &omap2xxx_l4_wkup_hwmod, |
398 | .slave = &omap2xxx_gpio1_hwmod, | |
844a3b63 PW |
399 | .clk = "gpios_ick", |
400 | .addr = omap2420_gpio1_addr_space, | |
401 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
402 | }; | |
403 | ||
404 | /* l4_wkup -> gpio2 */ | |
405 | static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { | |
406 | { | |
407 | .pa_start = 0x4801a000, | |
408 | .pa_end = 0x4801a1ff, | |
409 | .flags = ADDR_TYPE_RT | |
410 | }, | |
411 | { } | |
412 | }; | |
413 | ||
414 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { | |
cb48427e PW |
415 | .master = &omap2xxx_l4_wkup_hwmod, |
416 | .slave = &omap2xxx_gpio2_hwmod, | |
844a3b63 PW |
417 | .clk = "gpios_ick", |
418 | .addr = omap2420_gpio2_addr_space, | |
419 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
420 | }; | |
421 | ||
422 | /* l4_wkup -> gpio3 */ | |
423 | static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { | |
424 | { | |
425 | .pa_start = 0x4801c000, | |
426 | .pa_end = 0x4801c1ff, | |
427 | .flags = ADDR_TYPE_RT | |
428 | }, | |
429 | { } | |
430 | }; | |
431 | ||
432 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { | |
cb48427e PW |
433 | .master = &omap2xxx_l4_wkup_hwmod, |
434 | .slave = &omap2xxx_gpio3_hwmod, | |
844a3b63 PW |
435 | .clk = "gpios_ick", |
436 | .addr = omap2420_gpio3_addr_space, | |
437 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
438 | }; | |
439 | ||
440 | /* l4_wkup -> gpio4 */ | |
441 | static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { | |
442 | { | |
443 | .pa_start = 0x4801e000, | |
444 | .pa_end = 0x4801e1ff, | |
445 | .flags = ADDR_TYPE_RT | |
446 | }, | |
447 | { } | |
448 | }; | |
449 | ||
450 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { | |
cb48427e PW |
451 | .master = &omap2xxx_l4_wkup_hwmod, |
452 | .slave = &omap2xxx_gpio4_hwmod, | |
844a3b63 PW |
453 | .clk = "gpios_ick", |
454 | .addr = omap2420_gpio4_addr_space, | |
455 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
456 | }; | |
457 | ||
458 | /* dma_system -> L3 */ | |
459 | static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { | |
460 | .master = &omap2420_dma_system_hwmod, | |
cb48427e | 461 | .slave = &omap2xxx_l3_main_hwmod, |
844a3b63 PW |
462 | .clk = "core_l3_ck", |
463 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
464 | }; | |
465 | ||
466 | /* l4_core -> dma_system */ | |
467 | static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { | |
cb48427e | 468 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
469 | .slave = &omap2420_dma_system_hwmod, |
470 | .clk = "sdma_ick", | |
471 | .addr = omap2_dma_system_addrs, | |
472 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
473 | }; | |
474 | ||
475 | /* l4_core -> mailbox */ | |
476 | static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { | |
cb48427e | 477 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
478 | .slave = &omap2420_mailbox_hwmod, |
479 | .addr = omap2_mailbox_addrs, | |
480 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
481 | }; | |
482 | ||
483 | /* l4_core -> mcbsp1 */ | |
484 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { | |
cb48427e | 485 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
486 | .slave = &omap2420_mcbsp1_hwmod, |
487 | .clk = "mcbsp1_ick", | |
488 | .addr = omap2_mcbsp1_addrs, | |
489 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
490 | }; | |
491 | ||
492 | /* l4_core -> mcbsp2 */ | |
493 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { | |
cb48427e | 494 | .master = &omap2xxx_l4_core_hwmod, |
844a3b63 PW |
495 | .slave = &omap2420_mcbsp2_hwmod, |
496 | .clk = "mcbsp2_ick", | |
497 | .addr = omap2xxx_mcbsp2_addrs, | |
498 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
499 | }; | |
500 | ||
ad1b6662 TL |
501 | static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = { |
502 | { | |
503 | .pa_start = 0x4809c000, | |
504 | .pa_end = 0x4809c000 + SZ_128 - 1, | |
505 | .flags = ADDR_TYPE_RT, | |
506 | }, | |
507 | { } | |
508 | }; | |
509 | ||
510 | /* l4_core -> msdi1 */ | |
511 | static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = { | |
512 | .master = &omap2xxx_l4_core_hwmod, | |
513 | .slave = &omap2420_msdi1_hwmod, | |
514 | .clk = "mmc_ick", | |
515 | .addr = omap2420_msdi1_addrs, | |
516 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
517 | }; | |
518 | ||
f32bd778 PW |
519 | /* l4_core -> hdq1w interface */ |
520 | static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = { | |
521 | .master = &omap2xxx_l4_core_hwmod, | |
522 | .slave = &omap2420_hdq1w_hwmod, | |
523 | .clk = "hdq_ick", | |
524 | .addr = omap2_hdq1w_addr_space, | |
525 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
526 | .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, | |
527 | }; | |
528 | ||
529 | ||
c8d82ff6 VH |
530 | /* l4_wkup -> 32ksync_counter */ |
531 | static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = { | |
532 | { | |
533 | .pa_start = 0x48004000, | |
534 | .pa_end = 0x4800401f, | |
535 | .flags = ADDR_TYPE_RT | |
536 | }, | |
537 | { } | |
538 | }; | |
539 | ||
49484a60 AM |
540 | static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = { |
541 | { | |
542 | .pa_start = 0x6800a000, | |
543 | .pa_end = 0x6800afff, | |
544 | .flags = ADDR_TYPE_RT | |
545 | }, | |
546 | { } | |
547 | }; | |
548 | ||
c8d82ff6 VH |
549 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = { |
550 | .master = &omap2xxx_l4_wkup_hwmod, | |
551 | .slave = &omap2xxx_counter_32k_hwmod, | |
552 | .clk = "sync_32k_ick", | |
553 | .addr = omap2420_counter_32k_addrs, | |
554 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
555 | }; | |
556 | ||
49484a60 AM |
557 | static struct omap_hwmod_ocp_if omap2420_l3__gpmc = { |
558 | .master = &omap2xxx_l3_main_hwmod, | |
559 | .slave = &omap2xxx_gpmc_hwmod, | |
560 | .clk = "core_l3_ck", | |
561 | .addr = omap2420_gpmc_addrs, | |
562 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
563 | }; | |
564 | ||
0a78c5c5 | 565 | static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { |
6a29755f PW |
566 | &omap2xxx_l3_main__l4_core, |
567 | &omap2xxx_mpu__l3_main, | |
568 | &omap2xxx_dss__l3, | |
569 | &omap2xxx_l4_core__mcspi1, | |
570 | &omap2xxx_l4_core__mcspi2, | |
571 | &omap2xxx_l4_core__l4_wkup, | |
0a78c5c5 PW |
572 | &omap2_l4_core__uart1, |
573 | &omap2_l4_core__uart2, | |
574 | &omap2_l4_core__uart3, | |
575 | &omap2420_l4_core__i2c1, | |
576 | &omap2420_l4_core__i2c2, | |
577 | &omap2420_l3__iva, | |
3af35fbc | 578 | &omap2420_l3__dsp, |
0a78c5c5 | 579 | &omap2420_l4_wkup__timer1, |
6a29755f PW |
580 | &omap2xxx_l4_core__timer2, |
581 | &omap2xxx_l4_core__timer3, | |
582 | &omap2xxx_l4_core__timer4, | |
583 | &omap2xxx_l4_core__timer5, | |
584 | &omap2xxx_l4_core__timer6, | |
585 | &omap2xxx_l4_core__timer7, | |
586 | &omap2xxx_l4_core__timer8, | |
587 | &omap2xxx_l4_core__timer9, | |
588 | &omap2xxx_l4_core__timer10, | |
589 | &omap2xxx_l4_core__timer11, | |
590 | &omap2xxx_l4_core__timer12, | |
0a78c5c5 | 591 | &omap2420_l4_wkup__wd_timer2, |
6a29755f PW |
592 | &omap2xxx_l4_core__dss, |
593 | &omap2xxx_l4_core__dss_dispc, | |
594 | &omap2xxx_l4_core__dss_rfbi, | |
595 | &omap2xxx_l4_core__dss_venc, | |
0a78c5c5 PW |
596 | &omap2420_l4_wkup__gpio1, |
597 | &omap2420_l4_wkup__gpio2, | |
598 | &omap2420_l4_wkup__gpio3, | |
599 | &omap2420_l4_wkup__gpio4, | |
600 | &omap2420_dma_system__l3, | |
601 | &omap2420_l4_core__dma_system, | |
602 | &omap2420_l4_core__mailbox, | |
603 | &omap2420_l4_core__mcbsp1, | |
604 | &omap2420_l4_core__mcbsp2, | |
ad1b6662 | 605 | &omap2420_l4_core__msdi1, |
e9b0a2fb | 606 | &omap2xxx_l4_core__rng, |
f32bd778 | 607 | &omap2420_l4_core__hdq1w, |
c8d82ff6 | 608 | &omap2420_l4_wkup__counter_32k, |
49484a60 | 609 | &omap2420_l3__gpmc, |
02bfc030 PW |
610 | NULL, |
611 | }; | |
612 | ||
7359154e PW |
613 | int __init omap2420_hwmod_init(void) |
614 | { | |
9ebfd285 | 615 | omap_hwmod_init(); |
0a78c5c5 | 616 | return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs); |
7359154e | 617 | } |