[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_2xxx_ipblock_data.c

/*
 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
 *
 * Copyright (C) 2011 Nokia Corporation
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <plat/omap_hwmod.h>
#include <plat/serial.h>
#include <linux/platform_data/gpio-omap.h>
#include <plat/dma.h>
#include <plat/dmtimer.h>
#include <linux/platform_data/spi-omap2-mcspi.h>

#include "omap_hwmod_common_data.h"
#include "cm-regbits-24xx.h"
#include "prm-regbits-24xx.h"
#include "wd_timer.h"

struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
	{ .irq = 48 + OMAP_INTC_START, },
	{ .irq = -1 },
};

struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
	{ .name = "dispc", .dma_req = 5 },
	{ .dma_req = -1 }
};

/*
 * 'dispc' class
 * display controller
 */

static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2_dispc_hwmod_class = {
	.name	= "dispc",
	.sysc	= &omap2_dispc_sysc,
};

/* OMAP2xxx Timer Common */
static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
			   SYSC_HAS_AUTOIDLE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
	.name	= "timer",
	.sysc	= &omap2xxx_timer_sysc,
};

/*
 * 'wd_timer' class
 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 * overflow condition
 */

static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
	.name		= "wd_timer",
	.sysc		= &omap2xxx_wd_timer_sysc,
	.pre_shutdown	= &omap2_wd_timer_disable,
	.reset		= &omap2_wd_timer_reset,
};

/*
 * 'gpio' class
 * general purpose io module
 */
static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
			   SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
	.name = "gpio",
	.sysc = &omap2xxx_gpio_sysc,
	.rev = 0,
};

/* system dma */
static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x002c,
	.syss_offs	= 0x0028,
	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
			   SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
	.name	= "dma",
	.sysc	= &omap2xxx_dma_sysc,
};

/*
 * 'mailbox' class
 * mailbox module allowing communication between the on-chip processors
 * using a queued mailbox-interrupt mechanism.
 */

static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
	.rev_offs	= 0x000,
	.sysc_offs	= 0x010,
	.syss_offs	= 0x014,
	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
	.name	= "mailbox",
	.sysc	= &omap2xxx_mailbox_sysc,
};

/*
 * 'mcspi' class
 * multichannel serial port interface (mcspi) / master/slave synchronous serial
 * bus
 */

static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
				SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
				SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

struct omap_hwmod_class omap2xxx_mcspi_class = {
	.name	= "mcspi",
	.sysc	= &omap2xxx_mcspi_sysc,
	.rev	= OMAP2_MCSPI_REV,
};

/*
 * IP blocks
 */

/* L3 */
struct omap_hwmod omap2xxx_l3_main_hwmod = {
	.name		= "l3_main",
	.class		= &l3_hwmod_class,
	.flags		= HWMOD_NO_IDLEST,
};

/* L4 CORE */
struct omap_hwmod omap2xxx_l4_core_hwmod = {
	.name		= "l4_core",
	.class		= &l4_hwmod_class,
	.flags		= HWMOD_NO_IDLEST,
};

/* L4 WKUP */
struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
	.name		= "l4_wkup",
	.class		= &l4_hwmod_class,
	.flags		= HWMOD_NO_IDLEST,
};

/* MPU */
struct omap_hwmod omap2xxx_mpu_hwmod = {
	.name		= "mpu",
	.class		= &mpu_hwmod_class,
	.main_clk	= "mpu_ck",
};

/* IVA2 */
struct omap_hwmod omap2xxx_iva_hwmod = {
	.name		= "iva",
	.class		= &iva_hwmod_class,
};

/* always-on timers dev attribute */
static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
	.timer_capability       = OMAP_TIMER_ALWON,
};

/* pwm timers dev attribute */
static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
	.timer_capability       = OMAP_TIMER_HAS_PWM,
};

/* timer1 */

struct omap_hwmod omap2xxx_timer1_hwmod = {
	.name		= "timer1",
	.mpu_irqs	= omap2_timer1_mpu_irqs,
	.main_clk	= "gpt1_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT1_SHIFT,
			.module_offs = WKUP_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
		},
	},
	.dev_attr	= &capability_alwon_dev_attr,
	.class		= &omap2xxx_timer_hwmod_class,
};

/* timer2 */

struct omap_hwmod omap2xxx_timer2_hwmod = {
	.name		= "timer2",
	.mpu_irqs	= omap2_timer2_mpu_irqs,
	.main_clk	= "gpt2_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT2_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
		},
	},
	.class		= &omap2xxx_timer_hwmod_class,
};

/* timer3 */

struct omap_hwmod omap2xxx_timer3_hwmod = {
	.name		= "timer3",
	.mpu_irqs	= omap2_timer3_mpu_irqs,
	.main_clk	= "gpt3_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT3_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
		},
	},
	.class		= &omap2xxx_timer_hwmod_class,
};

/* timer4 */

struct omap_hwmod omap2xxx_timer4_hwmod = {
	.name		= "timer4",
	.mpu_irqs	= omap2_timer4_mpu_irqs,
	.main_clk	= "gpt4_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT4_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
		},
	},
	.class		= &omap2xxx_timer_hwmod_class,
};

/* timer5 */

struct omap_hwmod omap2xxx_timer5_hwmod = {
	.name		= "timer5",
	.mpu_irqs	= omap2_timer5_mpu_irqs,
	.main_clk	= "gpt5_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT5_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
		},
	},
	.class		= &omap2xxx_timer_hwmod_class,
};

/* timer6 */

struct omap_hwmod omap2xxx_timer6_hwmod = {
	.name		= "timer6",
	.mpu_irqs	= omap2_timer6_mpu_irqs,
	.main_clk	= "gpt6_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT6_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
		},
	},
	.class		= &omap2xxx_timer_hwmod_class,
};

/* timer7 */

struct omap_hwmod omap2xxx_timer7_hwmod = {
	.name		= "timer7",
	.mpu_irqs	= omap2_timer7_mpu_irqs,
	.main_clk	= "gpt7_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT7_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
		},
	},
	.class		= &omap2xxx_timer_hwmod_class,
};

/* timer8 */

struct omap_hwmod omap2xxx_timer8_hwmod = {
	.name		= "timer8",
	.mpu_irqs	= omap2_timer8_mpu_irqs,
	.main_clk	= "gpt8_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT8_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
		},
	},
	.class		= &omap2xxx_timer_hwmod_class,
};

/* timer9 */

struct omap_hwmod omap2xxx_timer9_hwmod = {
	.name		= "timer9",
	.mpu_irqs	= omap2_timer9_mpu_irqs,
	.main_clk	= "gpt9_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT9_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
		},
	},
	.dev_attr	= &capability_pwm_dev_attr,
	.class		= &omap2xxx_timer_hwmod_class,
};

/* timer10 */

struct omap_hwmod omap2xxx_timer10_hwmod = {
	.name		= "timer10",
	.mpu_irqs	= omap2_timer10_mpu_irqs,
	.main_clk	= "gpt10_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT10_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
		},
	},
	.dev_attr	= &capability_pwm_dev_attr,
	.class		= &omap2xxx_timer_hwmod_class,
};

/* timer11 */

struct omap_hwmod omap2xxx_timer11_hwmod = {
	.name		= "timer11",
	.mpu_irqs	= omap2_timer11_mpu_irqs,
	.main_clk	= "gpt11_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT11_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
		},
	},
	.dev_attr	= &capability_pwm_dev_attr,
	.class		= &omap2xxx_timer_hwmod_class,
};

/* timer12 */

struct omap_hwmod omap2xxx_timer12_hwmod = {
	.name		= "timer12",
	.mpu_irqs	= omap2xxx_timer12_mpu_irqs,
	.main_clk	= "gpt12_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPT12_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
		},
	},
	.dev_attr	= &capability_pwm_dev_attr,
	.class		= &omap2xxx_timer_hwmod_class,
};

/* wd_timer2 */
struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
	.name		= "wd_timer2",
	.class		= &omap2xxx_wd_timer_hwmod_class,
	.main_clk	= "mpu_wdt_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
			.module_offs = WKUP_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
		},
	},
};

/* UART1 */

struct omap_hwmod omap2xxx_uart1_hwmod = {
	.name		= "uart1",
	.mpu_irqs	= omap2_uart1_mpu_irqs,
	.sdma_reqs	= omap2_uart1_sdma_reqs,
	.main_clk	= "uart1_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_UART1_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
		},
	},
	.class		= &omap2_uart_class,
};

/* UART2 */

struct omap_hwmod omap2xxx_uart2_hwmod = {
	.name		= "uart2",
	.mpu_irqs	= omap2_uart2_mpu_irqs,
	.sdma_reqs	= omap2_uart2_sdma_reqs,
	.main_clk	= "uart2_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_UART2_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
		},
	},
	.class		= &omap2_uart_class,
};

/* UART3 */

struct omap_hwmod omap2xxx_uart3_hwmod = {
	.name		= "uart3",
	.mpu_irqs	= omap2_uart3_mpu_irqs,
	.sdma_reqs	= omap2_uart3_sdma_reqs,
	.main_clk	= "uart3_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 2,
			.module_bit = OMAP24XX_EN_UART3_SHIFT,
			.idlest_reg_id = 2,
			.idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
		},
	},
	.class		= &omap2_uart_class,
};

/* dss */

static struct omap_hwmod_opt_clk dss_opt_clks[] = {
	/*
	 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
	 * driver does not use these clocks.
	 */
	{ .role = "tv_clk", .clk = "dss_54m_fck" },
	{ .role = "sys_clk", .clk = "dss2_fck" },
};

struct omap_hwmod omap2xxx_dss_core_hwmod = {
	.name		= "dss_core",
	.class		= &omap2_dss_hwmod_class,
	.main_clk	= "dss1_fck", /* instead of dss_fck */
	.sdma_reqs	= omap2xxx_dss_sdma_chs,
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
		},
	},
	.opt_clks	= dss_opt_clks,
	.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
	.flags		= HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
};

struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
	.name		= "dss_dispc",
	.class		= &omap2_dispc_hwmod_class,
	.mpu_irqs	= omap2_dispc_irqs,
	.main_clk	= "dss1_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
		},
	},
	.flags		= HWMOD_NO_IDLEST,
	.dev_attr	= &omap2_3_dss_dispc_dev_attr
};

static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
	{ .role = "ick", .clk = "dss_ick" },
};

struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
	.name		= "dss_rfbi",
	.class		= &omap2_rfbi_hwmod_class,
	.main_clk	= "dss1_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
			.module_offs = CORE_MOD,
		},
	},
	.opt_clks	= dss_rfbi_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),
	.flags		= HWMOD_NO_IDLEST,
};

struct omap_hwmod omap2xxx_dss_venc_hwmod = {
	.name		= "dss_venc",
	.class		= &omap2_venc_hwmod_class,
	.main_clk	= "dss_54m_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_DSS1_SHIFT,
			.module_offs = CORE_MOD,
		},
	},
	.flags		= HWMOD_NO_IDLEST,
};

/* gpio dev_attr */
struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
	.bank_width = 32,
	.dbck_flag = false,
};

/* gpio1 */
struct omap_hwmod omap2xxx_gpio1_hwmod = {
	.name		= "gpio1",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs	= omap2_gpio1_irqs,
	.main_clk	= "gpios_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
			.module_offs = WKUP_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
		},
	},
	.class		= &omap2xxx_gpio_hwmod_class,
	.dev_attr	= &omap2xxx_gpio_dev_attr,
};

/* gpio2 */
struct omap_hwmod omap2xxx_gpio2_hwmod = {
	.name		= "gpio2",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs	= omap2_gpio2_irqs,
	.main_clk	= "gpios_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
			.module_offs = WKUP_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
		},
	},
	.class		= &omap2xxx_gpio_hwmod_class,
	.dev_attr	= &omap2xxx_gpio_dev_attr,
};

/* gpio3 */
struct omap_hwmod omap2xxx_gpio3_hwmod = {
	.name		= "gpio3",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs	= omap2_gpio3_irqs,
	.main_clk	= "gpios_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
			.module_offs = WKUP_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
		},
	},
	.class		= &omap2xxx_gpio_hwmod_class,
	.dev_attr	= &omap2xxx_gpio_dev_attr,
};

/* gpio4 */
struct omap_hwmod omap2xxx_gpio4_hwmod = {
	.name		= "gpio4",
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs	= omap2_gpio4_irqs,
	.main_clk	= "gpios_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
			.module_offs = WKUP_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
		},
	},
	.class		= &omap2xxx_gpio_hwmod_class,
	.dev_attr	= &omap2xxx_gpio_dev_attr,
};

/* mcspi1 */
static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
	.num_chipselect = 4,
};

struct omap_hwmod omap2xxx_mcspi1_hwmod = {
	.name		= "mcspi1",
	.mpu_irqs	= omap2_mcspi1_mpu_irqs,
	.sdma_reqs	= omap2_mcspi1_sdma_reqs,
	.main_clk	= "mcspi1_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
		},
	},
	.class		= &omap2xxx_mcspi_class,
	.dev_attr	= &omap_mcspi1_dev_attr,
};

/* mcspi2 */
static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
	.num_chipselect = 2,
};

struct omap_hwmod omap2xxx_mcspi2_hwmod = {
	.name		= "mcspi2",
	.mpu_irqs	= omap2_mcspi2_mpu_irqs,
	.sdma_reqs	= omap2_mcspi2_sdma_reqs,
	.main_clk	= "mcspi2_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
		},
	},
	.class		= &omap2xxx_mcspi_class,
	.dev_attr	= &omap_mcspi2_dev_attr,
};


static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
	.name	= "counter",
};

struct omap_hwmod omap2xxx_counter_32k_hwmod = {
	.name		= "counter_32k",
	.main_clk	= "func_32k_ck",
	.prcm		= {
		.omap2	= {
			.module_offs = WKUP_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
		},
	},
	.class		= &omap2xxx_counter_hwmod_class,
};
Commit	Line	Data
0d619a89 PW	1	/*
	2	* omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
	3	*
	4	* Copyright (C) 2011 Nokia Corporation
	5	* Paul Walmsley
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#include <plat/omap_hwmod.h>
	12	#include <plat/serial.h>
4b25408f	13	#include <linux/platform_data/gpio-omap.h>
d826ebfa	14	#include <plat/dma.h>
273b9465	15	#include <plat/dmtimer.h>
2203747c	16	#include <linux/platform_data/spi-omap2-mcspi.h>
0d619a89	17
0d619a89	18	#include "omap_hwmod_common_data.h"
cb48427e PW	19	#include "cm-regbits-24xx.h"
cb48427e PW	20	#include "prm-regbits-24xx.h"
273b9465	21	#include "wd_timer.h"
0d619a89 PW	22
0d619a89 PW	23	struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
7d7e1eba TL	24	{ .irq = 48 + OMAP_INTC_START, },
7d7e1eba TL	25	{ .irq = -1 },
0d619a89	26	};
d826ebfa PW	27
	28	struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
	29	{ .name = "dispc", .dma_req = 5 },
	30	{ .dma_req = -1 }
	31	};
1ac6d46e TV	32
	33	/*
	34	* 'dispc' class
	35	* display controller
	36	*/
	37
	38	static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
	39	.rev_offs = 0x0000,
	40	.sysc_offs = 0x0010,
	41	.syss_offs = 0x0014,
	42	.sysc_flags = (SYSC_HAS_SIDLEMODE \| SYSC_HAS_MIDLEMODE \|
	43	SYSC_HAS_SOFTRESET \| SYSC_HAS_AUTOIDLE),
	44	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART \|
	45	MSTANDBY_FORCE \| MSTANDBY_NO \| MSTANDBY_SMART),
	46	.sysc_fields = &omap_hwmod_sysc_type1,
	47	};
	48
	49	struct omap_hwmod_class omap2_dispc_hwmod_class = {
	50	.name = "dispc",
	51	.sysc = &omap2_dispc_sysc,
	52	};
	53
273b9465 PW	54	/* OMAP2xxx Timer Common */
	55	static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
	56	.rev_offs = 0x0000,
	57	.sysc_offs = 0x0010,
	58	.syss_offs = 0x0014,
	59	.sysc_flags = (SYSC_HAS_SIDLEMODE \| SYSC_HAS_CLOCKACTIVITY \|
	60	SYSC_HAS_ENAWAKEUP \| SYSC_HAS_SOFTRESET \|
	61	SYSC_HAS_AUTOIDLE),
	62	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
	63	.sysc_fields = &omap_hwmod_sysc_type1,
	64	};
	65
	66	struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
	67	.name = "timer",
	68	.sysc = &omap2xxx_timer_sysc,
273b9465 PW	69	};
	70
	71	/*
	72	* 'wd_timer' class
	73	* 32-bit watchdog upward counter that generates a pulse on the reset pin on
	74	* overflow condition
	75	*/
	76
	77	static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
	78	.rev_offs = 0x0000,
	79	.sysc_offs = 0x0010,
	80	.syss_offs = 0x0014,
	81	.sysc_flags = (SYSC_HAS_EMUFREE \| SYSC_HAS_SOFTRESET \|
	82	SYSC_HAS_AUTOIDLE \| SYSS_HAS_RESET_STATUS),
	83	.sysc_fields = &omap_hwmod_sysc_type1,
	84	};
	85
	86	struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
	87	.name = "wd_timer",
	88	.sysc = &omap2xxx_wd_timer_sysc,
414e4128 KH	89	.pre_shutdown = &omap2_wd_timer_disable,
414e4128 KH	90	.reset = &omap2_wd_timer_reset,
273b9465 PW	91	};
	92
	93	/*
	94	* 'gpio' class
	95	* general purpose io module
	96	*/
	97	static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
	98	.rev_offs = 0x0000,
	99	.sysc_offs = 0x0010,
	100	.syss_offs = 0x0014,
	101	.sysc_flags = (SYSC_HAS_ENAWAKEUP \| SYSC_HAS_SIDLEMODE \|
	102	SYSC_HAS_SOFTRESET \| SYSC_HAS_AUTOIDLE \|
	103	SYSS_HAS_RESET_STATUS),
	104	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
	105	.sysc_fields = &omap_hwmod_sysc_type1,
	106	};
	107
	108	struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
	109	.name = "gpio",
	110	.sysc = &omap2xxx_gpio_sysc,
	111	.rev = 0,
	112	};
	113
	114	/* system dma */
	115	static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
	116	.rev_offs = 0x0000,
	117	.sysc_offs = 0x002c,
	118	.syss_offs = 0x0028,
	119	.sysc_flags = (SYSC_HAS_SOFTRESET \| SYSC_HAS_MIDLEMODE \|
	120	SYSC_HAS_CLOCKACTIVITY \| SYSC_HAS_EMUFREE \|
	121	SYSC_HAS_AUTOIDLE \| SYSS_HAS_RESET_STATUS),
	122	.idlemodes = (MSTANDBY_FORCE \| MSTANDBY_NO \| MSTANDBY_SMART),
	123	.sysc_fields = &omap_hwmod_sysc_type1,
	124	};
	125
	126	struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
	127	.name = "dma",
	128	.sysc = &omap2xxx_dma_sysc,
	129	};
	130
	131	/*
	132	* 'mailbox' class
	133	* mailbox module allowing communication between the on-chip processors
	134	* using a queued mailbox-interrupt mechanism.
	135	*/
	136
	137	static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
	138	.rev_offs = 0x000,
	139	.sysc_offs = 0x010,
	140	.syss_offs = 0x014,
	141	.sysc_flags = (SYSC_HAS_CLOCKACTIVITY \| SYSC_HAS_SIDLEMODE \|
	142	SYSC_HAS_SOFTRESET \| SYSC_HAS_AUTOIDLE),
	143	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
	144	.sysc_fields = &omap_hwmod_sysc_type1,
	145	};
	146
	147	struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
	148	.name = "mailbox",
	149	.sysc = &omap2xxx_mailbox_sysc,
	150	};
	151
	152	/*
	153	* 'mcspi' class
	154	* multichannel serial port interface (mcspi) / master/slave synchronous serial
155	* bus
156	*/
157
158	static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
159	.rev_offs = 0x0000,
160	.sysc_offs = 0x0010,
161	.syss_offs = 0x0014,
162	.sysc_flags = (SYSC_HAS_CLOCKACTIVITY \| SYSC_HAS_SIDLEMODE \|
163	SYSC_HAS_ENAWAKEUP \| SYSC_HAS_SOFTRESET \|
164	SYSC_HAS_AUTOIDLE \| SYSS_HAS_RESET_STATUS),
165	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
166	.sysc_fields = &omap_hwmod_sysc_type1,
167	};
168
169	struct omap_hwmod_class omap2xxx_mcspi_class = {
170	.name = "mcspi",
171	.sysc = &omap2xxx_mcspi_sysc,
172	.rev = OMAP2_MCSPI_REV,
173	};
cb48427e PW	174
	175	/*
	176	* IP blocks
	177	*/
	178
	179	/* L3 */
	180	struct omap_hwmod omap2xxx_l3_main_hwmod = {
	181	.name = "l3_main",
	182	.class = &l3_hwmod_class,
	183	.flags = HWMOD_NO_IDLEST,
	184	};
	185
	186	/* L4 CORE */
	187	struct omap_hwmod omap2xxx_l4_core_hwmod = {
	188	.name = "l4_core",
	189	.class = &l4_hwmod_class,
	190	.flags = HWMOD_NO_IDLEST,
	191	};
	192
	193	/* L4 WKUP */
	194	struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
	195	.name = "l4_wkup",
	196	.class = &l4_hwmod_class,
	197	.flags = HWMOD_NO_IDLEST,
	198	};
	199
	200	/* MPU */
	201	struct omap_hwmod omap2xxx_mpu_hwmod = {
	202	.name = "mpu",
	203	.class = &mpu_hwmod_class,
	204	.main_clk = "mpu_ck",
	205	};
	206
	207	/* IVA2 */
	208	struct omap_hwmod omap2xxx_iva_hwmod = {
	209	.name = "iva",
	210	.class = &iva_hwmod_class,
	211	};
	212
	213	/* always-on timers dev attribute */
	214	static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
	215	.timer_capability = OMAP_TIMER_ALWON,
	216	};
	217
	218	/* pwm timers dev attribute */
	219	static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
	220	.timer_capability = OMAP_TIMER_HAS_PWM,
	221	};
	222
	223	/* timer1 */
	224
	225	struct omap_hwmod omap2xxx_timer1_hwmod = {
	226	.name = "timer1",
	227	.mpu_irqs = omap2_timer1_mpu_irqs,
	228	.main_clk = "gpt1_fck",
	229	.prcm = {
	230	.omap2 = {
	231	.prcm_reg_id = 1,
	232	.module_bit = OMAP24XX_EN_GPT1_SHIFT,
	233	.module_offs = WKUP_MOD,
	234	.idlest_reg_id = 1,
	235	.idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
	236	},
	237	},
238	.dev_attr = &capability_alwon_dev_attr,
239	.class = &omap2xxx_timer_hwmod_class,
240	};
241
242	/* timer2 */
243
244	struct omap_hwmod omap2xxx_timer2_hwmod = {
245	.name = "timer2",
246	.mpu_irqs = omap2_timer2_mpu_irqs,
247	.main_clk = "gpt2_fck",
248	.prcm = {
249	.omap2 = {
250	.prcm_reg_id = 1,
251	.module_bit = OMAP24XX_EN_GPT2_SHIFT,
252	.module_offs = CORE_MOD,
253	.idlest_reg_id = 1,
254	.idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
255	},
256	},
cb48427e PW	257	.class = &omap2xxx_timer_hwmod_class,
	258	};
	259
	260	/* timer3 */
	261
	262	struct omap_hwmod omap2xxx_timer3_hwmod = {
	263	.name = "timer3",
	264	.mpu_irqs = omap2_timer3_mpu_irqs,
	265	.main_clk = "gpt3_fck",
	266	.prcm = {
	267	.omap2 = {
	268	.prcm_reg_id = 1,
	269	.module_bit = OMAP24XX_EN_GPT3_SHIFT,
	270	.module_offs = CORE_MOD,
	271	.idlest_reg_id = 1,
	272	.idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
	273	},
	274	},
cb48427e PW	275	.class = &omap2xxx_timer_hwmod_class,
	276	};
	277
	278	/* timer4 */
	279
	280	struct omap_hwmod omap2xxx_timer4_hwmod = {
	281	.name = "timer4",
	282	.mpu_irqs = omap2_timer4_mpu_irqs,
	283	.main_clk = "gpt4_fck",
	284	.prcm = {
	285	.omap2 = {
	286	.prcm_reg_id = 1,
	287	.module_bit = OMAP24XX_EN_GPT4_SHIFT,
	288	.module_offs = CORE_MOD,
	289	.idlest_reg_id = 1,
	290	.idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
	291	},
	292	},
cb48427e PW	293	.class = &omap2xxx_timer_hwmod_class,
	294	};
	295
	296	/* timer5 */
	297
	298	struct omap_hwmod omap2xxx_timer5_hwmod = {
	299	.name = "timer5",
	300	.mpu_irqs = omap2_timer5_mpu_irqs,
	301	.main_clk = "gpt5_fck",
	302	.prcm = {
	303	.omap2 = {
	304	.prcm_reg_id = 1,
	305	.module_bit = OMAP24XX_EN_GPT5_SHIFT,
	306	.module_offs = CORE_MOD,
	307	.idlest_reg_id = 1,
	308	.idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
	309	},
	310	},
cb48427e PW	311	.class = &omap2xxx_timer_hwmod_class,
	312	};
	313
	314	/* timer6 */
	315
	316	struct omap_hwmod omap2xxx_timer6_hwmod = {
	317	.name = "timer6",
	318	.mpu_irqs = omap2_timer6_mpu_irqs,
	319	.main_clk = "gpt6_fck",
	320	.prcm = {
	321	.omap2 = {
	322	.prcm_reg_id = 1,
	323	.module_bit = OMAP24XX_EN_GPT6_SHIFT,
	324	.module_offs = CORE_MOD,
	325	.idlest_reg_id = 1,
	326	.idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
	327	},
	328	},
cb48427e PW	329	.class = &omap2xxx_timer_hwmod_class,
	330	};
	331
	332	/* timer7 */
	333
	334	struct omap_hwmod omap2xxx_timer7_hwmod = {
	335	.name = "timer7",
	336	.mpu_irqs = omap2_timer7_mpu_irqs,
	337	.main_clk = "gpt7_fck",
	338	.prcm = {
	339	.omap2 = {
	340	.prcm_reg_id = 1,
	341	.module_bit = OMAP24XX_EN_GPT7_SHIFT,
	342	.module_offs = CORE_MOD,
	343	.idlest_reg_id = 1,
	344	.idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
	345	},
	346	},
cb48427e PW	347	.class = &omap2xxx_timer_hwmod_class,
	348	};
	349
	350	/* timer8 */
	351
	352	struct omap_hwmod omap2xxx_timer8_hwmod = {
	353	.name = "timer8",
	354	.mpu_irqs = omap2_timer8_mpu_irqs,
	355	.main_clk = "gpt8_fck",
	356	.prcm = {
	357	.omap2 = {
	358	.prcm_reg_id = 1,
	359	.module_bit = OMAP24XX_EN_GPT8_SHIFT,
	360	.module_offs = CORE_MOD,
	361	.idlest_reg_id = 1,
	362	.idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
	363	},
	364	},
cb48427e PW	365	.class = &omap2xxx_timer_hwmod_class,
	366	};
	367
	368	/* timer9 */
	369
	370	struct omap_hwmod omap2xxx_timer9_hwmod = {
	371	.name = "timer9",
	372	.mpu_irqs = omap2_timer9_mpu_irqs,
	373	.main_clk = "gpt9_fck",
	374	.prcm = {
	375	.omap2 = {
	376	.prcm_reg_id = 1,
	377	.module_bit = OMAP24XX_EN_GPT9_SHIFT,
	378	.module_offs = CORE_MOD,
	379	.idlest_reg_id = 1,
	380	.idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
	381	},
	382	},
	383	.dev_attr = &capability_pwm_dev_attr,
	384	.class = &omap2xxx_timer_hwmod_class,
	385	};
	386
	387	/* timer10 */
	388
	389	struct omap_hwmod omap2xxx_timer10_hwmod = {
	390	.name = "timer10",
	391	.mpu_irqs = omap2_timer10_mpu_irqs,
	392	.main_clk = "gpt10_fck",
	393	.prcm = {
	394	.omap2 = {
	395	.prcm_reg_id = 1,
	396	.module_bit = OMAP24XX_EN_GPT10_SHIFT,
	397	.module_offs = CORE_MOD,
	398	.idlest_reg_id = 1,
	399	.idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
	400	},
	401	},
	402	.dev_attr = &capability_pwm_dev_attr,
	403	.class = &omap2xxx_timer_hwmod_class,
	404	};
	405
	406	/* timer11 */
	407
	408	struct omap_hwmod omap2xxx_timer11_hwmod = {
	409	.name = "timer11",
	410	.mpu_irqs = omap2_timer11_mpu_irqs,
	411	.main_clk = "gpt11_fck",
	412	.prcm = {
	413	.omap2 = {
	414	.prcm_reg_id = 1,
	415	.module_bit = OMAP24XX_EN_GPT11_SHIFT,
	416	.module_offs = CORE_MOD,
	417	.idlest_reg_id = 1,
	418	.idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
	419	},
	420	},
	421	.dev_attr = &capability_pwm_dev_attr,
	422	.class = &omap2xxx_timer_hwmod_class,
	423	};
	424
	425	/* timer12 */
	426
	427	struct omap_hwmod omap2xxx_timer12_hwmod = {
	428	.name = "timer12",
429	.mpu_irqs = omap2xxx_timer12_mpu_irqs,
430	.main_clk = "gpt12_fck",
431	.prcm = {
432	.omap2 = {
433	.prcm_reg_id = 1,
434	.module_bit = OMAP24XX_EN_GPT12_SHIFT,
435	.module_offs = CORE_MOD,
436	.idlest_reg_id = 1,
437	.idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
438	},
439	},
440	.dev_attr = &capability_pwm_dev_attr,
441	.class = &omap2xxx_timer_hwmod_class,
442	};
443
444	/* wd_timer2 */
445	struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
446	.name = "wd_timer2",
447	.class = &omap2xxx_wd_timer_hwmod_class,
448	.main_clk = "mpu_wdt_fck",
449	.prcm = {
450	.omap2 = {
451	.prcm_reg_id = 1,
452	.module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
453	.module_offs = WKUP_MOD,
454	.idlest_reg_id = 1,
455	.idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
456	},
457	},
458	};
459
460	/* UART1 */
461
462	struct omap_hwmod omap2xxx_uart1_hwmod = {
463	.name = "uart1",
464	.mpu_irqs = omap2_uart1_mpu_irqs,
465	.sdma_reqs = omap2_uart1_sdma_reqs,
466	.main_clk = "uart1_fck",
467	.prcm = {
468	.omap2 = {
469	.module_offs = CORE_MOD,
470	.prcm_reg_id = 1,
471	.module_bit = OMAP24XX_EN_UART1_SHIFT,
472	.idlest_reg_id = 1,
473	.idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
474	},
475	},
476	.class = &omap2_uart_class,
477	};
478
479	/* UART2 */
480
481	struct omap_hwmod omap2xxx_uart2_hwmod = {
482	.name = "uart2",
483	.mpu_irqs = omap2_uart2_mpu_irqs,
484	.sdma_reqs = omap2_uart2_sdma_reqs,
485	.main_clk = "uart2_fck",
486	.prcm = {
487	.omap2 = {
488	.module_offs = CORE_MOD,
489	.prcm_reg_id = 1,
490	.module_bit = OMAP24XX_EN_UART2_SHIFT,
491	.idlest_reg_id = 1,
492	.idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
493	},
494	},
495	.class = &omap2_uart_class,
496	};
497
498	/* UART3 */
499
500	struct omap_hwmod omap2xxx_uart3_hwmod = {
501	.name = "uart3",
502	.mpu_irqs = omap2_uart3_mpu_irqs,
503	.sdma_reqs = omap2_uart3_sdma_reqs,
504	.main_clk = "uart3_fck",
505	.prcm = {
506	.omap2 = {
507	.module_offs = CORE_MOD,
508	.prcm_reg_id = 2,
509	.module_bit = OMAP24XX_EN_UART3_SHIFT,
510	.idlest_reg_id = 2,
511	.idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
512	},
513	},
514	.class = &omap2_uart_class,
515	};
516
517	/* dss */
518
519	static struct omap_hwmod_opt_clk dss_opt_clks[] = {
520	/*
521	* The DSS HW needs all DSS clocks enabled during reset. The dss_core
522	* driver does not use these clocks.
523	*/
524	{ .role = "tv_clk", .clk = "dss_54m_fck" },
525	{ .role = "sys_clk", .clk = "dss2_fck" },
526	};
527
528	struct omap_hwmod omap2xxx_dss_core_hwmod = {
529	.name = "dss_core",
530	.class = &omap2_dss_hwmod_class,
531	.main_clk = "dss1_fck", /* instead of dss_fck */
532	.sdma_reqs = omap2xxx_dss_sdma_chs,
533	.prcm = {
534	.omap2 = {
535	.prcm_reg_id = 1,
536	.module_bit = OMAP24XX_EN_DSS1_SHIFT,
537	.module_offs = CORE_MOD,
538	.idlest_reg_id = 1,
539	.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
540	},
541	},
542	.opt_clks = dss_opt_clks,
543	.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
544	.flags = HWMOD_NO_IDLEST \| HWMOD_CONTROL_OPT_CLKS_IN_RESET,
545	};
546
547	struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
548	.name = "dss_dispc",
549	.class = &omap2_dispc_hwmod_class,
550	.mpu_irqs = omap2_dispc_irqs,
551	.main_clk = "dss1_fck",
552	.prcm = {
553	.omap2 = {
554	.prcm_reg_id = 1,
555	.module_bit = OMAP24XX_EN_DSS1_SHIFT,
556	.module_offs = CORE_MOD,
557	.idlest_reg_id = 1,
558	.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
559	},
560	},
561	.flags = HWMOD_NO_IDLEST,
562	.dev_attr = &omap2_3_dss_dispc_dev_attr
563	};
564
565	static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
566	{ .role = "ick", .clk = "dss_ick" },
567	};
568
569	struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
570	.name = "dss_rfbi",
571	.class = &omap2_rfbi_hwmod_class,
572	.main_clk = "dss1_fck",
573	.prcm = {
574	.omap2 = {
575	.prcm_reg_id = 1,
576	.module_bit = OMAP24XX_EN_DSS1_SHIFT,
577	.module_offs = CORE_MOD,
578	},
579	},
580	.opt_clks = dss_rfbi_opt_clks,
581	.opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
582	.flags = HWMOD_NO_IDLEST,
583	};
584
585	struct omap_hwmod omap2xxx_dss_venc_hwmod = {
586	.name = "dss_venc",
587	.class = &omap2_venc_hwmod_class,
588	.main_clk = "dss_54m_fck",
589	.prcm = {
590	.omap2 = {
591	.prcm_reg_id = 1,
592	.module_bit = OMAP24XX_EN_DSS1_SHIFT,
593	.module_offs = CORE_MOD,
594	},
595	},
596	.flags = HWMOD_NO_IDLEST,
597	};
598
599	/* gpio dev_attr */
600	struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
601	.bank_width = 32,
602	.dbck_flag = false,
603	};
604
605	/* gpio1 */
606	struct omap_hwmod omap2xxx_gpio1_hwmod = {
607	.name = "gpio1",
608	.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
609	.mpu_irqs = omap2_gpio1_irqs,
610	.main_clk = "gpios_fck",
611	.prcm = {
612	.omap2 = {
613	.prcm_reg_id = 1,
614	.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
615	.module_offs = WKUP_MOD,
616	.idlest_reg_id = 1,
617	.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
618	},
619	},
620	.class = &omap2xxx_gpio_hwmod_class,
621	.dev_attr = &omap2xxx_gpio_dev_attr,
622	};
623
624	/* gpio2 */
625	struct omap_hwmod omap2xxx_gpio2_hwmod = {
626	.name = "gpio2",
627	.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
628	.mpu_irqs = omap2_gpio2_irqs,
629	.main_clk = "gpios_fck",
630	.prcm = {
631	.omap2 = {
632	.prcm_reg_id = 1,
633	.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
634	.module_offs = WKUP_MOD,
635	.idlest_reg_id = 1,
636	.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
637	},
638	},
639	.class = &omap2xxx_gpio_hwmod_class,
640	.dev_attr = &omap2xxx_gpio_dev_attr,
641	};
642
643	/* gpio3 */
644	struct omap_hwmod omap2xxx_gpio3_hwmod = {
645	.name = "gpio3",
646	.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
647	.mpu_irqs = omap2_gpio3_irqs,
648	.main_clk = "gpios_fck",
649	.prcm = {
650	.omap2 = {
651	.prcm_reg_id = 1,
652	.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
653	.module_offs = WKUP_MOD,
654	.idlest_reg_id = 1,
655	.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
656	},
657	},
658	.class = &omap2xxx_gpio_hwmod_class,
659	.dev_attr = &omap2xxx_gpio_dev_attr,
660	};
661
662	/* gpio4 */
663	struct omap_hwmod omap2xxx_gpio4_hwmod = {
664	.name = "gpio4",
665	.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
666	.mpu_irqs = omap2_gpio4_irqs,
667	.main_clk = "gpios_fck",
668	.prcm = {
669	.omap2 = {
670	.prcm_reg_id = 1,
671	.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
672	.module_offs = WKUP_MOD,
673	.idlest_reg_id = 1,
674	.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
675	},
676	},
677	.class = &omap2xxx_gpio_hwmod_class,
678	.dev_attr = &omap2xxx_gpio_dev_attr,
679	};
680
681	/* mcspi1 */
682	static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
683	.num_chipselect = 4,
684	};
685
686	struct omap_hwmod omap2xxx_mcspi1_hwmod = {
687	.name = "mcspi1",
688	.mpu_irqs = omap2_mcspi1_mpu_irqs,
689	.sdma_reqs = omap2_mcspi1_sdma_reqs,
690	.main_clk = "mcspi1_fck",
691	.prcm = {
692	.omap2 = {
693	.module_offs = CORE_MOD,
694	.prcm_reg_id = 1,
695	.module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
696	.idlest_reg_id = 1,
697	.idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
698	},
699	},
700	.class = &omap2xxx_mcspi_class,
701	.dev_attr = &omap_mcspi1_dev_attr,
702	};
703
704	/* mcspi2 */
705	static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
706	.num_chipselect = 2,
707	};
708
709	struct omap_hwmod omap2xxx_mcspi2_hwmod = {
710	.name = "mcspi2",
711	.mpu_irqs = omap2_mcspi2_mpu_irqs,
712	.sdma_reqs = omap2_mcspi2_sdma_reqs,
713	.main_clk = "mcspi2_fck",
714	.prcm = {
715	.omap2 = {
716	.module_offs = CORE_MOD,
717	.prcm_reg_id = 1,
718	.module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
719	.idlest_reg_id = 1,
720	.idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
721	},
722	},
723	.class = &omap2xxx_mcspi_class,
724	.dev_attr = &omap_mcspi2_dev_attr,
725	};
c8d82ff6 VH	726
	727
	728	static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
	729	.name = "counter",
	730	};
	731
	732	struct omap_hwmod omap2xxx_counter_32k_hwmod = {
	733	.name = "counter_32k",
	734	.main_clk = "func_32k_ck",
	735	.prcm = {
	736	.omap2 = {
	737	.module_offs = WKUP_MOD,
	738	.prcm_reg_id = 1,
	739	.module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
	740	.idlest_reg_id = 1,
	741	.idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
	742	},
	743	},
	744	.class = &omap2xxx_counter_hwmod_class,
	745	};