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7359154e PW |
1 | /* |
2 | * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips | |
3 | * | |
78183f3f | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
7359154e PW |
5 | * Paul Walmsley |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * The data in this file should be completely autogeneratable from | |
12 | * the TI hardware database or other technical documentation. | |
13 | * | |
14 | * XXX these should be marked initdata for multi-OMAP kernels | |
15 | */ | |
16 | #include <plat/omap_hwmod.h> | |
17 | #include <mach/irqs.h> | |
18 | #include <plat/cpu.h> | |
19 | #include <plat/dma.h> | |
046465b7 | 20 | #include <plat/serial.h> |
e04d9e1e | 21 | #include <plat/l3_3xxx.h> |
4fe20e97 RN |
22 | #include <plat/l4_3xxx.h> |
23 | #include <plat/i2c.h> | |
70034d38 | 24 | #include <plat/gpio.h> |
6ab8946f | 25 | #include <plat/mmc.h> |
dc48e5fc | 26 | #include <plat/mcbsp.h> |
0f616a4e | 27 | #include <plat/mcspi.h> |
ce722d26 | 28 | #include <plat/dmtimer.h> |
7359154e | 29 | |
43b40992 PW |
30 | #include "omap_hwmod_common_data.h" |
31 | ||
7359154e | 32 | #include "prm-regbits-34xx.h" |
6b667f88 | 33 | #include "cm-regbits-34xx.h" |
ff2516fb | 34 | #include "wd_timer.h" |
273ff8c3 | 35 | #include <mach/am35xx.h> |
7359154e PW |
36 | |
37 | /* | |
38 | * OMAP3xxx hardware module integration data | |
39 | * | |
40 | * ALl of the data in this section should be autogeneratable from the | |
41 | * TI hardware database or other technical documentation. Data that | |
42 | * is driver-specific or driver-kernel integration-specific belongs | |
43 | * elsewhere. | |
44 | */ | |
45 | ||
46 | static struct omap_hwmod omap3xxx_mpu_hwmod; | |
540064bf | 47 | static struct omap_hwmod omap3xxx_iva_hwmod; |
4a7cf90a | 48 | static struct omap_hwmod omap3xxx_l3_main_hwmod; |
7359154e PW |
49 | static struct omap_hwmod omap3xxx_l4_core_hwmod; |
50 | static struct omap_hwmod omap3xxx_l4_per_hwmod; | |
6b667f88 | 51 | static struct omap_hwmod omap3xxx_wd_timer2_hwmod; |
e04d9e1e SG |
52 | static struct omap_hwmod omap3430es1_dss_core_hwmod; |
53 | static struct omap_hwmod omap3xxx_dss_core_hwmod; | |
54 | static struct omap_hwmod omap3xxx_dss_dispc_hwmod; | |
55 | static struct omap_hwmod omap3xxx_dss_dsi1_hwmod; | |
56 | static struct omap_hwmod omap3xxx_dss_rfbi_hwmod; | |
57 | static struct omap_hwmod omap3xxx_dss_venc_hwmod; | |
4fe20e97 RN |
58 | static struct omap_hwmod omap3xxx_i2c1_hwmod; |
59 | static struct omap_hwmod omap3xxx_i2c2_hwmod; | |
60 | static struct omap_hwmod omap3xxx_i2c3_hwmod; | |
70034d38 VC |
61 | static struct omap_hwmod omap3xxx_gpio1_hwmod; |
62 | static struct omap_hwmod omap3xxx_gpio2_hwmod; | |
63 | static struct omap_hwmod omap3xxx_gpio3_hwmod; | |
64 | static struct omap_hwmod omap3xxx_gpio4_hwmod; | |
65 | static struct omap_hwmod omap3xxx_gpio5_hwmod; | |
66 | static struct omap_hwmod omap3xxx_gpio6_hwmod; | |
d3442726 TG |
67 | static struct omap_hwmod omap34xx_sr1_hwmod; |
68 | static struct omap_hwmod omap34xx_sr2_hwmod; | |
0f616a4e C |
69 | static struct omap_hwmod omap34xx_mcspi1; |
70 | static struct omap_hwmod omap34xx_mcspi2; | |
71 | static struct omap_hwmod omap34xx_mcspi3; | |
72 | static struct omap_hwmod omap34xx_mcspi4; | |
b163605e PW |
73 | static struct omap_hwmod omap3xxx_mmc1_hwmod; |
74 | static struct omap_hwmod omap3xxx_mmc2_hwmod; | |
75 | static struct omap_hwmod omap3xxx_mmc3_hwmod; | |
273ff8c3 | 76 | static struct omap_hwmod am35xx_usbhsotg_hwmod; |
7359154e | 77 | |
01438ab6 MK |
78 | static struct omap_hwmod omap3xxx_dma_system_hwmod; |
79 | ||
dc48e5fc C |
80 | static struct omap_hwmod omap3xxx_mcbsp1_hwmod; |
81 | static struct omap_hwmod omap3xxx_mcbsp2_hwmod; | |
82 | static struct omap_hwmod omap3xxx_mcbsp3_hwmod; | |
83 | static struct omap_hwmod omap3xxx_mcbsp4_hwmod; | |
84 | static struct omap_hwmod omap3xxx_mcbsp5_hwmod; | |
85 | static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod; | |
86 | static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod; | |
de231388 KM |
87 | static struct omap_hwmod omap3xxx_usb_host_hs_hwmod; |
88 | static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod; | |
dc48e5fc | 89 | |
7359154e | 90 | /* L3 -> L4_CORE interface */ |
4a7cf90a KH |
91 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { |
92 | .master = &omap3xxx_l3_main_hwmod, | |
7359154e PW |
93 | .slave = &omap3xxx_l4_core_hwmod, |
94 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
95 | }; | |
96 | ||
97 | /* L3 -> L4_PER interface */ | |
4a7cf90a KH |
98 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { |
99 | .master = &omap3xxx_l3_main_hwmod, | |
7359154e PW |
100 | .slave = &omap3xxx_l4_per_hwmod, |
101 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
102 | }; | |
103 | ||
4bb194dc | 104 | /* L3 taret configuration and error log registers */ |
105 | static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { | |
106 | { .irq = INT_34XX_L3_DBG_IRQ }, | |
107 | { .irq = INT_34XX_L3_APP_IRQ }, | |
212738a4 | 108 | { .irq = -1 } |
4bb194dc | 109 | }; |
110 | ||
111 | static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { | |
112 | { | |
113 | .pa_start = 0x68000000, | |
114 | .pa_end = 0x6800ffff, | |
115 | .flags = ADDR_TYPE_RT, | |
116 | }, | |
78183f3f | 117 | { } |
4bb194dc | 118 | }; |
119 | ||
7359154e | 120 | /* MPU -> L3 interface */ |
4a7cf90a | 121 | static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { |
4bb194dc | 122 | .master = &omap3xxx_mpu_hwmod, |
123 | .slave = &omap3xxx_l3_main_hwmod, | |
124 | .addr = omap3xxx_l3_main_addrs, | |
7359154e PW |
125 | .user = OCP_USER_MPU, |
126 | }; | |
127 | ||
128 | /* Slave interfaces on the L3 interconnect */ | |
4a7cf90a KH |
129 | static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = { |
130 | &omap3xxx_mpu__l3_main, | |
7359154e PW |
131 | }; |
132 | ||
e04d9e1e SG |
133 | /* DSS -> l3 */ |
134 | static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { | |
135 | .master = &omap3xxx_dss_core_hwmod, | |
136 | .slave = &omap3xxx_l3_main_hwmod, | |
137 | .fw = { | |
138 | .omap2 = { | |
139 | .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, | |
140 | .flags = OMAP_FIREWALL_L3, | |
141 | } | |
142 | }, | |
143 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
144 | }; | |
145 | ||
7359154e | 146 | /* Master interfaces on the L3 interconnect */ |
4a7cf90a KH |
147 | static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = { |
148 | &omap3xxx_l3_main__l4_core, | |
149 | &omap3xxx_l3_main__l4_per, | |
7359154e PW |
150 | }; |
151 | ||
152 | /* L3 */ | |
4a7cf90a | 153 | static struct omap_hwmod omap3xxx_l3_main_hwmod = { |
fa98347e | 154 | .name = "l3_main", |
43b40992 | 155 | .class = &l3_hwmod_class, |
0d619a89 | 156 | .mpu_irqs = omap3xxx_l3_main_irqs, |
4a7cf90a KH |
157 | .masters = omap3xxx_l3_main_masters, |
158 | .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), | |
159 | .slaves = omap3xxx_l3_main_slaves, | |
160 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves), | |
2eb1875d | 161 | .flags = HWMOD_NO_IDLEST, |
7359154e PW |
162 | }; |
163 | ||
164 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod; | |
046465b7 KH |
165 | static struct omap_hwmod omap3xxx_uart1_hwmod; |
166 | static struct omap_hwmod omap3xxx_uart2_hwmod; | |
167 | static struct omap_hwmod omap3xxx_uart3_hwmod; | |
168 | static struct omap_hwmod omap3xxx_uart4_hwmod; | |
4bf90f65 | 169 | static struct omap_hwmod am35xx_uart4_hwmod; |
870ea2b8 | 170 | static struct omap_hwmod omap3xxx_usbhsotg_hwmod; |
7359154e | 171 | |
870ea2b8 HH |
172 | /* l3_core -> usbhsotg interface */ |
173 | static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { | |
174 | .master = &omap3xxx_usbhsotg_hwmod, | |
175 | .slave = &omap3xxx_l3_main_hwmod, | |
176 | .clk = "core_l3_ick", | |
177 | .user = OCP_USER_MPU, | |
178 | }; | |
7359154e | 179 | |
273ff8c3 HH |
180 | /* l3_core -> am35xx_usbhsotg interface */ |
181 | static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { | |
182 | .master = &am35xx_usbhsotg_hwmod, | |
183 | .slave = &omap3xxx_l3_main_hwmod, | |
184 | .clk = "core_l3_ick", | |
185 | .user = OCP_USER_MPU, | |
186 | }; | |
7359154e PW |
187 | /* L4_CORE -> L4_WKUP interface */ |
188 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { | |
189 | .master = &omap3xxx_l4_core_hwmod, | |
190 | .slave = &omap3xxx_l4_wkup_hwmod, | |
191 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
192 | }; | |
193 | ||
b163605e | 194 | /* L4 CORE -> MMC1 interface */ |
b163605e PW |
195 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = { |
196 | .master = &omap3xxx_l4_core_hwmod, | |
197 | .slave = &omap3xxx_mmc1_hwmod, | |
198 | .clk = "mmchs1_ick", | |
ded11383 | 199 | .addr = omap2430_mmc1_addr_space, |
b163605e PW |
200 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
201 | .flags = OMAP_FIREWALL_L4 | |
202 | }; | |
203 | ||
204 | /* L4 CORE -> MMC2 interface */ | |
b163605e PW |
205 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = { |
206 | .master = &omap3xxx_l4_core_hwmod, | |
207 | .slave = &omap3xxx_mmc2_hwmod, | |
208 | .clk = "mmchs2_ick", | |
ded11383 | 209 | .addr = omap2430_mmc2_addr_space, |
b163605e PW |
210 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
211 | .flags = OMAP_FIREWALL_L4 | |
212 | }; | |
213 | ||
214 | /* L4 CORE -> MMC3 interface */ | |
215 | static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { | |
216 | { | |
217 | .pa_start = 0x480ad000, | |
218 | .pa_end = 0x480ad1ff, | |
219 | .flags = ADDR_TYPE_RT, | |
220 | }, | |
78183f3f | 221 | { } |
b163605e PW |
222 | }; |
223 | ||
224 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { | |
225 | .master = &omap3xxx_l4_core_hwmod, | |
226 | .slave = &omap3xxx_mmc3_hwmod, | |
227 | .clk = "mmchs3_ick", | |
228 | .addr = omap3xxx_mmc3_addr_space, | |
b163605e PW |
229 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
230 | .flags = OMAP_FIREWALL_L4 | |
231 | }; | |
232 | ||
046465b7 KH |
233 | /* L4 CORE -> UART1 interface */ |
234 | static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { | |
235 | { | |
236 | .pa_start = OMAP3_UART1_BASE, | |
237 | .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, | |
238 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
239 | }, | |
78183f3f | 240 | { } |
046465b7 KH |
241 | }; |
242 | ||
243 | static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { | |
244 | .master = &omap3xxx_l4_core_hwmod, | |
245 | .slave = &omap3xxx_uart1_hwmod, | |
246 | .clk = "uart1_ick", | |
247 | .addr = omap3xxx_uart1_addr_space, | |
046465b7 KH |
248 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
249 | }; | |
250 | ||
251 | /* L4 CORE -> UART2 interface */ | |
252 | static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { | |
253 | { | |
254 | .pa_start = OMAP3_UART2_BASE, | |
255 | .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, | |
256 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
257 | }, | |
78183f3f | 258 | { } |
046465b7 KH |
259 | }; |
260 | ||
261 | static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { | |
262 | .master = &omap3xxx_l4_core_hwmod, | |
263 | .slave = &omap3xxx_uart2_hwmod, | |
264 | .clk = "uart2_ick", | |
265 | .addr = omap3xxx_uart2_addr_space, | |
046465b7 KH |
266 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
267 | }; | |
268 | ||
269 | /* L4 PER -> UART3 interface */ | |
270 | static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { | |
271 | { | |
272 | .pa_start = OMAP3_UART3_BASE, | |
273 | .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, | |
274 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
275 | }, | |
78183f3f | 276 | { } |
046465b7 KH |
277 | }; |
278 | ||
279 | static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { | |
280 | .master = &omap3xxx_l4_per_hwmod, | |
281 | .slave = &omap3xxx_uart3_hwmod, | |
282 | .clk = "uart3_ick", | |
283 | .addr = omap3xxx_uart3_addr_space, | |
046465b7 KH |
284 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
285 | }; | |
286 | ||
287 | /* L4 PER -> UART4 interface */ | |
288 | static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = { | |
289 | { | |
290 | .pa_start = OMAP3_UART4_BASE, | |
291 | .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, | |
292 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
293 | }, | |
78183f3f | 294 | { } |
046465b7 KH |
295 | }; |
296 | ||
297 | static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { | |
298 | .master = &omap3xxx_l4_per_hwmod, | |
299 | .slave = &omap3xxx_uart4_hwmod, | |
300 | .clk = "uart4_ick", | |
301 | .addr = omap3xxx_uart4_addr_space, | |
046465b7 KH |
302 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
303 | }; | |
304 | ||
4bf90f65 KM |
305 | /* AM35xx: L4 CORE -> UART4 interface */ |
306 | static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { | |
307 | { | |
308 | .pa_start = OMAP3_UART4_AM35XX_BASE, | |
309 | .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, | |
310 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
311 | }, | |
312 | }; | |
313 | ||
314 | static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { | |
315 | .master = &omap3xxx_l4_core_hwmod, | |
316 | .slave = &am35xx_uart4_hwmod, | |
317 | .clk = "uart4_ick", | |
318 | .addr = am35xx_uart4_addr_space, | |
319 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
320 | }; | |
321 | ||
4fe20e97 | 322 | /* L4 CORE -> I2C1 interface */ |
4fe20e97 RN |
323 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { |
324 | .master = &omap3xxx_l4_core_hwmod, | |
325 | .slave = &omap3xxx_i2c1_hwmod, | |
326 | .clk = "i2c1_ick", | |
ded11383 | 327 | .addr = omap2_i2c1_addr_space, |
4fe20e97 RN |
328 | .fw = { |
329 | .omap2 = { | |
330 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, | |
331 | .l4_prot_group = 7, | |
332 | .flags = OMAP_FIREWALL_L4, | |
333 | } | |
334 | }, | |
335 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
336 | }; | |
337 | ||
338 | /* L4 CORE -> I2C2 interface */ | |
4fe20e97 RN |
339 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { |
340 | .master = &omap3xxx_l4_core_hwmod, | |
341 | .slave = &omap3xxx_i2c2_hwmod, | |
342 | .clk = "i2c2_ick", | |
ded11383 | 343 | .addr = omap2_i2c2_addr_space, |
4fe20e97 RN |
344 | .fw = { |
345 | .omap2 = { | |
346 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, | |
347 | .l4_prot_group = 7, | |
348 | .flags = OMAP_FIREWALL_L4, | |
349 | } | |
350 | }, | |
351 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
352 | }; | |
353 | ||
354 | /* L4 CORE -> I2C3 interface */ | |
355 | static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { | |
356 | { | |
357 | .pa_start = 0x48060000, | |
ded11383 | 358 | .pa_end = 0x48060000 + SZ_128 - 1, |
4fe20e97 RN |
359 | .flags = ADDR_TYPE_RT, |
360 | }, | |
78183f3f | 361 | { } |
4fe20e97 RN |
362 | }; |
363 | ||
364 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { | |
365 | .master = &omap3xxx_l4_core_hwmod, | |
366 | .slave = &omap3xxx_i2c3_hwmod, | |
367 | .clk = "i2c3_ick", | |
368 | .addr = omap3xxx_i2c3_addr_space, | |
4fe20e97 RN |
369 | .fw = { |
370 | .omap2 = { | |
371 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, | |
372 | .l4_prot_group = 7, | |
373 | .flags = OMAP_FIREWALL_L4, | |
374 | } | |
375 | }, | |
376 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
377 | }; | |
378 | ||
d3442726 TG |
379 | /* L4 CORE -> SR1 interface */ |
380 | static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { | |
381 | { | |
382 | .pa_start = OMAP34XX_SR1_BASE, | |
383 | .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, | |
384 | .flags = ADDR_TYPE_RT, | |
385 | }, | |
78183f3f | 386 | { } |
d3442726 TG |
387 | }; |
388 | ||
389 | static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = { | |
390 | .master = &omap3xxx_l4_core_hwmod, | |
391 | .slave = &omap34xx_sr1_hwmod, | |
392 | .clk = "sr_l4_ick", | |
393 | .addr = omap3_sr1_addr_space, | |
d3442726 TG |
394 | .user = OCP_USER_MPU, |
395 | }; | |
396 | ||
397 | /* L4 CORE -> SR1 interface */ | |
398 | static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { | |
399 | { | |
400 | .pa_start = OMAP34XX_SR2_BASE, | |
401 | .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, | |
402 | .flags = ADDR_TYPE_RT, | |
403 | }, | |
78183f3f | 404 | { } |
d3442726 TG |
405 | }; |
406 | ||
407 | static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = { | |
408 | .master = &omap3xxx_l4_core_hwmod, | |
409 | .slave = &omap34xx_sr2_hwmod, | |
410 | .clk = "sr_l4_ick", | |
411 | .addr = omap3_sr2_addr_space, | |
d3442726 TG |
412 | .user = OCP_USER_MPU, |
413 | }; | |
414 | ||
870ea2b8 HH |
415 | /* |
416 | * usbhsotg interface data | |
417 | */ | |
418 | ||
419 | static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { | |
420 | { | |
421 | .pa_start = OMAP34XX_HSUSB_OTG_BASE, | |
422 | .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, | |
423 | .flags = ADDR_TYPE_RT | |
424 | }, | |
78183f3f | 425 | { } |
870ea2b8 HH |
426 | }; |
427 | ||
428 | /* l4_core -> usbhsotg */ | |
429 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { | |
430 | .master = &omap3xxx_l4_core_hwmod, | |
431 | .slave = &omap3xxx_usbhsotg_hwmod, | |
432 | .clk = "l4_ick", | |
433 | .addr = omap3xxx_usbhsotg_addrs, | |
870ea2b8 HH |
434 | .user = OCP_USER_MPU, |
435 | }; | |
436 | ||
437 | static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = { | |
438 | &omap3xxx_usbhsotg__l3, | |
439 | }; | |
440 | ||
441 | static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = { | |
442 | &omap3xxx_l4_core__usbhsotg, | |
443 | }; | |
444 | ||
273ff8c3 HH |
445 | static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { |
446 | { | |
447 | .pa_start = AM35XX_IPSS_USBOTGSS_BASE, | |
448 | .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, | |
449 | .flags = ADDR_TYPE_RT | |
450 | }, | |
78183f3f | 451 | { } |
273ff8c3 HH |
452 | }; |
453 | ||
454 | /* l4_core -> usbhsotg */ | |
455 | static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { | |
456 | .master = &omap3xxx_l4_core_hwmod, | |
457 | .slave = &am35xx_usbhsotg_hwmod, | |
458 | .clk = "l4_ick", | |
459 | .addr = am35xx_usbhsotg_addrs, | |
273ff8c3 HH |
460 | .user = OCP_USER_MPU, |
461 | }; | |
462 | ||
463 | static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = { | |
464 | &am35xx_usbhsotg__l3, | |
465 | }; | |
466 | ||
467 | static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = { | |
468 | &am35xx_l4_core__usbhsotg, | |
469 | }; | |
7359154e PW |
470 | /* Slave interfaces on the L4_CORE interconnect */ |
471 | static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { | |
4a7cf90a | 472 | &omap3xxx_l3_main__l4_core, |
7359154e PW |
473 | }; |
474 | ||
475 | /* L4 CORE */ | |
476 | static struct omap_hwmod omap3xxx_l4_core_hwmod = { | |
fa98347e | 477 | .name = "l4_core", |
43b40992 | 478 | .class = &l4_hwmod_class, |
7359154e PW |
479 | .slaves = omap3xxx_l4_core_slaves, |
480 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves), | |
2eb1875d | 481 | .flags = HWMOD_NO_IDLEST, |
7359154e PW |
482 | }; |
483 | ||
484 | /* Slave interfaces on the L4_PER interconnect */ | |
485 | static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = { | |
4a7cf90a | 486 | &omap3xxx_l3_main__l4_per, |
7359154e PW |
487 | }; |
488 | ||
7359154e PW |
489 | /* L4 PER */ |
490 | static struct omap_hwmod omap3xxx_l4_per_hwmod = { | |
fa98347e | 491 | .name = "l4_per", |
43b40992 | 492 | .class = &l4_hwmod_class, |
7359154e PW |
493 | .slaves = omap3xxx_l4_per_slaves, |
494 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves), | |
2eb1875d | 495 | .flags = HWMOD_NO_IDLEST, |
7359154e PW |
496 | }; |
497 | ||
498 | /* Slave interfaces on the L4_WKUP interconnect */ | |
499 | static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = { | |
500 | &omap3xxx_l4_core__l4_wkup, | |
501 | }; | |
502 | ||
7359154e PW |
503 | /* L4 WKUP */ |
504 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { | |
fa98347e | 505 | .name = "l4_wkup", |
43b40992 | 506 | .class = &l4_hwmod_class, |
7359154e PW |
507 | .slaves = omap3xxx_l4_wkup_slaves, |
508 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves), | |
2eb1875d | 509 | .flags = HWMOD_NO_IDLEST, |
7359154e PW |
510 | }; |
511 | ||
512 | /* Master interfaces on the MPU device */ | |
513 | static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = { | |
4a7cf90a | 514 | &omap3xxx_mpu__l3_main, |
7359154e PW |
515 | }; |
516 | ||
517 | /* MPU */ | |
518 | static struct omap_hwmod omap3xxx_mpu_hwmod = { | |
5c2c0296 | 519 | .name = "mpu", |
43b40992 | 520 | .class = &mpu_hwmod_class, |
7359154e PW |
521 | .main_clk = "arm_fck", |
522 | .masters = omap3xxx_mpu_masters, | |
523 | .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters), | |
7359154e PW |
524 | }; |
525 | ||
540064bf KH |
526 | /* |
527 | * IVA2_2 interface data | |
528 | */ | |
529 | ||
530 | /* IVA2 <- L3 interface */ | |
531 | static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { | |
532 | .master = &omap3xxx_l3_main_hwmod, | |
533 | .slave = &omap3xxx_iva_hwmod, | |
534 | .clk = "iva2_ck", | |
535 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
536 | }; | |
537 | ||
538 | static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = { | |
539 | &omap3xxx_l3__iva, | |
540 | }; | |
541 | ||
542 | /* | |
543 | * IVA2 (IVA2) | |
544 | */ | |
545 | ||
546 | static struct omap_hwmod omap3xxx_iva_hwmod = { | |
547 | .name = "iva", | |
548 | .class = &iva_hwmod_class, | |
549 | .masters = omap3xxx_iva_masters, | |
550 | .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters), | |
540064bf KH |
551 | }; |
552 | ||
ce722d26 TG |
553 | /* timer class */ |
554 | static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { | |
555 | .rev_offs = 0x0000, | |
556 | .sysc_offs = 0x0010, | |
557 | .syss_offs = 0x0014, | |
558 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
559 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
560 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), | |
561 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
562 | .sysc_fields = &omap_hwmod_sysc_type1, | |
6b667f88 VC |
563 | }; |
564 | ||
ce722d26 TG |
565 | static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { |
566 | .name = "timer", | |
567 | .sysc = &omap3xxx_timer_1ms_sysc, | |
568 | .rev = OMAP_TIMER_IP_VERSION_1, | |
6b667f88 VC |
569 | }; |
570 | ||
ce722d26 | 571 | static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { |
6b667f88 VC |
572 | .rev_offs = 0x0000, |
573 | .sysc_offs = 0x0010, | |
574 | .syss_offs = 0x0014, | |
ce722d26 TG |
575 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | |
576 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
6b667f88 | 577 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
ce722d26 | 578 | .sysc_fields = &omap_hwmod_sysc_type1, |
6b667f88 VC |
579 | }; |
580 | ||
ce722d26 TG |
581 | static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { |
582 | .name = "timer", | |
583 | .sysc = &omap3xxx_timer_sysc, | |
584 | .rev = OMAP_TIMER_IP_VERSION_1, | |
4fe20e97 RN |
585 | }; |
586 | ||
c345c8b0 TKD |
587 | /* secure timers dev attribute */ |
588 | static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { | |
589 | .timer_capability = OMAP_TIMER_SECURE, | |
590 | }; | |
591 | ||
592 | /* always-on timers dev attribute */ | |
593 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
594 | .timer_capability = OMAP_TIMER_ALWON, | |
595 | }; | |
596 | ||
597 | /* pwm timers dev attribute */ | |
598 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
599 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
600 | }; | |
601 | ||
ce722d26 TG |
602 | /* timer1 */ |
603 | static struct omap_hwmod omap3xxx_timer1_hwmod; | |
6b667f88 | 604 | |
ce722d26 TG |
605 | static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { |
606 | { | |
607 | .pa_start = 0x48318000, | |
608 | .pa_end = 0x48318000 + SZ_1K - 1, | |
609 | .flags = ADDR_TYPE_RT | |
610 | }, | |
78183f3f | 611 | { } |
6b667f88 VC |
612 | }; |
613 | ||
ce722d26 TG |
614 | /* l4_wkup -> timer1 */ |
615 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { | |
616 | .master = &omap3xxx_l4_wkup_hwmod, | |
617 | .slave = &omap3xxx_timer1_hwmod, | |
618 | .clk = "gpt1_ick", | |
619 | .addr = omap3xxx_timer1_addrs, | |
ce722d26 TG |
620 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
621 | }; | |
622 | ||
623 | /* timer1 slave port */ | |
624 | static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = { | |
625 | &omap3xxx_l4_wkup__timer1, | |
626 | }; | |
627 | ||
628 | /* timer1 hwmod */ | |
629 | static struct omap_hwmod omap3xxx_timer1_hwmod = { | |
630 | .name = "timer1", | |
0d619a89 | 631 | .mpu_irqs = omap2_timer1_mpu_irqs, |
ce722d26 | 632 | .main_clk = "gpt1_fck", |
6b667f88 VC |
633 | .prcm = { |
634 | .omap2 = { | |
635 | .prcm_reg_id = 1, | |
ce722d26 | 636 | .module_bit = OMAP3430_EN_GPT1_SHIFT, |
6b667f88 VC |
637 | .module_offs = WKUP_MOD, |
638 | .idlest_reg_id = 1, | |
ce722d26 | 639 | .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, |
6b667f88 VC |
640 | }, |
641 | }, | |
c345c8b0 | 642 | .dev_attr = &capability_alwon_dev_attr, |
ce722d26 TG |
643 | .slaves = omap3xxx_timer1_slaves, |
644 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves), | |
645 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
046465b7 KH |
646 | }; |
647 | ||
ce722d26 TG |
648 | /* timer2 */ |
649 | static struct omap_hwmod omap3xxx_timer2_hwmod; | |
046465b7 | 650 | |
ce722d26 TG |
651 | static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { |
652 | { | |
653 | .pa_start = 0x49032000, | |
654 | .pa_end = 0x49032000 + SZ_1K - 1, | |
655 | .flags = ADDR_TYPE_RT | |
656 | }, | |
78183f3f | 657 | { } |
046465b7 KH |
658 | }; |
659 | ||
ce722d26 TG |
660 | /* l4_per -> timer2 */ |
661 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { | |
662 | .master = &omap3xxx_l4_per_hwmod, | |
663 | .slave = &omap3xxx_timer2_hwmod, | |
664 | .clk = "gpt2_ick", | |
665 | .addr = omap3xxx_timer2_addrs, | |
ce722d26 | 666 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
046465b7 KH |
667 | }; |
668 | ||
ce722d26 TG |
669 | /* timer2 slave port */ |
670 | static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = { | |
671 | &omap3xxx_l4_per__timer2, | |
046465b7 KH |
672 | }; |
673 | ||
ce722d26 TG |
674 | /* timer2 hwmod */ |
675 | static struct omap_hwmod omap3xxx_timer2_hwmod = { | |
676 | .name = "timer2", | |
0d619a89 | 677 | .mpu_irqs = omap2_timer2_mpu_irqs, |
ce722d26 | 678 | .main_clk = "gpt2_fck", |
046465b7 KH |
679 | .prcm = { |
680 | .omap2 = { | |
046465b7 | 681 | .prcm_reg_id = 1, |
ce722d26 TG |
682 | .module_bit = OMAP3430_EN_GPT2_SHIFT, |
683 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 684 | .idlest_reg_id = 1, |
ce722d26 | 685 | .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, |
046465b7 KH |
686 | }, |
687 | }, | |
c345c8b0 | 688 | .dev_attr = &capability_alwon_dev_attr, |
ce722d26 TG |
689 | .slaves = omap3xxx_timer2_slaves, |
690 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves), | |
691 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
046465b7 KH |
692 | }; |
693 | ||
ce722d26 TG |
694 | /* timer3 */ |
695 | static struct omap_hwmod omap3xxx_timer3_hwmod; | |
046465b7 | 696 | |
ce722d26 TG |
697 | static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { |
698 | { | |
699 | .pa_start = 0x49034000, | |
700 | .pa_end = 0x49034000 + SZ_1K - 1, | |
701 | .flags = ADDR_TYPE_RT | |
702 | }, | |
78183f3f | 703 | { } |
046465b7 KH |
704 | }; |
705 | ||
ce722d26 TG |
706 | /* l4_per -> timer3 */ |
707 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { | |
708 | .master = &omap3xxx_l4_per_hwmod, | |
709 | .slave = &omap3xxx_timer3_hwmod, | |
710 | .clk = "gpt3_ick", | |
711 | .addr = omap3xxx_timer3_addrs, | |
ce722d26 | 712 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
046465b7 KH |
713 | }; |
714 | ||
ce722d26 TG |
715 | /* timer3 slave port */ |
716 | static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = { | |
717 | &omap3xxx_l4_per__timer3, | |
046465b7 KH |
718 | }; |
719 | ||
ce722d26 TG |
720 | /* timer3 hwmod */ |
721 | static struct omap_hwmod omap3xxx_timer3_hwmod = { | |
722 | .name = "timer3", | |
0d619a89 | 723 | .mpu_irqs = omap2_timer3_mpu_irqs, |
ce722d26 | 724 | .main_clk = "gpt3_fck", |
046465b7 KH |
725 | .prcm = { |
726 | .omap2 = { | |
046465b7 | 727 | .prcm_reg_id = 1, |
ce722d26 TG |
728 | .module_bit = OMAP3430_EN_GPT3_SHIFT, |
729 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 730 | .idlest_reg_id = 1, |
ce722d26 | 731 | .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, |
046465b7 KH |
732 | }, |
733 | }, | |
c345c8b0 | 734 | .dev_attr = &capability_alwon_dev_attr, |
ce722d26 TG |
735 | .slaves = omap3xxx_timer3_slaves, |
736 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves), | |
737 | .class = &omap3xxx_timer_hwmod_class, | |
046465b7 KH |
738 | }; |
739 | ||
ce722d26 TG |
740 | /* timer4 */ |
741 | static struct omap_hwmod omap3xxx_timer4_hwmod; | |
046465b7 | 742 | |
ce722d26 TG |
743 | static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { |
744 | { | |
745 | .pa_start = 0x49036000, | |
746 | .pa_end = 0x49036000 + SZ_1K - 1, | |
747 | .flags = ADDR_TYPE_RT | |
748 | }, | |
78183f3f | 749 | { } |
046465b7 KH |
750 | }; |
751 | ||
ce722d26 TG |
752 | /* l4_per -> timer4 */ |
753 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { | |
754 | .master = &omap3xxx_l4_per_hwmod, | |
755 | .slave = &omap3xxx_timer4_hwmod, | |
756 | .clk = "gpt4_ick", | |
757 | .addr = omap3xxx_timer4_addrs, | |
ce722d26 | 758 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
046465b7 KH |
759 | }; |
760 | ||
ce722d26 TG |
761 | /* timer4 slave port */ |
762 | static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = { | |
763 | &omap3xxx_l4_per__timer4, | |
046465b7 KH |
764 | }; |
765 | ||
ce722d26 TG |
766 | /* timer4 hwmod */ |
767 | static struct omap_hwmod omap3xxx_timer4_hwmod = { | |
768 | .name = "timer4", | |
0d619a89 | 769 | .mpu_irqs = omap2_timer4_mpu_irqs, |
ce722d26 | 770 | .main_clk = "gpt4_fck", |
046465b7 KH |
771 | .prcm = { |
772 | .omap2 = { | |
046465b7 | 773 | .prcm_reg_id = 1, |
ce722d26 TG |
774 | .module_bit = OMAP3430_EN_GPT4_SHIFT, |
775 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 776 | .idlest_reg_id = 1, |
ce722d26 | 777 | .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, |
046465b7 KH |
778 | }, |
779 | }, | |
c345c8b0 | 780 | .dev_attr = &capability_alwon_dev_attr, |
ce722d26 TG |
781 | .slaves = omap3xxx_timer4_slaves, |
782 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves), | |
783 | .class = &omap3xxx_timer_hwmod_class, | |
046465b7 KH |
784 | }; |
785 | ||
ce722d26 TG |
786 | /* timer5 */ |
787 | static struct omap_hwmod omap3xxx_timer5_hwmod; | |
046465b7 | 788 | |
ce722d26 TG |
789 | static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { |
790 | { | |
791 | .pa_start = 0x49038000, | |
792 | .pa_end = 0x49038000 + SZ_1K - 1, | |
793 | .flags = ADDR_TYPE_RT | |
794 | }, | |
78183f3f | 795 | { } |
046465b7 KH |
796 | }; |
797 | ||
ce722d26 TG |
798 | /* l4_per -> timer5 */ |
799 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { | |
800 | .master = &omap3xxx_l4_per_hwmod, | |
801 | .slave = &omap3xxx_timer5_hwmod, | |
802 | .clk = "gpt5_ick", | |
803 | .addr = omap3xxx_timer5_addrs, | |
ce722d26 | 804 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
046465b7 KH |
805 | }; |
806 | ||
ce722d26 TG |
807 | /* timer5 slave port */ |
808 | static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = { | |
809 | &omap3xxx_l4_per__timer5, | |
046465b7 KH |
810 | }; |
811 | ||
ce722d26 TG |
812 | /* timer5 hwmod */ |
813 | static struct omap_hwmod omap3xxx_timer5_hwmod = { | |
814 | .name = "timer5", | |
0d619a89 | 815 | .mpu_irqs = omap2_timer5_mpu_irqs, |
ce722d26 | 816 | .main_clk = "gpt5_fck", |
046465b7 KH |
817 | .prcm = { |
818 | .omap2 = { | |
046465b7 | 819 | .prcm_reg_id = 1, |
ce722d26 TG |
820 | .module_bit = OMAP3430_EN_GPT5_SHIFT, |
821 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 822 | .idlest_reg_id = 1, |
ce722d26 | 823 | .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, |
046465b7 KH |
824 | }, |
825 | }, | |
c345c8b0 | 826 | .dev_attr = &capability_alwon_dev_attr, |
ce722d26 TG |
827 | .slaves = omap3xxx_timer5_slaves, |
828 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves), | |
829 | .class = &omap3xxx_timer_hwmod_class, | |
4fe20e97 RN |
830 | }; |
831 | ||
ce722d26 TG |
832 | /* timer6 */ |
833 | static struct omap_hwmod omap3xxx_timer6_hwmod; | |
4fe20e97 | 834 | |
ce722d26 TG |
835 | static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { |
836 | { | |
837 | .pa_start = 0x4903A000, | |
838 | .pa_end = 0x4903A000 + SZ_1K - 1, | |
839 | .flags = ADDR_TYPE_RT | |
840 | }, | |
78183f3f | 841 | { } |
4fe20e97 RN |
842 | }; |
843 | ||
ce722d26 TG |
844 | /* l4_per -> timer6 */ |
845 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { | |
846 | .master = &omap3xxx_l4_per_hwmod, | |
847 | .slave = &omap3xxx_timer6_hwmod, | |
848 | .clk = "gpt6_ick", | |
849 | .addr = omap3xxx_timer6_addrs, | |
ce722d26 | 850 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4fe20e97 RN |
851 | }; |
852 | ||
ce722d26 TG |
853 | /* timer6 slave port */ |
854 | static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = { | |
855 | &omap3xxx_l4_per__timer6, | |
4fe20e97 RN |
856 | }; |
857 | ||
ce722d26 TG |
858 | /* timer6 hwmod */ |
859 | static struct omap_hwmod omap3xxx_timer6_hwmod = { | |
860 | .name = "timer6", | |
0d619a89 | 861 | .mpu_irqs = omap2_timer6_mpu_irqs, |
ce722d26 | 862 | .main_clk = "gpt6_fck", |
4fe20e97 RN |
863 | .prcm = { |
864 | .omap2 = { | |
4fe20e97 | 865 | .prcm_reg_id = 1, |
ce722d26 TG |
866 | .module_bit = OMAP3430_EN_GPT6_SHIFT, |
867 | .module_offs = OMAP3430_PER_MOD, | |
4fe20e97 | 868 | .idlest_reg_id = 1, |
ce722d26 | 869 | .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, |
4fe20e97 RN |
870 | }, |
871 | }, | |
c345c8b0 | 872 | .dev_attr = &capability_alwon_dev_attr, |
ce722d26 TG |
873 | .slaves = omap3xxx_timer6_slaves, |
874 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves), | |
875 | .class = &omap3xxx_timer_hwmod_class, | |
4fe20e97 RN |
876 | }; |
877 | ||
ce722d26 TG |
878 | /* timer7 */ |
879 | static struct omap_hwmod omap3xxx_timer7_hwmod; | |
4fe20e97 | 880 | |
ce722d26 TG |
881 | static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { |
882 | { | |
883 | .pa_start = 0x4903C000, | |
884 | .pa_end = 0x4903C000 + SZ_1K - 1, | |
885 | .flags = ADDR_TYPE_RT | |
886 | }, | |
78183f3f | 887 | { } |
4fe20e97 RN |
888 | }; |
889 | ||
ce722d26 TG |
890 | /* l4_per -> timer7 */ |
891 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { | |
892 | .master = &omap3xxx_l4_per_hwmod, | |
893 | .slave = &omap3xxx_timer7_hwmod, | |
894 | .clk = "gpt7_ick", | |
895 | .addr = omap3xxx_timer7_addrs, | |
ce722d26 | 896 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4fe20e97 RN |
897 | }; |
898 | ||
ce722d26 TG |
899 | /* timer7 slave port */ |
900 | static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = { | |
901 | &omap3xxx_l4_per__timer7, | |
4fe20e97 RN |
902 | }; |
903 | ||
ce722d26 TG |
904 | /* timer7 hwmod */ |
905 | static struct omap_hwmod omap3xxx_timer7_hwmod = { | |
906 | .name = "timer7", | |
0d619a89 | 907 | .mpu_irqs = omap2_timer7_mpu_irqs, |
ce722d26 | 908 | .main_clk = "gpt7_fck", |
4fe20e97 RN |
909 | .prcm = { |
910 | .omap2 = { | |
4fe20e97 | 911 | .prcm_reg_id = 1, |
ce722d26 TG |
912 | .module_bit = OMAP3430_EN_GPT7_SHIFT, |
913 | .module_offs = OMAP3430_PER_MOD, | |
4fe20e97 | 914 | .idlest_reg_id = 1, |
ce722d26 | 915 | .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, |
4fe20e97 RN |
916 | }, |
917 | }, | |
c345c8b0 | 918 | .dev_attr = &capability_alwon_dev_attr, |
ce722d26 TG |
919 | .slaves = omap3xxx_timer7_slaves, |
920 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves), | |
921 | .class = &omap3xxx_timer_hwmod_class, | |
4fe20e97 RN |
922 | }; |
923 | ||
ce722d26 TG |
924 | /* timer8 */ |
925 | static struct omap_hwmod omap3xxx_timer8_hwmod; | |
4fe20e97 | 926 | |
ce722d26 TG |
927 | static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { |
928 | { | |
929 | .pa_start = 0x4903E000, | |
930 | .pa_end = 0x4903E000 + SZ_1K - 1, | |
931 | .flags = ADDR_TYPE_RT | |
932 | }, | |
78183f3f | 933 | { } |
4fe20e97 RN |
934 | }; |
935 | ||
ce722d26 TG |
936 | /* l4_per -> timer8 */ |
937 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { | |
938 | .master = &omap3xxx_l4_per_hwmod, | |
939 | .slave = &omap3xxx_timer8_hwmod, | |
940 | .clk = "gpt8_ick", | |
941 | .addr = omap3xxx_timer8_addrs, | |
ce722d26 | 942 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4fe20e97 RN |
943 | }; |
944 | ||
ce722d26 TG |
945 | /* timer8 slave port */ |
946 | static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = { | |
947 | &omap3xxx_l4_per__timer8, | |
4fe20e97 RN |
948 | }; |
949 | ||
ce722d26 TG |
950 | /* timer8 hwmod */ |
951 | static struct omap_hwmod omap3xxx_timer8_hwmod = { | |
952 | .name = "timer8", | |
0d619a89 | 953 | .mpu_irqs = omap2_timer8_mpu_irqs, |
ce722d26 | 954 | .main_clk = "gpt8_fck", |
4fe20e97 RN |
955 | .prcm = { |
956 | .omap2 = { | |
4fe20e97 | 957 | .prcm_reg_id = 1, |
ce722d26 TG |
958 | .module_bit = OMAP3430_EN_GPT8_SHIFT, |
959 | .module_offs = OMAP3430_PER_MOD, | |
4fe20e97 | 960 | .idlest_reg_id = 1, |
ce722d26 | 961 | .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, |
4fe20e97 RN |
962 | }, |
963 | }, | |
c345c8b0 | 964 | .dev_attr = &capability_pwm_dev_attr, |
ce722d26 TG |
965 | .slaves = omap3xxx_timer8_slaves, |
966 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves), | |
967 | .class = &omap3xxx_timer_hwmod_class, | |
4fe20e97 RN |
968 | }; |
969 | ||
ce722d26 TG |
970 | /* timer9 */ |
971 | static struct omap_hwmod omap3xxx_timer9_hwmod; | |
ce722d26 TG |
972 | |
973 | static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { | |
70034d38 | 974 | { |
ce722d26 TG |
975 | .pa_start = 0x49040000, |
976 | .pa_end = 0x49040000 + SZ_1K - 1, | |
70034d38 VC |
977 | .flags = ADDR_TYPE_RT |
978 | }, | |
78183f3f | 979 | { } |
70034d38 VC |
980 | }; |
981 | ||
ce722d26 TG |
982 | /* l4_per -> timer9 */ |
983 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { | |
984 | .master = &omap3xxx_l4_per_hwmod, | |
985 | .slave = &omap3xxx_timer9_hwmod, | |
986 | .clk = "gpt9_ick", | |
987 | .addr = omap3xxx_timer9_addrs, | |
70034d38 VC |
988 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
989 | }; | |
990 | ||
ce722d26 TG |
991 | /* timer9 slave port */ |
992 | static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = { | |
993 | &omap3xxx_l4_per__timer9, | |
994 | }; | |
995 | ||
996 | /* timer9 hwmod */ | |
997 | static struct omap_hwmod omap3xxx_timer9_hwmod = { | |
998 | .name = "timer9", | |
0d619a89 | 999 | .mpu_irqs = omap2_timer9_mpu_irqs, |
ce722d26 TG |
1000 | .main_clk = "gpt9_fck", |
1001 | .prcm = { | |
1002 | .omap2 = { | |
1003 | .prcm_reg_id = 1, | |
1004 | .module_bit = OMAP3430_EN_GPT9_SHIFT, | |
1005 | .module_offs = OMAP3430_PER_MOD, | |
1006 | .idlest_reg_id = 1, | |
1007 | .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, | |
1008 | }, | |
70034d38 | 1009 | }, |
c345c8b0 | 1010 | .dev_attr = &capability_pwm_dev_attr, |
ce722d26 TG |
1011 | .slaves = omap3xxx_timer9_slaves, |
1012 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves), | |
1013 | .class = &omap3xxx_timer_hwmod_class, | |
70034d38 VC |
1014 | }; |
1015 | ||
ce722d26 TG |
1016 | /* timer10 */ |
1017 | static struct omap_hwmod omap3xxx_timer10_hwmod; | |
70034d38 | 1018 | |
ce722d26 TG |
1019 | /* l4_core -> timer10 */ |
1020 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { | |
1021 | .master = &omap3xxx_l4_core_hwmod, | |
1022 | .slave = &omap3xxx_timer10_hwmod, | |
1023 | .clk = "gpt10_ick", | |
ded11383 | 1024 | .addr = omap2_timer10_addrs, |
70034d38 VC |
1025 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1026 | }; | |
1027 | ||
ce722d26 TG |
1028 | /* timer10 slave port */ |
1029 | static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = { | |
1030 | &omap3xxx_l4_core__timer10, | |
1031 | }; | |
1032 | ||
1033 | /* timer10 hwmod */ | |
1034 | static struct omap_hwmod omap3xxx_timer10_hwmod = { | |
1035 | .name = "timer10", | |
0d619a89 | 1036 | .mpu_irqs = omap2_timer10_mpu_irqs, |
ce722d26 TG |
1037 | .main_clk = "gpt10_fck", |
1038 | .prcm = { | |
1039 | .omap2 = { | |
1040 | .prcm_reg_id = 1, | |
1041 | .module_bit = OMAP3430_EN_GPT10_SHIFT, | |
1042 | .module_offs = CORE_MOD, | |
1043 | .idlest_reg_id = 1, | |
1044 | .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, | |
1045 | }, | |
70034d38 | 1046 | }, |
c345c8b0 | 1047 | .dev_attr = &capability_pwm_dev_attr, |
ce722d26 TG |
1048 | .slaves = omap3xxx_timer10_slaves, |
1049 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves), | |
1050 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
70034d38 VC |
1051 | }; |
1052 | ||
ce722d26 TG |
1053 | /* timer11 */ |
1054 | static struct omap_hwmod omap3xxx_timer11_hwmod; | |
70034d38 | 1055 | |
ce722d26 TG |
1056 | /* l4_core -> timer11 */ |
1057 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { | |
1058 | .master = &omap3xxx_l4_core_hwmod, | |
1059 | .slave = &omap3xxx_timer11_hwmod, | |
1060 | .clk = "gpt11_ick", | |
ded11383 | 1061 | .addr = omap2_timer11_addrs, |
70034d38 VC |
1062 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1063 | }; | |
1064 | ||
ce722d26 TG |
1065 | /* timer11 slave port */ |
1066 | static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = { | |
1067 | &omap3xxx_l4_core__timer11, | |
1068 | }; | |
1069 | ||
1070 | /* timer11 hwmod */ | |
1071 | static struct omap_hwmod omap3xxx_timer11_hwmod = { | |
1072 | .name = "timer11", | |
0d619a89 | 1073 | .mpu_irqs = omap2_timer11_mpu_irqs, |
ce722d26 TG |
1074 | .main_clk = "gpt11_fck", |
1075 | .prcm = { | |
1076 | .omap2 = { | |
1077 | .prcm_reg_id = 1, | |
1078 | .module_bit = OMAP3430_EN_GPT11_SHIFT, | |
1079 | .module_offs = CORE_MOD, | |
1080 | .idlest_reg_id = 1, | |
1081 | .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, | |
1082 | }, | |
1083 | }, | |
c345c8b0 | 1084 | .dev_attr = &capability_pwm_dev_attr, |
ce722d26 TG |
1085 | .slaves = omap3xxx_timer11_slaves, |
1086 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves), | |
1087 | .class = &omap3xxx_timer_hwmod_class, | |
ce722d26 TG |
1088 | }; |
1089 | ||
1090 | /* timer12*/ | |
1091 | static struct omap_hwmod omap3xxx_timer12_hwmod; | |
1092 | static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { | |
1093 | { .irq = 95, }, | |
212738a4 | 1094 | { .irq = -1 } |
ce722d26 TG |
1095 | }; |
1096 | ||
1097 | static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { | |
70034d38 | 1098 | { |
ce722d26 TG |
1099 | .pa_start = 0x48304000, |
1100 | .pa_end = 0x48304000 + SZ_1K - 1, | |
70034d38 VC |
1101 | .flags = ADDR_TYPE_RT |
1102 | }, | |
78183f3f | 1103 | { } |
70034d38 VC |
1104 | }; |
1105 | ||
ce722d26 TG |
1106 | /* l4_core -> timer12 */ |
1107 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = { | |
1108 | .master = &omap3xxx_l4_core_hwmod, | |
1109 | .slave = &omap3xxx_timer12_hwmod, | |
1110 | .clk = "gpt12_ick", | |
1111 | .addr = omap3xxx_timer12_addrs, | |
70034d38 VC |
1112 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1113 | }; | |
1114 | ||
ce722d26 TG |
1115 | /* timer12 slave port */ |
1116 | static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = { | |
1117 | &omap3xxx_l4_core__timer12, | |
1118 | }; | |
70034d38 | 1119 | |
ce722d26 TG |
1120 | /* timer12 hwmod */ |
1121 | static struct omap_hwmod omap3xxx_timer12_hwmod = { | |
1122 | .name = "timer12", | |
1123 | .mpu_irqs = omap3xxx_timer12_mpu_irqs, | |
ce722d26 TG |
1124 | .main_clk = "gpt12_fck", |
1125 | .prcm = { | |
1126 | .omap2 = { | |
1127 | .prcm_reg_id = 1, | |
1128 | .module_bit = OMAP3430_EN_GPT12_SHIFT, | |
1129 | .module_offs = WKUP_MOD, | |
1130 | .idlest_reg_id = 1, | |
1131 | .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, | |
1132 | }, | |
1133 | }, | |
c345c8b0 | 1134 | .dev_attr = &capability_secure_dev_attr, |
ce722d26 TG |
1135 | .slaves = omap3xxx_timer12_slaves, |
1136 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves), | |
1137 | .class = &omap3xxx_timer_hwmod_class, | |
70034d38 VC |
1138 | }; |
1139 | ||
6b667f88 VC |
1140 | /* l4_wkup -> wd_timer2 */ |
1141 | static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { | |
1142 | { | |
1143 | .pa_start = 0x48314000, | |
1144 | .pa_end = 0x4831407f, | |
1145 | .flags = ADDR_TYPE_RT | |
1146 | }, | |
78183f3f | 1147 | { } |
70034d38 VC |
1148 | }; |
1149 | ||
6b667f88 VC |
1150 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { |
1151 | .master = &omap3xxx_l4_wkup_hwmod, | |
1152 | .slave = &omap3xxx_wd_timer2_hwmod, | |
1153 | .clk = "wdt2_ick", | |
1154 | .addr = omap3xxx_wd_timer2_addrs, | |
6b667f88 | 1155 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
1156 | }; |
1157 | ||
6b667f88 VC |
1158 | /* |
1159 | * 'wd_timer' class | |
1160 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
1161 | * overflow condition | |
1162 | */ | |
1163 | ||
1164 | static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { | |
1165 | .rev_offs = 0x0000, | |
1166 | .sysc_offs = 0x0010, | |
1167 | .syss_offs = 0x0014, | |
1168 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | | |
1169 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
2d403fe0 | 1170 | SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | |
d73d65fa | 1171 | SYSS_HAS_RESET_STATUS), |
6b667f88 VC |
1172 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
1173 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1174 | }; |
1175 | ||
4fe20e97 RN |
1176 | /* I2C common */ |
1177 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
1178 | .rev_offs = 0x00, | |
1179 | .sysc_offs = 0x20, | |
1180 | .syss_offs = 0x10, | |
1181 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1182 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
2d403fe0 | 1183 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
4fe20e97 | 1184 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
3e47dc6a | 1185 | .clockact = CLOCKACT_TEST_ICLK, |
4fe20e97 | 1186 | .sysc_fields = &omap_hwmod_sysc_type1, |
70034d38 VC |
1187 | }; |
1188 | ||
6b667f88 | 1189 | static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { |
ff2516fb PW |
1190 | .name = "wd_timer", |
1191 | .sysc = &omap3xxx_wd_timer_sysc, | |
1192 | .pre_shutdown = &omap2_wd_timer_disable | |
70034d38 VC |
1193 | }; |
1194 | ||
6b667f88 VC |
1195 | /* wd_timer2 */ |
1196 | static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = { | |
1197 | &omap3xxx_l4_wkup__wd_timer2, | |
1198 | }; | |
1199 | ||
1200 | static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { | |
1201 | .name = "wd_timer2", | |
1202 | .class = &omap3xxx_wd_timer_hwmod_class, | |
1203 | .main_clk = "wdt2_fck", | |
70034d38 VC |
1204 | .prcm = { |
1205 | .omap2 = { | |
1206 | .prcm_reg_id = 1, | |
6b667f88 | 1207 | .module_bit = OMAP3430_EN_WDT2_SHIFT, |
70034d38 VC |
1208 | .module_offs = WKUP_MOD, |
1209 | .idlest_reg_id = 1, | |
6b667f88 | 1210 | .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, |
70034d38 VC |
1211 | }, |
1212 | }, | |
6b667f88 VC |
1213 | .slaves = omap3xxx_wd_timer2_slaves, |
1214 | .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves), | |
2f4dd595 PW |
1215 | /* |
1216 | * XXX: Use software supervised mode, HW supervised smartidle seems to | |
1217 | * block CORE power domain idle transitions. Maybe a HW bug in wdt2? | |
1218 | */ | |
1219 | .flags = HWMOD_SWSUP_SIDLE, | |
70034d38 VC |
1220 | }; |
1221 | ||
046465b7 KH |
1222 | /* UART1 */ |
1223 | ||
046465b7 KH |
1224 | static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { |
1225 | &omap3_l4_core__uart1, | |
1226 | }; | |
1227 | ||
1228 | static struct omap_hwmod omap3xxx_uart1_hwmod = { | |
1229 | .name = "uart1", | |
0d619a89 | 1230 | .mpu_irqs = omap2_uart1_mpu_irqs, |
d826ebfa | 1231 | .sdma_reqs = omap2_uart1_sdma_reqs, |
046465b7 | 1232 | .main_clk = "uart1_fck", |
70034d38 VC |
1233 | .prcm = { |
1234 | .omap2 = { | |
046465b7 | 1235 | .module_offs = CORE_MOD, |
70034d38 | 1236 | .prcm_reg_id = 1, |
046465b7 | 1237 | .module_bit = OMAP3430_EN_UART1_SHIFT, |
70034d38 | 1238 | .idlest_reg_id = 1, |
046465b7 | 1239 | .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, |
70034d38 VC |
1240 | }, |
1241 | }, | |
046465b7 KH |
1242 | .slaves = omap3xxx_uart1_slaves, |
1243 | .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), | |
273b9465 | 1244 | .class = &omap2_uart_class, |
70034d38 VC |
1245 | }; |
1246 | ||
046465b7 KH |
1247 | /* UART2 */ |
1248 | ||
046465b7 KH |
1249 | static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = { |
1250 | &omap3_l4_core__uart2, | |
70034d38 VC |
1251 | }; |
1252 | ||
046465b7 KH |
1253 | static struct omap_hwmod omap3xxx_uart2_hwmod = { |
1254 | .name = "uart2", | |
0d619a89 | 1255 | .mpu_irqs = omap2_uart2_mpu_irqs, |
d826ebfa | 1256 | .sdma_reqs = omap2_uart2_sdma_reqs, |
046465b7 | 1257 | .main_clk = "uart2_fck", |
70034d38 VC |
1258 | .prcm = { |
1259 | .omap2 = { | |
046465b7 | 1260 | .module_offs = CORE_MOD, |
70034d38 | 1261 | .prcm_reg_id = 1, |
046465b7 KH |
1262 | .module_bit = OMAP3430_EN_UART2_SHIFT, |
1263 | .idlest_reg_id = 1, | |
1264 | .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, | |
1265 | }, | |
1266 | }, | |
1267 | .slaves = omap3xxx_uart2_slaves, | |
1268 | .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), | |
273b9465 | 1269 | .class = &omap2_uart_class, |
046465b7 KH |
1270 | }; |
1271 | ||
1272 | /* UART3 */ | |
1273 | ||
046465b7 KH |
1274 | static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = { |
1275 | &omap3_l4_per__uart3, | |
1276 | }; | |
1277 | ||
1278 | static struct omap_hwmod omap3xxx_uart3_hwmod = { | |
1279 | .name = "uart3", | |
0d619a89 | 1280 | .mpu_irqs = omap2_uart3_mpu_irqs, |
d826ebfa | 1281 | .sdma_reqs = omap2_uart3_sdma_reqs, |
046465b7 KH |
1282 | .main_clk = "uart3_fck", |
1283 | .prcm = { | |
1284 | .omap2 = { | |
70034d38 | 1285 | .module_offs = OMAP3430_PER_MOD, |
046465b7 KH |
1286 | .prcm_reg_id = 1, |
1287 | .module_bit = OMAP3430_EN_UART3_SHIFT, | |
70034d38 | 1288 | .idlest_reg_id = 1, |
046465b7 | 1289 | .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, |
70034d38 VC |
1290 | }, |
1291 | }, | |
046465b7 KH |
1292 | .slaves = omap3xxx_uart3_slaves, |
1293 | .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), | |
273b9465 | 1294 | .class = &omap2_uart_class, |
70034d38 VC |
1295 | }; |
1296 | ||
046465b7 KH |
1297 | /* UART4 */ |
1298 | ||
1299 | static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { | |
1300 | { .irq = INT_36XX_UART4_IRQ, }, | |
212738a4 | 1301 | { .irq = -1 } |
70034d38 VC |
1302 | }; |
1303 | ||
046465b7 KH |
1304 | static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { |
1305 | { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, | |
1306 | { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, | |
bc614958 | 1307 | { .dma_req = -1 } |
70034d38 VC |
1308 | }; |
1309 | ||
046465b7 KH |
1310 | static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { |
1311 | &omap3_l4_per__uart4, | |
70034d38 VC |
1312 | }; |
1313 | ||
046465b7 KH |
1314 | static struct omap_hwmod omap3xxx_uart4_hwmod = { |
1315 | .name = "uart4", | |
1316 | .mpu_irqs = uart4_mpu_irqs, | |
046465b7 | 1317 | .sdma_reqs = uart4_sdma_reqs, |
046465b7 KH |
1318 | .main_clk = "uart4_fck", |
1319 | .prcm = { | |
1320 | .omap2 = { | |
1321 | .module_offs = OMAP3430_PER_MOD, | |
1322 | .prcm_reg_id = 1, | |
1323 | .module_bit = OMAP3630_EN_UART4_SHIFT, | |
1324 | .idlest_reg_id = 1, | |
1325 | .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, | |
1326 | }, | |
1327 | }, | |
1328 | .slaves = omap3xxx_uart4_slaves, | |
1329 | .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), | |
273b9465 | 1330 | .class = &omap2_uart_class, |
046465b7 KH |
1331 | }; |
1332 | ||
4bf90f65 KM |
1333 | static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { |
1334 | { .irq = INT_35XX_UART4_IRQ, }, | |
1335 | }; | |
1336 | ||
1337 | static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { | |
1338 | { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, | |
1339 | { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, | |
1340 | }; | |
1341 | ||
1342 | static struct omap_hwmod_ocp_if *am35xx_uart4_slaves[] = { | |
1343 | &am35xx_l4_core__uart4, | |
1344 | }; | |
1345 | ||
1346 | static struct omap_hwmod am35xx_uart4_hwmod = { | |
1347 | .name = "uart4", | |
1348 | .mpu_irqs = am35xx_uart4_mpu_irqs, | |
1349 | .sdma_reqs = am35xx_uart4_sdma_reqs, | |
1350 | .main_clk = "uart4_fck", | |
1351 | .prcm = { | |
1352 | .omap2 = { | |
1353 | .module_offs = CORE_MOD, | |
1354 | .prcm_reg_id = 1, | |
1355 | .module_bit = OMAP3430_EN_UART4_SHIFT, | |
1356 | .idlest_reg_id = 1, | |
1357 | .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT, | |
1358 | }, | |
1359 | }, | |
1360 | .slaves = am35xx_uart4_slaves, | |
1361 | .slaves_cnt = ARRAY_SIZE(am35xx_uart4_slaves), | |
1362 | .class = &omap2_uart_class, | |
1363 | }; | |
1364 | ||
1365 | ||
4fe20e97 | 1366 | static struct omap_hwmod_class i2c_class = { |
6d3c55fd A |
1367 | .name = "i2c", |
1368 | .sysc = &i2c_sysc, | |
1369 | .rev = OMAP_I2C_IP_VERSION_1, | |
1370 | .reset = &omap_i2c_reset, | |
4fe20e97 RN |
1371 | }; |
1372 | ||
e04d9e1e SG |
1373 | static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { |
1374 | { .name = "dispc", .dma_req = 5 }, | |
1375 | { .name = "dsi1", .dma_req = 74 }, | |
bc614958 | 1376 | { .dma_req = -1 } |
e04d9e1e SG |
1377 | }; |
1378 | ||
1379 | /* dss */ | |
1380 | /* dss master ports */ | |
1381 | static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = { | |
1382 | &omap3xxx_dss__l3, | |
1383 | }; | |
1384 | ||
e04d9e1e SG |
1385 | /* l4_core -> dss */ |
1386 | static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { | |
1387 | .master = &omap3xxx_l4_core_hwmod, | |
1388 | .slave = &omap3430es1_dss_core_hwmod, | |
1389 | .clk = "dss_ick", | |
ded11383 | 1390 | .addr = omap2_dss_addrs, |
e04d9e1e SG |
1391 | .fw = { |
1392 | .omap2 = { | |
1393 | .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, | |
1394 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
1395 | .flags = OMAP_FIREWALL_L4, | |
1396 | } | |
1397 | }, | |
1398 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1399 | }; | |
1400 | ||
1401 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { | |
1402 | .master = &omap3xxx_l4_core_hwmod, | |
1403 | .slave = &omap3xxx_dss_core_hwmod, | |
1404 | .clk = "dss_ick", | |
ded11383 | 1405 | .addr = omap2_dss_addrs, |
e04d9e1e SG |
1406 | .fw = { |
1407 | .omap2 = { | |
1408 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, | |
1409 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
1410 | .flags = OMAP_FIREWALL_L4, | |
1411 | } | |
1412 | }, | |
1413 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1414 | }; | |
1415 | ||
1416 | /* dss slave ports */ | |
1417 | static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = { | |
1418 | &omap3430es1_l4_core__dss, | |
1419 | }; | |
1420 | ||
1421 | static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = { | |
1422 | &omap3xxx_l4_core__dss, | |
1423 | }; | |
1424 | ||
1425 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
8c3105ca TV |
1426 | /* |
1427 | * The DSS HW needs all DSS clocks enabled during reset. The dss_core | |
1428 | * driver does not use these clocks. | |
1429 | */ | |
e04d9e1e | 1430 | { .role = "sys_clk", .clk = "dss2_alwon_fck" }, |
8c3105ca TV |
1431 | { .role = "tv_clk", .clk = "dss_tv_fck" }, |
1432 | /* required only on OMAP3430 */ | |
1433 | { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, | |
e04d9e1e SG |
1434 | }; |
1435 | ||
1436 | static struct omap_hwmod omap3430es1_dss_core_hwmod = { | |
1437 | .name = "dss_core", | |
273b9465 | 1438 | .class = &omap2_dss_hwmod_class, |
e04d9e1e | 1439 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ |
e04d9e1e | 1440 | .sdma_reqs = omap3xxx_dss_sdma_chs, |
e04d9e1e SG |
1441 | .prcm = { |
1442 | .omap2 = { | |
1443 | .prcm_reg_id = 1, | |
1444 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
1445 | .module_offs = OMAP3430_DSS_MOD, | |
1446 | .idlest_reg_id = 1, | |
1447 | .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, | |
1448 | }, | |
1449 | }, | |
1450 | .opt_clks = dss_opt_clks, | |
1451 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
1452 | .slaves = omap3430es1_dss_slaves, | |
1453 | .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves), | |
1454 | .masters = omap3xxx_dss_masters, | |
1455 | .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), | |
8c3105ca | 1456 | .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
e04d9e1e SG |
1457 | }; |
1458 | ||
1459 | static struct omap_hwmod omap3xxx_dss_core_hwmod = { | |
1460 | .name = "dss_core", | |
8c3105ca | 1461 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
273b9465 | 1462 | .class = &omap2_dss_hwmod_class, |
e04d9e1e | 1463 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ |
e04d9e1e | 1464 | .sdma_reqs = omap3xxx_dss_sdma_chs, |
e04d9e1e SG |
1465 | .prcm = { |
1466 | .omap2 = { | |
1467 | .prcm_reg_id = 1, | |
1468 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
1469 | .module_offs = OMAP3430_DSS_MOD, | |
1470 | .idlest_reg_id = 1, | |
1471 | .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, | |
1472 | .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, | |
1473 | }, | |
1474 | }, | |
1475 | .opt_clks = dss_opt_clks, | |
1476 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
1477 | .slaves = omap3xxx_dss_slaves, | |
1478 | .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves), | |
1479 | .masters = omap3xxx_dss_masters, | |
1480 | .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), | |
e04d9e1e SG |
1481 | }; |
1482 | ||
1ac6d46e TV |
1483 | /* |
1484 | * 'dispc' class | |
1485 | * display controller | |
1486 | */ | |
1487 | ||
1488 | static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { | |
1489 | .rev_offs = 0x0000, | |
1490 | .sysc_offs = 0x0010, | |
1491 | .syss_offs = 0x0014, | |
1492 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | |
1493 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1494 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1495 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1496 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1497 | }; | |
1498 | ||
1499 | static struct omap_hwmod_class omap3_dispc_hwmod_class = { | |
1500 | .name = "dispc", | |
1501 | .sysc = &omap3_dispc_sysc, | |
1502 | }; | |
1503 | ||
e04d9e1e SG |
1504 | /* l4_core -> dss_dispc */ |
1505 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { | |
1506 | .master = &omap3xxx_l4_core_hwmod, | |
1507 | .slave = &omap3xxx_dss_dispc_hwmod, | |
1508 | .clk = "dss_ick", | |
ded11383 | 1509 | .addr = omap2_dss_dispc_addrs, |
e04d9e1e SG |
1510 | .fw = { |
1511 | .omap2 = { | |
1512 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, | |
1513 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
1514 | .flags = OMAP_FIREWALL_L4, | |
1515 | } | |
1516 | }, | |
1517 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1518 | }; | |
1519 | ||
1520 | /* dss_dispc slave ports */ | |
1521 | static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = { | |
1522 | &omap3xxx_l4_core__dss_dispc, | |
1523 | }; | |
1524 | ||
1525 | static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { | |
1526 | .name = "dss_dispc", | |
1ac6d46e | 1527 | .class = &omap3_dispc_hwmod_class, |
0d619a89 | 1528 | .mpu_irqs = omap2_dispc_irqs, |
e04d9e1e SG |
1529 | .main_clk = "dss1_alwon_fck", |
1530 | .prcm = { | |
1531 | .omap2 = { | |
1532 | .prcm_reg_id = 1, | |
1533 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
1534 | .module_offs = OMAP3430_DSS_MOD, | |
1535 | }, | |
1536 | }, | |
1537 | .slaves = omap3xxx_dss_dispc_slaves, | |
1538 | .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves), | |
e04d9e1e | 1539 | .flags = HWMOD_NO_IDLEST, |
b923d40d | 1540 | .dev_attr = &omap2_3_dss_dispc_dev_attr |
e04d9e1e SG |
1541 | }; |
1542 | ||
1543 | /* | |
1544 | * 'dsi' class | |
1545 | * display serial interface controller | |
1546 | */ | |
1547 | ||
1548 | static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { | |
1549 | .name = "dsi", | |
1550 | }; | |
1551 | ||
affe360d | 1552 | static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { |
1553 | { .irq = 25 }, | |
212738a4 | 1554 | { .irq = -1 } |
affe360d | 1555 | }; |
1556 | ||
e04d9e1e SG |
1557 | /* dss_dsi1 */ |
1558 | static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { | |
1559 | { | |
1560 | .pa_start = 0x4804FC00, | |
1561 | .pa_end = 0x4804FFFF, | |
1562 | .flags = ADDR_TYPE_RT | |
1563 | }, | |
78183f3f | 1564 | { } |
e04d9e1e SG |
1565 | }; |
1566 | ||
1567 | /* l4_core -> dss_dsi1 */ | |
1568 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { | |
1569 | .master = &omap3xxx_l4_core_hwmod, | |
1570 | .slave = &omap3xxx_dss_dsi1_hwmod, | |
6c3d7e34 | 1571 | .clk = "dss_ick", |
e04d9e1e | 1572 | .addr = omap3xxx_dss_dsi1_addrs, |
e04d9e1e SG |
1573 | .fw = { |
1574 | .omap2 = { | |
1575 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, | |
1576 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
1577 | .flags = OMAP_FIREWALL_L4, | |
1578 | } | |
1579 | }, | |
1580 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1581 | }; | |
1582 | ||
1583 | /* dss_dsi1 slave ports */ | |
1584 | static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = { | |
1585 | &omap3xxx_l4_core__dss_dsi1, | |
1586 | }; | |
1587 | ||
6c3d7e34 TV |
1588 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { |
1589 | { .role = "sys_clk", .clk = "dss2_alwon_fck" }, | |
1590 | }; | |
1591 | ||
e04d9e1e SG |
1592 | static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { |
1593 | .name = "dss_dsi1", | |
1594 | .class = &omap3xxx_dsi_hwmod_class, | |
affe360d | 1595 | .mpu_irqs = omap3xxx_dsi1_irqs, |
e04d9e1e SG |
1596 | .main_clk = "dss1_alwon_fck", |
1597 | .prcm = { | |
1598 | .omap2 = { | |
1599 | .prcm_reg_id = 1, | |
1600 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
1601 | .module_offs = OMAP3430_DSS_MOD, | |
1602 | }, | |
1603 | }, | |
6c3d7e34 TV |
1604 | .opt_clks = dss_dsi1_opt_clks, |
1605 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
e04d9e1e SG |
1606 | .slaves = omap3xxx_dss_dsi1_slaves, |
1607 | .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves), | |
e04d9e1e SG |
1608 | .flags = HWMOD_NO_IDLEST, |
1609 | }; | |
1610 | ||
e04d9e1e SG |
1611 | /* l4_core -> dss_rfbi */ |
1612 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { | |
1613 | .master = &omap3xxx_l4_core_hwmod, | |
1614 | .slave = &omap3xxx_dss_rfbi_hwmod, | |
1615 | .clk = "dss_ick", | |
ded11383 | 1616 | .addr = omap2_dss_rfbi_addrs, |
e04d9e1e SG |
1617 | .fw = { |
1618 | .omap2 = { | |
1619 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, | |
1620 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , | |
1621 | .flags = OMAP_FIREWALL_L4, | |
1622 | } | |
1623 | }, | |
1624 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1625 | }; | |
1626 | ||
1627 | /* dss_rfbi slave ports */ | |
1628 | static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = { | |
1629 | &omap3xxx_l4_core__dss_rfbi, | |
1630 | }; | |
1631 | ||
6c3d7e34 TV |
1632 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
1633 | { .role = "ick", .clk = "dss_ick" }, | |
1634 | }; | |
1635 | ||
e04d9e1e SG |
1636 | static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { |
1637 | .name = "dss_rfbi", | |
273b9465 | 1638 | .class = &omap2_rfbi_hwmod_class, |
e04d9e1e SG |
1639 | .main_clk = "dss1_alwon_fck", |
1640 | .prcm = { | |
1641 | .omap2 = { | |
1642 | .prcm_reg_id = 1, | |
1643 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
1644 | .module_offs = OMAP3430_DSS_MOD, | |
1645 | }, | |
1646 | }, | |
6c3d7e34 TV |
1647 | .opt_clks = dss_rfbi_opt_clks, |
1648 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
e04d9e1e SG |
1649 | .slaves = omap3xxx_dss_rfbi_slaves, |
1650 | .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves), | |
e04d9e1e SG |
1651 | .flags = HWMOD_NO_IDLEST, |
1652 | }; | |
1653 | ||
e04d9e1e SG |
1654 | /* l4_core -> dss_venc */ |
1655 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { | |
1656 | .master = &omap3xxx_l4_core_hwmod, | |
1657 | .slave = &omap3xxx_dss_venc_hwmod, | |
6c3d7e34 | 1658 | .clk = "dss_ick", |
ded11383 | 1659 | .addr = omap2_dss_venc_addrs, |
e04d9e1e SG |
1660 | .fw = { |
1661 | .omap2 = { | |
1662 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, | |
1663 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
1664 | .flags = OMAP_FIREWALL_L4, | |
1665 | } | |
1666 | }, | |
c39bee8a | 1667 | .flags = OCPIF_SWSUP_IDLE, |
e04d9e1e SG |
1668 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1669 | }; | |
1670 | ||
1671 | /* dss_venc slave ports */ | |
1672 | static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = { | |
1673 | &omap3xxx_l4_core__dss_venc, | |
1674 | }; | |
1675 | ||
6c3d7e34 TV |
1676 | static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { |
1677 | /* required only on OMAP3430 */ | |
1678 | { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, | |
1679 | }; | |
1680 | ||
e04d9e1e SG |
1681 | static struct omap_hwmod omap3xxx_dss_venc_hwmod = { |
1682 | .name = "dss_venc", | |
273b9465 | 1683 | .class = &omap2_venc_hwmod_class, |
6c3d7e34 | 1684 | .main_clk = "dss_tv_fck", |
e04d9e1e SG |
1685 | .prcm = { |
1686 | .omap2 = { | |
1687 | .prcm_reg_id = 1, | |
1688 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
1689 | .module_offs = OMAP3430_DSS_MOD, | |
1690 | }, | |
1691 | }, | |
6c3d7e34 TV |
1692 | .opt_clks = dss_venc_opt_clks, |
1693 | .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), | |
e04d9e1e SG |
1694 | .slaves = omap3xxx_dss_venc_slaves, |
1695 | .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves), | |
e04d9e1e SG |
1696 | .flags = HWMOD_NO_IDLEST, |
1697 | }; | |
1698 | ||
4fe20e97 RN |
1699 | /* I2C1 */ |
1700 | ||
1701 | static struct omap_i2c_dev_attr i2c1_dev_attr = { | |
1702 | .fifo_depth = 8, /* bytes */ | |
4d4441a6 AG |
1703 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | |
1704 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
1705 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
4fe20e97 RN |
1706 | }; |
1707 | ||
4fe20e97 RN |
1708 | static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = { |
1709 | &omap3_l4_core__i2c1, | |
1710 | }; | |
1711 | ||
1712 | static struct omap_hwmod omap3xxx_i2c1_hwmod = { | |
1713 | .name = "i2c1", | |
3e47dc6a | 1714 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
0d619a89 | 1715 | .mpu_irqs = omap2_i2c1_mpu_irqs, |
d826ebfa | 1716 | .sdma_reqs = omap2_i2c1_sdma_reqs, |
4fe20e97 RN |
1717 | .main_clk = "i2c1_fck", |
1718 | .prcm = { | |
1719 | .omap2 = { | |
1720 | .module_offs = CORE_MOD, | |
1721 | .prcm_reg_id = 1, | |
1722 | .module_bit = OMAP3430_EN_I2C1_SHIFT, | |
1723 | .idlest_reg_id = 1, | |
1724 | .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, | |
1725 | }, | |
1726 | }, | |
1727 | .slaves = omap3xxx_i2c1_slaves, | |
1728 | .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves), | |
1729 | .class = &i2c_class, | |
1730 | .dev_attr = &i2c1_dev_attr, | |
4fe20e97 RN |
1731 | }; |
1732 | ||
1733 | /* I2C2 */ | |
1734 | ||
1735 | static struct omap_i2c_dev_attr i2c2_dev_attr = { | |
1736 | .fifo_depth = 8, /* bytes */ | |
4d4441a6 AG |
1737 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | |
1738 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
1739 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
4fe20e97 RN |
1740 | }; |
1741 | ||
4fe20e97 RN |
1742 | static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = { |
1743 | &omap3_l4_core__i2c2, | |
1744 | }; | |
1745 | ||
1746 | static struct omap_hwmod omap3xxx_i2c2_hwmod = { | |
1747 | .name = "i2c2", | |
3e47dc6a | 1748 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
0d619a89 | 1749 | .mpu_irqs = omap2_i2c2_mpu_irqs, |
d826ebfa | 1750 | .sdma_reqs = omap2_i2c2_sdma_reqs, |
4fe20e97 RN |
1751 | .main_clk = "i2c2_fck", |
1752 | .prcm = { | |
1753 | .omap2 = { | |
1754 | .module_offs = CORE_MOD, | |
1755 | .prcm_reg_id = 1, | |
1756 | .module_bit = OMAP3430_EN_I2C2_SHIFT, | |
1757 | .idlest_reg_id = 1, | |
1758 | .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, | |
1759 | }, | |
1760 | }, | |
1761 | .slaves = omap3xxx_i2c2_slaves, | |
1762 | .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves), | |
1763 | .class = &i2c_class, | |
1764 | .dev_attr = &i2c2_dev_attr, | |
4fe20e97 RN |
1765 | }; |
1766 | ||
1767 | /* I2C3 */ | |
1768 | ||
1769 | static struct omap_i2c_dev_attr i2c3_dev_attr = { | |
1770 | .fifo_depth = 64, /* bytes */ | |
4d4441a6 AG |
1771 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | |
1772 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
1773 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
4fe20e97 RN |
1774 | }; |
1775 | ||
1776 | static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { | |
1777 | { .irq = INT_34XX_I2C3_IRQ, }, | |
212738a4 | 1778 | { .irq = -1 } |
4fe20e97 RN |
1779 | }; |
1780 | ||
1781 | static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { | |
1782 | { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, | |
1783 | { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, | |
bc614958 | 1784 | { .dma_req = -1 } |
4fe20e97 RN |
1785 | }; |
1786 | ||
1787 | static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = { | |
1788 | &omap3_l4_core__i2c3, | |
1789 | }; | |
1790 | ||
1791 | static struct omap_hwmod omap3xxx_i2c3_hwmod = { | |
1792 | .name = "i2c3", | |
3e47dc6a | 1793 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
4fe20e97 | 1794 | .mpu_irqs = i2c3_mpu_irqs, |
4fe20e97 | 1795 | .sdma_reqs = i2c3_sdma_reqs, |
4fe20e97 RN |
1796 | .main_clk = "i2c3_fck", |
1797 | .prcm = { | |
1798 | .omap2 = { | |
1799 | .module_offs = CORE_MOD, | |
1800 | .prcm_reg_id = 1, | |
1801 | .module_bit = OMAP3430_EN_I2C3_SHIFT, | |
1802 | .idlest_reg_id = 1, | |
1803 | .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, | |
1804 | }, | |
1805 | }, | |
1806 | .slaves = omap3xxx_i2c3_slaves, | |
1807 | .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves), | |
1808 | .class = &i2c_class, | |
1809 | .dev_attr = &i2c3_dev_attr, | |
4fe20e97 RN |
1810 | }; |
1811 | ||
70034d38 VC |
1812 | /* l4_wkup -> gpio1 */ |
1813 | static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { | |
1814 | { | |
1815 | .pa_start = 0x48310000, | |
1816 | .pa_end = 0x483101ff, | |
1817 | .flags = ADDR_TYPE_RT | |
1818 | }, | |
78183f3f | 1819 | { } |
70034d38 VC |
1820 | }; |
1821 | ||
1822 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { | |
1823 | .master = &omap3xxx_l4_wkup_hwmod, | |
1824 | .slave = &omap3xxx_gpio1_hwmod, | |
1825 | .addr = omap3xxx_gpio1_addrs, | |
70034d38 VC |
1826 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1827 | }; | |
1828 | ||
1829 | /* l4_per -> gpio2 */ | |
1830 | static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { | |
1831 | { | |
1832 | .pa_start = 0x49050000, | |
1833 | .pa_end = 0x490501ff, | |
1834 | .flags = ADDR_TYPE_RT | |
1835 | }, | |
78183f3f | 1836 | { } |
70034d38 VC |
1837 | }; |
1838 | ||
1839 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { | |
1840 | .master = &omap3xxx_l4_per_hwmod, | |
1841 | .slave = &omap3xxx_gpio2_hwmod, | |
1842 | .addr = omap3xxx_gpio2_addrs, | |
70034d38 VC |
1843 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1844 | }; | |
1845 | ||
1846 | /* l4_per -> gpio3 */ | |
1847 | static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { | |
1848 | { | |
1849 | .pa_start = 0x49052000, | |
1850 | .pa_end = 0x490521ff, | |
1851 | .flags = ADDR_TYPE_RT | |
1852 | }, | |
78183f3f | 1853 | { } |
70034d38 VC |
1854 | }; |
1855 | ||
1856 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { | |
1857 | .master = &omap3xxx_l4_per_hwmod, | |
1858 | .slave = &omap3xxx_gpio3_hwmod, | |
1859 | .addr = omap3xxx_gpio3_addrs, | |
70034d38 VC |
1860 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1861 | }; | |
1862 | ||
1863 | /* l4_per -> gpio4 */ | |
1864 | static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { | |
1865 | { | |
1866 | .pa_start = 0x49054000, | |
1867 | .pa_end = 0x490541ff, | |
1868 | .flags = ADDR_TYPE_RT | |
1869 | }, | |
78183f3f | 1870 | { } |
70034d38 VC |
1871 | }; |
1872 | ||
1873 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { | |
1874 | .master = &omap3xxx_l4_per_hwmod, | |
1875 | .slave = &omap3xxx_gpio4_hwmod, | |
1876 | .addr = omap3xxx_gpio4_addrs, | |
70034d38 VC |
1877 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1878 | }; | |
1879 | ||
1880 | /* l4_per -> gpio5 */ | |
1881 | static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { | |
1882 | { | |
1883 | .pa_start = 0x49056000, | |
1884 | .pa_end = 0x490561ff, | |
1885 | .flags = ADDR_TYPE_RT | |
1886 | }, | |
78183f3f | 1887 | { } |
70034d38 VC |
1888 | }; |
1889 | ||
1890 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { | |
1891 | .master = &omap3xxx_l4_per_hwmod, | |
1892 | .slave = &omap3xxx_gpio5_hwmod, | |
1893 | .addr = omap3xxx_gpio5_addrs, | |
70034d38 VC |
1894 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1895 | }; | |
1896 | ||
1897 | /* l4_per -> gpio6 */ | |
1898 | static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { | |
1899 | { | |
1900 | .pa_start = 0x49058000, | |
1901 | .pa_end = 0x490581ff, | |
1902 | .flags = ADDR_TYPE_RT | |
1903 | }, | |
78183f3f | 1904 | { } |
70034d38 VC |
1905 | }; |
1906 | ||
1907 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { | |
1908 | .master = &omap3xxx_l4_per_hwmod, | |
1909 | .slave = &omap3xxx_gpio6_hwmod, | |
1910 | .addr = omap3xxx_gpio6_addrs, | |
70034d38 VC |
1911 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1912 | }; | |
1913 | ||
1914 | /* | |
1915 | * 'gpio' class | |
1916 | * general purpose io module | |
1917 | */ | |
1918 | ||
1919 | static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { | |
1920 | .rev_offs = 0x0000, | |
1921 | .sysc_offs = 0x0010, | |
1922 | .syss_offs = 0x0014, | |
1923 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
2d403fe0 PW |
1924 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
1925 | SYSS_HAS_RESET_STATUS), | |
70034d38 VC |
1926 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
1927 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1928 | }; | |
1929 | ||
1930 | static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { | |
1931 | .name = "gpio", | |
1932 | .sysc = &omap3xxx_gpio_sysc, | |
1933 | .rev = 1, | |
1934 | }; | |
1935 | ||
1936 | /* gpio_dev_attr*/ | |
1937 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
1938 | .bank_width = 32, | |
1939 | .dbck_flag = true, | |
1940 | }; | |
1941 | ||
1942 | /* gpio1 */ | |
70034d38 VC |
1943 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
1944 | { .role = "dbclk", .clk = "gpio1_dbck", }, | |
1945 | }; | |
1946 | ||
1947 | static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = { | |
1948 | &omap3xxx_l4_wkup__gpio1, | |
1949 | }; | |
1950 | ||
1951 | static struct omap_hwmod omap3xxx_gpio1_hwmod = { | |
1952 | .name = "gpio1", | |
f95440ca | 1953 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 1954 | .mpu_irqs = omap2_gpio1_irqs, |
70034d38 VC |
1955 | .main_clk = "gpio1_ick", |
1956 | .opt_clks = gpio1_opt_clks, | |
1957 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
1958 | .prcm = { | |
1959 | .omap2 = { | |
1960 | .prcm_reg_id = 1, | |
1961 | .module_bit = OMAP3430_EN_GPIO1_SHIFT, | |
1962 | .module_offs = WKUP_MOD, | |
1963 | .idlest_reg_id = 1, | |
1964 | .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, | |
1965 | }, | |
1966 | }, | |
1967 | .slaves = omap3xxx_gpio1_slaves, | |
1968 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves), | |
1969 | .class = &omap3xxx_gpio_hwmod_class, | |
1970 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
1971 | }; |
1972 | ||
1973 | /* gpio2 */ | |
70034d38 VC |
1974 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
1975 | { .role = "dbclk", .clk = "gpio2_dbck", }, | |
1976 | }; | |
1977 | ||
1978 | static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = { | |
1979 | &omap3xxx_l4_per__gpio2, | |
1980 | }; | |
1981 | ||
1982 | static struct omap_hwmod omap3xxx_gpio2_hwmod = { | |
1983 | .name = "gpio2", | |
f95440ca | 1984 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 1985 | .mpu_irqs = omap2_gpio2_irqs, |
70034d38 VC |
1986 | .main_clk = "gpio2_ick", |
1987 | .opt_clks = gpio2_opt_clks, | |
1988 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
1989 | .prcm = { | |
1990 | .omap2 = { | |
1991 | .prcm_reg_id = 1, | |
1992 | .module_bit = OMAP3430_EN_GPIO2_SHIFT, | |
1993 | .module_offs = OMAP3430_PER_MOD, | |
1994 | .idlest_reg_id = 1, | |
1995 | .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, | |
1996 | }, | |
1997 | }, | |
1998 | .slaves = omap3xxx_gpio2_slaves, | |
1999 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves), | |
2000 | .class = &omap3xxx_gpio_hwmod_class, | |
2001 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
2002 | }; |
2003 | ||
2004 | /* gpio3 */ | |
70034d38 VC |
2005 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
2006 | { .role = "dbclk", .clk = "gpio3_dbck", }, | |
2007 | }; | |
2008 | ||
2009 | static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = { | |
2010 | &omap3xxx_l4_per__gpio3, | |
2011 | }; | |
2012 | ||
2013 | static struct omap_hwmod omap3xxx_gpio3_hwmod = { | |
2014 | .name = "gpio3", | |
f95440ca | 2015 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 2016 | .mpu_irqs = omap2_gpio3_irqs, |
70034d38 VC |
2017 | .main_clk = "gpio3_ick", |
2018 | .opt_clks = gpio3_opt_clks, | |
2019 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
2020 | .prcm = { | |
2021 | .omap2 = { | |
2022 | .prcm_reg_id = 1, | |
2023 | .module_bit = OMAP3430_EN_GPIO3_SHIFT, | |
2024 | .module_offs = OMAP3430_PER_MOD, | |
2025 | .idlest_reg_id = 1, | |
2026 | .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, | |
2027 | }, | |
2028 | }, | |
2029 | .slaves = omap3xxx_gpio3_slaves, | |
2030 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves), | |
2031 | .class = &omap3xxx_gpio_hwmod_class, | |
2032 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
2033 | }; |
2034 | ||
2035 | /* gpio4 */ | |
70034d38 VC |
2036 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
2037 | { .role = "dbclk", .clk = "gpio4_dbck", }, | |
2038 | }; | |
2039 | ||
2040 | static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = { | |
2041 | &omap3xxx_l4_per__gpio4, | |
2042 | }; | |
2043 | ||
2044 | static struct omap_hwmod omap3xxx_gpio4_hwmod = { | |
2045 | .name = "gpio4", | |
f95440ca | 2046 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 2047 | .mpu_irqs = omap2_gpio4_irqs, |
70034d38 VC |
2048 | .main_clk = "gpio4_ick", |
2049 | .opt_clks = gpio4_opt_clks, | |
2050 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
2051 | .prcm = { | |
2052 | .omap2 = { | |
2053 | .prcm_reg_id = 1, | |
2054 | .module_bit = OMAP3430_EN_GPIO4_SHIFT, | |
2055 | .module_offs = OMAP3430_PER_MOD, | |
2056 | .idlest_reg_id = 1, | |
2057 | .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, | |
2058 | }, | |
2059 | }, | |
2060 | .slaves = omap3xxx_gpio4_slaves, | |
2061 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves), | |
2062 | .class = &omap3xxx_gpio_hwmod_class, | |
2063 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
2064 | }; |
2065 | ||
2066 | /* gpio5 */ | |
2067 | static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { | |
2068 | { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ | |
212738a4 | 2069 | { .irq = -1 } |
70034d38 VC |
2070 | }; |
2071 | ||
2072 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { | |
2073 | { .role = "dbclk", .clk = "gpio5_dbck", }, | |
2074 | }; | |
2075 | ||
2076 | static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = { | |
2077 | &omap3xxx_l4_per__gpio5, | |
2078 | }; | |
2079 | ||
2080 | static struct omap_hwmod omap3xxx_gpio5_hwmod = { | |
2081 | .name = "gpio5", | |
f95440ca | 2082 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
70034d38 | 2083 | .mpu_irqs = omap3xxx_gpio5_irqs, |
70034d38 VC |
2084 | .main_clk = "gpio5_ick", |
2085 | .opt_clks = gpio5_opt_clks, | |
2086 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
2087 | .prcm = { | |
2088 | .omap2 = { | |
2089 | .prcm_reg_id = 1, | |
2090 | .module_bit = OMAP3430_EN_GPIO5_SHIFT, | |
2091 | .module_offs = OMAP3430_PER_MOD, | |
2092 | .idlest_reg_id = 1, | |
2093 | .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, | |
2094 | }, | |
2095 | }, | |
2096 | .slaves = omap3xxx_gpio5_slaves, | |
2097 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves), | |
2098 | .class = &omap3xxx_gpio_hwmod_class, | |
2099 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
2100 | }; |
2101 | ||
2102 | /* gpio6 */ | |
2103 | static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { | |
2104 | { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ | |
212738a4 | 2105 | { .irq = -1 } |
70034d38 VC |
2106 | }; |
2107 | ||
2108 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { | |
2109 | { .role = "dbclk", .clk = "gpio6_dbck", }, | |
2110 | }; | |
2111 | ||
2112 | static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = { | |
2113 | &omap3xxx_l4_per__gpio6, | |
2114 | }; | |
2115 | ||
2116 | static struct omap_hwmod omap3xxx_gpio6_hwmod = { | |
2117 | .name = "gpio6", | |
f95440ca | 2118 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
70034d38 | 2119 | .mpu_irqs = omap3xxx_gpio6_irqs, |
70034d38 VC |
2120 | .main_clk = "gpio6_ick", |
2121 | .opt_clks = gpio6_opt_clks, | |
2122 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
2123 | .prcm = { | |
2124 | .omap2 = { | |
2125 | .prcm_reg_id = 1, | |
2126 | .module_bit = OMAP3430_EN_GPIO6_SHIFT, | |
2127 | .module_offs = OMAP3430_PER_MOD, | |
2128 | .idlest_reg_id = 1, | |
2129 | .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, | |
2130 | }, | |
2131 | }, | |
2132 | .slaves = omap3xxx_gpio6_slaves, | |
2133 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves), | |
2134 | .class = &omap3xxx_gpio_hwmod_class, | |
2135 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
2136 | }; |
2137 | ||
01438ab6 MK |
2138 | /* dma_system -> L3 */ |
2139 | static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { | |
2140 | .master = &omap3xxx_dma_system_hwmod, | |
2141 | .slave = &omap3xxx_l3_main_hwmod, | |
2142 | .clk = "core_l3_ick", | |
2143 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2144 | }; | |
2145 | ||
2146 | /* dma attributes */ | |
2147 | static struct omap_dma_dev_attr dma_dev_attr = { | |
2148 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
2149 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
2150 | .lch_count = 32, | |
2151 | }; | |
2152 | ||
2153 | static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { | |
2154 | .rev_offs = 0x0000, | |
2155 | .sysc_offs = 0x002c, | |
2156 | .syss_offs = 0x0028, | |
2157 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
2158 | SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
2d403fe0 PW |
2159 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | |
2160 | SYSS_HAS_RESET_STATUS), | |
01438ab6 MK |
2161 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
2162 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
2163 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2164 | }; | |
2165 | ||
2166 | static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { | |
2167 | .name = "dma", | |
2168 | .sysc = &omap3xxx_dma_sysc, | |
2169 | }; | |
2170 | ||
2171 | /* dma_system */ | |
01438ab6 MK |
2172 | static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { |
2173 | { | |
2174 | .pa_start = 0x48056000, | |
1286eeb2 | 2175 | .pa_end = 0x48056fff, |
01438ab6 MK |
2176 | .flags = ADDR_TYPE_RT |
2177 | }, | |
78183f3f | 2178 | { } |
01438ab6 MK |
2179 | }; |
2180 | ||
2181 | /* dma_system master ports */ | |
2182 | static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = { | |
2183 | &omap3xxx_dma_system__l3, | |
2184 | }; | |
2185 | ||
2186 | /* l4_cfg -> dma_system */ | |
2187 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { | |
2188 | .master = &omap3xxx_l4_core_hwmod, | |
2189 | .slave = &omap3xxx_dma_system_hwmod, | |
2190 | .clk = "core_l4_ick", | |
2191 | .addr = omap3xxx_dma_system_addrs, | |
01438ab6 MK |
2192 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2193 | }; | |
2194 | ||
2195 | /* dma_system slave ports */ | |
2196 | static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = { | |
2197 | &omap3xxx_l4_core__dma_system, | |
2198 | }; | |
2199 | ||
2200 | static struct omap_hwmod omap3xxx_dma_system_hwmod = { | |
2201 | .name = "dma", | |
2202 | .class = &omap3xxx_dma_hwmod_class, | |
0d619a89 | 2203 | .mpu_irqs = omap2_dma_system_irqs, |
01438ab6 MK |
2204 | .main_clk = "core_l3_ick", |
2205 | .prcm = { | |
2206 | .omap2 = { | |
2207 | .module_offs = CORE_MOD, | |
2208 | .prcm_reg_id = 1, | |
2209 | .module_bit = OMAP3430_ST_SDMA_SHIFT, | |
2210 | .idlest_reg_id = 1, | |
2211 | .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, | |
2212 | }, | |
2213 | }, | |
2214 | .slaves = omap3xxx_dma_system_slaves, | |
2215 | .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves), | |
2216 | .masters = omap3xxx_dma_system_masters, | |
2217 | .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters), | |
2218 | .dev_attr = &dma_dev_attr, | |
01438ab6 MK |
2219 | .flags = HWMOD_NO_IDLEST, |
2220 | }; | |
2221 | ||
70034d38 | 2222 | /* |
dc48e5fc C |
2223 | * 'mcbsp' class |
2224 | * multi channel buffered serial port controller | |
70034d38 VC |
2225 | */ |
2226 | ||
dc48e5fc C |
2227 | static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { |
2228 | .sysc_offs = 0x008c, | |
2229 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
2230 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
70034d38 | 2231 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
dc48e5fc C |
2232 | .sysc_fields = &omap_hwmod_sysc_type1, |
2233 | .clockact = 0x2, | |
70034d38 VC |
2234 | }; |
2235 | ||
dc48e5fc C |
2236 | static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { |
2237 | .name = "mcbsp", | |
2238 | .sysc = &omap3xxx_mcbsp_sysc, | |
2239 | .rev = MCBSP_CONFIG_TYPE3, | |
70034d38 VC |
2240 | }; |
2241 | ||
dc48e5fc C |
2242 | /* mcbsp1 */ |
2243 | static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { | |
2244 | { .name = "irq", .irq = 16 }, | |
2245 | { .name = "tx", .irq = 59 }, | |
2246 | { .name = "rx", .irq = 60 }, | |
212738a4 | 2247 | { .irq = -1 } |
70034d38 VC |
2248 | }; |
2249 | ||
dc48e5fc C |
2250 | static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { |
2251 | { | |
2252 | .name = "mpu", | |
2253 | .pa_start = 0x48074000, | |
2254 | .pa_end = 0x480740ff, | |
2255 | .flags = ADDR_TYPE_RT | |
2256 | }, | |
78183f3f | 2257 | { } |
70034d38 VC |
2258 | }; |
2259 | ||
dc48e5fc C |
2260 | /* l4_core -> mcbsp1 */ |
2261 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { | |
2262 | .master = &omap3xxx_l4_core_hwmod, | |
2263 | .slave = &omap3xxx_mcbsp1_hwmod, | |
2264 | .clk = "mcbsp1_ick", | |
2265 | .addr = omap3xxx_mcbsp1_addrs, | |
dc48e5fc | 2266 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2267 | }; |
2268 | ||
dc48e5fc C |
2269 | /* mcbsp1 slave ports */ |
2270 | static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = { | |
2271 | &omap3xxx_l4_core__mcbsp1, | |
2272 | }; | |
2273 | ||
2274 | static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { | |
2275 | .name = "mcbsp1", | |
2276 | .class = &omap3xxx_mcbsp_hwmod_class, | |
2277 | .mpu_irqs = omap3xxx_mcbsp1_irqs, | |
d826ebfa | 2278 | .sdma_reqs = omap2_mcbsp1_sdma_reqs, |
dc48e5fc | 2279 | .main_clk = "mcbsp1_fck", |
70034d38 VC |
2280 | .prcm = { |
2281 | .omap2 = { | |
2282 | .prcm_reg_id = 1, | |
dc48e5fc C |
2283 | .module_bit = OMAP3430_EN_MCBSP1_SHIFT, |
2284 | .module_offs = CORE_MOD, | |
70034d38 | 2285 | .idlest_reg_id = 1, |
dc48e5fc | 2286 | .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, |
70034d38 VC |
2287 | }, |
2288 | }, | |
dc48e5fc C |
2289 | .slaves = omap3xxx_mcbsp1_slaves, |
2290 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves), | |
70034d38 VC |
2291 | }; |
2292 | ||
dc48e5fc C |
2293 | /* mcbsp2 */ |
2294 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { | |
2295 | { .name = "irq", .irq = 17 }, | |
2296 | { .name = "tx", .irq = 62 }, | |
2297 | { .name = "rx", .irq = 63 }, | |
212738a4 | 2298 | { .irq = -1 } |
70034d38 VC |
2299 | }; |
2300 | ||
dc48e5fc C |
2301 | static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { |
2302 | { | |
2303 | .name = "mpu", | |
2304 | .pa_start = 0x49022000, | |
2305 | .pa_end = 0x490220ff, | |
2306 | .flags = ADDR_TYPE_RT | |
70034d38 | 2307 | }, |
78183f3f | 2308 | { } |
70034d38 VC |
2309 | }; |
2310 | ||
dc48e5fc C |
2311 | /* l4_per -> mcbsp2 */ |
2312 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { | |
2313 | .master = &omap3xxx_l4_per_hwmod, | |
2314 | .slave = &omap3xxx_mcbsp2_hwmod, | |
2315 | .clk = "mcbsp2_ick", | |
2316 | .addr = omap3xxx_mcbsp2_addrs, | |
dc48e5fc | 2317 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2318 | }; |
2319 | ||
dc48e5fc C |
2320 | /* mcbsp2 slave ports */ |
2321 | static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = { | |
2322 | &omap3xxx_l4_per__mcbsp2, | |
70034d38 VC |
2323 | }; |
2324 | ||
8b1906f1 KVA |
2325 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { |
2326 | .sidetone = "mcbsp2_sidetone", | |
70034d38 VC |
2327 | }; |
2328 | ||
dc48e5fc C |
2329 | static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { |
2330 | .name = "mcbsp2", | |
2331 | .class = &omap3xxx_mcbsp_hwmod_class, | |
2332 | .mpu_irqs = omap3xxx_mcbsp2_irqs, | |
d826ebfa | 2333 | .sdma_reqs = omap2_mcbsp2_sdma_reqs, |
dc48e5fc | 2334 | .main_clk = "mcbsp2_fck", |
70034d38 VC |
2335 | .prcm = { |
2336 | .omap2 = { | |
2337 | .prcm_reg_id = 1, | |
dc48e5fc | 2338 | .module_bit = OMAP3430_EN_MCBSP2_SHIFT, |
70034d38 VC |
2339 | .module_offs = OMAP3430_PER_MOD, |
2340 | .idlest_reg_id = 1, | |
dc48e5fc | 2341 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, |
70034d38 VC |
2342 | }, |
2343 | }, | |
dc48e5fc C |
2344 | .slaves = omap3xxx_mcbsp2_slaves, |
2345 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves), | |
8b1906f1 | 2346 | .dev_attr = &omap34xx_mcbsp2_dev_attr, |
70034d38 VC |
2347 | }; |
2348 | ||
dc48e5fc C |
2349 | /* mcbsp3 */ |
2350 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { | |
2351 | { .name = "irq", .irq = 22 }, | |
2352 | { .name = "tx", .irq = 89 }, | |
2353 | { .name = "rx", .irq = 90 }, | |
212738a4 | 2354 | { .irq = -1 } |
70034d38 VC |
2355 | }; |
2356 | ||
dc48e5fc C |
2357 | static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { |
2358 | { | |
2359 | .name = "mpu", | |
2360 | .pa_start = 0x49024000, | |
2361 | .pa_end = 0x490240ff, | |
2362 | .flags = ADDR_TYPE_RT | |
2363 | }, | |
78183f3f | 2364 | { } |
70034d38 VC |
2365 | }; |
2366 | ||
dc48e5fc C |
2367 | /* l4_per -> mcbsp3 */ |
2368 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { | |
2369 | .master = &omap3xxx_l4_per_hwmod, | |
2370 | .slave = &omap3xxx_mcbsp3_hwmod, | |
2371 | .clk = "mcbsp3_ick", | |
2372 | .addr = omap3xxx_mcbsp3_addrs, | |
dc48e5fc C |
2373 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2374 | }; | |
2375 | ||
2376 | /* mcbsp3 slave ports */ | |
2377 | static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = { | |
2378 | &omap3xxx_l4_per__mcbsp3, | |
2379 | }; | |
2380 | ||
8b1906f1 KVA |
2381 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { |
2382 | .sidetone = "mcbsp3_sidetone", | |
2383 | }; | |
2384 | ||
dc48e5fc C |
2385 | static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { |
2386 | .name = "mcbsp3", | |
2387 | .class = &omap3xxx_mcbsp_hwmod_class, | |
2388 | .mpu_irqs = omap3xxx_mcbsp3_irqs, | |
d826ebfa | 2389 | .sdma_reqs = omap2_mcbsp3_sdma_reqs, |
dc48e5fc | 2390 | .main_clk = "mcbsp3_fck", |
70034d38 VC |
2391 | .prcm = { |
2392 | .omap2 = { | |
2393 | .prcm_reg_id = 1, | |
dc48e5fc | 2394 | .module_bit = OMAP3430_EN_MCBSP3_SHIFT, |
70034d38 VC |
2395 | .module_offs = OMAP3430_PER_MOD, |
2396 | .idlest_reg_id = 1, | |
dc48e5fc | 2397 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, |
70034d38 VC |
2398 | }, |
2399 | }, | |
dc48e5fc C |
2400 | .slaves = omap3xxx_mcbsp3_slaves, |
2401 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves), | |
8b1906f1 | 2402 | .dev_attr = &omap34xx_mcbsp3_dev_attr, |
70034d38 VC |
2403 | }; |
2404 | ||
dc48e5fc C |
2405 | /* mcbsp4 */ |
2406 | static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { | |
2407 | { .name = "irq", .irq = 23 }, | |
2408 | { .name = "tx", .irq = 54 }, | |
2409 | { .name = "rx", .irq = 55 }, | |
212738a4 | 2410 | { .irq = -1 } |
70034d38 VC |
2411 | }; |
2412 | ||
dc48e5fc C |
2413 | static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { |
2414 | { .name = "rx", .dma_req = 20 }, | |
2415 | { .name = "tx", .dma_req = 19 }, | |
bc614958 | 2416 | { .dma_req = -1 } |
70034d38 VC |
2417 | }; |
2418 | ||
dc48e5fc C |
2419 | static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { |
2420 | { | |
2421 | .name = "mpu", | |
2422 | .pa_start = 0x49026000, | |
2423 | .pa_end = 0x490260ff, | |
2424 | .flags = ADDR_TYPE_RT | |
2425 | }, | |
78183f3f | 2426 | { } |
70034d38 VC |
2427 | }; |
2428 | ||
dc48e5fc C |
2429 | /* l4_per -> mcbsp4 */ |
2430 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { | |
2431 | .master = &omap3xxx_l4_per_hwmod, | |
2432 | .slave = &omap3xxx_mcbsp4_hwmod, | |
2433 | .clk = "mcbsp4_ick", | |
2434 | .addr = omap3xxx_mcbsp4_addrs, | |
dc48e5fc | 2435 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2436 | }; |
2437 | ||
dc48e5fc C |
2438 | /* mcbsp4 slave ports */ |
2439 | static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = { | |
2440 | &omap3xxx_l4_per__mcbsp4, | |
70034d38 VC |
2441 | }; |
2442 | ||
dc48e5fc C |
2443 | static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { |
2444 | .name = "mcbsp4", | |
2445 | .class = &omap3xxx_mcbsp_hwmod_class, | |
2446 | .mpu_irqs = omap3xxx_mcbsp4_irqs, | |
dc48e5fc | 2447 | .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, |
dc48e5fc | 2448 | .main_clk = "mcbsp4_fck", |
70034d38 VC |
2449 | .prcm = { |
2450 | .omap2 = { | |
2451 | .prcm_reg_id = 1, | |
dc48e5fc | 2452 | .module_bit = OMAP3430_EN_MCBSP4_SHIFT, |
70034d38 VC |
2453 | .module_offs = OMAP3430_PER_MOD, |
2454 | .idlest_reg_id = 1, | |
dc48e5fc | 2455 | .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, |
70034d38 VC |
2456 | }, |
2457 | }, | |
dc48e5fc C |
2458 | .slaves = omap3xxx_mcbsp4_slaves, |
2459 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves), | |
70034d38 VC |
2460 | }; |
2461 | ||
dc48e5fc C |
2462 | /* mcbsp5 */ |
2463 | static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { | |
2464 | { .name = "irq", .irq = 27 }, | |
2465 | { .name = "tx", .irq = 81 }, | |
2466 | { .name = "rx", .irq = 82 }, | |
212738a4 | 2467 | { .irq = -1 } |
70034d38 VC |
2468 | }; |
2469 | ||
dc48e5fc C |
2470 | static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { |
2471 | { .name = "rx", .dma_req = 22 }, | |
2472 | { .name = "tx", .dma_req = 21 }, | |
bc614958 | 2473 | { .dma_req = -1 } |
70034d38 VC |
2474 | }; |
2475 | ||
dc48e5fc C |
2476 | static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { |
2477 | { | |
2478 | .name = "mpu", | |
2479 | .pa_start = 0x48096000, | |
2480 | .pa_end = 0x480960ff, | |
2481 | .flags = ADDR_TYPE_RT | |
2482 | }, | |
78183f3f | 2483 | { } |
70034d38 VC |
2484 | }; |
2485 | ||
dc48e5fc C |
2486 | /* l4_core -> mcbsp5 */ |
2487 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { | |
2488 | .master = &omap3xxx_l4_core_hwmod, | |
2489 | .slave = &omap3xxx_mcbsp5_hwmod, | |
2490 | .clk = "mcbsp5_ick", | |
2491 | .addr = omap3xxx_mcbsp5_addrs, | |
dc48e5fc C |
2492 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2493 | }; | |
2494 | ||
2495 | /* mcbsp5 slave ports */ | |
2496 | static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = { | |
2497 | &omap3xxx_l4_core__mcbsp5, | |
2498 | }; | |
2499 | ||
2500 | static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { | |
2501 | .name = "mcbsp5", | |
2502 | .class = &omap3xxx_mcbsp_hwmod_class, | |
2503 | .mpu_irqs = omap3xxx_mcbsp5_irqs, | |
dc48e5fc | 2504 | .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, |
dc48e5fc | 2505 | .main_clk = "mcbsp5_fck", |
70034d38 VC |
2506 | .prcm = { |
2507 | .omap2 = { | |
2508 | .prcm_reg_id = 1, | |
dc48e5fc C |
2509 | .module_bit = OMAP3430_EN_MCBSP5_SHIFT, |
2510 | .module_offs = CORE_MOD, | |
70034d38 | 2511 | .idlest_reg_id = 1, |
dc48e5fc | 2512 | .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, |
70034d38 VC |
2513 | }, |
2514 | }, | |
dc48e5fc C |
2515 | .slaves = omap3xxx_mcbsp5_slaves, |
2516 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves), | |
70034d38 | 2517 | }; |
dc48e5fc | 2518 | /* 'mcbsp sidetone' class */ |
70034d38 | 2519 | |
dc48e5fc C |
2520 | static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { |
2521 | .sysc_offs = 0x0010, | |
2522 | .sysc_flags = SYSC_HAS_AUTOIDLE, | |
2523 | .sysc_fields = &omap_hwmod_sysc_type1, | |
01438ab6 MK |
2524 | }; |
2525 | ||
dc48e5fc C |
2526 | static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { |
2527 | .name = "mcbsp_sidetone", | |
2528 | .sysc = &omap3xxx_mcbsp_sidetone_sysc, | |
01438ab6 MK |
2529 | }; |
2530 | ||
dc48e5fc C |
2531 | /* mcbsp2_sidetone */ |
2532 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { | |
2533 | { .name = "irq", .irq = 4 }, | |
212738a4 | 2534 | { .irq = -1 } |
01438ab6 MK |
2535 | }; |
2536 | ||
dc48e5fc C |
2537 | static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { |
2538 | { | |
2539 | .name = "sidetone", | |
2540 | .pa_start = 0x49028000, | |
2541 | .pa_end = 0x490280ff, | |
2542 | .flags = ADDR_TYPE_RT | |
2543 | }, | |
78183f3f | 2544 | { } |
01438ab6 MK |
2545 | }; |
2546 | ||
dc48e5fc C |
2547 | /* l4_per -> mcbsp2_sidetone */ |
2548 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { | |
2549 | .master = &omap3xxx_l4_per_hwmod, | |
2550 | .slave = &omap3xxx_mcbsp2_sidetone_hwmod, | |
2551 | .clk = "mcbsp2_ick", | |
2552 | .addr = omap3xxx_mcbsp2_sidetone_addrs, | |
dc48e5fc | 2553 | .user = OCP_USER_MPU, |
01438ab6 MK |
2554 | }; |
2555 | ||
dc48e5fc C |
2556 | /* mcbsp2_sidetone slave ports */ |
2557 | static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = { | |
2558 | &omap3xxx_l4_per__mcbsp2_sidetone, | |
2559 | }; | |
2560 | ||
2561 | static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { | |
2562 | .name = "mcbsp2_sidetone", | |
2563 | .class = &omap3xxx_mcbsp_sidetone_hwmod_class, | |
2564 | .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, | |
dc48e5fc C |
2565 | .main_clk = "mcbsp2_fck", |
2566 | .prcm = { | |
2567 | .omap2 = { | |
2568 | .prcm_reg_id = 1, | |
2569 | .module_bit = OMAP3430_EN_MCBSP2_SHIFT, | |
2570 | .module_offs = OMAP3430_PER_MOD, | |
2571 | .idlest_reg_id = 1, | |
2572 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, | |
2573 | }, | |
01438ab6 | 2574 | }, |
dc48e5fc C |
2575 | .slaves = omap3xxx_mcbsp2_sidetone_slaves, |
2576 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves), | |
01438ab6 MK |
2577 | }; |
2578 | ||
dc48e5fc C |
2579 | /* mcbsp3_sidetone */ |
2580 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { | |
2581 | { .name = "irq", .irq = 5 }, | |
212738a4 | 2582 | { .irq = -1 } |
01438ab6 MK |
2583 | }; |
2584 | ||
dc48e5fc C |
2585 | static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { |
2586 | { | |
2587 | .name = "sidetone", | |
2588 | .pa_start = 0x4902A000, | |
2589 | .pa_end = 0x4902A0ff, | |
2590 | .flags = ADDR_TYPE_RT | |
2591 | }, | |
78183f3f | 2592 | { } |
01438ab6 MK |
2593 | }; |
2594 | ||
dc48e5fc C |
2595 | /* l4_per -> mcbsp3_sidetone */ |
2596 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { | |
2597 | .master = &omap3xxx_l4_per_hwmod, | |
2598 | .slave = &omap3xxx_mcbsp3_sidetone_hwmod, | |
2599 | .clk = "mcbsp3_ick", | |
2600 | .addr = omap3xxx_mcbsp3_sidetone_addrs, | |
dc48e5fc | 2601 | .user = OCP_USER_MPU, |
01438ab6 MK |
2602 | }; |
2603 | ||
dc48e5fc C |
2604 | /* mcbsp3_sidetone slave ports */ |
2605 | static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = { | |
2606 | &omap3xxx_l4_per__mcbsp3_sidetone, | |
2607 | }; | |
2608 | ||
2609 | static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { | |
2610 | .name = "mcbsp3_sidetone", | |
2611 | .class = &omap3xxx_mcbsp_sidetone_hwmod_class, | |
2612 | .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, | |
dc48e5fc C |
2613 | .main_clk = "mcbsp3_fck", |
2614 | .prcm = { | |
01438ab6 | 2615 | .omap2 = { |
dc48e5fc C |
2616 | .prcm_reg_id = 1, |
2617 | .module_bit = OMAP3430_EN_MCBSP3_SHIFT, | |
2618 | .module_offs = OMAP3430_PER_MOD, | |
2619 | .idlest_reg_id = 1, | |
2620 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, | |
01438ab6 MK |
2621 | }, |
2622 | }, | |
dc48e5fc C |
2623 | .slaves = omap3xxx_mcbsp3_sidetone_slaves, |
2624 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves), | |
01438ab6 MK |
2625 | }; |
2626 | ||
dc48e5fc | 2627 | |
d3442726 TG |
2628 | /* SR common */ |
2629 | static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { | |
2630 | .clkact_shift = 20, | |
2631 | }; | |
2632 | ||
2633 | static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { | |
2634 | .sysc_offs = 0x24, | |
2635 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), | |
2636 | .clockact = CLOCKACT_TEST_ICLK, | |
2637 | .sysc_fields = &omap34xx_sr_sysc_fields, | |
2638 | }; | |
2639 | ||
2640 | static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { | |
2641 | .name = "smartreflex", | |
2642 | .sysc = &omap34xx_sr_sysc, | |
2643 | .rev = 1, | |
2644 | }; | |
2645 | ||
2646 | static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { | |
2647 | .sidle_shift = 24, | |
2648 | .enwkup_shift = 26 | |
2649 | }; | |
2650 | ||
2651 | static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { | |
2652 | .sysc_offs = 0x38, | |
2653 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2654 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
2655 | SYSC_NO_CACHE), | |
2656 | .sysc_fields = &omap36xx_sr_sysc_fields, | |
2657 | }; | |
2658 | ||
2659 | static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { | |
2660 | .name = "smartreflex", | |
2661 | .sysc = &omap36xx_sr_sysc, | |
2662 | .rev = 2, | |
2663 | }; | |
2664 | ||
2665 | /* SR1 */ | |
2666 | static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = { | |
2667 | &omap3_l4_core__sr1, | |
2668 | }; | |
2669 | ||
2670 | static struct omap_hwmod omap34xx_sr1_hwmod = { | |
2671 | .name = "sr1_hwmod", | |
2672 | .class = &omap34xx_smartreflex_hwmod_class, | |
2673 | .main_clk = "sr1_fck", | |
280a7275 | 2674 | .vdd_name = "mpu_iva", |
d3442726 TG |
2675 | .prcm = { |
2676 | .omap2 = { | |
2677 | .prcm_reg_id = 1, | |
2678 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
2679 | .module_offs = WKUP_MOD, | |
2680 | .idlest_reg_id = 1, | |
2681 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
2682 | }, | |
2683 | }, | |
2684 | .slaves = omap3_sr1_slaves, | |
2685 | .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), | |
d3442726 TG |
2686 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
2687 | }; | |
2688 | ||
2689 | static struct omap_hwmod omap36xx_sr1_hwmod = { | |
2690 | .name = "sr1_hwmod", | |
2691 | .class = &omap36xx_smartreflex_hwmod_class, | |
2692 | .main_clk = "sr1_fck", | |
280a7275 | 2693 | .vdd_name = "mpu_iva", |
d3442726 TG |
2694 | .prcm = { |
2695 | .omap2 = { | |
2696 | .prcm_reg_id = 1, | |
2697 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
2698 | .module_offs = WKUP_MOD, | |
2699 | .idlest_reg_id = 1, | |
2700 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
2701 | }, | |
2702 | }, | |
2703 | .slaves = omap3_sr1_slaves, | |
2704 | .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), | |
d3442726 TG |
2705 | }; |
2706 | ||
2707 | /* SR2 */ | |
2708 | static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = { | |
2709 | &omap3_l4_core__sr2, | |
2710 | }; | |
2711 | ||
2712 | static struct omap_hwmod omap34xx_sr2_hwmod = { | |
2713 | .name = "sr2_hwmod", | |
2714 | .class = &omap34xx_smartreflex_hwmod_class, | |
2715 | .main_clk = "sr2_fck", | |
2716 | .vdd_name = "core", | |
2717 | .prcm = { | |
2718 | .omap2 = { | |
2719 | .prcm_reg_id = 1, | |
2720 | .module_bit = OMAP3430_EN_SR2_SHIFT, | |
2721 | .module_offs = WKUP_MOD, | |
2722 | .idlest_reg_id = 1, | |
2723 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, | |
2724 | }, | |
2725 | }, | |
2726 | .slaves = omap3_sr2_slaves, | |
2727 | .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), | |
d3442726 TG |
2728 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
2729 | }; | |
2730 | ||
2731 | static struct omap_hwmod omap36xx_sr2_hwmod = { | |
2732 | .name = "sr2_hwmod", | |
2733 | .class = &omap36xx_smartreflex_hwmod_class, | |
2734 | .main_clk = "sr2_fck", | |
2735 | .vdd_name = "core", | |
2736 | .prcm = { | |
2737 | .omap2 = { | |
2738 | .prcm_reg_id = 1, | |
2739 | .module_bit = OMAP3430_EN_SR2_SHIFT, | |
2740 | .module_offs = WKUP_MOD, | |
2741 | .idlest_reg_id = 1, | |
2742 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, | |
2743 | }, | |
2744 | }, | |
2745 | .slaves = omap3_sr2_slaves, | |
2746 | .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), | |
d3442726 TG |
2747 | }; |
2748 | ||
0f9dfdd3 FC |
2749 | /* |
2750 | * 'mailbox' class | |
2751 | * mailbox module allowing communication between the on-chip processors | |
2752 | * using a queued mailbox-interrupt mechanism. | |
2753 | */ | |
2754 | ||
2755 | static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { | |
2756 | .rev_offs = 0x000, | |
2757 | .sysc_offs = 0x010, | |
2758 | .syss_offs = 0x014, | |
2759 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
2760 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
2761 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2762 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2763 | }; | |
2764 | ||
2765 | static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { | |
2766 | .name = "mailbox", | |
2767 | .sysc = &omap3xxx_mailbox_sysc, | |
2768 | }; | |
2769 | ||
2770 | static struct omap_hwmod omap3xxx_mailbox_hwmod; | |
2771 | static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { | |
2772 | { .irq = 26 }, | |
212738a4 | 2773 | { .irq = -1 } |
0f9dfdd3 FC |
2774 | }; |
2775 | ||
2776 | static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { | |
2777 | { | |
2778 | .pa_start = 0x48094000, | |
2779 | .pa_end = 0x480941ff, | |
2780 | .flags = ADDR_TYPE_RT, | |
2781 | }, | |
78183f3f | 2782 | { } |
0f9dfdd3 FC |
2783 | }; |
2784 | ||
2785 | /* l4_core -> mailbox */ | |
2786 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { | |
2787 | .master = &omap3xxx_l4_core_hwmod, | |
2788 | .slave = &omap3xxx_mailbox_hwmod, | |
2789 | .addr = omap3xxx_mailbox_addrs, | |
0f9dfdd3 FC |
2790 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2791 | }; | |
2792 | ||
2793 | /* mailbox slave ports */ | |
2794 | static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = { | |
2795 | &omap3xxx_l4_core__mailbox, | |
2796 | }; | |
2797 | ||
2798 | static struct omap_hwmod omap3xxx_mailbox_hwmod = { | |
2799 | .name = "mailbox", | |
2800 | .class = &omap3xxx_mailbox_hwmod_class, | |
2801 | .mpu_irqs = omap3xxx_mailbox_irqs, | |
0f9dfdd3 FC |
2802 | .main_clk = "mailboxes_ick", |
2803 | .prcm = { | |
2804 | .omap2 = { | |
2805 | .prcm_reg_id = 1, | |
2806 | .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, | |
2807 | .module_offs = CORE_MOD, | |
2808 | .idlest_reg_id = 1, | |
2809 | .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, | |
2810 | }, | |
2811 | }, | |
2812 | .slaves = omap3xxx_mailbox_slaves, | |
2813 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves), | |
0f9dfdd3 FC |
2814 | }; |
2815 | ||
0f616a4e | 2816 | /* l4 core -> mcspi1 interface */ |
0f616a4e C |
2817 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { |
2818 | .master = &omap3xxx_l4_core_hwmod, | |
2819 | .slave = &omap34xx_mcspi1, | |
2820 | .clk = "mcspi1_ick", | |
ded11383 | 2821 | .addr = omap2_mcspi1_addr_space, |
0f616a4e C |
2822 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2823 | }; | |
2824 | ||
2825 | /* l4 core -> mcspi2 interface */ | |
0f616a4e C |
2826 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { |
2827 | .master = &omap3xxx_l4_core_hwmod, | |
2828 | .slave = &omap34xx_mcspi2, | |
2829 | .clk = "mcspi2_ick", | |
ded11383 | 2830 | .addr = omap2_mcspi2_addr_space, |
0f616a4e C |
2831 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2832 | }; | |
2833 | ||
2834 | /* l4 core -> mcspi3 interface */ | |
0f616a4e C |
2835 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { |
2836 | .master = &omap3xxx_l4_core_hwmod, | |
2837 | .slave = &omap34xx_mcspi3, | |
2838 | .clk = "mcspi3_ick", | |
ded11383 | 2839 | .addr = omap2430_mcspi3_addr_space, |
0f616a4e C |
2840 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2841 | }; | |
2842 | ||
2843 | /* l4 core -> mcspi4 interface */ | |
2844 | static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { | |
2845 | { | |
2846 | .pa_start = 0x480ba000, | |
2847 | .pa_end = 0x480ba0ff, | |
2848 | .flags = ADDR_TYPE_RT, | |
2849 | }, | |
78183f3f | 2850 | { } |
0f616a4e C |
2851 | }; |
2852 | ||
2853 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { | |
2854 | .master = &omap3xxx_l4_core_hwmod, | |
2855 | .slave = &omap34xx_mcspi4, | |
2856 | .clk = "mcspi4_ick", | |
2857 | .addr = omap34xx_mcspi4_addr_space, | |
0f616a4e C |
2858 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2859 | }; | |
2860 | ||
2861 | /* | |
2862 | * 'mcspi' class | |
2863 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
2864 | * bus | |
2865 | */ | |
2866 | ||
2867 | static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { | |
2868 | .rev_offs = 0x0000, | |
2869 | .sysc_offs = 0x0010, | |
2870 | .syss_offs = 0x0014, | |
2871 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
2872 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
2873 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
2874 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2875 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2876 | }; | |
2877 | ||
2878 | static struct omap_hwmod_class omap34xx_mcspi_class = { | |
2879 | .name = "mcspi", | |
2880 | .sysc = &omap34xx_mcspi_sysc, | |
2881 | .rev = OMAP3_MCSPI_REV, | |
2882 | }; | |
2883 | ||
2884 | /* mcspi1 */ | |
0f616a4e C |
2885 | static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = { |
2886 | &omap34xx_l4_core__mcspi1, | |
2887 | }; | |
2888 | ||
2889 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { | |
2890 | .num_chipselect = 4, | |
2891 | }; | |
2892 | ||
2893 | static struct omap_hwmod omap34xx_mcspi1 = { | |
2894 | .name = "mcspi1", | |
0d619a89 | 2895 | .mpu_irqs = omap2_mcspi1_mpu_irqs, |
d826ebfa | 2896 | .sdma_reqs = omap2_mcspi1_sdma_reqs, |
0f616a4e C |
2897 | .main_clk = "mcspi1_fck", |
2898 | .prcm = { | |
2899 | .omap2 = { | |
2900 | .module_offs = CORE_MOD, | |
2901 | .prcm_reg_id = 1, | |
2902 | .module_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
2903 | .idlest_reg_id = 1, | |
2904 | .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, | |
2905 | }, | |
2906 | }, | |
2907 | .slaves = omap34xx_mcspi1_slaves, | |
2908 | .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves), | |
2909 | .class = &omap34xx_mcspi_class, | |
2910 | .dev_attr = &omap_mcspi1_dev_attr, | |
0f616a4e C |
2911 | }; |
2912 | ||
2913 | /* mcspi2 */ | |
0f616a4e C |
2914 | static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = { |
2915 | &omap34xx_l4_core__mcspi2, | |
2916 | }; | |
2917 | ||
2918 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { | |
2919 | .num_chipselect = 2, | |
2920 | }; | |
2921 | ||
2922 | static struct omap_hwmod omap34xx_mcspi2 = { | |
2923 | .name = "mcspi2", | |
0d619a89 | 2924 | .mpu_irqs = omap2_mcspi2_mpu_irqs, |
d826ebfa | 2925 | .sdma_reqs = omap2_mcspi2_sdma_reqs, |
0f616a4e | 2926 | .main_clk = "mcspi2_fck", |
70034d38 VC |
2927 | .prcm = { |
2928 | .omap2 = { | |
0f616a4e | 2929 | .module_offs = CORE_MOD, |
70034d38 | 2930 | .prcm_reg_id = 1, |
0f616a4e | 2931 | .module_bit = OMAP3430_EN_MCSPI2_SHIFT, |
70034d38 | 2932 | .idlest_reg_id = 1, |
0f616a4e | 2933 | .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, |
70034d38 VC |
2934 | }, |
2935 | }, | |
0f616a4e C |
2936 | .slaves = omap34xx_mcspi2_slaves, |
2937 | .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves), | |
2938 | .class = &omap34xx_mcspi_class, | |
2939 | .dev_attr = &omap_mcspi2_dev_attr, | |
70034d38 VC |
2940 | }; |
2941 | ||
0f616a4e C |
2942 | /* mcspi3 */ |
2943 | static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { | |
2944 | { .name = "irq", .irq = 91 }, /* 91 */ | |
212738a4 | 2945 | { .irq = -1 } |
70034d38 VC |
2946 | }; |
2947 | ||
0f616a4e C |
2948 | static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { |
2949 | { .name = "tx0", .dma_req = 15 }, | |
2950 | { .name = "rx0", .dma_req = 16 }, | |
2951 | { .name = "tx1", .dma_req = 23 }, | |
2952 | { .name = "rx1", .dma_req = 24 }, | |
bc614958 | 2953 | { .dma_req = -1 } |
70034d38 VC |
2954 | }; |
2955 | ||
0f616a4e C |
2956 | static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = { |
2957 | &omap34xx_l4_core__mcspi3, | |
70034d38 VC |
2958 | }; |
2959 | ||
0f616a4e C |
2960 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { |
2961 | .num_chipselect = 2, | |
2962 | }; | |
2963 | ||
2964 | static struct omap_hwmod omap34xx_mcspi3 = { | |
2965 | .name = "mcspi3", | |
2966 | .mpu_irqs = omap34xx_mcspi3_mpu_irqs, | |
0f616a4e | 2967 | .sdma_reqs = omap34xx_mcspi3_sdma_reqs, |
0f616a4e | 2968 | .main_clk = "mcspi3_fck", |
70034d38 VC |
2969 | .prcm = { |
2970 | .omap2 = { | |
0f616a4e | 2971 | .module_offs = CORE_MOD, |
70034d38 | 2972 | .prcm_reg_id = 1, |
0f616a4e | 2973 | .module_bit = OMAP3430_EN_MCSPI3_SHIFT, |
70034d38 | 2974 | .idlest_reg_id = 1, |
0f616a4e | 2975 | .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, |
70034d38 VC |
2976 | }, |
2977 | }, | |
0f616a4e C |
2978 | .slaves = omap34xx_mcspi3_slaves, |
2979 | .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves), | |
2980 | .class = &omap34xx_mcspi_class, | |
2981 | .dev_attr = &omap_mcspi3_dev_attr, | |
70034d38 VC |
2982 | }; |
2983 | ||
0f616a4e C |
2984 | /* SPI4 */ |
2985 | static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { | |
2986 | { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ | |
212738a4 | 2987 | { .irq = -1 } |
70034d38 VC |
2988 | }; |
2989 | ||
0f616a4e C |
2990 | static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { |
2991 | { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ | |
2992 | { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ | |
bc614958 | 2993 | { .dma_req = -1 } |
70034d38 VC |
2994 | }; |
2995 | ||
0f616a4e C |
2996 | static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = { |
2997 | &omap34xx_l4_core__mcspi4, | |
70034d38 VC |
2998 | }; |
2999 | ||
0f616a4e C |
3000 | static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { |
3001 | .num_chipselect = 1, | |
3002 | }; | |
3003 | ||
3004 | static struct omap_hwmod omap34xx_mcspi4 = { | |
3005 | .name = "mcspi4", | |
3006 | .mpu_irqs = omap34xx_mcspi4_mpu_irqs, | |
0f616a4e | 3007 | .sdma_reqs = omap34xx_mcspi4_sdma_reqs, |
0f616a4e | 3008 | .main_clk = "mcspi4_fck", |
70034d38 VC |
3009 | .prcm = { |
3010 | .omap2 = { | |
0f616a4e | 3011 | .module_offs = CORE_MOD, |
70034d38 | 3012 | .prcm_reg_id = 1, |
0f616a4e | 3013 | .module_bit = OMAP3430_EN_MCSPI4_SHIFT, |
70034d38 | 3014 | .idlest_reg_id = 1, |
0f616a4e | 3015 | .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, |
70034d38 VC |
3016 | }, |
3017 | }, | |
0f616a4e C |
3018 | .slaves = omap34xx_mcspi4_slaves, |
3019 | .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves), | |
3020 | .class = &omap34xx_mcspi_class, | |
3021 | .dev_attr = &omap_mcspi4_dev_attr, | |
70034d38 VC |
3022 | }; |
3023 | ||
870ea2b8 HH |
3024 | /* |
3025 | * usbhsotg | |
3026 | */ | |
3027 | static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { | |
3028 | .rev_offs = 0x0400, | |
3029 | .sysc_offs = 0x0404, | |
3030 | .syss_offs = 0x0408, | |
3031 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| | |
3032 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
3033 | SYSC_HAS_AUTOIDLE), | |
01438ab6 | 3034 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
870ea2b8 | 3035 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
01438ab6 MK |
3036 | .sysc_fields = &omap_hwmod_sysc_type1, |
3037 | }; | |
3038 | ||
870ea2b8 HH |
3039 | static struct omap_hwmod_class usbotg_class = { |
3040 | .name = "usbotg", | |
3041 | .sysc = &omap3xxx_usbhsotg_sysc, | |
01438ab6 | 3042 | }; |
870ea2b8 HH |
3043 | /* usb_otg_hs */ |
3044 | static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { | |
01438ab6 | 3045 | |
870ea2b8 HH |
3046 | { .name = "mc", .irq = 92 }, |
3047 | { .name = "dma", .irq = 93 }, | |
212738a4 | 3048 | { .irq = -1 } |
01438ab6 MK |
3049 | }; |
3050 | ||
870ea2b8 HH |
3051 | static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { |
3052 | .name = "usb_otg_hs", | |
3053 | .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, | |
870ea2b8 HH |
3054 | .main_clk = "hsotgusb_ick", |
3055 | .prcm = { | |
3056 | .omap2 = { | |
3057 | .prcm_reg_id = 1, | |
3058 | .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, | |
3059 | .module_offs = CORE_MOD, | |
3060 | .idlest_reg_id = 1, | |
3061 | .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, | |
3062 | .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT | |
3063 | }, | |
01438ab6 | 3064 | }, |
870ea2b8 HH |
3065 | .masters = omap3xxx_usbhsotg_masters, |
3066 | .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters), | |
3067 | .slaves = omap3xxx_usbhsotg_slaves, | |
3068 | .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves), | |
3069 | .class = &usbotg_class, | |
3070 | ||
3071 | /* | |
3072 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially | |
3073 | * broken when autoidle is enabled | |
3074 | * workaround is to disable the autoidle bit at module level. | |
3075 | */ | |
3076 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | |
3077 | | HWMOD_SWSUP_MSTANDBY, | |
01438ab6 MK |
3078 | }; |
3079 | ||
273ff8c3 HH |
3080 | /* usb_otg_hs */ |
3081 | static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { | |
01438ab6 | 3082 | |
273ff8c3 | 3083 | { .name = "mc", .irq = 71 }, |
212738a4 | 3084 | { .irq = -1 } |
01438ab6 MK |
3085 | }; |
3086 | ||
273ff8c3 HH |
3087 | static struct omap_hwmod_class am35xx_usbotg_class = { |
3088 | .name = "am35xx_usbotg", | |
3089 | .sysc = NULL, | |
01438ab6 MK |
3090 | }; |
3091 | ||
273ff8c3 HH |
3092 | static struct omap_hwmod am35xx_usbhsotg_hwmod = { |
3093 | .name = "am35x_otg_hs", | |
3094 | .mpu_irqs = am35xx_usbhsotg_mpu_irqs, | |
273ff8c3 | 3095 | .main_clk = NULL, |
01438ab6 MK |
3096 | .prcm = { |
3097 | .omap2 = { | |
01438ab6 MK |
3098 | }, |
3099 | }, | |
273ff8c3 HH |
3100 | .masters = am35xx_usbhsotg_masters, |
3101 | .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters), | |
3102 | .slaves = am35xx_usbhsotg_slaves, | |
3103 | .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves), | |
3104 | .class = &am35xx_usbotg_class, | |
01438ab6 MK |
3105 | }; |
3106 | ||
b163605e PW |
3107 | /* MMC/SD/SDIO common */ |
3108 | ||
3109 | static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { | |
3110 | .rev_offs = 0x1fc, | |
3111 | .sysc_offs = 0x10, | |
3112 | .syss_offs = 0x14, | |
3113 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
3114 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
3115 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
3116 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
3117 | .sysc_fields = &omap_hwmod_sysc_type1, | |
d3442726 TG |
3118 | }; |
3119 | ||
b163605e PW |
3120 | static struct omap_hwmod_class omap34xx_mmc_class = { |
3121 | .name = "mmc", | |
3122 | .sysc = &omap34xx_mmc_sysc, | |
d3442726 TG |
3123 | }; |
3124 | ||
b163605e PW |
3125 | /* MMC/SD/SDIO1 */ |
3126 | ||
3127 | static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { | |
3128 | { .irq = 83, }, | |
212738a4 | 3129 | { .irq = -1 } |
d3442726 TG |
3130 | }; |
3131 | ||
b163605e PW |
3132 | static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { |
3133 | { .name = "tx", .dma_req = 61, }, | |
3134 | { .name = "rx", .dma_req = 62, }, | |
bc614958 | 3135 | { .dma_req = -1 } |
d3442726 TG |
3136 | }; |
3137 | ||
b163605e PW |
3138 | static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { |
3139 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
d3442726 TG |
3140 | }; |
3141 | ||
b163605e PW |
3142 | static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = { |
3143 | &omap3xxx_l4_core__mmc1, | |
d3442726 TG |
3144 | }; |
3145 | ||
6ab8946f KK |
3146 | static struct omap_mmc_dev_attr mmc1_dev_attr = { |
3147 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
d3442726 TG |
3148 | }; |
3149 | ||
a52e2ab6 PW |
3150 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ |
3151 | static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = { | |
3152 | .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | | |
3153 | OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), | |
3154 | }; | |
3155 | ||
3156 | static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { | |
3157 | .name = "mmc1", | |
3158 | .mpu_irqs = omap34xx_mmc1_mpu_irqs, | |
3159 | .sdma_reqs = omap34xx_mmc1_sdma_reqs, | |
3160 | .opt_clks = omap34xx_mmc1_opt_clks, | |
3161 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), | |
3162 | .main_clk = "mmchs1_fck", | |
3163 | .prcm = { | |
3164 | .omap2 = { | |
3165 | .module_offs = CORE_MOD, | |
3166 | .prcm_reg_id = 1, | |
3167 | .module_bit = OMAP3430_EN_MMC1_SHIFT, | |
3168 | .idlest_reg_id = 1, | |
3169 | .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, | |
3170 | }, | |
3171 | }, | |
3172 | .dev_attr = &mmc1_pre_es3_dev_attr, | |
3173 | .slaves = omap3xxx_mmc1_slaves, | |
3174 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves), | |
3175 | .class = &omap34xx_mmc_class, | |
3176 | }; | |
3177 | ||
3178 | static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { | |
b163605e PW |
3179 | .name = "mmc1", |
3180 | .mpu_irqs = omap34xx_mmc1_mpu_irqs, | |
b163605e | 3181 | .sdma_reqs = omap34xx_mmc1_sdma_reqs, |
b163605e PW |
3182 | .opt_clks = omap34xx_mmc1_opt_clks, |
3183 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), | |
3184 | .main_clk = "mmchs1_fck", | |
d3442726 TG |
3185 | .prcm = { |
3186 | .omap2 = { | |
b163605e | 3187 | .module_offs = CORE_MOD, |
d3442726 | 3188 | .prcm_reg_id = 1, |
b163605e | 3189 | .module_bit = OMAP3430_EN_MMC1_SHIFT, |
d3442726 | 3190 | .idlest_reg_id = 1, |
b163605e | 3191 | .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, |
d3442726 TG |
3192 | }, |
3193 | }, | |
6ab8946f | 3194 | .dev_attr = &mmc1_dev_attr, |
b163605e PW |
3195 | .slaves = omap3xxx_mmc1_slaves, |
3196 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves), | |
3197 | .class = &omap34xx_mmc_class, | |
d3442726 TG |
3198 | }; |
3199 | ||
b163605e PW |
3200 | /* MMC/SD/SDIO2 */ |
3201 | ||
3202 | static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { | |
3203 | { .irq = INT_24XX_MMC2_IRQ, }, | |
212738a4 | 3204 | { .irq = -1 } |
d3442726 TG |
3205 | }; |
3206 | ||
b163605e PW |
3207 | static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { |
3208 | { .name = "tx", .dma_req = 47, }, | |
3209 | { .name = "rx", .dma_req = 48, }, | |
bc614958 | 3210 | { .dma_req = -1 } |
d3442726 TG |
3211 | }; |
3212 | ||
b163605e PW |
3213 | static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { |
3214 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
3215 | }; | |
3216 | ||
3217 | static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = { | |
3218 | &omap3xxx_l4_core__mmc2, | |
3219 | }; | |
3220 | ||
a52e2ab6 PW |
3221 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ |
3222 | static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { | |
3223 | .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, | |
3224 | }; | |
3225 | ||
3226 | static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { | |
3227 | .name = "mmc2", | |
3228 | .mpu_irqs = omap34xx_mmc2_mpu_irqs, | |
3229 | .sdma_reqs = omap34xx_mmc2_sdma_reqs, | |
3230 | .opt_clks = omap34xx_mmc2_opt_clks, | |
3231 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), | |
3232 | .main_clk = "mmchs2_fck", | |
3233 | .prcm = { | |
3234 | .omap2 = { | |
3235 | .module_offs = CORE_MOD, | |
3236 | .prcm_reg_id = 1, | |
3237 | .module_bit = OMAP3430_EN_MMC2_SHIFT, | |
3238 | .idlest_reg_id = 1, | |
3239 | .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, | |
3240 | }, | |
3241 | }, | |
3242 | .dev_attr = &mmc2_pre_es3_dev_attr, | |
3243 | .slaves = omap3xxx_mmc2_slaves, | |
3244 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves), | |
3245 | .class = &omap34xx_mmc_class, | |
3246 | }; | |
3247 | ||
3248 | static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { | |
b163605e PW |
3249 | .name = "mmc2", |
3250 | .mpu_irqs = omap34xx_mmc2_mpu_irqs, | |
b163605e | 3251 | .sdma_reqs = omap34xx_mmc2_sdma_reqs, |
b163605e PW |
3252 | .opt_clks = omap34xx_mmc2_opt_clks, |
3253 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), | |
3254 | .main_clk = "mmchs2_fck", | |
d3442726 TG |
3255 | .prcm = { |
3256 | .omap2 = { | |
b163605e | 3257 | .module_offs = CORE_MOD, |
d3442726 | 3258 | .prcm_reg_id = 1, |
b163605e | 3259 | .module_bit = OMAP3430_EN_MMC2_SHIFT, |
d3442726 | 3260 | .idlest_reg_id = 1, |
b163605e | 3261 | .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, |
d3442726 TG |
3262 | }, |
3263 | }, | |
b163605e PW |
3264 | .slaves = omap3xxx_mmc2_slaves, |
3265 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves), | |
3266 | .class = &omap34xx_mmc_class, | |
d3442726 TG |
3267 | }; |
3268 | ||
b163605e PW |
3269 | /* MMC/SD/SDIO3 */ |
3270 | ||
3271 | static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { | |
3272 | { .irq = 94, }, | |
212738a4 | 3273 | { .irq = -1 } |
b163605e PW |
3274 | }; |
3275 | ||
3276 | static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { | |
3277 | { .name = "tx", .dma_req = 77, }, | |
3278 | { .name = "rx", .dma_req = 78, }, | |
bc614958 | 3279 | { .dma_req = -1 } |
b163605e PW |
3280 | }; |
3281 | ||
3282 | static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { | |
3283 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
3284 | }; | |
3285 | ||
3286 | static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = { | |
3287 | &omap3xxx_l4_core__mmc3, | |
3288 | }; | |
3289 | ||
3290 | static struct omap_hwmod omap3xxx_mmc3_hwmod = { | |
3291 | .name = "mmc3", | |
3292 | .mpu_irqs = omap34xx_mmc3_mpu_irqs, | |
b163605e | 3293 | .sdma_reqs = omap34xx_mmc3_sdma_reqs, |
b163605e PW |
3294 | .opt_clks = omap34xx_mmc3_opt_clks, |
3295 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), | |
3296 | .main_clk = "mmchs3_fck", | |
d3442726 TG |
3297 | .prcm = { |
3298 | .omap2 = { | |
3299 | .prcm_reg_id = 1, | |
b163605e | 3300 | .module_bit = OMAP3430_EN_MMC3_SHIFT, |
d3442726 | 3301 | .idlest_reg_id = 1, |
b163605e | 3302 | .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, |
d3442726 TG |
3303 | }, |
3304 | }, | |
b163605e PW |
3305 | .slaves = omap3xxx_mmc3_slaves, |
3306 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves), | |
3307 | .class = &omap34xx_mmc_class, | |
d3442726 TG |
3308 | }; |
3309 | ||
de231388 KM |
3310 | /* |
3311 | * 'usb_host_hs' class | |
3312 | * high-speed multi-port usb host controller | |
3313 | */ | |
3314 | static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { | |
3315 | .master = &omap3xxx_usb_host_hs_hwmod, | |
3316 | .slave = &omap3xxx_l3_main_hwmod, | |
3317 | .clk = "core_l3_ick", | |
3318 | .user = OCP_USER_MPU, | |
3319 | }; | |
3320 | ||
3321 | static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { | |
3322 | .rev_offs = 0x0000, | |
3323 | .sysc_offs = 0x0010, | |
3324 | .syss_offs = 0x0014, | |
3325 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
3326 | SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
3327 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
3328 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3329 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
3330 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3331 | }; | |
3332 | ||
3333 | static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { | |
3334 | .name = "usb_host_hs", | |
3335 | .sysc = &omap3xxx_usb_host_hs_sysc, | |
3336 | }; | |
3337 | ||
3338 | static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_masters[] = { | |
3339 | &omap3xxx_usb_host_hs__l3_main_2, | |
3340 | }; | |
3341 | ||
3342 | static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = { | |
3343 | { | |
3344 | .name = "uhh", | |
3345 | .pa_start = 0x48064000, | |
3346 | .pa_end = 0x480643ff, | |
3347 | .flags = ADDR_TYPE_RT | |
3348 | }, | |
3349 | { | |
3350 | .name = "ohci", | |
3351 | .pa_start = 0x48064400, | |
3352 | .pa_end = 0x480647ff, | |
3353 | }, | |
3354 | { | |
3355 | .name = "ehci", | |
3356 | .pa_start = 0x48064800, | |
3357 | .pa_end = 0x48064cff, | |
3358 | }, | |
3359 | {} | |
3360 | }; | |
3361 | ||
3362 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { | |
3363 | .master = &omap3xxx_l4_core_hwmod, | |
3364 | .slave = &omap3xxx_usb_host_hs_hwmod, | |
3365 | .clk = "usbhost_ick", | |
3366 | .addr = omap3xxx_usb_host_hs_addrs, | |
3367 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3368 | }; | |
3369 | ||
3370 | static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_slaves[] = { | |
3371 | &omap3xxx_l4_core__usb_host_hs, | |
3372 | }; | |
3373 | ||
3374 | static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { | |
3375 | { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, | |
3376 | }; | |
3377 | ||
3378 | static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { | |
3379 | { .name = "ohci-irq", .irq = 76 }, | |
3380 | { .name = "ehci-irq", .irq = 77 }, | |
3381 | { .irq = -1 } | |
3382 | }; | |
3383 | ||
3384 | static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { | |
3385 | .name = "usb_host_hs", | |
3386 | .class = &omap3xxx_usb_host_hs_hwmod_class, | |
3387 | .clkdm_name = "l3_init_clkdm", | |
3388 | .mpu_irqs = omap3xxx_usb_host_hs_irqs, | |
3389 | .main_clk = "usbhost_48m_fck", | |
3390 | .prcm = { | |
3391 | .omap2 = { | |
3392 | .module_offs = OMAP3430ES2_USBHOST_MOD, | |
3393 | .prcm_reg_id = 1, | |
3394 | .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, | |
3395 | .idlest_reg_id = 1, | |
3396 | .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, | |
3397 | .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, | |
3398 | }, | |
3399 | }, | |
3400 | .opt_clks = omap3xxx_usb_host_hs_opt_clks, | |
3401 | .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks), | |
3402 | .slaves = omap3xxx_usb_host_hs_slaves, | |
3403 | .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_slaves), | |
3404 | .masters = omap3xxx_usb_host_hs_masters, | |
3405 | .masters_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_masters), | |
3406 | ||
3407 | /* | |
3408 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
3409 | * id: i660 | |
3410 | * | |
3411 | * Description: | |
3412 | * In the following configuration : | |
3413 | * - USBHOST module is set to smart-idle mode | |
3414 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
3415 | * happens when the system is going to a low power mode : all ports | |
3416 | * have been suspended, the master part of the USBHOST module has | |
3417 | * entered the standby state, and SW has cut the functional clocks) | |
3418 | * - an USBHOST interrupt occurs before the module is able to answer | |
3419 | * idle_ack, typically a remote wakeup IRQ. | |
3420 | * Then the USB HOST module will enter a deadlock situation where it | |
3421 | * is no more accessible nor functional. | |
3422 | * | |
3423 | * Workaround: | |
3424 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
3425 | */ | |
3426 | ||
3427 | /* | |
3428 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
3429 | * Id: i571 | |
3430 | * | |
3431 | * Description: | |
3432 | * When the USBHOST module is set to smart-standby mode, and when it is | |
3433 | * ready to enter the standby state (i.e. all ports are suspended and | |
3434 | * all attached devices are in suspend mode), then it can wrongly assert | |
3435 | * the Mstandby signal too early while there are still some residual OCP | |
3436 | * transactions ongoing. If this condition occurs, the internal state | |
3437 | * machine may go to an undefined state and the USB link may be stuck | |
3438 | * upon the next resume. | |
3439 | * | |
3440 | * Workaround: | |
3441 | * Don't use smart standby; use only force standby, | |
3442 | * hence HWMOD_SWSUP_MSTANDBY | |
3443 | */ | |
3444 | ||
3445 | /* | |
3446 | * During system boot; If the hwmod framework resets the module | |
3447 | * the module will have smart idle settings; which can lead to deadlock | |
3448 | * (above Errata Id:i660); so, dont reset the module during boot; | |
3449 | * Use HWMOD_INIT_NO_RESET. | |
3450 | */ | |
3451 | ||
3452 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | | |
3453 | HWMOD_INIT_NO_RESET, | |
3454 | }; | |
3455 | ||
3456 | /* | |
3457 | * 'usb_tll_hs' class | |
3458 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
3459 | */ | |
3460 | static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { | |
3461 | .rev_offs = 0x0000, | |
3462 | .sysc_offs = 0x0010, | |
3463 | .syss_offs = 0x0014, | |
3464 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
3465 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
3466 | SYSC_HAS_AUTOIDLE), | |
3467 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
3468 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3469 | }; | |
3470 | ||
3471 | static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { | |
3472 | .name = "usb_tll_hs", | |
3473 | .sysc = &omap3xxx_usb_tll_hs_sysc, | |
3474 | }; | |
3475 | ||
3476 | static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { | |
3477 | { .name = "tll-irq", .irq = 78 }, | |
3478 | { .irq = -1 } | |
3479 | }; | |
3480 | ||
3481 | static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { | |
3482 | { | |
3483 | .name = "tll", | |
3484 | .pa_start = 0x48062000, | |
3485 | .pa_end = 0x48062fff, | |
3486 | .flags = ADDR_TYPE_RT | |
3487 | }, | |
3488 | {} | |
3489 | }; | |
3490 | ||
3491 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { | |
3492 | .master = &omap3xxx_l4_core_hwmod, | |
3493 | .slave = &omap3xxx_usb_tll_hs_hwmod, | |
3494 | .clk = "usbtll_ick", | |
3495 | .addr = omap3xxx_usb_tll_hs_addrs, | |
3496 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3497 | }; | |
3498 | ||
3499 | static struct omap_hwmod_ocp_if *omap3xxx_usb_tll_hs_slaves[] = { | |
3500 | &omap3xxx_l4_core__usb_tll_hs, | |
3501 | }; | |
3502 | ||
3503 | static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { | |
3504 | .name = "usb_tll_hs", | |
3505 | .class = &omap3xxx_usb_tll_hs_hwmod_class, | |
3506 | .clkdm_name = "l3_init_clkdm", | |
3507 | .mpu_irqs = omap3xxx_usb_tll_hs_irqs, | |
3508 | .main_clk = "usbtll_fck", | |
3509 | .prcm = { | |
3510 | .omap2 = { | |
3511 | .module_offs = CORE_MOD, | |
3512 | .prcm_reg_id = 3, | |
3513 | .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | |
3514 | .idlest_reg_id = 3, | |
3515 | .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, | |
3516 | }, | |
3517 | }, | |
3518 | .slaves = omap3xxx_usb_tll_hs_slaves, | |
3519 | .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_tll_hs_slaves), | |
3520 | }; | |
3521 | ||
7359154e | 3522 | static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { |
4a7cf90a | 3523 | &omap3xxx_l3_main_hwmod, |
7359154e PW |
3524 | &omap3xxx_l4_core_hwmod, |
3525 | &omap3xxx_l4_per_hwmod, | |
3526 | &omap3xxx_l4_wkup_hwmod, | |
b163605e | 3527 | &omap3xxx_mmc3_hwmod, |
7359154e | 3528 | &omap3xxx_mpu_hwmod, |
ce722d26 TG |
3529 | |
3530 | &omap3xxx_timer1_hwmod, | |
3531 | &omap3xxx_timer2_hwmod, | |
3532 | &omap3xxx_timer3_hwmod, | |
3533 | &omap3xxx_timer4_hwmod, | |
3534 | &omap3xxx_timer5_hwmod, | |
3535 | &omap3xxx_timer6_hwmod, | |
3536 | &omap3xxx_timer7_hwmod, | |
3537 | &omap3xxx_timer8_hwmod, | |
3538 | &omap3xxx_timer9_hwmod, | |
3539 | &omap3xxx_timer10_hwmod, | |
3540 | &omap3xxx_timer11_hwmod, | |
ce722d26 | 3541 | |
6b667f88 | 3542 | &omap3xxx_wd_timer2_hwmod, |
046465b7 KH |
3543 | &omap3xxx_uart1_hwmod, |
3544 | &omap3xxx_uart2_hwmod, | |
3545 | &omap3xxx_uart3_hwmod, | |
de231388 | 3546 | |
e04d9e1e | 3547 | /* dss class */ |
e04d9e1e SG |
3548 | &omap3xxx_dss_dispc_hwmod, |
3549 | &omap3xxx_dss_dsi1_hwmod, | |
3550 | &omap3xxx_dss_rfbi_hwmod, | |
3551 | &omap3xxx_dss_venc_hwmod, | |
3552 | ||
3553 | /* i2c class */ | |
4fe20e97 RN |
3554 | &omap3xxx_i2c1_hwmod, |
3555 | &omap3xxx_i2c2_hwmod, | |
3556 | &omap3xxx_i2c3_hwmod, | |
70034d38 VC |
3557 | |
3558 | /* gpio class */ | |
3559 | &omap3xxx_gpio1_hwmod, | |
3560 | &omap3xxx_gpio2_hwmod, | |
3561 | &omap3xxx_gpio3_hwmod, | |
3562 | &omap3xxx_gpio4_hwmod, | |
3563 | &omap3xxx_gpio5_hwmod, | |
3564 | &omap3xxx_gpio6_hwmod, | |
01438ab6 MK |
3565 | |
3566 | /* dma_system class*/ | |
3567 | &omap3xxx_dma_system_hwmod, | |
0f616a4e | 3568 | |
dc48e5fc C |
3569 | /* mcbsp class */ |
3570 | &omap3xxx_mcbsp1_hwmod, | |
3571 | &omap3xxx_mcbsp2_hwmod, | |
3572 | &omap3xxx_mcbsp3_hwmod, | |
3573 | &omap3xxx_mcbsp4_hwmod, | |
3574 | &omap3xxx_mcbsp5_hwmod, | |
3575 | &omap3xxx_mcbsp2_sidetone_hwmod, | |
3576 | &omap3xxx_mcbsp3_sidetone_hwmod, | |
3577 | ||
0f9dfdd3 | 3578 | |
0f616a4e C |
3579 | /* mcspi class */ |
3580 | &omap34xx_mcspi1, | |
3581 | &omap34xx_mcspi2, | |
3582 | &omap34xx_mcspi3, | |
3583 | &omap34xx_mcspi4, | |
04aa67de | 3584 | |
d6504acd PW |
3585 | NULL, |
3586 | }; | |
3587 | ||
91a36bdb AK |
3588 | /* GP-only hwmods */ |
3589 | static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = { | |
3590 | &omap3xxx_timer12_hwmod, | |
3591 | NULL | |
3592 | }; | |
3593 | ||
d6504acd PW |
3594 | /* 3430ES1-only hwmods */ |
3595 | static __initdata struct omap_hwmod *omap3430es1_hwmods[] = { | |
3596 | &omap3430es1_dss_core_hwmod, | |
3597 | NULL | |
3598 | }; | |
3599 | ||
3600 | /* 3430ES2+-only hwmods */ | |
3601 | static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = { | |
3602 | &omap3xxx_dss_core_hwmod, | |
870ea2b8 | 3603 | &omap3xxx_usbhsotg_hwmod, |
de231388 KM |
3604 | &omap3xxx_usb_host_hs_hwmod, |
3605 | &omap3xxx_usb_tll_hs_hwmod, | |
d6504acd PW |
3606 | NULL |
3607 | }; | |
870ea2b8 | 3608 | |
a52e2ab6 PW |
3609 | /* <= 3430ES3-only hwmods */ |
3610 | static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = { | |
3611 | &omap3xxx_pre_es3_mmc1_hwmod, | |
3612 | &omap3xxx_pre_es3_mmc2_hwmod, | |
3613 | NULL | |
3614 | }; | |
3615 | ||
3616 | /* 3430ES3+-only hwmods */ | |
3617 | static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = { | |
3618 | &omap3xxx_es3plus_mmc1_hwmod, | |
3619 | &omap3xxx_es3plus_mmc2_hwmod, | |
3620 | NULL | |
3621 | }; | |
3622 | ||
d6504acd PW |
3623 | /* 34xx-only hwmods (all ES revisions) */ |
3624 | static __initdata struct omap_hwmod *omap34xx_hwmods[] = { | |
7e89098c | 3625 | &omap3xxx_iva_hwmod, |
d6504acd PW |
3626 | &omap34xx_sr1_hwmod, |
3627 | &omap34xx_sr2_hwmod, | |
7e89098c | 3628 | &omap3xxx_mailbox_hwmod, |
d6504acd PW |
3629 | NULL |
3630 | }; | |
273ff8c3 | 3631 | |
d6504acd PW |
3632 | /* 36xx-only hwmods (all ES revisions) */ |
3633 | static __initdata struct omap_hwmod *omap36xx_hwmods[] = { | |
7e89098c | 3634 | &omap3xxx_iva_hwmod, |
d6504acd PW |
3635 | &omap3xxx_uart4_hwmod, |
3636 | &omap3xxx_dss_core_hwmod, | |
3637 | &omap36xx_sr1_hwmod, | |
3638 | &omap36xx_sr2_hwmod, | |
3639 | &omap3xxx_usbhsotg_hwmod, | |
7e89098c | 3640 | &omap3xxx_mailbox_hwmod, |
de231388 KM |
3641 | &omap3xxx_usb_host_hs_hwmod, |
3642 | &omap3xxx_usb_tll_hs_hwmod, | |
a52e2ab6 PW |
3643 | &omap3xxx_es3plus_mmc1_hwmod, |
3644 | &omap3xxx_es3plus_mmc2_hwmod, | |
d6504acd PW |
3645 | NULL |
3646 | }; | |
3647 | ||
3648 | static __initdata struct omap_hwmod *am35xx_hwmods[] = { | |
3649 | &omap3xxx_dss_core_hwmod, /* XXX ??? */ | |
3650 | &am35xx_usbhsotg_hwmod, | |
4bf90f65 | 3651 | &am35xx_uart4_hwmod, |
de231388 KM |
3652 | &omap3xxx_usb_host_hs_hwmod, |
3653 | &omap3xxx_usb_tll_hs_hwmod, | |
a52e2ab6 PW |
3654 | &omap3xxx_es3plus_mmc1_hwmod, |
3655 | &omap3xxx_es3plus_mmc2_hwmod, | |
d6504acd | 3656 | NULL |
7359154e PW |
3657 | }; |
3658 | ||
3659 | int __init omap3xxx_hwmod_init(void) | |
3660 | { | |
d6504acd PW |
3661 | int r; |
3662 | struct omap_hwmod **h = NULL; | |
3663 | unsigned int rev; | |
3664 | ||
3665 | /* Register hwmods common to all OMAP3 */ | |
3666 | r = omap_hwmod_register(omap3xxx_hwmods); | |
ace90216 | 3667 | if (r < 0) |
d6504acd PW |
3668 | return r; |
3669 | ||
91a36bdb AK |
3670 | /* Register GP-only hwmods. */ |
3671 | if (omap_type() == OMAP2_DEVICE_TYPE_GP) { | |
3672 | r = omap_hwmod_register(omap3xxx_gp_hwmods); | |
3673 | if (r < 0) | |
3674 | return r; | |
3675 | } | |
3676 | ||
d6504acd PW |
3677 | rev = omap_rev(); |
3678 | ||
3679 | /* | |
3680 | * Register hwmods common to individual OMAP3 families, all | |
3681 | * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) | |
3682 | * All possible revisions should be included in this conditional. | |
3683 | */ | |
3684 | if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || | |
3685 | rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || | |
3686 | rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { | |
3687 | h = omap34xx_hwmods; | |
3688 | } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) { | |
3689 | h = am35xx_hwmods; | |
3690 | } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || | |
3691 | rev == OMAP3630_REV_ES1_2) { | |
3692 | h = omap36xx_hwmods; | |
3693 | } else { | |
3694 | WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); | |
3695 | return -EINVAL; | |
3696 | }; | |
3697 | ||
3698 | r = omap_hwmod_register(h); | |
ace90216 | 3699 | if (r < 0) |
d6504acd PW |
3700 | return r; |
3701 | ||
3702 | /* | |
3703 | * Register hwmods specific to certain ES levels of a | |
3704 | * particular family of silicon (e.g., 34xx ES1.0) | |
3705 | */ | |
3706 | h = NULL; | |
3707 | if (rev == OMAP3430_REV_ES1_0) { | |
3708 | h = omap3430es1_hwmods; | |
3709 | } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || | |
3710 | rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || | |
3711 | rev == OMAP3430_REV_ES3_1_2) { | |
3712 | h = omap3430es2plus_hwmods; | |
3713 | }; | |
3714 | ||
a52e2ab6 PW |
3715 | if (h) { |
3716 | r = omap_hwmod_register(h); | |
3717 | if (r < 0) | |
3718 | return r; | |
3719 | } | |
3720 | ||
3721 | h = NULL; | |
3722 | if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || | |
3723 | rev == OMAP3430_REV_ES2_1) { | |
3724 | h = omap3430_pre_es3_hwmods; | |
3725 | } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || | |
3726 | rev == OMAP3430_REV_ES3_1_2) { | |
3727 | h = omap3430_es3plus_hwmods; | |
3728 | }; | |
3729 | ||
d6504acd PW |
3730 | if (h) |
3731 | r = omap_hwmod_register(h); | |
3732 | ||
3733 | return r; | |
7359154e | 3734 | } |