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7359154e PW |
1 | /* |
2 | * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips | |
3 | * | |
78183f3f | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
0a78c5c5 | 5 | * Copyright (C) 2012 Texas Instruments, Inc. |
7359154e PW |
6 | * Paul Walmsley |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * The data in this file should be completely autogeneratable from | |
13 | * the TI hardware database or other technical documentation. | |
14 | * | |
15 | * XXX these should be marked initdata for multi-OMAP kernels | |
16 | */ | |
17 | #include <plat/omap_hwmod.h> | |
18 | #include <mach/irqs.h> | |
19 | #include <plat/cpu.h> | |
20 | #include <plat/dma.h> | |
046465b7 | 21 | #include <plat/serial.h> |
e04d9e1e | 22 | #include <plat/l3_3xxx.h> |
4fe20e97 RN |
23 | #include <plat/l4_3xxx.h> |
24 | #include <plat/i2c.h> | |
70034d38 | 25 | #include <plat/gpio.h> |
6ab8946f | 26 | #include <plat/mmc.h> |
dc48e5fc | 27 | #include <plat/mcbsp.h> |
0f616a4e | 28 | #include <plat/mcspi.h> |
ce722d26 | 29 | #include <plat/dmtimer.h> |
7359154e | 30 | |
43b40992 PW |
31 | #include "omap_hwmod_common_data.h" |
32 | ||
cea6b942 | 33 | #include "smartreflex.h" |
7359154e | 34 | #include "prm-regbits-34xx.h" |
6b667f88 | 35 | #include "cm-regbits-34xx.h" |
ff2516fb | 36 | #include "wd_timer.h" |
273ff8c3 | 37 | #include <mach/am35xx.h> |
7359154e PW |
38 | |
39 | /* | |
40 | * OMAP3xxx hardware module integration data | |
41 | * | |
844a3b63 | 42 | * All of the data in this section should be autogeneratable from the |
7359154e PW |
43 | * TI hardware database or other technical documentation. Data that |
44 | * is driver-specific or driver-kernel integration-specific belongs | |
45 | * elsewhere. | |
46 | */ | |
47 | ||
844a3b63 PW |
48 | /* |
49 | * IP blocks | |
50 | */ | |
7359154e | 51 | |
844a3b63 | 52 | /* L3 */ |
4bb194dc | 53 | static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { |
54 | { .irq = INT_34XX_L3_DBG_IRQ }, | |
55 | { .irq = INT_34XX_L3_APP_IRQ }, | |
212738a4 | 56 | { .irq = -1 } |
4bb194dc | 57 | }; |
58 | ||
4a7cf90a | 59 | static struct omap_hwmod omap3xxx_l3_main_hwmod = { |
fa98347e | 60 | .name = "l3_main", |
43b40992 | 61 | .class = &l3_hwmod_class, |
0d619a89 | 62 | .mpu_irqs = omap3xxx_l3_main_irqs, |
2eb1875d | 63 | .flags = HWMOD_NO_IDLEST, |
7359154e PW |
64 | }; |
65 | ||
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66 | /* L4 CORE */ |
67 | static struct omap_hwmod omap3xxx_l4_core_hwmod = { | |
68 | .name = "l4_core", | |
69 | .class = &l4_hwmod_class, | |
70 | .flags = HWMOD_NO_IDLEST, | |
870ea2b8 | 71 | }; |
7359154e | 72 | |
844a3b63 PW |
73 | /* L4 PER */ |
74 | static struct omap_hwmod omap3xxx_l4_per_hwmod = { | |
75 | .name = "l4_per", | |
76 | .class = &l4_hwmod_class, | |
77 | .flags = HWMOD_NO_IDLEST, | |
273ff8c3 | 78 | }; |
844a3b63 PW |
79 | |
80 | /* L4 WKUP */ | |
81 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { | |
82 | .name = "l4_wkup", | |
83 | .class = &l4_hwmod_class, | |
84 | .flags = HWMOD_NO_IDLEST, | |
7359154e PW |
85 | }; |
86 | ||
844a3b63 PW |
87 | /* L4 SEC */ |
88 | static struct omap_hwmod omap3xxx_l4_sec_hwmod = { | |
89 | .name = "l4_sec", | |
90 | .class = &l4_hwmod_class, | |
91 | .flags = HWMOD_NO_IDLEST, | |
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92 | }; |
93 | ||
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94 | /* MPU */ |
95 | static struct omap_hwmod omap3xxx_mpu_hwmod = { | |
96 | .name = "mpu", | |
97 | .class = &mpu_hwmod_class, | |
98 | .main_clk = "arm_fck", | |
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99 | }; |
100 | ||
844a3b63 | 101 | /* IVA2 (IVA2) */ |
f42c5496 PW |
102 | static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = { |
103 | { .name = "logic", .rst_shift = 0 }, | |
104 | { .name = "seq0", .rst_shift = 1 }, | |
105 | { .name = "seq1", .rst_shift = 2 }, | |
106 | }; | |
107 | ||
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108 | static struct omap_hwmod omap3xxx_iva_hwmod = { |
109 | .name = "iva", | |
110 | .class = &iva_hwmod_class, | |
f42c5496 PW |
111 | .clkdm_name = "iva2_clkdm", |
112 | .rst_lines = omap3xxx_iva_resets, | |
113 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets), | |
114 | .main_clk = "iva2_ck", | |
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115 | }; |
116 | ||
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117 | /* timer class */ |
118 | static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { | |
119 | .rev_offs = 0x0000, | |
120 | .sysc_offs = 0x0010, | |
121 | .syss_offs = 0x0014, | |
122 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
123 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
124 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), | |
125 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
126 | .sysc_fields = &omap_hwmod_sysc_type1, | |
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127 | }; |
128 | ||
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129 | static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { |
130 | .name = "timer", | |
131 | .sysc = &omap3xxx_timer_1ms_sysc, | |
132 | .rev = OMAP_TIMER_IP_VERSION_1, | |
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133 | }; |
134 | ||
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135 | static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { |
136 | .rev_offs = 0x0000, | |
137 | .sysc_offs = 0x0010, | |
138 | .syss_offs = 0x0014, | |
139 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
140 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
141 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
142 | .sysc_fields = &omap_hwmod_sysc_type1, | |
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143 | }; |
144 | ||
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145 | static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { |
146 | .name = "timer", | |
147 | .sysc = &omap3xxx_timer_sysc, | |
148 | .rev = OMAP_TIMER_IP_VERSION_1, | |
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149 | }; |
150 | ||
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151 | /* secure timers dev attribute */ |
152 | static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { | |
153 | .timer_capability = OMAP_TIMER_SECURE, | |
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154 | }; |
155 | ||
844a3b63 PW |
156 | /* always-on timers dev attribute */ |
157 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
158 | .timer_capability = OMAP_TIMER_ALWON, | |
046465b7 KH |
159 | }; |
160 | ||
844a3b63 PW |
161 | /* pwm timers dev attribute */ |
162 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
163 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
046465b7 KH |
164 | }; |
165 | ||
844a3b63 PW |
166 | /* timer1 */ |
167 | static struct omap_hwmod omap3xxx_timer1_hwmod = { | |
168 | .name = "timer1", | |
169 | .mpu_irqs = omap2_timer1_mpu_irqs, | |
170 | .main_clk = "gpt1_fck", | |
171 | .prcm = { | |
172 | .omap2 = { | |
173 | .prcm_reg_id = 1, | |
174 | .module_bit = OMAP3430_EN_GPT1_SHIFT, | |
175 | .module_offs = WKUP_MOD, | |
176 | .idlest_reg_id = 1, | |
177 | .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, | |
178 | }, | |
046465b7 | 179 | }, |
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180 | .dev_attr = &capability_alwon_dev_attr, |
181 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
046465b7 KH |
182 | }; |
183 | ||
844a3b63 PW |
184 | /* timer2 */ |
185 | static struct omap_hwmod omap3xxx_timer2_hwmod = { | |
186 | .name = "timer2", | |
187 | .mpu_irqs = omap2_timer2_mpu_irqs, | |
188 | .main_clk = "gpt2_fck", | |
189 | .prcm = { | |
190 | .omap2 = { | |
191 | .prcm_reg_id = 1, | |
192 | .module_bit = OMAP3430_EN_GPT2_SHIFT, | |
193 | .module_offs = OMAP3430_PER_MOD, | |
194 | .idlest_reg_id = 1, | |
195 | .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, | |
196 | }, | |
197 | }, | |
198 | .dev_attr = &capability_alwon_dev_attr, | |
199 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
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200 | }; |
201 | ||
844a3b63 PW |
202 | /* timer3 */ |
203 | static struct omap_hwmod omap3xxx_timer3_hwmod = { | |
204 | .name = "timer3", | |
205 | .mpu_irqs = omap2_timer3_mpu_irqs, | |
206 | .main_clk = "gpt3_fck", | |
207 | .prcm = { | |
208 | .omap2 = { | |
209 | .prcm_reg_id = 1, | |
210 | .module_bit = OMAP3430_EN_GPT3_SHIFT, | |
211 | .module_offs = OMAP3430_PER_MOD, | |
212 | .idlest_reg_id = 1, | |
213 | .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, | |
214 | }, | |
215 | }, | |
216 | .dev_attr = &capability_alwon_dev_attr, | |
217 | .class = &omap3xxx_timer_hwmod_class, | |
046465b7 KH |
218 | }; |
219 | ||
844a3b63 PW |
220 | /* timer4 */ |
221 | static struct omap_hwmod omap3xxx_timer4_hwmod = { | |
222 | .name = "timer4", | |
223 | .mpu_irqs = omap2_timer4_mpu_irqs, | |
224 | .main_clk = "gpt4_fck", | |
225 | .prcm = { | |
226 | .omap2 = { | |
227 | .prcm_reg_id = 1, | |
228 | .module_bit = OMAP3430_EN_GPT4_SHIFT, | |
229 | .module_offs = OMAP3430_PER_MOD, | |
230 | .idlest_reg_id = 1, | |
231 | .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, | |
232 | }, | |
233 | }, | |
234 | .dev_attr = &capability_alwon_dev_attr, | |
235 | .class = &omap3xxx_timer_hwmod_class, | |
046465b7 KH |
236 | }; |
237 | ||
844a3b63 PW |
238 | /* timer5 */ |
239 | static struct omap_hwmod omap3xxx_timer5_hwmod = { | |
240 | .name = "timer5", | |
241 | .mpu_irqs = omap2_timer5_mpu_irqs, | |
242 | .main_clk = "gpt5_fck", | |
243 | .prcm = { | |
244 | .omap2 = { | |
245 | .prcm_reg_id = 1, | |
246 | .module_bit = OMAP3430_EN_GPT5_SHIFT, | |
247 | .module_offs = OMAP3430_PER_MOD, | |
248 | .idlest_reg_id = 1, | |
249 | .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, | |
250 | }, | |
4bf90f65 | 251 | }, |
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252 | .dev_attr = &capability_alwon_dev_attr, |
253 | .class = &omap3xxx_timer_hwmod_class, | |
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254 | }; |
255 | ||
844a3b63 PW |
256 | /* timer6 */ |
257 | static struct omap_hwmod omap3xxx_timer6_hwmod = { | |
258 | .name = "timer6", | |
259 | .mpu_irqs = omap2_timer6_mpu_irqs, | |
260 | .main_clk = "gpt6_fck", | |
261 | .prcm = { | |
262 | .omap2 = { | |
263 | .prcm_reg_id = 1, | |
264 | .module_bit = OMAP3430_EN_GPT6_SHIFT, | |
265 | .module_offs = OMAP3430_PER_MOD, | |
266 | .idlest_reg_id = 1, | |
267 | .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, | |
268 | }, | |
269 | }, | |
270 | .dev_attr = &capability_alwon_dev_attr, | |
271 | .class = &omap3xxx_timer_hwmod_class, | |
4bf90f65 KM |
272 | }; |
273 | ||
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274 | /* timer7 */ |
275 | static struct omap_hwmod omap3xxx_timer7_hwmod = { | |
276 | .name = "timer7", | |
277 | .mpu_irqs = omap2_timer7_mpu_irqs, | |
278 | .main_clk = "gpt7_fck", | |
279 | .prcm = { | |
4fe20e97 | 280 | .omap2 = { |
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281 | .prcm_reg_id = 1, |
282 | .module_bit = OMAP3430_EN_GPT7_SHIFT, | |
283 | .module_offs = OMAP3430_PER_MOD, | |
284 | .idlest_reg_id = 1, | |
285 | .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, | |
286 | }, | |
4fe20e97 | 287 | }, |
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288 | .dev_attr = &capability_alwon_dev_attr, |
289 | .class = &omap3xxx_timer_hwmod_class, | |
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290 | }; |
291 | ||
844a3b63 PW |
292 | /* timer8 */ |
293 | static struct omap_hwmod omap3xxx_timer8_hwmod = { | |
294 | .name = "timer8", | |
295 | .mpu_irqs = omap2_timer8_mpu_irqs, | |
296 | .main_clk = "gpt8_fck", | |
297 | .prcm = { | |
4fe20e97 | 298 | .omap2 = { |
844a3b63 PW |
299 | .prcm_reg_id = 1, |
300 | .module_bit = OMAP3430_EN_GPT8_SHIFT, | |
301 | .module_offs = OMAP3430_PER_MOD, | |
302 | .idlest_reg_id = 1, | |
303 | .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, | |
304 | }, | |
4fe20e97 | 305 | }, |
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306 | .dev_attr = &capability_pwm_dev_attr, |
307 | .class = &omap3xxx_timer_hwmod_class, | |
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308 | }; |
309 | ||
844a3b63 PW |
310 | /* timer9 */ |
311 | static struct omap_hwmod omap3xxx_timer9_hwmod = { | |
312 | .name = "timer9", | |
313 | .mpu_irqs = omap2_timer9_mpu_irqs, | |
314 | .main_clk = "gpt9_fck", | |
315 | .prcm = { | |
316 | .omap2 = { | |
317 | .prcm_reg_id = 1, | |
318 | .module_bit = OMAP3430_EN_GPT9_SHIFT, | |
319 | .module_offs = OMAP3430_PER_MOD, | |
320 | .idlest_reg_id = 1, | |
321 | .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, | |
322 | }, | |
4fe20e97 | 323 | }, |
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324 | .dev_attr = &capability_pwm_dev_attr, |
325 | .class = &omap3xxx_timer_hwmod_class, | |
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326 | }; |
327 | ||
844a3b63 PW |
328 | /* timer10 */ |
329 | static struct omap_hwmod omap3xxx_timer10_hwmod = { | |
330 | .name = "timer10", | |
331 | .mpu_irqs = omap2_timer10_mpu_irqs, | |
332 | .main_clk = "gpt10_fck", | |
333 | .prcm = { | |
4fe20e97 | 334 | .omap2 = { |
844a3b63 PW |
335 | .prcm_reg_id = 1, |
336 | .module_bit = OMAP3430_EN_GPT10_SHIFT, | |
337 | .module_offs = CORE_MOD, | |
338 | .idlest_reg_id = 1, | |
339 | .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, | |
340 | }, | |
4fe20e97 | 341 | }, |
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342 | .dev_attr = &capability_pwm_dev_attr, |
343 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
4fe20e97 RN |
344 | }; |
345 | ||
844a3b63 PW |
346 | /* timer11 */ |
347 | static struct omap_hwmod omap3xxx_timer11_hwmod = { | |
348 | .name = "timer11", | |
349 | .mpu_irqs = omap2_timer11_mpu_irqs, | |
350 | .main_clk = "gpt11_fck", | |
351 | .prcm = { | |
352 | .omap2 = { | |
353 | .prcm_reg_id = 1, | |
354 | .module_bit = OMAP3430_EN_GPT11_SHIFT, | |
355 | .module_offs = CORE_MOD, | |
356 | .idlest_reg_id = 1, | |
357 | .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, | |
358 | }, | |
359 | }, | |
360 | .dev_attr = &capability_pwm_dev_attr, | |
361 | .class = &omap3xxx_timer_hwmod_class, | |
d62bc78a NM |
362 | }; |
363 | ||
844a3b63 PW |
364 | /* timer12 */ |
365 | static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { | |
366 | { .irq = 95, }, | |
d62bc78a NM |
367 | { .irq = -1 } |
368 | }; | |
369 | ||
844a3b63 PW |
370 | static struct omap_hwmod omap3xxx_timer12_hwmod = { |
371 | .name = "timer12", | |
372 | .mpu_irqs = omap3xxx_timer12_mpu_irqs, | |
373 | .main_clk = "gpt12_fck", | |
374 | .prcm = { | |
375 | .omap2 = { | |
376 | .prcm_reg_id = 1, | |
377 | .module_bit = OMAP3430_EN_GPT12_SHIFT, | |
378 | .module_offs = WKUP_MOD, | |
379 | .idlest_reg_id = 1, | |
380 | .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, | |
381 | }, | |
d3442726 | 382 | }, |
844a3b63 PW |
383 | .dev_attr = &capability_secure_dev_attr, |
384 | .class = &omap3xxx_timer_hwmod_class, | |
d3442726 TG |
385 | }; |
386 | ||
844a3b63 PW |
387 | /* |
388 | * 'wd_timer' class | |
389 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
390 | * overflow condition | |
391 | */ | |
392 | ||
393 | static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { | |
394 | .rev_offs = 0x0000, | |
395 | .sysc_offs = 0x0010, | |
396 | .syss_offs = 0x0014, | |
397 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | | |
398 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
399 | SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
400 | SYSS_HAS_RESET_STATUS), | |
401 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
402 | .sysc_fields = &omap_hwmod_sysc_type1, | |
d3442726 TG |
403 | }; |
404 | ||
844a3b63 PW |
405 | /* I2C common */ |
406 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
407 | .rev_offs = 0x00, | |
408 | .sysc_offs = 0x20, | |
409 | .syss_offs = 0x10, | |
410 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
411 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
412 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
413 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
414 | .clockact = CLOCKACT_TEST_ICLK, | |
415 | .sysc_fields = &omap_hwmod_sysc_type1, | |
d3442726 TG |
416 | }; |
417 | ||
844a3b63 PW |
418 | static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { |
419 | .name = "wd_timer", | |
420 | .sysc = &omap3xxx_wd_timer_sysc, | |
421 | .pre_shutdown = &omap2_wd_timer_disable | |
d3442726 TG |
422 | }; |
423 | ||
844a3b63 PW |
424 | static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { |
425 | .name = "wd_timer2", | |
426 | .class = &omap3xxx_wd_timer_hwmod_class, | |
427 | .main_clk = "wdt2_fck", | |
428 | .prcm = { | |
429 | .omap2 = { | |
430 | .prcm_reg_id = 1, | |
431 | .module_bit = OMAP3430_EN_WDT2_SHIFT, | |
432 | .module_offs = WKUP_MOD, | |
433 | .idlest_reg_id = 1, | |
434 | .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, | |
435 | }, | |
436 | }, | |
437 | /* | |
438 | * XXX: Use software supervised mode, HW supervised smartidle seems to | |
439 | * block CORE power domain idle transitions. Maybe a HW bug in wdt2? | |
440 | */ | |
441 | .flags = HWMOD_SWSUP_SIDLE, | |
442 | }; | |
870ea2b8 | 443 | |
844a3b63 PW |
444 | /* UART1 */ |
445 | static struct omap_hwmod omap3xxx_uart1_hwmod = { | |
446 | .name = "uart1", | |
447 | .mpu_irqs = omap2_uart1_mpu_irqs, | |
448 | .sdma_reqs = omap2_uart1_sdma_reqs, | |
449 | .main_clk = "uart1_fck", | |
450 | .prcm = { | |
451 | .omap2 = { | |
452 | .module_offs = CORE_MOD, | |
453 | .prcm_reg_id = 1, | |
454 | .module_bit = OMAP3430_EN_UART1_SHIFT, | |
455 | .idlest_reg_id = 1, | |
456 | .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, | |
457 | }, | |
870ea2b8 | 458 | }, |
844a3b63 | 459 | .class = &omap2_uart_class, |
870ea2b8 HH |
460 | }; |
461 | ||
844a3b63 PW |
462 | /* UART2 */ |
463 | static struct omap_hwmod omap3xxx_uart2_hwmod = { | |
464 | .name = "uart2", | |
465 | .mpu_irqs = omap2_uart2_mpu_irqs, | |
466 | .sdma_reqs = omap2_uart2_sdma_reqs, | |
467 | .main_clk = "uart2_fck", | |
468 | .prcm = { | |
469 | .omap2 = { | |
470 | .module_offs = CORE_MOD, | |
471 | .prcm_reg_id = 1, | |
472 | .module_bit = OMAP3430_EN_UART2_SHIFT, | |
473 | .idlest_reg_id = 1, | |
474 | .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, | |
475 | }, | |
476 | }, | |
477 | .class = &omap2_uart_class, | |
870ea2b8 HH |
478 | }; |
479 | ||
844a3b63 PW |
480 | /* UART3 */ |
481 | static struct omap_hwmod omap3xxx_uart3_hwmod = { | |
482 | .name = "uart3", | |
483 | .mpu_irqs = omap2_uart3_mpu_irqs, | |
484 | .sdma_reqs = omap2_uart3_sdma_reqs, | |
485 | .main_clk = "uart3_fck", | |
486 | .prcm = { | |
487 | .omap2 = { | |
488 | .module_offs = OMAP3430_PER_MOD, | |
489 | .prcm_reg_id = 1, | |
490 | .module_bit = OMAP3430_EN_UART3_SHIFT, | |
491 | .idlest_reg_id = 1, | |
492 | .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, | |
493 | }, | |
273ff8c3 | 494 | }, |
844a3b63 | 495 | .class = &omap2_uart_class, |
273ff8c3 HH |
496 | }; |
497 | ||
844a3b63 PW |
498 | /* UART4 */ |
499 | static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { | |
500 | { .irq = INT_36XX_UART4_IRQ, }, | |
501 | { .irq = -1 } | |
273ff8c3 HH |
502 | }; |
503 | ||
844a3b63 PW |
504 | static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { |
505 | { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, | |
506 | { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, | |
507 | { .dma_req = -1 } | |
7359154e PW |
508 | }; |
509 | ||
844a3b63 PW |
510 | static struct omap_hwmod omap36xx_uart4_hwmod = { |
511 | .name = "uart4", | |
512 | .mpu_irqs = uart4_mpu_irqs, | |
513 | .sdma_reqs = uart4_sdma_reqs, | |
514 | .main_clk = "uart4_fck", | |
515 | .prcm = { | |
516 | .omap2 = { | |
517 | .module_offs = OMAP3430_PER_MOD, | |
518 | .prcm_reg_id = 1, | |
519 | .module_bit = OMAP3630_EN_UART4_SHIFT, | |
520 | .idlest_reg_id = 1, | |
521 | .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, | |
522 | }, | |
523 | }, | |
524 | .class = &omap2_uart_class, | |
7359154e PW |
525 | }; |
526 | ||
844a3b63 PW |
527 | static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { |
528 | { .irq = INT_35XX_UART4_IRQ, }, | |
43085705 PW |
529 | }; |
530 | ||
844a3b63 PW |
531 | static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { |
532 | { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, | |
533 | { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, | |
7359154e PW |
534 | }; |
535 | ||
844a3b63 PW |
536 | static struct omap_hwmod am35xx_uart4_hwmod = { |
537 | .name = "uart4", | |
538 | .mpu_irqs = am35xx_uart4_mpu_irqs, | |
539 | .sdma_reqs = am35xx_uart4_sdma_reqs, | |
540 | .main_clk = "uart4_fck", | |
541 | .prcm = { | |
542 | .omap2 = { | |
543 | .module_offs = CORE_MOD, | |
544 | .prcm_reg_id = 1, | |
545 | .module_bit = OMAP3430_EN_UART4_SHIFT, | |
546 | .idlest_reg_id = 1, | |
547 | .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT, | |
548 | }, | |
549 | }, | |
550 | .class = &omap2_uart_class, | |
551 | }; | |
552 | ||
553 | static struct omap_hwmod_class i2c_class = { | |
554 | .name = "i2c", | |
555 | .sysc = &i2c_sysc, | |
556 | .rev = OMAP_I2C_IP_VERSION_1, | |
557 | .reset = &omap_i2c_reset, | |
558 | }; | |
559 | ||
560 | static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { | |
561 | { .name = "dispc", .dma_req = 5 }, | |
562 | { .name = "dsi1", .dma_req = 74 }, | |
563 | { .dma_req = -1 } | |
43085705 PW |
564 | }; |
565 | ||
844a3b63 PW |
566 | /* dss */ |
567 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
568 | /* | |
569 | * The DSS HW needs all DSS clocks enabled during reset. The dss_core | |
570 | * driver does not use these clocks. | |
571 | */ | |
572 | { .role = "sys_clk", .clk = "dss2_alwon_fck" }, | |
573 | { .role = "tv_clk", .clk = "dss_tv_fck" }, | |
574 | /* required only on OMAP3430 */ | |
575 | { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, | |
7359154e PW |
576 | }; |
577 | ||
844a3b63 PW |
578 | static struct omap_hwmod omap3430es1_dss_core_hwmod = { |
579 | .name = "dss_core", | |
580 | .class = &omap2_dss_hwmod_class, | |
581 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ | |
582 | .sdma_reqs = omap3xxx_dss_sdma_chs, | |
583 | .prcm = { | |
584 | .omap2 = { | |
585 | .prcm_reg_id = 1, | |
586 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
587 | .module_offs = OMAP3430_DSS_MOD, | |
588 | .idlest_reg_id = 1, | |
589 | .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, | |
590 | }, | |
591 | }, | |
592 | .opt_clks = dss_opt_clks, | |
593 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
594 | .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
595 | }; | |
540064bf | 596 | |
844a3b63 PW |
597 | static struct omap_hwmod omap3xxx_dss_core_hwmod = { |
598 | .name = "dss_core", | |
599 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
600 | .class = &omap2_dss_hwmod_class, | |
601 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ | |
602 | .sdma_reqs = omap3xxx_dss_sdma_chs, | |
603 | .prcm = { | |
604 | .omap2 = { | |
605 | .prcm_reg_id = 1, | |
606 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
607 | .module_offs = OMAP3430_DSS_MOD, | |
608 | .idlest_reg_id = 1, | |
609 | .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, | |
610 | .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, | |
611 | }, | |
612 | }, | |
613 | .opt_clks = dss_opt_clks, | |
614 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
540064bf KH |
615 | }; |
616 | ||
540064bf | 617 | /* |
844a3b63 PW |
618 | * 'dispc' class |
619 | * display controller | |
540064bf KH |
620 | */ |
621 | ||
844a3b63 | 622 | static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { |
ce722d26 TG |
623 | .rev_offs = 0x0000, |
624 | .sysc_offs = 0x0010, | |
625 | .syss_offs = 0x0014, | |
844a3b63 PW |
626 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | |
627 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
628 | SYSC_HAS_ENAWAKEUP), | |
629 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
630 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
ce722d26 | 631 | .sysc_fields = &omap_hwmod_sysc_type1, |
6b667f88 VC |
632 | }; |
633 | ||
844a3b63 PW |
634 | static struct omap_hwmod_class omap3_dispc_hwmod_class = { |
635 | .name = "dispc", | |
636 | .sysc = &omap3_dispc_sysc, | |
6b667f88 VC |
637 | }; |
638 | ||
844a3b63 PW |
639 | static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { |
640 | .name = "dss_dispc", | |
641 | .class = &omap3_dispc_hwmod_class, | |
642 | .mpu_irqs = omap2_dispc_irqs, | |
643 | .main_clk = "dss1_alwon_fck", | |
644 | .prcm = { | |
645 | .omap2 = { | |
646 | .prcm_reg_id = 1, | |
647 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
648 | .module_offs = OMAP3430_DSS_MOD, | |
649 | }, | |
650 | }, | |
651 | .flags = HWMOD_NO_IDLEST, | |
652 | .dev_attr = &omap2_3_dss_dispc_dev_attr | |
6b667f88 VC |
653 | }; |
654 | ||
844a3b63 PW |
655 | /* |
656 | * 'dsi' class | |
657 | * display serial interface controller | |
658 | */ | |
4fe20e97 | 659 | |
844a3b63 PW |
660 | static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { |
661 | .name = "dsi", | |
c345c8b0 TKD |
662 | }; |
663 | ||
844a3b63 PW |
664 | static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { |
665 | { .irq = 25 }, | |
666 | { .irq = -1 } | |
c345c8b0 TKD |
667 | }; |
668 | ||
844a3b63 PW |
669 | /* dss_dsi1 */ |
670 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { | |
671 | { .role = "sys_clk", .clk = "dss2_alwon_fck" }, | |
c345c8b0 TKD |
672 | }; |
673 | ||
844a3b63 PW |
674 | static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { |
675 | .name = "dss_dsi1", | |
676 | .class = &omap3xxx_dsi_hwmod_class, | |
677 | .mpu_irqs = omap3xxx_dsi1_irqs, | |
678 | .main_clk = "dss1_alwon_fck", | |
679 | .prcm = { | |
680 | .omap2 = { | |
681 | .prcm_reg_id = 1, | |
682 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
683 | .module_offs = OMAP3430_DSS_MOD, | |
684 | }, | |
ce722d26 | 685 | }, |
844a3b63 PW |
686 | .opt_clks = dss_dsi1_opt_clks, |
687 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
688 | .flags = HWMOD_NO_IDLEST, | |
6b667f88 VC |
689 | }; |
690 | ||
844a3b63 PW |
691 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
692 | { .role = "ick", .clk = "dss_ick" }, | |
ce722d26 TG |
693 | }; |
694 | ||
844a3b63 PW |
695 | static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { |
696 | .name = "dss_rfbi", | |
697 | .class = &omap2_rfbi_hwmod_class, | |
698 | .main_clk = "dss1_alwon_fck", | |
6b667f88 VC |
699 | .prcm = { |
700 | .omap2 = { | |
701 | .prcm_reg_id = 1, | |
844a3b63 PW |
702 | .module_bit = OMAP3430_EN_DSS1_SHIFT, |
703 | .module_offs = OMAP3430_DSS_MOD, | |
6b667f88 VC |
704 | }, |
705 | }, | |
844a3b63 PW |
706 | .opt_clks = dss_rfbi_opt_clks, |
707 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
708 | .flags = HWMOD_NO_IDLEST, | |
046465b7 KH |
709 | }; |
710 | ||
844a3b63 PW |
711 | static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { |
712 | /* required only on OMAP3430 */ | |
713 | { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, | |
046465b7 KH |
714 | }; |
715 | ||
844a3b63 PW |
716 | static struct omap_hwmod omap3xxx_dss_venc_hwmod = { |
717 | .name = "dss_venc", | |
718 | .class = &omap2_venc_hwmod_class, | |
719 | .main_clk = "dss_tv_fck", | |
046465b7 KH |
720 | .prcm = { |
721 | .omap2 = { | |
046465b7 | 722 | .prcm_reg_id = 1, |
844a3b63 PW |
723 | .module_bit = OMAP3430_EN_DSS1_SHIFT, |
724 | .module_offs = OMAP3430_DSS_MOD, | |
046465b7 KH |
725 | }, |
726 | }, | |
844a3b63 PW |
727 | .opt_clks = dss_venc_opt_clks, |
728 | .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), | |
729 | .flags = HWMOD_NO_IDLEST, | |
046465b7 KH |
730 | }; |
731 | ||
844a3b63 PW |
732 | /* I2C1 */ |
733 | static struct omap_i2c_dev_attr i2c1_dev_attr = { | |
734 | .fifo_depth = 8, /* bytes */ | |
735 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
736 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
737 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
046465b7 KH |
738 | }; |
739 | ||
844a3b63 PW |
740 | static struct omap_hwmod omap3xxx_i2c1_hwmod = { |
741 | .name = "i2c1", | |
742 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
743 | .mpu_irqs = omap2_i2c1_mpu_irqs, | |
744 | .sdma_reqs = omap2_i2c1_sdma_reqs, | |
745 | .main_clk = "i2c1_fck", | |
046465b7 KH |
746 | .prcm = { |
747 | .omap2 = { | |
844a3b63 | 748 | .module_offs = CORE_MOD, |
046465b7 | 749 | .prcm_reg_id = 1, |
844a3b63 | 750 | .module_bit = OMAP3430_EN_I2C1_SHIFT, |
046465b7 | 751 | .idlest_reg_id = 1, |
844a3b63 | 752 | .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, |
046465b7 KH |
753 | }, |
754 | }, | |
844a3b63 PW |
755 | .class = &i2c_class, |
756 | .dev_attr = &i2c1_dev_attr, | |
046465b7 KH |
757 | }; |
758 | ||
844a3b63 PW |
759 | /* I2C2 */ |
760 | static struct omap_i2c_dev_attr i2c2_dev_attr = { | |
761 | .fifo_depth = 8, /* bytes */ | |
762 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
763 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
764 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
046465b7 KH |
765 | }; |
766 | ||
844a3b63 PW |
767 | static struct omap_hwmod omap3xxx_i2c2_hwmod = { |
768 | .name = "i2c2", | |
769 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
770 | .mpu_irqs = omap2_i2c2_mpu_irqs, | |
771 | .sdma_reqs = omap2_i2c2_sdma_reqs, | |
772 | .main_clk = "i2c2_fck", | |
046465b7 KH |
773 | .prcm = { |
774 | .omap2 = { | |
844a3b63 | 775 | .module_offs = CORE_MOD, |
046465b7 | 776 | .prcm_reg_id = 1, |
844a3b63 | 777 | .module_bit = OMAP3430_EN_I2C2_SHIFT, |
046465b7 | 778 | .idlest_reg_id = 1, |
844a3b63 | 779 | .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, |
046465b7 KH |
780 | }, |
781 | }, | |
844a3b63 PW |
782 | .class = &i2c_class, |
783 | .dev_attr = &i2c2_dev_attr, | |
046465b7 KH |
784 | }; |
785 | ||
844a3b63 PW |
786 | /* I2C3 */ |
787 | static struct omap_i2c_dev_attr i2c3_dev_attr = { | |
788 | .fifo_depth = 64, /* bytes */ | |
789 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
790 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
791 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
792 | }; | |
046465b7 | 793 | |
844a3b63 PW |
794 | static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { |
795 | { .irq = INT_34XX_I2C3_IRQ, }, | |
796 | { .irq = -1 } | |
046465b7 KH |
797 | }; |
798 | ||
844a3b63 PW |
799 | static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { |
800 | { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, | |
801 | { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, | |
802 | { .dma_req = -1 } | |
046465b7 KH |
803 | }; |
804 | ||
844a3b63 PW |
805 | static struct omap_hwmod omap3xxx_i2c3_hwmod = { |
806 | .name = "i2c3", | |
807 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
808 | .mpu_irqs = i2c3_mpu_irqs, | |
809 | .sdma_reqs = i2c3_sdma_reqs, | |
810 | .main_clk = "i2c3_fck", | |
046465b7 KH |
811 | .prcm = { |
812 | .omap2 = { | |
844a3b63 | 813 | .module_offs = CORE_MOD, |
046465b7 | 814 | .prcm_reg_id = 1, |
844a3b63 | 815 | .module_bit = OMAP3430_EN_I2C3_SHIFT, |
046465b7 | 816 | .idlest_reg_id = 1, |
844a3b63 | 817 | .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, |
046465b7 KH |
818 | }, |
819 | }, | |
844a3b63 PW |
820 | .class = &i2c_class, |
821 | .dev_attr = &i2c3_dev_attr, | |
4fe20e97 RN |
822 | }; |
823 | ||
844a3b63 PW |
824 | /* |
825 | * 'gpio' class | |
826 | * general purpose io module | |
827 | */ | |
4fe20e97 | 828 | |
844a3b63 PW |
829 | static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { |
830 | .rev_offs = 0x0000, | |
831 | .sysc_offs = 0x0010, | |
832 | .syss_offs = 0x0014, | |
833 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
834 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
835 | SYSS_HAS_RESET_STATUS), | |
836 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
837 | .sysc_fields = &omap_hwmod_sysc_type1, | |
4fe20e97 RN |
838 | }; |
839 | ||
844a3b63 PW |
840 | static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { |
841 | .name = "gpio", | |
842 | .sysc = &omap3xxx_gpio_sysc, | |
843 | .rev = 1, | |
4fe20e97 RN |
844 | }; |
845 | ||
844a3b63 PW |
846 | /* gpio_dev_attr */ |
847 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
848 | .bank_width = 32, | |
849 | .dbck_flag = true, | |
850 | }; | |
851 | ||
852 | /* gpio1 */ | |
853 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | |
854 | { .role = "dbclk", .clk = "gpio1_dbck", }, | |
855 | }; | |
856 | ||
857 | static struct omap_hwmod omap3xxx_gpio1_hwmod = { | |
858 | .name = "gpio1", | |
859 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
860 | .mpu_irqs = omap2_gpio1_irqs, | |
861 | .main_clk = "gpio1_ick", | |
862 | .opt_clks = gpio1_opt_clks, | |
863 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
4fe20e97 RN |
864 | .prcm = { |
865 | .omap2 = { | |
4fe20e97 | 866 | .prcm_reg_id = 1, |
844a3b63 PW |
867 | .module_bit = OMAP3430_EN_GPIO1_SHIFT, |
868 | .module_offs = WKUP_MOD, | |
4fe20e97 | 869 | .idlest_reg_id = 1, |
844a3b63 | 870 | .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, |
4fe20e97 RN |
871 | }, |
872 | }, | |
844a3b63 PW |
873 | .class = &omap3xxx_gpio_hwmod_class, |
874 | .dev_attr = &gpio_dev_attr, | |
4fe20e97 RN |
875 | }; |
876 | ||
844a3b63 PW |
877 | /* gpio2 */ |
878 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | |
879 | { .role = "dbclk", .clk = "gpio2_dbck", }, | |
4fe20e97 RN |
880 | }; |
881 | ||
844a3b63 PW |
882 | static struct omap_hwmod omap3xxx_gpio2_hwmod = { |
883 | .name = "gpio2", | |
884 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
885 | .mpu_irqs = omap2_gpio2_irqs, | |
886 | .main_clk = "gpio2_ick", | |
887 | .opt_clks = gpio2_opt_clks, | |
888 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
4fe20e97 RN |
889 | .prcm = { |
890 | .omap2 = { | |
4fe20e97 | 891 | .prcm_reg_id = 1, |
844a3b63 | 892 | .module_bit = OMAP3430_EN_GPIO2_SHIFT, |
ce722d26 | 893 | .module_offs = OMAP3430_PER_MOD, |
4fe20e97 | 894 | .idlest_reg_id = 1, |
844a3b63 | 895 | .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, |
4fe20e97 RN |
896 | }, |
897 | }, | |
844a3b63 PW |
898 | .class = &omap3xxx_gpio_hwmod_class, |
899 | .dev_attr = &gpio_dev_attr, | |
4fe20e97 RN |
900 | }; |
901 | ||
844a3b63 PW |
902 | /* gpio3 */ |
903 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { | |
904 | { .role = "dbclk", .clk = "gpio3_dbck", }, | |
4fe20e97 RN |
905 | }; |
906 | ||
844a3b63 PW |
907 | static struct omap_hwmod omap3xxx_gpio3_hwmod = { |
908 | .name = "gpio3", | |
909 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
910 | .mpu_irqs = omap2_gpio3_irqs, | |
911 | .main_clk = "gpio3_ick", | |
912 | .opt_clks = gpio3_opt_clks, | |
913 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
4fe20e97 RN |
914 | .prcm = { |
915 | .omap2 = { | |
4fe20e97 | 916 | .prcm_reg_id = 1, |
844a3b63 | 917 | .module_bit = OMAP3430_EN_GPIO3_SHIFT, |
ce722d26 | 918 | .module_offs = OMAP3430_PER_MOD, |
4fe20e97 | 919 | .idlest_reg_id = 1, |
844a3b63 | 920 | .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, |
4fe20e97 RN |
921 | }, |
922 | }, | |
844a3b63 PW |
923 | .class = &omap3xxx_gpio_hwmod_class, |
924 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
925 | }; |
926 | ||
844a3b63 PW |
927 | /* gpio4 */ |
928 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { | |
929 | { .role = "dbclk", .clk = "gpio4_dbck", }, | |
70034d38 VC |
930 | }; |
931 | ||
844a3b63 PW |
932 | static struct omap_hwmod omap3xxx_gpio4_hwmod = { |
933 | .name = "gpio4", | |
934 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
935 | .mpu_irqs = omap2_gpio4_irqs, | |
936 | .main_clk = "gpio4_ick", | |
937 | .opt_clks = gpio4_opt_clks, | |
938 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
ce722d26 TG |
939 | .prcm = { |
940 | .omap2 = { | |
941 | .prcm_reg_id = 1, | |
844a3b63 | 942 | .module_bit = OMAP3430_EN_GPIO4_SHIFT, |
ce722d26 TG |
943 | .module_offs = OMAP3430_PER_MOD, |
944 | .idlest_reg_id = 1, | |
844a3b63 | 945 | .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, |
ce722d26 | 946 | }, |
70034d38 | 947 | }, |
844a3b63 PW |
948 | .class = &omap3xxx_gpio_hwmod_class, |
949 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
950 | }; |
951 | ||
844a3b63 PW |
952 | /* gpio5 */ |
953 | static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { | |
954 | { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ | |
955 | { .irq = -1 } | |
956 | }; | |
70034d38 | 957 | |
844a3b63 PW |
958 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
959 | { .role = "dbclk", .clk = "gpio5_dbck", }, | |
70034d38 VC |
960 | }; |
961 | ||
844a3b63 PW |
962 | static struct omap_hwmod omap3xxx_gpio5_hwmod = { |
963 | .name = "gpio5", | |
964 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
965 | .mpu_irqs = omap3xxx_gpio5_irqs, | |
966 | .main_clk = "gpio5_ick", | |
967 | .opt_clks = gpio5_opt_clks, | |
968 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
ce722d26 TG |
969 | .prcm = { |
970 | .omap2 = { | |
971 | .prcm_reg_id = 1, | |
844a3b63 PW |
972 | .module_bit = OMAP3430_EN_GPIO5_SHIFT, |
973 | .module_offs = OMAP3430_PER_MOD, | |
ce722d26 | 974 | .idlest_reg_id = 1, |
844a3b63 | 975 | .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, |
ce722d26 | 976 | }, |
70034d38 | 977 | }, |
844a3b63 PW |
978 | .class = &omap3xxx_gpio_hwmod_class, |
979 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
980 | }; |
981 | ||
844a3b63 PW |
982 | /* gpio6 */ |
983 | static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { | |
984 | { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ | |
985 | { .irq = -1 } | |
986 | }; | |
70034d38 | 987 | |
844a3b63 PW |
988 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
989 | { .role = "dbclk", .clk = "gpio6_dbck", }, | |
70034d38 VC |
990 | }; |
991 | ||
844a3b63 PW |
992 | static struct omap_hwmod omap3xxx_gpio6_hwmod = { |
993 | .name = "gpio6", | |
994 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
995 | .mpu_irqs = omap3xxx_gpio6_irqs, | |
996 | .main_clk = "gpio6_ick", | |
997 | .opt_clks = gpio6_opt_clks, | |
998 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
ce722d26 TG |
999 | .prcm = { |
1000 | .omap2 = { | |
1001 | .prcm_reg_id = 1, | |
844a3b63 PW |
1002 | .module_bit = OMAP3430_EN_GPIO6_SHIFT, |
1003 | .module_offs = OMAP3430_PER_MOD, | |
ce722d26 | 1004 | .idlest_reg_id = 1, |
844a3b63 | 1005 | .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, |
ce722d26 TG |
1006 | }, |
1007 | }, | |
844a3b63 PW |
1008 | .class = &omap3xxx_gpio_hwmod_class, |
1009 | .dev_attr = &gpio_dev_attr, | |
ce722d26 TG |
1010 | }; |
1011 | ||
844a3b63 PW |
1012 | /* dma attributes */ |
1013 | static struct omap_dma_dev_attr dma_dev_attr = { | |
1014 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
1015 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
1016 | .lch_count = 32, | |
ce722d26 TG |
1017 | }; |
1018 | ||
844a3b63 PW |
1019 | static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { |
1020 | .rev_offs = 0x0000, | |
1021 | .sysc_offs = 0x002c, | |
1022 | .syss_offs = 0x0028, | |
1023 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1024 | SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
1025 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | | |
1026 | SYSS_HAS_RESET_STATUS), | |
1027 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1028 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1029 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1030 | }; |
1031 | ||
844a3b63 PW |
1032 | static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { |
1033 | .name = "dma", | |
1034 | .sysc = &omap3xxx_dma_sysc, | |
70034d38 VC |
1035 | }; |
1036 | ||
844a3b63 PW |
1037 | /* dma_system */ |
1038 | static struct omap_hwmod omap3xxx_dma_system_hwmod = { | |
1039 | .name = "dma", | |
1040 | .class = &omap3xxx_dma_hwmod_class, | |
1041 | .mpu_irqs = omap2_dma_system_irqs, | |
1042 | .main_clk = "core_l3_ick", | |
1043 | .prcm = { | |
ce722d26 | 1044 | .omap2 = { |
844a3b63 PW |
1045 | .module_offs = CORE_MOD, |
1046 | .prcm_reg_id = 1, | |
1047 | .module_bit = OMAP3430_ST_SDMA_SHIFT, | |
1048 | .idlest_reg_id = 1, | |
1049 | .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, | |
ce722d26 TG |
1050 | }, |
1051 | }, | |
844a3b63 PW |
1052 | .dev_attr = &dma_dev_attr, |
1053 | .flags = HWMOD_NO_IDLEST, | |
70034d38 VC |
1054 | }; |
1055 | ||
844a3b63 PW |
1056 | /* |
1057 | * 'mcbsp' class | |
1058 | * multi channel buffered serial port controller | |
1059 | */ | |
1060 | ||
1061 | static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { | |
1062 | .sysc_offs = 0x008c, | |
1063 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
1064 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1065 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1066 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1067 | .clockact = 0x2, | |
70034d38 VC |
1068 | }; |
1069 | ||
844a3b63 PW |
1070 | static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { |
1071 | .name = "mcbsp", | |
1072 | .sysc = &omap3xxx_mcbsp_sysc, | |
1073 | .rev = MCBSP_CONFIG_TYPE3, | |
70034d38 VC |
1074 | }; |
1075 | ||
844a3b63 PW |
1076 | /* mcbsp1 */ |
1077 | static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { | |
1c2badc1 | 1078 | { .name = "common", .irq = 16 }, |
844a3b63 PW |
1079 | { .name = "tx", .irq = 59 }, |
1080 | { .name = "rx", .irq = 60 }, | |
1081 | { .irq = -1 } | |
1082 | }; | |
6b667f88 | 1083 | |
844a3b63 PW |
1084 | static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { |
1085 | .name = "mcbsp1", | |
1086 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1087 | .mpu_irqs = omap3xxx_mcbsp1_irqs, | |
1088 | .sdma_reqs = omap2_mcbsp1_sdma_reqs, | |
1089 | .main_clk = "mcbsp1_fck", | |
1090 | .prcm = { | |
1091 | .omap2 = { | |
1092 | .prcm_reg_id = 1, | |
1093 | .module_bit = OMAP3430_EN_MCBSP1_SHIFT, | |
1094 | .module_offs = CORE_MOD, | |
1095 | .idlest_reg_id = 1, | |
1096 | .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, | |
1097 | }, | |
1098 | }, | |
70034d38 VC |
1099 | }; |
1100 | ||
844a3b63 PW |
1101 | /* mcbsp2 */ |
1102 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { | |
1c2badc1 | 1103 | { .name = "common", .irq = 17 }, |
844a3b63 PW |
1104 | { .name = "tx", .irq = 62 }, |
1105 | { .name = "rx", .irq = 63 }, | |
1106 | { .irq = -1 } | |
70034d38 VC |
1107 | }; |
1108 | ||
844a3b63 PW |
1109 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { |
1110 | .sidetone = "mcbsp2_sidetone", | |
70034d38 VC |
1111 | }; |
1112 | ||
844a3b63 PW |
1113 | static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { |
1114 | .name = "mcbsp2", | |
1115 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1116 | .mpu_irqs = omap3xxx_mcbsp2_irqs, | |
1117 | .sdma_reqs = omap2_mcbsp2_sdma_reqs, | |
1118 | .main_clk = "mcbsp2_fck", | |
70034d38 VC |
1119 | .prcm = { |
1120 | .omap2 = { | |
1121 | .prcm_reg_id = 1, | |
844a3b63 PW |
1122 | .module_bit = OMAP3430_EN_MCBSP2_SHIFT, |
1123 | .module_offs = OMAP3430_PER_MOD, | |
70034d38 | 1124 | .idlest_reg_id = 1, |
844a3b63 | 1125 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, |
70034d38 VC |
1126 | }, |
1127 | }, | |
844a3b63 | 1128 | .dev_attr = &omap34xx_mcbsp2_dev_attr, |
70034d38 VC |
1129 | }; |
1130 | ||
844a3b63 PW |
1131 | /* mcbsp3 */ |
1132 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { | |
1c2badc1 | 1133 | { .name = "common", .irq = 22 }, |
844a3b63 PW |
1134 | { .name = "tx", .irq = 89 }, |
1135 | { .name = "rx", .irq = 90 }, | |
1136 | { .irq = -1 } | |
1137 | }; | |
1138 | ||
1139 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { | |
1140 | .sidetone = "mcbsp3_sidetone", | |
1141 | }; | |
1142 | ||
1143 | static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { | |
1144 | .name = "mcbsp3", | |
1145 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1146 | .mpu_irqs = omap3xxx_mcbsp3_irqs, | |
1147 | .sdma_reqs = omap2_mcbsp3_sdma_reqs, | |
1148 | .main_clk = "mcbsp3_fck", | |
70034d38 VC |
1149 | .prcm = { |
1150 | .omap2 = { | |
1151 | .prcm_reg_id = 1, | |
844a3b63 PW |
1152 | .module_bit = OMAP3430_EN_MCBSP3_SHIFT, |
1153 | .module_offs = OMAP3430_PER_MOD, | |
70034d38 | 1154 | .idlest_reg_id = 1, |
844a3b63 | 1155 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, |
70034d38 VC |
1156 | }, |
1157 | }, | |
844a3b63 | 1158 | .dev_attr = &omap34xx_mcbsp3_dev_attr, |
70034d38 VC |
1159 | }; |
1160 | ||
844a3b63 PW |
1161 | /* mcbsp4 */ |
1162 | static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { | |
1c2badc1 | 1163 | { .name = "common", .irq = 23 }, |
844a3b63 PW |
1164 | { .name = "tx", .irq = 54 }, |
1165 | { .name = "rx", .irq = 55 }, | |
1166 | { .irq = -1 } | |
1167 | }; | |
1168 | ||
1169 | static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { | |
1170 | { .name = "rx", .dma_req = 20 }, | |
1171 | { .name = "tx", .dma_req = 19 }, | |
1172 | { .dma_req = -1 } | |
1173 | }; | |
1174 | ||
1175 | static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { | |
1176 | .name = "mcbsp4", | |
1177 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1178 | .mpu_irqs = omap3xxx_mcbsp4_irqs, | |
1179 | .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, | |
1180 | .main_clk = "mcbsp4_fck", | |
70034d38 VC |
1181 | .prcm = { |
1182 | .omap2 = { | |
1183 | .prcm_reg_id = 1, | |
844a3b63 PW |
1184 | .module_bit = OMAP3430_EN_MCBSP4_SHIFT, |
1185 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 1186 | .idlest_reg_id = 1, |
844a3b63 | 1187 | .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, |
046465b7 KH |
1188 | }, |
1189 | }, | |
046465b7 KH |
1190 | }; |
1191 | ||
844a3b63 PW |
1192 | /* mcbsp5 */ |
1193 | static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { | |
1c2badc1 | 1194 | { .name = "common", .irq = 27 }, |
844a3b63 PW |
1195 | { .name = "tx", .irq = 81 }, |
1196 | { .name = "rx", .irq = 82 }, | |
1197 | { .irq = -1 } | |
1198 | }; | |
1199 | ||
1200 | static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { | |
1201 | { .name = "rx", .dma_req = 22 }, | |
1202 | { .name = "tx", .dma_req = 21 }, | |
1203 | { .dma_req = -1 } | |
1204 | }; | |
1205 | ||
1206 | static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { | |
1207 | .name = "mcbsp5", | |
1208 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1209 | .mpu_irqs = omap3xxx_mcbsp5_irqs, | |
1210 | .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, | |
1211 | .main_clk = "mcbsp5_fck", | |
046465b7 KH |
1212 | .prcm = { |
1213 | .omap2 = { | |
046465b7 | 1214 | .prcm_reg_id = 1, |
844a3b63 PW |
1215 | .module_bit = OMAP3430_EN_MCBSP5_SHIFT, |
1216 | .module_offs = CORE_MOD, | |
70034d38 | 1217 | .idlest_reg_id = 1, |
844a3b63 | 1218 | .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, |
70034d38 VC |
1219 | }, |
1220 | }, | |
70034d38 VC |
1221 | }; |
1222 | ||
844a3b63 PW |
1223 | /* 'mcbsp sidetone' class */ |
1224 | static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { | |
1225 | .sysc_offs = 0x0010, | |
1226 | .sysc_flags = SYSC_HAS_AUTOIDLE, | |
1227 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1228 | }; | |
046465b7 | 1229 | |
844a3b63 PW |
1230 | static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { |
1231 | .name = "mcbsp_sidetone", | |
1232 | .sysc = &omap3xxx_mcbsp_sidetone_sysc, | |
70034d38 VC |
1233 | }; |
1234 | ||
844a3b63 PW |
1235 | /* mcbsp2_sidetone */ |
1236 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { | |
1237 | { .name = "irq", .irq = 4 }, | |
1238 | { .irq = -1 } | |
70034d38 VC |
1239 | }; |
1240 | ||
844a3b63 PW |
1241 | static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { |
1242 | .name = "mcbsp2_sidetone", | |
1243 | .class = &omap3xxx_mcbsp_sidetone_hwmod_class, | |
1244 | .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, | |
1245 | .main_clk = "mcbsp2_fck", | |
046465b7 KH |
1246 | .prcm = { |
1247 | .omap2 = { | |
046465b7 | 1248 | .prcm_reg_id = 1, |
844a3b63 PW |
1249 | .module_bit = OMAP3430_EN_MCBSP2_SHIFT, |
1250 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 1251 | .idlest_reg_id = 1, |
844a3b63 | 1252 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, |
046465b7 KH |
1253 | }, |
1254 | }, | |
4bf90f65 KM |
1255 | }; |
1256 | ||
844a3b63 PW |
1257 | /* mcbsp3_sidetone */ |
1258 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { | |
1259 | { .name = "irq", .irq = 5 }, | |
1260 | { .irq = -1 } | |
4bf90f65 KM |
1261 | }; |
1262 | ||
844a3b63 PW |
1263 | static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { |
1264 | .name = "mcbsp3_sidetone", | |
1265 | .class = &omap3xxx_mcbsp_sidetone_hwmod_class, | |
1266 | .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, | |
1267 | .main_clk = "mcbsp3_fck", | |
0a78c5c5 | 1268 | .prcm = { |
4bf90f65 | 1269 | .omap2 = { |
4bf90f65 | 1270 | .prcm_reg_id = 1, |
844a3b63 PW |
1271 | .module_bit = OMAP3430_EN_MCBSP3_SHIFT, |
1272 | .module_offs = OMAP3430_PER_MOD, | |
4bf90f65 | 1273 | .idlest_reg_id = 1, |
844a3b63 | 1274 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, |
4bf90f65 KM |
1275 | }, |
1276 | }, | |
4bf90f65 KM |
1277 | }; |
1278 | ||
844a3b63 PW |
1279 | /* SR common */ |
1280 | static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { | |
1281 | .clkact_shift = 20, | |
1282 | }; | |
4bf90f65 | 1283 | |
844a3b63 PW |
1284 | static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { |
1285 | .sysc_offs = 0x24, | |
1286 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), | |
1287 | .clockact = CLOCKACT_TEST_ICLK, | |
1288 | .sysc_fields = &omap34xx_sr_sysc_fields, | |
4fe20e97 RN |
1289 | }; |
1290 | ||
844a3b63 PW |
1291 | static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { |
1292 | .name = "smartreflex", | |
1293 | .sysc = &omap34xx_sr_sysc, | |
1294 | .rev = 1, | |
e04d9e1e SG |
1295 | }; |
1296 | ||
844a3b63 PW |
1297 | static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { |
1298 | .sidle_shift = 24, | |
1299 | .enwkup_shift = 26, | |
1300 | }; | |
e04d9e1e | 1301 | |
844a3b63 PW |
1302 | static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { |
1303 | .sysc_offs = 0x38, | |
1304 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1305 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
1306 | SYSC_NO_CACHE), | |
1307 | .sysc_fields = &omap36xx_sr_sysc_fields, | |
1308 | }; | |
1309 | ||
1310 | static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { | |
1311 | .name = "smartreflex", | |
1312 | .sysc = &omap36xx_sr_sysc, | |
1313 | .rev = 2, | |
1314 | }; | |
1315 | ||
1316 | /* SR1 */ | |
1317 | static struct omap_smartreflex_dev_attr sr1_dev_attr = { | |
1318 | .sensor_voltdm_name = "mpu_iva", | |
1319 | }; | |
1320 | ||
1321 | static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { | |
1322 | { .irq = 18 }, | |
1323 | { .irq = -1 } | |
1324 | }; | |
1325 | ||
1326 | static struct omap_hwmod omap34xx_sr1_hwmod = { | |
1327 | .name = "sr1", | |
1328 | .class = &omap34xx_smartreflex_hwmod_class, | |
1329 | .main_clk = "sr1_fck", | |
1330 | .prcm = { | |
e04d9e1e | 1331 | .omap2 = { |
844a3b63 PW |
1332 | .prcm_reg_id = 1, |
1333 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
1334 | .module_offs = WKUP_MOD, | |
1335 | .idlest_reg_id = 1, | |
1336 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
1337 | }, | |
e04d9e1e | 1338 | }, |
844a3b63 PW |
1339 | .dev_attr = &sr1_dev_attr, |
1340 | .mpu_irqs = omap3_smartreflex_mpu_irqs, | |
1341 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
e04d9e1e SG |
1342 | }; |
1343 | ||
844a3b63 PW |
1344 | static struct omap_hwmod omap36xx_sr1_hwmod = { |
1345 | .name = "sr1", | |
1346 | .class = &omap36xx_smartreflex_hwmod_class, | |
1347 | .main_clk = "sr1_fck", | |
1348 | .prcm = { | |
e04d9e1e | 1349 | .omap2 = { |
844a3b63 PW |
1350 | .prcm_reg_id = 1, |
1351 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
1352 | .module_offs = WKUP_MOD, | |
1353 | .idlest_reg_id = 1, | |
1354 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
1355 | }, | |
e04d9e1e | 1356 | }, |
844a3b63 PW |
1357 | .dev_attr = &sr1_dev_attr, |
1358 | .mpu_irqs = omap3_smartreflex_mpu_irqs, | |
e04d9e1e SG |
1359 | }; |
1360 | ||
844a3b63 PW |
1361 | /* SR2 */ |
1362 | static struct omap_smartreflex_dev_attr sr2_dev_attr = { | |
1363 | .sensor_voltdm_name = "core", | |
e04d9e1e SG |
1364 | }; |
1365 | ||
844a3b63 PW |
1366 | static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { |
1367 | { .irq = 19 }, | |
1368 | { .irq = -1 } | |
1369 | }; | |
1370 | ||
1371 | static struct omap_hwmod omap34xx_sr2_hwmod = { | |
1372 | .name = "sr2", | |
1373 | .class = &omap34xx_smartreflex_hwmod_class, | |
1374 | .main_clk = "sr2_fck", | |
e04d9e1e SG |
1375 | .prcm = { |
1376 | .omap2 = { | |
1377 | .prcm_reg_id = 1, | |
844a3b63 PW |
1378 | .module_bit = OMAP3430_EN_SR2_SHIFT, |
1379 | .module_offs = WKUP_MOD, | |
e04d9e1e | 1380 | .idlest_reg_id = 1, |
844a3b63 | 1381 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, |
e04d9e1e SG |
1382 | }, |
1383 | }, | |
844a3b63 PW |
1384 | .dev_attr = &sr2_dev_attr, |
1385 | .mpu_irqs = omap3_smartreflex_core_irqs, | |
1386 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
e04d9e1e SG |
1387 | }; |
1388 | ||
844a3b63 PW |
1389 | static struct omap_hwmod omap36xx_sr2_hwmod = { |
1390 | .name = "sr2", | |
1391 | .class = &omap36xx_smartreflex_hwmod_class, | |
1392 | .main_clk = "sr2_fck", | |
e04d9e1e SG |
1393 | .prcm = { |
1394 | .omap2 = { | |
1395 | .prcm_reg_id = 1, | |
844a3b63 PW |
1396 | .module_bit = OMAP3430_EN_SR2_SHIFT, |
1397 | .module_offs = WKUP_MOD, | |
e04d9e1e | 1398 | .idlest_reg_id = 1, |
844a3b63 | 1399 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, |
e04d9e1e SG |
1400 | }, |
1401 | }, | |
844a3b63 PW |
1402 | .dev_attr = &sr2_dev_attr, |
1403 | .mpu_irqs = omap3_smartreflex_core_irqs, | |
e04d9e1e SG |
1404 | }; |
1405 | ||
1ac6d46e | 1406 | /* |
844a3b63 PW |
1407 | * 'mailbox' class |
1408 | * mailbox module allowing communication between the on-chip processors | |
1409 | * using a queued mailbox-interrupt mechanism. | |
1ac6d46e TV |
1410 | */ |
1411 | ||
844a3b63 PW |
1412 | static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { |
1413 | .rev_offs = 0x000, | |
1414 | .sysc_offs = 0x010, | |
1415 | .syss_offs = 0x014, | |
1416 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1417 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1418 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1ac6d46e TV |
1419 | .sysc_fields = &omap_hwmod_sysc_type1, |
1420 | }; | |
1421 | ||
844a3b63 PW |
1422 | static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { |
1423 | .name = "mailbox", | |
1424 | .sysc = &omap3xxx_mailbox_sysc, | |
1ac6d46e TV |
1425 | }; |
1426 | ||
844a3b63 PW |
1427 | static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { |
1428 | { .irq = 26 }, | |
1429 | { .irq = -1 } | |
e04d9e1e SG |
1430 | }; |
1431 | ||
844a3b63 PW |
1432 | static struct omap_hwmod omap3xxx_mailbox_hwmod = { |
1433 | .name = "mailbox", | |
1434 | .class = &omap3xxx_mailbox_hwmod_class, | |
1435 | .mpu_irqs = omap3xxx_mailbox_irqs, | |
1436 | .main_clk = "mailboxes_ick", | |
e04d9e1e SG |
1437 | .prcm = { |
1438 | .omap2 = { | |
1439 | .prcm_reg_id = 1, | |
844a3b63 PW |
1440 | .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, |
1441 | .module_offs = CORE_MOD, | |
1442 | .idlest_reg_id = 1, | |
1443 | .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, | |
e04d9e1e SG |
1444 | }, |
1445 | }, | |
e04d9e1e SG |
1446 | }; |
1447 | ||
1448 | /* | |
844a3b63 PW |
1449 | * 'mcspi' class |
1450 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
1451 | * bus | |
e04d9e1e SG |
1452 | */ |
1453 | ||
844a3b63 PW |
1454 | static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { |
1455 | .rev_offs = 0x0000, | |
1456 | .sysc_offs = 0x0010, | |
1457 | .syss_offs = 0x0014, | |
1458 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1459 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1460 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1461 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1462 | .sysc_fields = &omap_hwmod_sysc_type1, | |
e04d9e1e SG |
1463 | }; |
1464 | ||
844a3b63 PW |
1465 | static struct omap_hwmod_class omap34xx_mcspi_class = { |
1466 | .name = "mcspi", | |
1467 | .sysc = &omap34xx_mcspi_sysc, | |
1468 | .rev = OMAP3_MCSPI_REV, | |
affe360d | 1469 | }; |
1470 | ||
844a3b63 PW |
1471 | /* mcspi1 */ |
1472 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { | |
1473 | .num_chipselect = 4, | |
e04d9e1e SG |
1474 | }; |
1475 | ||
844a3b63 PW |
1476 | static struct omap_hwmod omap34xx_mcspi1 = { |
1477 | .name = "mcspi1", | |
1478 | .mpu_irqs = omap2_mcspi1_mpu_irqs, | |
1479 | .sdma_reqs = omap2_mcspi1_sdma_reqs, | |
1480 | .main_clk = "mcspi1_fck", | |
1481 | .prcm = { | |
e04d9e1e | 1482 | .omap2 = { |
844a3b63 PW |
1483 | .module_offs = CORE_MOD, |
1484 | .prcm_reg_id = 1, | |
1485 | .module_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
1486 | .idlest_reg_id = 1, | |
1487 | .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, | |
1488 | }, | |
e04d9e1e | 1489 | }, |
844a3b63 PW |
1490 | .class = &omap34xx_mcspi_class, |
1491 | .dev_attr = &omap_mcspi1_dev_attr, | |
e04d9e1e SG |
1492 | }; |
1493 | ||
844a3b63 PW |
1494 | /* mcspi2 */ |
1495 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { | |
1496 | .num_chipselect = 2, | |
6c3d7e34 TV |
1497 | }; |
1498 | ||
844a3b63 PW |
1499 | static struct omap_hwmod omap34xx_mcspi2 = { |
1500 | .name = "mcspi2", | |
1501 | .mpu_irqs = omap2_mcspi2_mpu_irqs, | |
1502 | .sdma_reqs = omap2_mcspi2_sdma_reqs, | |
1503 | .main_clk = "mcspi2_fck", | |
e04d9e1e SG |
1504 | .prcm = { |
1505 | .omap2 = { | |
844a3b63 | 1506 | .module_offs = CORE_MOD, |
e04d9e1e | 1507 | .prcm_reg_id = 1, |
844a3b63 PW |
1508 | .module_bit = OMAP3430_EN_MCSPI2_SHIFT, |
1509 | .idlest_reg_id = 1, | |
1510 | .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, | |
e04d9e1e SG |
1511 | }, |
1512 | }, | |
844a3b63 PW |
1513 | .class = &omap34xx_mcspi_class, |
1514 | .dev_attr = &omap_mcspi2_dev_attr, | |
e04d9e1e SG |
1515 | }; |
1516 | ||
844a3b63 PW |
1517 | /* mcspi3 */ |
1518 | static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { | |
1519 | { .name = "irq", .irq = 91 }, /* 91 */ | |
1520 | { .irq = -1 } | |
1521 | }; | |
1522 | ||
1523 | static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { | |
1524 | { .name = "tx0", .dma_req = 15 }, | |
1525 | { .name = "rx0", .dma_req = 16 }, | |
1526 | { .name = "tx1", .dma_req = 23 }, | |
1527 | { .name = "rx1", .dma_req = 24 }, | |
1528 | { .dma_req = -1 } | |
e04d9e1e SG |
1529 | }; |
1530 | ||
844a3b63 PW |
1531 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { |
1532 | .num_chipselect = 2, | |
6c3d7e34 TV |
1533 | }; |
1534 | ||
844a3b63 PW |
1535 | static struct omap_hwmod omap34xx_mcspi3 = { |
1536 | .name = "mcspi3", | |
1537 | .mpu_irqs = omap34xx_mcspi3_mpu_irqs, | |
1538 | .sdma_reqs = omap34xx_mcspi3_sdma_reqs, | |
1539 | .main_clk = "mcspi3_fck", | |
e04d9e1e SG |
1540 | .prcm = { |
1541 | .omap2 = { | |
844a3b63 | 1542 | .module_offs = CORE_MOD, |
e04d9e1e | 1543 | .prcm_reg_id = 1, |
844a3b63 PW |
1544 | .module_bit = OMAP3430_EN_MCSPI3_SHIFT, |
1545 | .idlest_reg_id = 1, | |
1546 | .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, | |
e04d9e1e SG |
1547 | }, |
1548 | }, | |
844a3b63 PW |
1549 | .class = &omap34xx_mcspi_class, |
1550 | .dev_attr = &omap_mcspi3_dev_attr, | |
e04d9e1e SG |
1551 | }; |
1552 | ||
844a3b63 PW |
1553 | /* mcspi4 */ |
1554 | static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { | |
1555 | { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ | |
1556 | { .irq = -1 } | |
e04d9e1e SG |
1557 | }; |
1558 | ||
844a3b63 PW |
1559 | static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { |
1560 | { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ | |
1561 | { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ | |
1562 | { .dma_req = -1 } | |
6c3d7e34 TV |
1563 | }; |
1564 | ||
844a3b63 PW |
1565 | static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { |
1566 | .num_chipselect = 1, | |
1567 | }; | |
1568 | ||
1569 | static struct omap_hwmod omap34xx_mcspi4 = { | |
1570 | .name = "mcspi4", | |
1571 | .mpu_irqs = omap34xx_mcspi4_mpu_irqs, | |
1572 | .sdma_reqs = omap34xx_mcspi4_sdma_reqs, | |
1573 | .main_clk = "mcspi4_fck", | |
e04d9e1e SG |
1574 | .prcm = { |
1575 | .omap2 = { | |
844a3b63 | 1576 | .module_offs = CORE_MOD, |
e04d9e1e | 1577 | .prcm_reg_id = 1, |
844a3b63 PW |
1578 | .module_bit = OMAP3430_EN_MCSPI4_SHIFT, |
1579 | .idlest_reg_id = 1, | |
1580 | .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, | |
e04d9e1e SG |
1581 | }, |
1582 | }, | |
844a3b63 PW |
1583 | .class = &omap34xx_mcspi_class, |
1584 | .dev_attr = &omap_mcspi4_dev_attr, | |
e04d9e1e SG |
1585 | }; |
1586 | ||
844a3b63 PW |
1587 | /* usbhsotg */ |
1588 | static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { | |
1589 | .rev_offs = 0x0400, | |
1590 | .sysc_offs = 0x0404, | |
1591 | .syss_offs = 0x0408, | |
1592 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| | |
1593 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1594 | SYSC_HAS_AUTOIDLE), | |
1595 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1596 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1597 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1598 | }; | |
4fe20e97 | 1599 | |
844a3b63 PW |
1600 | static struct omap_hwmod_class usbotg_class = { |
1601 | .name = "usbotg", | |
1602 | .sysc = &omap3xxx_usbhsotg_sysc, | |
4fe20e97 RN |
1603 | }; |
1604 | ||
844a3b63 PW |
1605 | /* usb_otg_hs */ |
1606 | static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { | |
1607 | ||
1608 | { .name = "mc", .irq = 92 }, | |
1609 | { .name = "dma", .irq = 93 }, | |
1610 | { .irq = -1 } | |
1611 | }; | |
1612 | ||
1613 | static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { | |
1614 | .name = "usb_otg_hs", | |
1615 | .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, | |
1616 | .main_clk = "hsotgusb_ick", | |
4fe20e97 RN |
1617 | .prcm = { |
1618 | .omap2 = { | |
4fe20e97 | 1619 | .prcm_reg_id = 1, |
844a3b63 PW |
1620 | .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, |
1621 | .module_offs = CORE_MOD, | |
4fe20e97 | 1622 | .idlest_reg_id = 1, |
844a3b63 PW |
1623 | .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, |
1624 | .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT | |
4fe20e97 RN |
1625 | }, |
1626 | }, | |
844a3b63 PW |
1627 | .class = &usbotg_class, |
1628 | ||
1629 | /* | |
1630 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially | |
1631 | * broken when autoidle is enabled | |
1632 | * workaround is to disable the autoidle bit at module level. | |
1633 | */ | |
1634 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | |
1635 | | HWMOD_SWSUP_MSTANDBY, | |
4fe20e97 RN |
1636 | }; |
1637 | ||
844a3b63 PW |
1638 | /* usb_otg_hs */ |
1639 | static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { | |
4fe20e97 | 1640 | |
844a3b63 PW |
1641 | { .name = "mc", .irq = 71 }, |
1642 | { .irq = -1 } | |
4fe20e97 RN |
1643 | }; |
1644 | ||
844a3b63 PW |
1645 | static struct omap_hwmod_class am35xx_usbotg_class = { |
1646 | .name = "am35xx_usbotg", | |
1647 | .sysc = NULL, | |
1648 | }; | |
1649 | ||
1650 | static struct omap_hwmod am35xx_usbhsotg_hwmod = { | |
1651 | .name = "am35x_otg_hs", | |
1652 | .mpu_irqs = am35xx_usbhsotg_mpu_irqs, | |
1653 | .main_clk = NULL, | |
1654 | .prcm = { | |
4fe20e97 | 1655 | .omap2 = { |
4fe20e97 RN |
1656 | }, |
1657 | }, | |
844a3b63 | 1658 | .class = &am35xx_usbotg_class, |
4fe20e97 RN |
1659 | }; |
1660 | ||
844a3b63 PW |
1661 | /* MMC/SD/SDIO common */ |
1662 | static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { | |
1663 | .rev_offs = 0x1fc, | |
1664 | .sysc_offs = 0x10, | |
1665 | .syss_offs = 0x14, | |
1666 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1667 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1668 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1669 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1670 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1671 | }; | |
4fe20e97 | 1672 | |
844a3b63 PW |
1673 | static struct omap_hwmod_class omap34xx_mmc_class = { |
1674 | .name = "mmc", | |
1675 | .sysc = &omap34xx_mmc_sysc, | |
4fe20e97 RN |
1676 | }; |
1677 | ||
844a3b63 PW |
1678 | /* MMC/SD/SDIO1 */ |
1679 | ||
1680 | static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { | |
1681 | { .irq = 83, }, | |
212738a4 | 1682 | { .irq = -1 } |
4fe20e97 RN |
1683 | }; |
1684 | ||
844a3b63 PW |
1685 | static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { |
1686 | { .name = "tx", .dma_req = 61, }, | |
1687 | { .name = "rx", .dma_req = 62, }, | |
bc614958 | 1688 | { .dma_req = -1 } |
4fe20e97 RN |
1689 | }; |
1690 | ||
844a3b63 PW |
1691 | static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { |
1692 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
1693 | }; | |
1694 | ||
1695 | static struct omap_mmc_dev_attr mmc1_dev_attr = { | |
1696 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
1697 | }; | |
1698 | ||
1699 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ | |
1700 | static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = { | |
1701 | .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | | |
1702 | OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), | |
1703 | }; | |
1704 | ||
1705 | static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { | |
1706 | .name = "mmc1", | |
1707 | .mpu_irqs = omap34xx_mmc1_mpu_irqs, | |
1708 | .sdma_reqs = omap34xx_mmc1_sdma_reqs, | |
1709 | .opt_clks = omap34xx_mmc1_opt_clks, | |
1710 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), | |
1711 | .main_clk = "mmchs1_fck", | |
4fe20e97 RN |
1712 | .prcm = { |
1713 | .omap2 = { | |
1714 | .module_offs = CORE_MOD, | |
1715 | .prcm_reg_id = 1, | |
844a3b63 | 1716 | .module_bit = OMAP3430_EN_MMC1_SHIFT, |
4fe20e97 | 1717 | .idlest_reg_id = 1, |
844a3b63 | 1718 | .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, |
4fe20e97 RN |
1719 | }, |
1720 | }, | |
844a3b63 PW |
1721 | .dev_attr = &mmc1_pre_es3_dev_attr, |
1722 | .class = &omap34xx_mmc_class, | |
4fe20e97 RN |
1723 | }; |
1724 | ||
844a3b63 PW |
1725 | static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { |
1726 | .name = "mmc1", | |
1727 | .mpu_irqs = omap34xx_mmc1_mpu_irqs, | |
1728 | .sdma_reqs = omap34xx_mmc1_sdma_reqs, | |
1729 | .opt_clks = omap34xx_mmc1_opt_clks, | |
1730 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), | |
1731 | .main_clk = "mmchs1_fck", | |
1732 | .prcm = { | |
1733 | .omap2 = { | |
1734 | .module_offs = CORE_MOD, | |
1735 | .prcm_reg_id = 1, | |
1736 | .module_bit = OMAP3430_EN_MMC1_SHIFT, | |
1737 | .idlest_reg_id = 1, | |
1738 | .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, | |
1739 | }, | |
70034d38 | 1740 | }, |
844a3b63 PW |
1741 | .dev_attr = &mmc1_dev_attr, |
1742 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1743 | }; |
1744 | ||
844a3b63 | 1745 | /* MMC/SD/SDIO2 */ |
70034d38 | 1746 | |
844a3b63 PW |
1747 | static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { |
1748 | { .irq = INT_24XX_MMC2_IRQ, }, | |
1749 | { .irq = -1 } | |
70034d38 VC |
1750 | }; |
1751 | ||
844a3b63 PW |
1752 | static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { |
1753 | { .name = "tx", .dma_req = 47, }, | |
1754 | { .name = "rx", .dma_req = 48, }, | |
1755 | { .dma_req = -1 } | |
70034d38 VC |
1756 | }; |
1757 | ||
844a3b63 PW |
1758 | static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { |
1759 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
70034d38 VC |
1760 | }; |
1761 | ||
844a3b63 PW |
1762 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ |
1763 | static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { | |
1764 | .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, | |
70034d38 VC |
1765 | }; |
1766 | ||
844a3b63 PW |
1767 | static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { |
1768 | .name = "mmc2", | |
1769 | .mpu_irqs = omap34xx_mmc2_mpu_irqs, | |
1770 | .sdma_reqs = omap34xx_mmc2_sdma_reqs, | |
1771 | .opt_clks = omap34xx_mmc2_opt_clks, | |
1772 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), | |
1773 | .main_clk = "mmchs2_fck", | |
1774 | .prcm = { | |
1775 | .omap2 = { | |
1776 | .module_offs = CORE_MOD, | |
1777 | .prcm_reg_id = 1, | |
1778 | .module_bit = OMAP3430_EN_MMC2_SHIFT, | |
1779 | .idlest_reg_id = 1, | |
1780 | .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, | |
1781 | }, | |
70034d38 | 1782 | }, |
844a3b63 PW |
1783 | .dev_attr = &mmc2_pre_es3_dev_attr, |
1784 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1785 | }; |
1786 | ||
844a3b63 PW |
1787 | static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { |
1788 | .name = "mmc2", | |
1789 | .mpu_irqs = omap34xx_mmc2_mpu_irqs, | |
1790 | .sdma_reqs = omap34xx_mmc2_sdma_reqs, | |
1791 | .opt_clks = omap34xx_mmc2_opt_clks, | |
1792 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), | |
1793 | .main_clk = "mmchs2_fck", | |
1794 | .prcm = { | |
1795 | .omap2 = { | |
1796 | .module_offs = CORE_MOD, | |
1797 | .prcm_reg_id = 1, | |
1798 | .module_bit = OMAP3430_EN_MMC2_SHIFT, | |
1799 | .idlest_reg_id = 1, | |
1800 | .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, | |
1801 | }, | |
1802 | }, | |
1803 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1804 | }; |
1805 | ||
844a3b63 PW |
1806 | /* MMC/SD/SDIO3 */ |
1807 | ||
1808 | static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { | |
1809 | { .irq = 94, }, | |
1810 | { .irq = -1 } | |
70034d38 VC |
1811 | }; |
1812 | ||
844a3b63 PW |
1813 | static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { |
1814 | { .name = "tx", .dma_req = 77, }, | |
1815 | { .name = "rx", .dma_req = 78, }, | |
1816 | { .dma_req = -1 } | |
70034d38 VC |
1817 | }; |
1818 | ||
844a3b63 PW |
1819 | static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { |
1820 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
70034d38 VC |
1821 | }; |
1822 | ||
844a3b63 PW |
1823 | static struct omap_hwmod omap3xxx_mmc3_hwmod = { |
1824 | .name = "mmc3", | |
1825 | .mpu_irqs = omap34xx_mmc3_mpu_irqs, | |
1826 | .sdma_reqs = omap34xx_mmc3_sdma_reqs, | |
1827 | .opt_clks = omap34xx_mmc3_opt_clks, | |
1828 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), | |
1829 | .main_clk = "mmchs3_fck", | |
1830 | .prcm = { | |
1831 | .omap2 = { | |
1832 | .prcm_reg_id = 1, | |
1833 | .module_bit = OMAP3430_EN_MMC3_SHIFT, | |
1834 | .idlest_reg_id = 1, | |
1835 | .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, | |
1836 | }, | |
1837 | }, | |
1838 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1839 | }; |
1840 | ||
1841 | /* | |
844a3b63 PW |
1842 | * 'usb_host_hs' class |
1843 | * high-speed multi-port usb host controller | |
70034d38 VC |
1844 | */ |
1845 | ||
844a3b63 | 1846 | static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { |
70034d38 VC |
1847 | .rev_offs = 0x0000, |
1848 | .sysc_offs = 0x0010, | |
1849 | .syss_offs = 0x0014, | |
844a3b63 PW |
1850 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | |
1851 | SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
1852 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1853 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1854 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1855 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1856 | }; |
1857 | ||
844a3b63 PW |
1858 | static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { |
1859 | .name = "usb_host_hs", | |
1860 | .sysc = &omap3xxx_usb_host_hs_sysc, | |
70034d38 VC |
1861 | }; |
1862 | ||
844a3b63 PW |
1863 | static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { |
1864 | { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, | |
70034d38 VC |
1865 | }; |
1866 | ||
844a3b63 PW |
1867 | static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { |
1868 | { .name = "ohci-irq", .irq = 76 }, | |
1869 | { .name = "ehci-irq", .irq = 77 }, | |
1870 | { .irq = -1 } | |
70034d38 VC |
1871 | }; |
1872 | ||
844a3b63 PW |
1873 | static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { |
1874 | .name = "usb_host_hs", | |
1875 | .class = &omap3xxx_usb_host_hs_hwmod_class, | |
1876 | .clkdm_name = "l3_init_clkdm", | |
1877 | .mpu_irqs = omap3xxx_usb_host_hs_irqs, | |
1878 | .main_clk = "usbhost_48m_fck", | |
1879 | .prcm = { | |
70034d38 | 1880 | .omap2 = { |
844a3b63 | 1881 | .module_offs = OMAP3430ES2_USBHOST_MOD, |
70034d38 | 1882 | .prcm_reg_id = 1, |
844a3b63 | 1883 | .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, |
70034d38 | 1884 | .idlest_reg_id = 1, |
844a3b63 PW |
1885 | .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, |
1886 | .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, | |
70034d38 VC |
1887 | }, |
1888 | }, | |
844a3b63 PW |
1889 | .opt_clks = omap3xxx_usb_host_hs_opt_clks, |
1890 | .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks), | |
70034d38 | 1891 | |
844a3b63 PW |
1892 | /* |
1893 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
1894 | * id: i660 | |
1895 | * | |
1896 | * Description: | |
1897 | * In the following configuration : | |
1898 | * - USBHOST module is set to smart-idle mode | |
1899 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
1900 | * happens when the system is going to a low power mode : all ports | |
1901 | * have been suspended, the master part of the USBHOST module has | |
1902 | * entered the standby state, and SW has cut the functional clocks) | |
1903 | * - an USBHOST interrupt occurs before the module is able to answer | |
1904 | * idle_ack, typically a remote wakeup IRQ. | |
1905 | * Then the USB HOST module will enter a deadlock situation where it | |
1906 | * is no more accessible nor functional. | |
1907 | * | |
1908 | * Workaround: | |
1909 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
1910 | */ | |
1911 | ||
1912 | /* | |
1913 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
1914 | * Id: i571 | |
1915 | * | |
1916 | * Description: | |
1917 | * When the USBHOST module is set to smart-standby mode, and when it is | |
1918 | * ready to enter the standby state (i.e. all ports are suspended and | |
1919 | * all attached devices are in suspend mode), then it can wrongly assert | |
1920 | * the Mstandby signal too early while there are still some residual OCP | |
1921 | * transactions ongoing. If this condition occurs, the internal state | |
1922 | * machine may go to an undefined state and the USB link may be stuck | |
1923 | * upon the next resume. | |
1924 | * | |
1925 | * Workaround: | |
1926 | * Don't use smart standby; use only force standby, | |
1927 | * hence HWMOD_SWSUP_MSTANDBY | |
1928 | */ | |
1929 | ||
1930 | /* | |
1931 | * During system boot; If the hwmod framework resets the module | |
1932 | * the module will have smart idle settings; which can lead to deadlock | |
1933 | * (above Errata Id:i660); so, dont reset the module during boot; | |
1934 | * Use HWMOD_INIT_NO_RESET. | |
1935 | */ | |
70034d38 | 1936 | |
844a3b63 PW |
1937 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | |
1938 | HWMOD_INIT_NO_RESET, | |
70034d38 VC |
1939 | }; |
1940 | ||
844a3b63 PW |
1941 | /* |
1942 | * 'usb_tll_hs' class | |
1943 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
1944 | */ | |
1945 | static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { | |
1946 | .rev_offs = 0x0000, | |
1947 | .sysc_offs = 0x0010, | |
1948 | .syss_offs = 0x0014, | |
1949 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1950 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1951 | SYSC_HAS_AUTOIDLE), | |
1952 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1953 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1954 | }; |
1955 | ||
844a3b63 PW |
1956 | static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { |
1957 | .name = "usb_tll_hs", | |
1958 | .sysc = &omap3xxx_usb_tll_hs_sysc, | |
70034d38 VC |
1959 | }; |
1960 | ||
844a3b63 PW |
1961 | static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { |
1962 | { .name = "tll-irq", .irq = 78 }, | |
1963 | { .irq = -1 } | |
70034d38 VC |
1964 | }; |
1965 | ||
844a3b63 PW |
1966 | static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { |
1967 | .name = "usb_tll_hs", | |
1968 | .class = &omap3xxx_usb_tll_hs_hwmod_class, | |
1969 | .clkdm_name = "l3_init_clkdm", | |
1970 | .mpu_irqs = omap3xxx_usb_tll_hs_irqs, | |
1971 | .main_clk = "usbtll_fck", | |
1972 | .prcm = { | |
70034d38 | 1973 | .omap2 = { |
844a3b63 PW |
1974 | .module_offs = CORE_MOD, |
1975 | .prcm_reg_id = 3, | |
1976 | .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | |
1977 | .idlest_reg_id = 3, | |
1978 | .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, | |
70034d38 VC |
1979 | }, |
1980 | }, | |
70034d38 VC |
1981 | }; |
1982 | ||
45a4bb06 PW |
1983 | static struct omap_hwmod omap3xxx_hdq1w_hwmod = { |
1984 | .name = "hdq1w", | |
1985 | .mpu_irqs = omap2_hdq1w_mpu_irqs, | |
1986 | .main_clk = "hdq_fck", | |
1987 | .prcm = { | |
1988 | .omap2 = { | |
1989 | .module_offs = CORE_MOD, | |
1990 | .prcm_reg_id = 1, | |
1991 | .module_bit = OMAP3430_EN_HDQ_SHIFT, | |
1992 | .idlest_reg_id = 1, | |
1993 | .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT, | |
1994 | }, | |
1995 | }, | |
1996 | .class = &omap2_hdq1w_class, | |
1997 | }; | |
1998 | ||
844a3b63 PW |
1999 | /* |
2000 | * interfaces | |
2001 | */ | |
2002 | ||
2003 | /* L3 -> L4_CORE interface */ | |
2004 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { | |
2005 | .master = &omap3xxx_l3_main_hwmod, | |
2006 | .slave = &omap3xxx_l4_core_hwmod, | |
2007 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2008 | }; |
2009 | ||
844a3b63 PW |
2010 | /* L3 -> L4_PER interface */ |
2011 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { | |
2012 | .master = &omap3xxx_l3_main_hwmod, | |
2013 | .slave = &omap3xxx_l4_per_hwmod, | |
2014 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2015 | }; |
2016 | ||
844a3b63 PW |
2017 | static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { |
2018 | { | |
2019 | .pa_start = 0x68000000, | |
2020 | .pa_end = 0x6800ffff, | |
2021 | .flags = ADDR_TYPE_RT, | |
70034d38 | 2022 | }, |
844a3b63 | 2023 | { } |
70034d38 VC |
2024 | }; |
2025 | ||
844a3b63 PW |
2026 | /* MPU -> L3 interface */ |
2027 | static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { | |
2028 | .master = &omap3xxx_mpu_hwmod, | |
2029 | .slave = &omap3xxx_l3_main_hwmod, | |
2030 | .addr = omap3xxx_l3_main_addrs, | |
2031 | .user = OCP_USER_MPU, | |
70034d38 VC |
2032 | }; |
2033 | ||
844a3b63 PW |
2034 | /* DSS -> l3 */ |
2035 | static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = { | |
2036 | .master = &omap3430es1_dss_core_hwmod, | |
2037 | .slave = &omap3xxx_l3_main_hwmod, | |
2038 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2039 | }; |
2040 | ||
844a3b63 PW |
2041 | static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { |
2042 | .master = &omap3xxx_dss_core_hwmod, | |
2043 | .slave = &omap3xxx_l3_main_hwmod, | |
2044 | .fw = { | |
70034d38 | 2045 | .omap2 = { |
844a3b63 PW |
2046 | .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, |
2047 | .flags = OMAP_FIREWALL_L3, | |
2048 | } | |
70034d38 | 2049 | }, |
844a3b63 | 2050 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2051 | }; |
2052 | ||
844a3b63 PW |
2053 | /* l3_core -> usbhsotg interface */ |
2054 | static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { | |
2055 | .master = &omap3xxx_usbhsotg_hwmod, | |
01438ab6 MK |
2056 | .slave = &omap3xxx_l3_main_hwmod, |
2057 | .clk = "core_l3_ick", | |
844a3b63 | 2058 | .user = OCP_USER_MPU, |
01438ab6 MK |
2059 | }; |
2060 | ||
844a3b63 PW |
2061 | /* l3_core -> am35xx_usbhsotg interface */ |
2062 | static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { | |
2063 | .master = &am35xx_usbhsotg_hwmod, | |
2064 | .slave = &omap3xxx_l3_main_hwmod, | |
2065 | .clk = "core_l3_ick", | |
2066 | .user = OCP_USER_MPU, | |
01438ab6 | 2067 | }; |
844a3b63 PW |
2068 | /* L4_CORE -> L4_WKUP interface */ |
2069 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { | |
2070 | .master = &omap3xxx_l4_core_hwmod, | |
2071 | .slave = &omap3xxx_l4_wkup_hwmod, | |
2072 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2073 | }; |
2074 | ||
844a3b63 PW |
2075 | /* L4 CORE -> MMC1 interface */ |
2076 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = { | |
01438ab6 | 2077 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2078 | .slave = &omap3xxx_pre_es3_mmc1_hwmod, |
2079 | .clk = "mmchs1_ick", | |
2080 | .addr = omap2430_mmc1_addr_space, | |
01438ab6 | 2081 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 | 2082 | .flags = OMAP_FIREWALL_L4 |
01438ab6 MK |
2083 | }; |
2084 | ||
844a3b63 PW |
2085 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { |
2086 | .master = &omap3xxx_l4_core_hwmod, | |
2087 | .slave = &omap3xxx_es3plus_mmc1_hwmod, | |
2088 | .clk = "mmchs1_ick", | |
2089 | .addr = omap2430_mmc1_addr_space, | |
2090 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2091 | .flags = OMAP_FIREWALL_L4 | |
01438ab6 MK |
2092 | }; |
2093 | ||
844a3b63 PW |
2094 | /* L4 CORE -> MMC2 interface */ |
2095 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = { | |
2096 | .master = &omap3xxx_l4_core_hwmod, | |
2097 | .slave = &omap3xxx_pre_es3_mmc2_hwmod, | |
2098 | .clk = "mmchs2_ick", | |
2099 | .addr = omap2430_mmc2_addr_space, | |
2100 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2101 | .flags = OMAP_FIREWALL_L4 | |
2102 | }; | |
70034d38 | 2103 | |
844a3b63 PW |
2104 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { |
2105 | .master = &omap3xxx_l4_core_hwmod, | |
2106 | .slave = &omap3xxx_es3plus_mmc2_hwmod, | |
2107 | .clk = "mmchs2_ick", | |
2108 | .addr = omap2430_mmc2_addr_space, | |
2109 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2110 | .flags = OMAP_FIREWALL_L4 | |
70034d38 VC |
2111 | }; |
2112 | ||
844a3b63 PW |
2113 | /* L4 CORE -> MMC3 interface */ |
2114 | static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { | |
2115 | { | |
2116 | .pa_start = 0x480ad000, | |
2117 | .pa_end = 0x480ad1ff, | |
2118 | .flags = ADDR_TYPE_RT, | |
2119 | }, | |
2120 | { } | |
70034d38 VC |
2121 | }; |
2122 | ||
844a3b63 PW |
2123 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { |
2124 | .master = &omap3xxx_l4_core_hwmod, | |
2125 | .slave = &omap3xxx_mmc3_hwmod, | |
2126 | .clk = "mmchs3_ick", | |
2127 | .addr = omap3xxx_mmc3_addr_space, | |
2128 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2129 | .flags = OMAP_FIREWALL_L4 | |
70034d38 VC |
2130 | }; |
2131 | ||
844a3b63 PW |
2132 | /* L4 CORE -> UART1 interface */ |
2133 | static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { | |
dc48e5fc | 2134 | { |
844a3b63 PW |
2135 | .pa_start = OMAP3_UART1_BASE, |
2136 | .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, | |
2137 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
dc48e5fc | 2138 | }, |
78183f3f | 2139 | { } |
70034d38 VC |
2140 | }; |
2141 | ||
844a3b63 | 2142 | static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { |
dc48e5fc | 2143 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2144 | .slave = &omap3xxx_uart1_hwmod, |
2145 | .clk = "uart1_ick", | |
2146 | .addr = omap3xxx_uart1_addr_space, | |
dc48e5fc | 2147 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2148 | }; |
2149 | ||
844a3b63 PW |
2150 | /* L4 CORE -> UART2 interface */ |
2151 | static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { | |
2152 | { | |
2153 | .pa_start = OMAP3_UART2_BASE, | |
2154 | .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, | |
2155 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2156 | }, |
844a3b63 | 2157 | { } |
70034d38 VC |
2158 | }; |
2159 | ||
844a3b63 PW |
2160 | static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { |
2161 | .master = &omap3xxx_l4_core_hwmod, | |
2162 | .slave = &omap3xxx_uart2_hwmod, | |
2163 | .clk = "uart2_ick", | |
2164 | .addr = omap3xxx_uart2_addr_space, | |
2165 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2166 | }; |
2167 | ||
844a3b63 PW |
2168 | /* L4 PER -> UART3 interface */ |
2169 | static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { | |
dc48e5fc | 2170 | { |
844a3b63 PW |
2171 | .pa_start = OMAP3_UART3_BASE, |
2172 | .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, | |
2173 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2174 | }, |
78183f3f | 2175 | { } |
70034d38 VC |
2176 | }; |
2177 | ||
844a3b63 | 2178 | static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { |
dc48e5fc | 2179 | .master = &omap3xxx_l4_per_hwmod, |
844a3b63 PW |
2180 | .slave = &omap3xxx_uart3_hwmod, |
2181 | .clk = "uart3_ick", | |
2182 | .addr = omap3xxx_uart3_addr_space, | |
dc48e5fc | 2183 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2184 | }; |
2185 | ||
844a3b63 PW |
2186 | /* L4 PER -> UART4 interface */ |
2187 | static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = { | |
2188 | { | |
2189 | .pa_start = OMAP3_UART4_BASE, | |
2190 | .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, | |
2191 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2192 | }, |
844a3b63 | 2193 | { } |
70034d38 VC |
2194 | }; |
2195 | ||
844a3b63 PW |
2196 | static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { |
2197 | .master = &omap3xxx_l4_per_hwmod, | |
2198 | .slave = &omap36xx_uart4_hwmod, | |
2199 | .clk = "uart4_ick", | |
2200 | .addr = omap36xx_uart4_addr_space, | |
2201 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2202 | }; |
2203 | ||
844a3b63 PW |
2204 | /* AM35xx: L4 CORE -> UART4 interface */ |
2205 | static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { | |
dc48e5fc | 2206 | { |
844a3b63 PW |
2207 | .pa_start = OMAP3_UART4_AM35XX_BASE, |
2208 | .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, | |
2209 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
dc48e5fc | 2210 | }, |
70034d38 VC |
2211 | }; |
2212 | ||
844a3b63 PW |
2213 | static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { |
2214 | .master = &omap3xxx_l4_core_hwmod, | |
2215 | .slave = &am35xx_uart4_hwmod, | |
2216 | .clk = "uart4_ick", | |
2217 | .addr = am35xx_uart4_addr_space, | |
dc48e5fc C |
2218 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2219 | }; | |
2220 | ||
844a3b63 PW |
2221 | /* L4 CORE -> I2C1 interface */ |
2222 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { | |
2223 | .master = &omap3xxx_l4_core_hwmod, | |
2224 | .slave = &omap3xxx_i2c1_hwmod, | |
2225 | .clk = "i2c1_ick", | |
2226 | .addr = omap2_i2c1_addr_space, | |
2227 | .fw = { | |
2228 | .omap2 = { | |
2229 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, | |
2230 | .l4_prot_group = 7, | |
2231 | .flags = OMAP_FIREWALL_L4, | |
2232 | } | |
2233 | }, | |
2234 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
8b1906f1 KVA |
2235 | }; |
2236 | ||
844a3b63 PW |
2237 | /* L4 CORE -> I2C2 interface */ |
2238 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { | |
2239 | .master = &omap3xxx_l4_core_hwmod, | |
2240 | .slave = &omap3xxx_i2c2_hwmod, | |
2241 | .clk = "i2c2_ick", | |
2242 | .addr = omap2_i2c2_addr_space, | |
2243 | .fw = { | |
70034d38 | 2244 | .omap2 = { |
844a3b63 PW |
2245 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, |
2246 | .l4_prot_group = 7, | |
2247 | .flags = OMAP_FIREWALL_L4, | |
2248 | } | |
70034d38 | 2249 | }, |
844a3b63 | 2250 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2251 | }; |
2252 | ||
844a3b63 PW |
2253 | /* L4 CORE -> I2C3 interface */ |
2254 | static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { | |
2255 | { | |
2256 | .pa_start = 0x48060000, | |
2257 | .pa_end = 0x48060000 + SZ_128 - 1, | |
2258 | .flags = ADDR_TYPE_RT, | |
2259 | }, | |
2260 | { } | |
70034d38 VC |
2261 | }; |
2262 | ||
844a3b63 PW |
2263 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { |
2264 | .master = &omap3xxx_l4_core_hwmod, | |
2265 | .slave = &omap3xxx_i2c3_hwmod, | |
2266 | .clk = "i2c3_ick", | |
2267 | .addr = omap3xxx_i2c3_addr_space, | |
2268 | .fw = { | |
2269 | .omap2 = { | |
2270 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, | |
2271 | .l4_prot_group = 7, | |
2272 | .flags = OMAP_FIREWALL_L4, | |
2273 | } | |
2274 | }, | |
2275 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2276 | }; |
2277 | ||
844a3b63 PW |
2278 | /* L4 CORE -> SR1 interface */ |
2279 | static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { | |
dc48e5fc | 2280 | { |
844a3b63 PW |
2281 | .pa_start = OMAP34XX_SR1_BASE, |
2282 | .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, | |
2283 | .flags = ADDR_TYPE_RT, | |
dc48e5fc | 2284 | }, |
78183f3f | 2285 | { } |
70034d38 VC |
2286 | }; |
2287 | ||
844a3b63 PW |
2288 | static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { |
2289 | .master = &omap3xxx_l4_core_hwmod, | |
2290 | .slave = &omap34xx_sr1_hwmod, | |
2291 | .clk = "sr_l4_ick", | |
2292 | .addr = omap3_sr1_addr_space, | |
2293 | .user = OCP_USER_MPU, | |
70034d38 VC |
2294 | }; |
2295 | ||
844a3b63 PW |
2296 | static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = { |
2297 | .master = &omap3xxx_l4_core_hwmod, | |
2298 | .slave = &omap36xx_sr1_hwmod, | |
2299 | .clk = "sr_l4_ick", | |
2300 | .addr = omap3_sr1_addr_space, | |
2301 | .user = OCP_USER_MPU, | |
2302 | }; | |
2303 | ||
2304 | /* L4 CORE -> SR1 interface */ | |
2305 | static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { | |
2306 | { | |
2307 | .pa_start = OMAP34XX_SR2_BASE, | |
2308 | .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, | |
2309 | .flags = ADDR_TYPE_RT, | |
70034d38 | 2310 | }, |
844a3b63 | 2311 | { } |
70034d38 VC |
2312 | }; |
2313 | ||
844a3b63 PW |
2314 | static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { |
2315 | .master = &omap3xxx_l4_core_hwmod, | |
2316 | .slave = &omap34xx_sr2_hwmod, | |
2317 | .clk = "sr_l4_ick", | |
2318 | .addr = omap3_sr2_addr_space, | |
2319 | .user = OCP_USER_MPU, | |
70034d38 VC |
2320 | }; |
2321 | ||
844a3b63 PW |
2322 | static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { |
2323 | .master = &omap3xxx_l4_core_hwmod, | |
2324 | .slave = &omap36xx_sr2_hwmod, | |
2325 | .clk = "sr_l4_ick", | |
2326 | .addr = omap3_sr2_addr_space, | |
2327 | .user = OCP_USER_MPU, | |
70034d38 VC |
2328 | }; |
2329 | ||
844a3b63 | 2330 | static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { |
dc48e5fc | 2331 | { |
844a3b63 PW |
2332 | .pa_start = OMAP34XX_HSUSB_OTG_BASE, |
2333 | .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, | |
dc48e5fc C |
2334 | .flags = ADDR_TYPE_RT |
2335 | }, | |
78183f3f | 2336 | { } |
70034d38 VC |
2337 | }; |
2338 | ||
844a3b63 PW |
2339 | /* l4_core -> usbhsotg */ |
2340 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { | |
dc48e5fc | 2341 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2342 | .slave = &omap3xxx_usbhsotg_hwmod, |
2343 | .clk = "l4_ick", | |
2344 | .addr = omap3xxx_usbhsotg_addrs, | |
2345 | .user = OCP_USER_MPU, | |
dc48e5fc C |
2346 | }; |
2347 | ||
844a3b63 PW |
2348 | static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { |
2349 | { | |
2350 | .pa_start = AM35XX_IPSS_USBOTGSS_BASE, | |
2351 | .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, | |
2352 | .flags = ADDR_TYPE_RT | |
70034d38 | 2353 | }, |
844a3b63 | 2354 | { } |
70034d38 VC |
2355 | }; |
2356 | ||
844a3b63 PW |
2357 | /* l4_core -> usbhsotg */ |
2358 | static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { | |
2359 | .master = &omap3xxx_l4_core_hwmod, | |
2360 | .slave = &am35xx_usbhsotg_hwmod, | |
2361 | .clk = "l4_ick", | |
2362 | .addr = am35xx_usbhsotg_addrs, | |
2363 | .user = OCP_USER_MPU, | |
01438ab6 MK |
2364 | }; |
2365 | ||
844a3b63 PW |
2366 | /* L4_WKUP -> L4_SEC interface */ |
2367 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = { | |
2368 | .master = &omap3xxx_l4_wkup_hwmod, | |
2369 | .slave = &omap3xxx_l4_sec_hwmod, | |
2370 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2371 | }; |
2372 | ||
844a3b63 PW |
2373 | /* IVA2 <- L3 interface */ |
2374 | static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { | |
2375 | .master = &omap3xxx_l3_main_hwmod, | |
2376 | .slave = &omap3xxx_iva_hwmod, | |
064931ab | 2377 | .clk = "core_l3_ick", |
844a3b63 | 2378 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
01438ab6 MK |
2379 | }; |
2380 | ||
844a3b63 | 2381 | static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { |
dc48e5fc | 2382 | { |
844a3b63 PW |
2383 | .pa_start = 0x48318000, |
2384 | .pa_end = 0x48318000 + SZ_1K - 1, | |
dc48e5fc C |
2385 | .flags = ADDR_TYPE_RT |
2386 | }, | |
78183f3f | 2387 | { } |
01438ab6 MK |
2388 | }; |
2389 | ||
844a3b63 PW |
2390 | /* l4_wkup -> timer1 */ |
2391 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { | |
2392 | .master = &omap3xxx_l4_wkup_hwmod, | |
2393 | .slave = &omap3xxx_timer1_hwmod, | |
2394 | .clk = "gpt1_ick", | |
2395 | .addr = omap3xxx_timer1_addrs, | |
2396 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2397 | }; |
2398 | ||
844a3b63 PW |
2399 | static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { |
2400 | { | |
2401 | .pa_start = 0x49032000, | |
2402 | .pa_end = 0x49032000 + SZ_1K - 1, | |
2403 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2404 | }, |
844a3b63 | 2405 | { } |
01438ab6 MK |
2406 | }; |
2407 | ||
844a3b63 PW |
2408 | /* l4_per -> timer2 */ |
2409 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { | |
2410 | .master = &omap3xxx_l4_per_hwmod, | |
2411 | .slave = &omap3xxx_timer2_hwmod, | |
2412 | .clk = "gpt2_ick", | |
2413 | .addr = omap3xxx_timer2_addrs, | |
2414 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2415 | }; |
2416 | ||
844a3b63 | 2417 | static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { |
dc48e5fc | 2418 | { |
844a3b63 PW |
2419 | .pa_start = 0x49034000, |
2420 | .pa_end = 0x49034000 + SZ_1K - 1, | |
dc48e5fc C |
2421 | .flags = ADDR_TYPE_RT |
2422 | }, | |
78183f3f | 2423 | { } |
01438ab6 MK |
2424 | }; |
2425 | ||
844a3b63 PW |
2426 | /* l4_per -> timer3 */ |
2427 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { | |
dc48e5fc | 2428 | .master = &omap3xxx_l4_per_hwmod, |
844a3b63 PW |
2429 | .slave = &omap3xxx_timer3_hwmod, |
2430 | .clk = "gpt3_ick", | |
2431 | .addr = omap3xxx_timer3_addrs, | |
2432 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2433 | }; |
2434 | ||
844a3b63 PW |
2435 | static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { |
2436 | { | |
2437 | .pa_start = 0x49036000, | |
2438 | .pa_end = 0x49036000 + SZ_1K - 1, | |
2439 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2440 | }, |
844a3b63 | 2441 | { } |
01438ab6 MK |
2442 | }; |
2443 | ||
844a3b63 PW |
2444 | /* l4_per -> timer4 */ |
2445 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { | |
2446 | .master = &omap3xxx_l4_per_hwmod, | |
2447 | .slave = &omap3xxx_timer4_hwmod, | |
2448 | .clk = "gpt4_ick", | |
2449 | .addr = omap3xxx_timer4_addrs, | |
2450 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2451 | }; |
2452 | ||
844a3b63 PW |
2453 | static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { |
2454 | { | |
2455 | .pa_start = 0x49038000, | |
2456 | .pa_end = 0x49038000 + SZ_1K - 1, | |
2457 | .flags = ADDR_TYPE_RT | |
2458 | }, | |
2459 | { } | |
d3442726 TG |
2460 | }; |
2461 | ||
844a3b63 PW |
2462 | /* l4_per -> timer5 */ |
2463 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { | |
2464 | .master = &omap3xxx_l4_per_hwmod, | |
2465 | .slave = &omap3xxx_timer5_hwmod, | |
2466 | .clk = "gpt5_ick", | |
2467 | .addr = omap3xxx_timer5_addrs, | |
2468 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2469 | }; |
2470 | ||
844a3b63 PW |
2471 | static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { |
2472 | { | |
2473 | .pa_start = 0x4903A000, | |
2474 | .pa_end = 0x4903A000 + SZ_1K - 1, | |
2475 | .flags = ADDR_TYPE_RT | |
2476 | }, | |
2477 | { } | |
cea6b942 SG |
2478 | }; |
2479 | ||
844a3b63 PW |
2480 | /* l4_per -> timer6 */ |
2481 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { | |
2482 | .master = &omap3xxx_l4_per_hwmod, | |
2483 | .slave = &omap3xxx_timer6_hwmod, | |
2484 | .clk = "gpt6_ick", | |
2485 | .addr = omap3xxx_timer6_addrs, | |
2486 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2487 | }; |
2488 | ||
844a3b63 PW |
2489 | static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { |
2490 | { | |
2491 | .pa_start = 0x4903C000, | |
2492 | .pa_end = 0x4903C000 + SZ_1K - 1, | |
2493 | .flags = ADDR_TYPE_RT | |
d3442726 | 2494 | }, |
844a3b63 | 2495 | { } |
d3442726 TG |
2496 | }; |
2497 | ||
844a3b63 PW |
2498 | /* l4_per -> timer7 */ |
2499 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { | |
2500 | .master = &omap3xxx_l4_per_hwmod, | |
2501 | .slave = &omap3xxx_timer7_hwmod, | |
2502 | .clk = "gpt7_ick", | |
2503 | .addr = omap3xxx_timer7_addrs, | |
2504 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
cea6b942 SG |
2505 | }; |
2506 | ||
844a3b63 PW |
2507 | static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { |
2508 | { | |
2509 | .pa_start = 0x4903E000, | |
2510 | .pa_end = 0x4903E000 + SZ_1K - 1, | |
2511 | .flags = ADDR_TYPE_RT | |
d3442726 | 2512 | }, |
844a3b63 | 2513 | { } |
d3442726 TG |
2514 | }; |
2515 | ||
844a3b63 PW |
2516 | /* l4_per -> timer8 */ |
2517 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { | |
2518 | .master = &omap3xxx_l4_per_hwmod, | |
2519 | .slave = &omap3xxx_timer8_hwmod, | |
2520 | .clk = "gpt8_ick", | |
2521 | .addr = omap3xxx_timer8_addrs, | |
2522 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2523 | }; |
2524 | ||
844a3b63 PW |
2525 | static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { |
2526 | { | |
2527 | .pa_start = 0x49040000, | |
2528 | .pa_end = 0x49040000 + SZ_1K - 1, | |
2529 | .flags = ADDR_TYPE_RT | |
2530 | }, | |
2531 | { } | |
2532 | }; | |
0f9dfdd3 | 2533 | |
844a3b63 PW |
2534 | /* l4_per -> timer9 */ |
2535 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { | |
2536 | .master = &omap3xxx_l4_per_hwmod, | |
2537 | .slave = &omap3xxx_timer9_hwmod, | |
2538 | .clk = "gpt9_ick", | |
2539 | .addr = omap3xxx_timer9_addrs, | |
2540 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2541 | }; |
2542 | ||
844a3b63 PW |
2543 | /* l4_core -> timer10 */ |
2544 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { | |
2545 | .master = &omap3xxx_l4_core_hwmod, | |
2546 | .slave = &omap3xxx_timer10_hwmod, | |
2547 | .clk = "gpt10_ick", | |
2548 | .addr = omap2_timer10_addrs, | |
2549 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2550 | }; |
2551 | ||
844a3b63 PW |
2552 | /* l4_core -> timer11 */ |
2553 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { | |
2554 | .master = &omap3xxx_l4_core_hwmod, | |
2555 | .slave = &omap3xxx_timer11_hwmod, | |
2556 | .clk = "gpt11_ick", | |
2557 | .addr = omap2_timer11_addrs, | |
2558 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2559 | }; |
2560 | ||
844a3b63 | 2561 | static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { |
0f9dfdd3 | 2562 | { |
844a3b63 PW |
2563 | .pa_start = 0x48304000, |
2564 | .pa_end = 0x48304000 + SZ_1K - 1, | |
2565 | .flags = ADDR_TYPE_RT | |
0f9dfdd3 | 2566 | }, |
78183f3f | 2567 | { } |
0f9dfdd3 FC |
2568 | }; |
2569 | ||
844a3b63 PW |
2570 | /* l4_core -> timer12 */ |
2571 | static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { | |
2572 | .master = &omap3xxx_l4_sec_hwmod, | |
2573 | .slave = &omap3xxx_timer12_hwmod, | |
2574 | .clk = "gpt12_ick", | |
2575 | .addr = omap3xxx_timer12_addrs, | |
0f9dfdd3 FC |
2576 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2577 | }; | |
2578 | ||
844a3b63 PW |
2579 | /* l4_wkup -> wd_timer2 */ |
2580 | static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { | |
2581 | { | |
2582 | .pa_start = 0x48314000, | |
2583 | .pa_end = 0x4831407f, | |
2584 | .flags = ADDR_TYPE_RT | |
0f9dfdd3 | 2585 | }, |
844a3b63 | 2586 | { } |
0f9dfdd3 FC |
2587 | }; |
2588 | ||
844a3b63 PW |
2589 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { |
2590 | .master = &omap3xxx_l4_wkup_hwmod, | |
2591 | .slave = &omap3xxx_wd_timer2_hwmod, | |
2592 | .clk = "wdt2_ick", | |
2593 | .addr = omap3xxx_wd_timer2_addrs, | |
2594 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2595 | }; | |
2596 | ||
2597 | /* l4_core -> dss */ | |
2598 | static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { | |
0f616a4e | 2599 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2600 | .slave = &omap3430es1_dss_core_hwmod, |
2601 | .clk = "dss_ick", | |
2602 | .addr = omap2_dss_addrs, | |
2603 | .fw = { | |
2604 | .omap2 = { | |
2605 | .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, | |
2606 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2607 | .flags = OMAP_FIREWALL_L4, | |
2608 | } | |
2609 | }, | |
0f616a4e C |
2610 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2611 | }; | |
2612 | ||
844a3b63 | 2613 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { |
0f616a4e | 2614 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2615 | .slave = &omap3xxx_dss_core_hwmod, |
2616 | .clk = "dss_ick", | |
2617 | .addr = omap2_dss_addrs, | |
2618 | .fw = { | |
2619 | .omap2 = { | |
2620 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, | |
2621 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2622 | .flags = OMAP_FIREWALL_L4, | |
2623 | } | |
2624 | }, | |
0f616a4e C |
2625 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2626 | }; | |
2627 | ||
844a3b63 PW |
2628 | /* l4_core -> dss_dispc */ |
2629 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { | |
0f616a4e | 2630 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2631 | .slave = &omap3xxx_dss_dispc_hwmod, |
2632 | .clk = "dss_ick", | |
2633 | .addr = omap2_dss_dispc_addrs, | |
2634 | .fw = { | |
2635 | .omap2 = { | |
2636 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, | |
2637 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2638 | .flags = OMAP_FIREWALL_L4, | |
2639 | } | |
2640 | }, | |
0f616a4e C |
2641 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2642 | }; | |
2643 | ||
844a3b63 | 2644 | static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { |
0f616a4e | 2645 | { |
844a3b63 PW |
2646 | .pa_start = 0x4804FC00, |
2647 | .pa_end = 0x4804FFFF, | |
2648 | .flags = ADDR_TYPE_RT | |
0f616a4e | 2649 | }, |
78183f3f | 2650 | { } |
0f616a4e C |
2651 | }; |
2652 | ||
844a3b63 PW |
2653 | /* l4_core -> dss_dsi1 */ |
2654 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { | |
0f616a4e | 2655 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2656 | .slave = &omap3xxx_dss_dsi1_hwmod, |
2657 | .clk = "dss_ick", | |
2658 | .addr = omap3xxx_dss_dsi1_addrs, | |
2659 | .fw = { | |
2660 | .omap2 = { | |
2661 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, | |
2662 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2663 | .flags = OMAP_FIREWALL_L4, | |
2664 | } | |
2665 | }, | |
0f616a4e C |
2666 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2667 | }; | |
2668 | ||
844a3b63 PW |
2669 | /* l4_core -> dss_rfbi */ |
2670 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { | |
2671 | .master = &omap3xxx_l4_core_hwmod, | |
2672 | .slave = &omap3xxx_dss_rfbi_hwmod, | |
2673 | .clk = "dss_ick", | |
2674 | .addr = omap2_dss_rfbi_addrs, | |
2675 | .fw = { | |
0f616a4e | 2676 | .omap2 = { |
844a3b63 PW |
2677 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, |
2678 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , | |
2679 | .flags = OMAP_FIREWALL_L4, | |
2680 | } | |
0f616a4e | 2681 | }, |
844a3b63 | 2682 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
0f616a4e C |
2683 | }; |
2684 | ||
844a3b63 PW |
2685 | /* l4_core -> dss_venc */ |
2686 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { | |
2687 | .master = &omap3xxx_l4_core_hwmod, | |
2688 | .slave = &omap3xxx_dss_venc_hwmod, | |
2689 | .clk = "dss_ick", | |
2690 | .addr = omap2_dss_venc_addrs, | |
2691 | .fw = { | |
70034d38 | 2692 | .omap2 = { |
844a3b63 PW |
2693 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, |
2694 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2695 | .flags = OMAP_FIREWALL_L4, | |
2696 | } | |
70034d38 | 2697 | }, |
844a3b63 PW |
2698 | .flags = OCPIF_SWSUP_IDLE, |
2699 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2700 | }; |
2701 | ||
844a3b63 PW |
2702 | /* l4_wkup -> gpio1 */ |
2703 | static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { | |
2704 | { | |
2705 | .pa_start = 0x48310000, | |
2706 | .pa_end = 0x483101ff, | |
2707 | .flags = ADDR_TYPE_RT | |
2708 | }, | |
2709 | { } | |
70034d38 VC |
2710 | }; |
2711 | ||
844a3b63 PW |
2712 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { |
2713 | .master = &omap3xxx_l4_wkup_hwmod, | |
2714 | .slave = &omap3xxx_gpio1_hwmod, | |
2715 | .addr = omap3xxx_gpio1_addrs, | |
2716 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f616a4e C |
2717 | }; |
2718 | ||
844a3b63 PW |
2719 | /* l4_per -> gpio2 */ |
2720 | static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { | |
2721 | { | |
2722 | .pa_start = 0x49050000, | |
2723 | .pa_end = 0x490501ff, | |
2724 | .flags = ADDR_TYPE_RT | |
70034d38 | 2725 | }, |
844a3b63 | 2726 | { } |
70034d38 VC |
2727 | }; |
2728 | ||
844a3b63 PW |
2729 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { |
2730 | .master = &omap3xxx_l4_per_hwmod, | |
2731 | .slave = &omap3xxx_gpio2_hwmod, | |
2732 | .addr = omap3xxx_gpio2_addrs, | |
2733 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2734 | }; |
2735 | ||
844a3b63 PW |
2736 | /* l4_per -> gpio3 */ |
2737 | static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { | |
2738 | { | |
2739 | .pa_start = 0x49052000, | |
2740 | .pa_end = 0x490521ff, | |
2741 | .flags = ADDR_TYPE_RT | |
2742 | }, | |
2743 | { } | |
70034d38 VC |
2744 | }; |
2745 | ||
844a3b63 PW |
2746 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { |
2747 | .master = &omap3xxx_l4_per_hwmod, | |
2748 | .slave = &omap3xxx_gpio3_hwmod, | |
2749 | .addr = omap3xxx_gpio3_addrs, | |
2750 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f616a4e C |
2751 | }; |
2752 | ||
844a3b63 PW |
2753 | /* l4_per -> gpio4 */ |
2754 | static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { | |
2755 | { | |
2756 | .pa_start = 0x49054000, | |
2757 | .pa_end = 0x490541ff, | |
2758 | .flags = ADDR_TYPE_RT | |
70034d38 | 2759 | }, |
844a3b63 | 2760 | { } |
70034d38 VC |
2761 | }; |
2762 | ||
844a3b63 PW |
2763 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { |
2764 | .master = &omap3xxx_l4_per_hwmod, | |
2765 | .slave = &omap3xxx_gpio4_hwmod, | |
2766 | .addr = omap3xxx_gpio4_addrs, | |
2767 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2768 | }; |
2769 | ||
844a3b63 PW |
2770 | /* l4_per -> gpio5 */ |
2771 | static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { | |
2772 | { | |
2773 | .pa_start = 0x49056000, | |
2774 | .pa_end = 0x490561ff, | |
2775 | .flags = ADDR_TYPE_RT | |
2776 | }, | |
2777 | { } | |
01438ab6 MK |
2778 | }; |
2779 | ||
844a3b63 PW |
2780 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { |
2781 | .master = &omap3xxx_l4_per_hwmod, | |
2782 | .slave = &omap3xxx_gpio5_hwmod, | |
2783 | .addr = omap3xxx_gpio5_addrs, | |
2784 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2785 | }; |
2786 | ||
844a3b63 PW |
2787 | /* l4_per -> gpio6 */ |
2788 | static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { | |
2789 | { | |
2790 | .pa_start = 0x49058000, | |
2791 | .pa_end = 0x490581ff, | |
2792 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2793 | }, |
844a3b63 | 2794 | { } |
01438ab6 MK |
2795 | }; |
2796 | ||
844a3b63 PW |
2797 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { |
2798 | .master = &omap3xxx_l4_per_hwmod, | |
2799 | .slave = &omap3xxx_gpio6_hwmod, | |
2800 | .addr = omap3xxx_gpio6_addrs, | |
2801 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2802 | }; |
2803 | ||
844a3b63 PW |
2804 | /* dma_system -> L3 */ |
2805 | static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { | |
2806 | .master = &omap3xxx_dma_system_hwmod, | |
2807 | .slave = &omap3xxx_l3_main_hwmod, | |
2808 | .clk = "core_l3_ick", | |
2809 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2810 | }; |
2811 | ||
844a3b63 PW |
2812 | static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { |
2813 | { | |
2814 | .pa_start = 0x48056000, | |
2815 | .pa_end = 0x48056fff, | |
2816 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2817 | }, |
844a3b63 | 2818 | { } |
01438ab6 MK |
2819 | }; |
2820 | ||
844a3b63 PW |
2821 | /* l4_cfg -> dma_system */ |
2822 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { | |
2823 | .master = &omap3xxx_l4_core_hwmod, | |
2824 | .slave = &omap3xxx_dma_system_hwmod, | |
2825 | .clk = "core_l4_ick", | |
2826 | .addr = omap3xxx_dma_system_addrs, | |
2827 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2828 | }; |
2829 | ||
844a3b63 PW |
2830 | static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { |
2831 | { | |
2832 | .name = "mpu", | |
2833 | .pa_start = 0x48074000, | |
2834 | .pa_end = 0x480740ff, | |
2835 | .flags = ADDR_TYPE_RT | |
2836 | }, | |
2837 | { } | |
d3442726 TG |
2838 | }; |
2839 | ||
844a3b63 PW |
2840 | /* l4_core -> mcbsp1 */ |
2841 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { | |
2842 | .master = &omap3xxx_l4_core_hwmod, | |
2843 | .slave = &omap3xxx_mcbsp1_hwmod, | |
2844 | .clk = "mcbsp1_ick", | |
2845 | .addr = omap3xxx_mcbsp1_addrs, | |
2846 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2847 | }; |
2848 | ||
844a3b63 PW |
2849 | static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { |
2850 | { | |
2851 | .name = "mpu", | |
2852 | .pa_start = 0x49022000, | |
2853 | .pa_end = 0x490220ff, | |
2854 | .flags = ADDR_TYPE_RT | |
2855 | }, | |
2856 | { } | |
d3442726 TG |
2857 | }; |
2858 | ||
844a3b63 PW |
2859 | /* l4_per -> mcbsp2 */ |
2860 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { | |
2861 | .master = &omap3xxx_l4_per_hwmod, | |
2862 | .slave = &omap3xxx_mcbsp2_hwmod, | |
2863 | .clk = "mcbsp2_ick", | |
2864 | .addr = omap3xxx_mcbsp2_addrs, | |
2865 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2866 | }; |
2867 | ||
844a3b63 PW |
2868 | static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { |
2869 | { | |
2870 | .name = "mpu", | |
2871 | .pa_start = 0x49024000, | |
2872 | .pa_end = 0x490240ff, | |
2873 | .flags = ADDR_TYPE_RT | |
2874 | }, | |
2875 | { } | |
d3442726 TG |
2876 | }; |
2877 | ||
844a3b63 PW |
2878 | /* l4_per -> mcbsp3 */ |
2879 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { | |
2880 | .master = &omap3xxx_l4_per_hwmod, | |
2881 | .slave = &omap3xxx_mcbsp3_hwmod, | |
2882 | .clk = "mcbsp3_ick", | |
2883 | .addr = omap3xxx_mcbsp3_addrs, | |
2884 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
a52e2ab6 PW |
2885 | }; |
2886 | ||
844a3b63 PW |
2887 | static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { |
2888 | { | |
2889 | .name = "mpu", | |
2890 | .pa_start = 0x49026000, | |
2891 | .pa_end = 0x490260ff, | |
2892 | .flags = ADDR_TYPE_RT | |
a52e2ab6 | 2893 | }, |
844a3b63 | 2894 | { } |
a52e2ab6 PW |
2895 | }; |
2896 | ||
844a3b63 PW |
2897 | /* l4_per -> mcbsp4 */ |
2898 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { | |
2899 | .master = &omap3xxx_l4_per_hwmod, | |
2900 | .slave = &omap3xxx_mcbsp4_hwmod, | |
2901 | .clk = "mcbsp4_ick", | |
2902 | .addr = omap3xxx_mcbsp4_addrs, | |
2903 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2904 | }; |
2905 | ||
844a3b63 PW |
2906 | static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { |
2907 | { | |
2908 | .name = "mpu", | |
2909 | .pa_start = 0x48096000, | |
2910 | .pa_end = 0x480960ff, | |
2911 | .flags = ADDR_TYPE_RT | |
2912 | }, | |
2913 | { } | |
2914 | }; | |
b163605e | 2915 | |
844a3b63 PW |
2916 | /* l4_core -> mcbsp5 */ |
2917 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { | |
2918 | .master = &omap3xxx_l4_core_hwmod, | |
2919 | .slave = &omap3xxx_mcbsp5_hwmod, | |
2920 | .clk = "mcbsp5_ick", | |
2921 | .addr = omap3xxx_mcbsp5_addrs, | |
2922 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2923 | }; |
2924 | ||
844a3b63 PW |
2925 | static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { |
2926 | { | |
2927 | .name = "sidetone", | |
2928 | .pa_start = 0x49028000, | |
2929 | .pa_end = 0x490280ff, | |
2930 | .flags = ADDR_TYPE_RT | |
2931 | }, | |
2932 | { } | |
d3442726 TG |
2933 | }; |
2934 | ||
844a3b63 PW |
2935 | /* l4_per -> mcbsp2_sidetone */ |
2936 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { | |
2937 | .master = &omap3xxx_l4_per_hwmod, | |
2938 | .slave = &omap3xxx_mcbsp2_sidetone_hwmod, | |
2939 | .clk = "mcbsp2_ick", | |
2940 | .addr = omap3xxx_mcbsp2_sidetone_addrs, | |
2941 | .user = OCP_USER_MPU, | |
b163605e PW |
2942 | }; |
2943 | ||
844a3b63 PW |
2944 | static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { |
2945 | { | |
2946 | .name = "sidetone", | |
2947 | .pa_start = 0x4902A000, | |
2948 | .pa_end = 0x4902A0ff, | |
2949 | .flags = ADDR_TYPE_RT | |
2950 | }, | |
2951 | { } | |
a52e2ab6 PW |
2952 | }; |
2953 | ||
844a3b63 PW |
2954 | /* l4_per -> mcbsp3_sidetone */ |
2955 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { | |
2956 | .master = &omap3xxx_l4_per_hwmod, | |
2957 | .slave = &omap3xxx_mcbsp3_sidetone_hwmod, | |
2958 | .clk = "mcbsp3_ick", | |
2959 | .addr = omap3xxx_mcbsp3_sidetone_addrs, | |
2960 | .user = OCP_USER_MPU, | |
a52e2ab6 PW |
2961 | }; |
2962 | ||
844a3b63 PW |
2963 | static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { |
2964 | { | |
2965 | .pa_start = 0x48094000, | |
2966 | .pa_end = 0x480941ff, | |
2967 | .flags = ADDR_TYPE_RT, | |
d3442726 | 2968 | }, |
844a3b63 | 2969 | { } |
d3442726 TG |
2970 | }; |
2971 | ||
844a3b63 PW |
2972 | /* l4_core -> mailbox */ |
2973 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { | |
2974 | .master = &omap3xxx_l4_core_hwmod, | |
2975 | .slave = &omap3xxx_mailbox_hwmod, | |
2976 | .addr = omap3xxx_mailbox_addrs, | |
2977 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2978 | }; | |
b163605e | 2979 | |
844a3b63 PW |
2980 | /* l4 core -> mcspi1 interface */ |
2981 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { | |
2982 | .master = &omap3xxx_l4_core_hwmod, | |
2983 | .slave = &omap34xx_mcspi1, | |
2984 | .clk = "mcspi1_ick", | |
2985 | .addr = omap2_mcspi1_addr_space, | |
2986 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
2987 | }; |
2988 | ||
844a3b63 PW |
2989 | /* l4 core -> mcspi2 interface */ |
2990 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { | |
2991 | .master = &omap3xxx_l4_core_hwmod, | |
2992 | .slave = &omap34xx_mcspi2, | |
2993 | .clk = "mcspi2_ick", | |
2994 | .addr = omap2_mcspi2_addr_space, | |
2995 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
2996 | }; |
2997 | ||
844a3b63 PW |
2998 | /* l4 core -> mcspi3 interface */ |
2999 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { | |
3000 | .master = &omap3xxx_l4_core_hwmod, | |
3001 | .slave = &omap34xx_mcspi3, | |
3002 | .clk = "mcspi3_ick", | |
3003 | .addr = omap2430_mcspi3_addr_space, | |
3004 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
3005 | }; |
3006 | ||
844a3b63 PW |
3007 | /* l4 core -> mcspi4 interface */ |
3008 | static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { | |
3009 | { | |
3010 | .pa_start = 0x480ba000, | |
3011 | .pa_end = 0x480ba0ff, | |
3012 | .flags = ADDR_TYPE_RT, | |
d3442726 | 3013 | }, |
844a3b63 PW |
3014 | { } |
3015 | }; | |
3016 | ||
3017 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { | |
3018 | .master = &omap3xxx_l4_core_hwmod, | |
3019 | .slave = &omap34xx_mcspi4, | |
3020 | .clk = "mcspi4_ick", | |
3021 | .addr = omap34xx_mcspi4_addr_space, | |
3022 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3023 | }; |
3024 | ||
de231388 KM |
3025 | static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { |
3026 | .master = &omap3xxx_usb_host_hs_hwmod, | |
3027 | .slave = &omap3xxx_l3_main_hwmod, | |
3028 | .clk = "core_l3_ick", | |
3029 | .user = OCP_USER_MPU, | |
3030 | }; | |
3031 | ||
de231388 KM |
3032 | static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = { |
3033 | { | |
3034 | .name = "uhh", | |
3035 | .pa_start = 0x48064000, | |
3036 | .pa_end = 0x480643ff, | |
3037 | .flags = ADDR_TYPE_RT | |
3038 | }, | |
3039 | { | |
3040 | .name = "ohci", | |
3041 | .pa_start = 0x48064400, | |
3042 | .pa_end = 0x480647ff, | |
3043 | }, | |
3044 | { | |
3045 | .name = "ehci", | |
3046 | .pa_start = 0x48064800, | |
3047 | .pa_end = 0x48064cff, | |
3048 | }, | |
3049 | {} | |
3050 | }; | |
3051 | ||
3052 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { | |
3053 | .master = &omap3xxx_l4_core_hwmod, | |
3054 | .slave = &omap3xxx_usb_host_hs_hwmod, | |
3055 | .clk = "usbhost_ick", | |
3056 | .addr = omap3xxx_usb_host_hs_addrs, | |
3057 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3058 | }; | |
3059 | ||
de231388 KM |
3060 | static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { |
3061 | { | |
3062 | .name = "tll", | |
3063 | .pa_start = 0x48062000, | |
3064 | .pa_end = 0x48062fff, | |
3065 | .flags = ADDR_TYPE_RT | |
3066 | }, | |
3067 | {} | |
3068 | }; | |
3069 | ||
3070 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { | |
3071 | .master = &omap3xxx_l4_core_hwmod, | |
3072 | .slave = &omap3xxx_usb_tll_hs_hwmod, | |
3073 | .clk = "usbtll_ick", | |
3074 | .addr = omap3xxx_usb_tll_hs_addrs, | |
3075 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3076 | }; | |
3077 | ||
45a4bb06 PW |
3078 | /* l4_core -> hdq1w interface */ |
3079 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = { | |
3080 | .master = &omap3xxx_l4_core_hwmod, | |
3081 | .slave = &omap3xxx_hdq1w_hwmod, | |
3082 | .clk = "hdq_ick", | |
3083 | .addr = omap2_hdq1w_addr_space, | |
3084 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3085 | .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, | |
3086 | }; | |
3087 | ||
0a78c5c5 PW |
3088 | static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { |
3089 | &omap3xxx_l3_main__l4_core, | |
3090 | &omap3xxx_l3_main__l4_per, | |
3091 | &omap3xxx_mpu__l3_main, | |
3092 | &omap3xxx_l4_core__l4_wkup, | |
3093 | &omap3xxx_l4_core__mmc3, | |
3094 | &omap3_l4_core__uart1, | |
3095 | &omap3_l4_core__uart2, | |
3096 | &omap3_l4_per__uart3, | |
3097 | &omap3_l4_core__i2c1, | |
3098 | &omap3_l4_core__i2c2, | |
3099 | &omap3_l4_core__i2c3, | |
3100 | &omap3xxx_l4_wkup__l4_sec, | |
3101 | &omap3xxx_l4_wkup__timer1, | |
3102 | &omap3xxx_l4_per__timer2, | |
3103 | &omap3xxx_l4_per__timer3, | |
3104 | &omap3xxx_l4_per__timer4, | |
3105 | &omap3xxx_l4_per__timer5, | |
3106 | &omap3xxx_l4_per__timer6, | |
3107 | &omap3xxx_l4_per__timer7, | |
3108 | &omap3xxx_l4_per__timer8, | |
3109 | &omap3xxx_l4_per__timer9, | |
3110 | &omap3xxx_l4_core__timer10, | |
3111 | &omap3xxx_l4_core__timer11, | |
3112 | &omap3xxx_l4_wkup__wd_timer2, | |
3113 | &omap3xxx_l4_wkup__gpio1, | |
3114 | &omap3xxx_l4_per__gpio2, | |
3115 | &omap3xxx_l4_per__gpio3, | |
3116 | &omap3xxx_l4_per__gpio4, | |
3117 | &omap3xxx_l4_per__gpio5, | |
3118 | &omap3xxx_l4_per__gpio6, | |
3119 | &omap3xxx_dma_system__l3, | |
3120 | &omap3xxx_l4_core__dma_system, | |
3121 | &omap3xxx_l4_core__mcbsp1, | |
3122 | &omap3xxx_l4_per__mcbsp2, | |
3123 | &omap3xxx_l4_per__mcbsp3, | |
3124 | &omap3xxx_l4_per__mcbsp4, | |
3125 | &omap3xxx_l4_core__mcbsp5, | |
3126 | &omap3xxx_l4_per__mcbsp2_sidetone, | |
3127 | &omap3xxx_l4_per__mcbsp3_sidetone, | |
3128 | &omap34xx_l4_core__mcspi1, | |
3129 | &omap34xx_l4_core__mcspi2, | |
3130 | &omap34xx_l4_core__mcspi3, | |
3131 | &omap34xx_l4_core__mcspi4, | |
d6504acd PW |
3132 | NULL, |
3133 | }; | |
3134 | ||
0a78c5c5 PW |
3135 | /* GP-only hwmod links */ |
3136 | static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = { | |
3137 | &omap3xxx_l4_sec__timer12, | |
91a36bdb AK |
3138 | NULL |
3139 | }; | |
3140 | ||
0a78c5c5 PW |
3141 | /* 3430ES1-only hwmod links */ |
3142 | static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { | |
3143 | &omap3430es1_dss__l3, | |
3144 | &omap3430es1_l4_core__dss, | |
d6504acd PW |
3145 | NULL |
3146 | }; | |
3147 | ||
0a78c5c5 PW |
3148 | /* 3430ES2+-only hwmod links */ |
3149 | static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = { | |
3150 | &omap3xxx_dss__l3, | |
3151 | &omap3xxx_l4_core__dss, | |
3152 | &omap3xxx_usbhsotg__l3, | |
3153 | &omap3xxx_l4_core__usbhsotg, | |
3154 | &omap3xxx_usb_host_hs__l3_main_2, | |
3155 | &omap3xxx_l4_core__usb_host_hs, | |
3156 | &omap3xxx_l4_core__usb_tll_hs, | |
d6504acd PW |
3157 | NULL |
3158 | }; | |
870ea2b8 | 3159 | |
0a78c5c5 PW |
3160 | /* <= 3430ES3-only hwmod links */ |
3161 | static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = { | |
3162 | &omap3xxx_l4_core__pre_es3_mmc1, | |
3163 | &omap3xxx_l4_core__pre_es3_mmc2, | |
a52e2ab6 PW |
3164 | NULL |
3165 | }; | |
3166 | ||
0a78c5c5 PW |
3167 | /* 3430ES3+-only hwmod links */ |
3168 | static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = { | |
3169 | &omap3xxx_l4_core__es3plus_mmc1, | |
3170 | &omap3xxx_l4_core__es3plus_mmc2, | |
a52e2ab6 PW |
3171 | NULL |
3172 | }; | |
3173 | ||
0a78c5c5 PW |
3174 | /* 34xx-only hwmod links (all ES revisions) */ |
3175 | static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { | |
3176 | &omap3xxx_l3__iva, | |
3177 | &omap34xx_l4_core__sr1, | |
3178 | &omap34xx_l4_core__sr2, | |
3179 | &omap3xxx_l4_core__mailbox, | |
45a4bb06 | 3180 | &omap3xxx_l4_core__hdq1w, |
d6504acd PW |
3181 | NULL |
3182 | }; | |
273ff8c3 | 3183 | |
0a78c5c5 PW |
3184 | /* 36xx-only hwmod links (all ES revisions) */ |
3185 | static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { | |
3186 | &omap3xxx_l3__iva, | |
3187 | &omap36xx_l4_per__uart4, | |
3188 | &omap3xxx_dss__l3, | |
3189 | &omap3xxx_l4_core__dss, | |
3190 | &omap36xx_l4_core__sr1, | |
3191 | &omap36xx_l4_core__sr2, | |
3192 | &omap3xxx_usbhsotg__l3, | |
3193 | &omap3xxx_l4_core__usbhsotg, | |
3194 | &omap3xxx_l4_core__mailbox, | |
3195 | &omap3xxx_usb_host_hs__l3_main_2, | |
3196 | &omap3xxx_l4_core__usb_host_hs, | |
3197 | &omap3xxx_l4_core__usb_tll_hs, | |
3198 | &omap3xxx_l4_core__es3plus_mmc1, | |
3199 | &omap3xxx_l4_core__es3plus_mmc2, | |
45a4bb06 | 3200 | &omap3xxx_l4_core__hdq1w, |
d6504acd PW |
3201 | NULL |
3202 | }; | |
3203 | ||
0a78c5c5 PW |
3204 | static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { |
3205 | &omap3xxx_dss__l3, | |
3206 | &omap3xxx_l4_core__dss, | |
3207 | &am35xx_usbhsotg__l3, | |
3208 | &am35xx_l4_core__usbhsotg, | |
3209 | &am35xx_l4_core__uart4, | |
3210 | &omap3xxx_usb_host_hs__l3_main_2, | |
3211 | &omap3xxx_l4_core__usb_host_hs, | |
3212 | &omap3xxx_l4_core__usb_tll_hs, | |
3213 | &omap3xxx_l4_core__es3plus_mmc1, | |
3214 | &omap3xxx_l4_core__es3plus_mmc2, | |
d6504acd | 3215 | NULL |
7359154e PW |
3216 | }; |
3217 | ||
0a78c5c5 PW |
3218 | static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { |
3219 | &omap3xxx_l4_core__dss_dispc, | |
3220 | &omap3xxx_l4_core__dss_dsi1, | |
3221 | &omap3xxx_l4_core__dss_rfbi, | |
3222 | &omap3xxx_l4_core__dss_venc, | |
1d2f56c8 IY |
3223 | NULL |
3224 | }; | |
3225 | ||
7359154e PW |
3226 | int __init omap3xxx_hwmod_init(void) |
3227 | { | |
d6504acd | 3228 | int r; |
0a78c5c5 | 3229 | struct omap_hwmod_ocp_if **h = NULL; |
d6504acd PW |
3230 | unsigned int rev; |
3231 | ||
0a78c5c5 PW |
3232 | /* Register hwmod links common to all OMAP3 */ |
3233 | r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); | |
ace90216 | 3234 | if (r < 0) |
d6504acd PW |
3235 | return r; |
3236 | ||
0a78c5c5 | 3237 | /* Register GP-only hwmod links. */ |
91a36bdb | 3238 | if (omap_type() == OMAP2_DEVICE_TYPE_GP) { |
0a78c5c5 | 3239 | r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs); |
91a36bdb AK |
3240 | if (r < 0) |
3241 | return r; | |
3242 | } | |
3243 | ||
d6504acd PW |
3244 | rev = omap_rev(); |
3245 | ||
3246 | /* | |
0a78c5c5 | 3247 | * Register hwmod links common to individual OMAP3 families, all |
d6504acd PW |
3248 | * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) |
3249 | * All possible revisions should be included in this conditional. | |
3250 | */ | |
3251 | if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || | |
3252 | rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || | |
3253 | rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3254 | h = omap34xx_hwmod_ocp_ifs; |
d6504acd | 3255 | } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) { |
0a78c5c5 | 3256 | h = am35xx_hwmod_ocp_ifs; |
d6504acd PW |
3257 | } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || |
3258 | rev == OMAP3630_REV_ES1_2) { | |
0a78c5c5 | 3259 | h = omap36xx_hwmod_ocp_ifs; |
d6504acd PW |
3260 | } else { |
3261 | WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); | |
3262 | return -EINVAL; | |
3263 | }; | |
3264 | ||
0a78c5c5 | 3265 | r = omap_hwmod_register_links(h); |
ace90216 | 3266 | if (r < 0) |
d6504acd PW |
3267 | return r; |
3268 | ||
3269 | /* | |
0a78c5c5 | 3270 | * Register hwmod links specific to certain ES levels of a |
d6504acd PW |
3271 | * particular family of silicon (e.g., 34xx ES1.0) |
3272 | */ | |
3273 | h = NULL; | |
3274 | if (rev == OMAP3430_REV_ES1_0) { | |
0a78c5c5 | 3275 | h = omap3430es1_hwmod_ocp_ifs; |
d6504acd PW |
3276 | } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || |
3277 | rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || | |
3278 | rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3279 | h = omap3430es2plus_hwmod_ocp_ifs; |
d6504acd PW |
3280 | }; |
3281 | ||
a52e2ab6 | 3282 | if (h) { |
0a78c5c5 | 3283 | r = omap_hwmod_register_links(h); |
a52e2ab6 PW |
3284 | if (r < 0) |
3285 | return r; | |
3286 | } | |
3287 | ||
3288 | h = NULL; | |
3289 | if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || | |
3290 | rev == OMAP3430_REV_ES2_1) { | |
0a78c5c5 | 3291 | h = omap3430_pre_es3_hwmod_ocp_ifs; |
a52e2ab6 PW |
3292 | } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || |
3293 | rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3294 | h = omap3430_es3plus_hwmod_ocp_ifs; |
a52e2ab6 PW |
3295 | }; |
3296 | ||
d6504acd | 3297 | if (h) |
0a78c5c5 | 3298 | r = omap_hwmod_register_links(h); |
1d2f56c8 IY |
3299 | if (r < 0) |
3300 | return r; | |
3301 | ||
3302 | /* | |
3303 | * DSS code presumes that dss_core hwmod is handled first, | |
3304 | * _before_ any other DSS related hwmods so register common | |
0a78c5c5 PW |
3305 | * DSS hwmod links last to ensure that dss_core is already |
3306 | * registered. Otherwise some change things may happen, for | |
3307 | * ex. if dispc is handled before dss_core and DSS is enabled | |
3308 | * in bootloader DISPC will be reset with outputs enabled | |
3309 | * which sometimes leads to unrecoverable L3 error. XXX The | |
3310 | * long-term fix to this is to ensure hwmods are set up in | |
3311 | * dependency order in the hwmod core code. | |
1d2f56c8 | 3312 | */ |
0a78c5c5 | 3313 | r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs); |
d6504acd PW |
3314 | |
3315 | return r; | |
7359154e | 3316 | } |