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7359154e PW |
1 | /* |
2 | * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips | |
3 | * | |
78183f3f | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
7359154e PW |
5 | * Paul Walmsley |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * The data in this file should be completely autogeneratable from | |
12 | * the TI hardware database or other technical documentation. | |
13 | * | |
14 | * XXX these should be marked initdata for multi-OMAP kernels | |
15 | */ | |
16 | #include <plat/omap_hwmod.h> | |
17 | #include <mach/irqs.h> | |
18 | #include <plat/cpu.h> | |
19 | #include <plat/dma.h> | |
046465b7 | 20 | #include <plat/serial.h> |
e04d9e1e | 21 | #include <plat/l3_3xxx.h> |
4fe20e97 RN |
22 | #include <plat/l4_3xxx.h> |
23 | #include <plat/i2c.h> | |
70034d38 | 24 | #include <plat/gpio.h> |
6ab8946f | 25 | #include <plat/mmc.h> |
dc48e5fc | 26 | #include <plat/mcbsp.h> |
0f616a4e | 27 | #include <plat/mcspi.h> |
ce722d26 | 28 | #include <plat/dmtimer.h> |
7359154e | 29 | |
43b40992 PW |
30 | #include "omap_hwmod_common_data.h" |
31 | ||
7359154e | 32 | #include "prm-regbits-34xx.h" |
6b667f88 | 33 | #include "cm-regbits-34xx.h" |
ff2516fb | 34 | #include "wd_timer.h" |
273ff8c3 | 35 | #include <mach/am35xx.h> |
7359154e PW |
36 | |
37 | /* | |
38 | * OMAP3xxx hardware module integration data | |
39 | * | |
40 | * ALl of the data in this section should be autogeneratable from the | |
41 | * TI hardware database or other technical documentation. Data that | |
42 | * is driver-specific or driver-kernel integration-specific belongs | |
43 | * elsewhere. | |
44 | */ | |
45 | ||
46 | static struct omap_hwmod omap3xxx_mpu_hwmod; | |
540064bf | 47 | static struct omap_hwmod omap3xxx_iva_hwmod; |
4a7cf90a | 48 | static struct omap_hwmod omap3xxx_l3_main_hwmod; |
7359154e PW |
49 | static struct omap_hwmod omap3xxx_l4_core_hwmod; |
50 | static struct omap_hwmod omap3xxx_l4_per_hwmod; | |
6b667f88 | 51 | static struct omap_hwmod omap3xxx_wd_timer2_hwmod; |
e04d9e1e SG |
52 | static struct omap_hwmod omap3430es1_dss_core_hwmod; |
53 | static struct omap_hwmod omap3xxx_dss_core_hwmod; | |
54 | static struct omap_hwmod omap3xxx_dss_dispc_hwmod; | |
55 | static struct omap_hwmod omap3xxx_dss_dsi1_hwmod; | |
56 | static struct omap_hwmod omap3xxx_dss_rfbi_hwmod; | |
57 | static struct omap_hwmod omap3xxx_dss_venc_hwmod; | |
4fe20e97 RN |
58 | static struct omap_hwmod omap3xxx_i2c1_hwmod; |
59 | static struct omap_hwmod omap3xxx_i2c2_hwmod; | |
60 | static struct omap_hwmod omap3xxx_i2c3_hwmod; | |
70034d38 VC |
61 | static struct omap_hwmod omap3xxx_gpio1_hwmod; |
62 | static struct omap_hwmod omap3xxx_gpio2_hwmod; | |
63 | static struct omap_hwmod omap3xxx_gpio3_hwmod; | |
64 | static struct omap_hwmod omap3xxx_gpio4_hwmod; | |
65 | static struct omap_hwmod omap3xxx_gpio5_hwmod; | |
66 | static struct omap_hwmod omap3xxx_gpio6_hwmod; | |
d3442726 TG |
67 | static struct omap_hwmod omap34xx_sr1_hwmod; |
68 | static struct omap_hwmod omap34xx_sr2_hwmod; | |
0f616a4e C |
69 | static struct omap_hwmod omap34xx_mcspi1; |
70 | static struct omap_hwmod omap34xx_mcspi2; | |
71 | static struct omap_hwmod omap34xx_mcspi3; | |
72 | static struct omap_hwmod omap34xx_mcspi4; | |
b163605e PW |
73 | static struct omap_hwmod omap3xxx_mmc1_hwmod; |
74 | static struct omap_hwmod omap3xxx_mmc2_hwmod; | |
75 | static struct omap_hwmod omap3xxx_mmc3_hwmod; | |
273ff8c3 | 76 | static struct omap_hwmod am35xx_usbhsotg_hwmod; |
7359154e | 77 | |
01438ab6 MK |
78 | static struct omap_hwmod omap3xxx_dma_system_hwmod; |
79 | ||
dc48e5fc C |
80 | static struct omap_hwmod omap3xxx_mcbsp1_hwmod; |
81 | static struct omap_hwmod omap3xxx_mcbsp2_hwmod; | |
82 | static struct omap_hwmod omap3xxx_mcbsp3_hwmod; | |
83 | static struct omap_hwmod omap3xxx_mcbsp4_hwmod; | |
84 | static struct omap_hwmod omap3xxx_mcbsp5_hwmod; | |
85 | static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod; | |
86 | static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod; | |
87 | ||
7359154e | 88 | /* L3 -> L4_CORE interface */ |
4a7cf90a KH |
89 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { |
90 | .master = &omap3xxx_l3_main_hwmod, | |
7359154e PW |
91 | .slave = &omap3xxx_l4_core_hwmod, |
92 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
93 | }; | |
94 | ||
95 | /* L3 -> L4_PER interface */ | |
4a7cf90a KH |
96 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { |
97 | .master = &omap3xxx_l3_main_hwmod, | |
7359154e PW |
98 | .slave = &omap3xxx_l4_per_hwmod, |
99 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
100 | }; | |
101 | ||
4bb194dc | 102 | /* L3 taret configuration and error log registers */ |
103 | static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { | |
104 | { .irq = INT_34XX_L3_DBG_IRQ }, | |
105 | { .irq = INT_34XX_L3_APP_IRQ }, | |
212738a4 | 106 | { .irq = -1 } |
4bb194dc | 107 | }; |
108 | ||
109 | static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { | |
110 | { | |
111 | .pa_start = 0x68000000, | |
112 | .pa_end = 0x6800ffff, | |
113 | .flags = ADDR_TYPE_RT, | |
114 | }, | |
78183f3f | 115 | { } |
4bb194dc | 116 | }; |
117 | ||
7359154e | 118 | /* MPU -> L3 interface */ |
4a7cf90a | 119 | static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { |
4bb194dc | 120 | .master = &omap3xxx_mpu_hwmod, |
121 | .slave = &omap3xxx_l3_main_hwmod, | |
122 | .addr = omap3xxx_l3_main_addrs, | |
7359154e PW |
123 | .user = OCP_USER_MPU, |
124 | }; | |
125 | ||
126 | /* Slave interfaces on the L3 interconnect */ | |
4a7cf90a KH |
127 | static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = { |
128 | &omap3xxx_mpu__l3_main, | |
7359154e PW |
129 | }; |
130 | ||
e04d9e1e SG |
131 | /* DSS -> l3 */ |
132 | static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { | |
133 | .master = &omap3xxx_dss_core_hwmod, | |
134 | .slave = &omap3xxx_l3_main_hwmod, | |
135 | .fw = { | |
136 | .omap2 = { | |
137 | .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, | |
138 | .flags = OMAP_FIREWALL_L3, | |
139 | } | |
140 | }, | |
141 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
142 | }; | |
143 | ||
7359154e | 144 | /* Master interfaces on the L3 interconnect */ |
4a7cf90a KH |
145 | static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = { |
146 | &omap3xxx_l3_main__l4_core, | |
147 | &omap3xxx_l3_main__l4_per, | |
7359154e PW |
148 | }; |
149 | ||
150 | /* L3 */ | |
4a7cf90a | 151 | static struct omap_hwmod omap3xxx_l3_main_hwmod = { |
fa98347e | 152 | .name = "l3_main", |
43b40992 | 153 | .class = &l3_hwmod_class, |
0d619a89 | 154 | .mpu_irqs = omap3xxx_l3_main_irqs, |
4a7cf90a KH |
155 | .masters = omap3xxx_l3_main_masters, |
156 | .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), | |
157 | .slaves = omap3xxx_l3_main_slaves, | |
158 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves), | |
2eb1875d KH |
159 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
160 | .flags = HWMOD_NO_IDLEST, | |
7359154e PW |
161 | }; |
162 | ||
163 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod; | |
046465b7 KH |
164 | static struct omap_hwmod omap3xxx_uart1_hwmod; |
165 | static struct omap_hwmod omap3xxx_uart2_hwmod; | |
166 | static struct omap_hwmod omap3xxx_uart3_hwmod; | |
167 | static struct omap_hwmod omap3xxx_uart4_hwmod; | |
870ea2b8 | 168 | static struct omap_hwmod omap3xxx_usbhsotg_hwmod; |
7359154e | 169 | |
870ea2b8 HH |
170 | /* l3_core -> usbhsotg interface */ |
171 | static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { | |
172 | .master = &omap3xxx_usbhsotg_hwmod, | |
173 | .slave = &omap3xxx_l3_main_hwmod, | |
174 | .clk = "core_l3_ick", | |
175 | .user = OCP_USER_MPU, | |
176 | }; | |
7359154e | 177 | |
273ff8c3 HH |
178 | /* l3_core -> am35xx_usbhsotg interface */ |
179 | static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { | |
180 | .master = &am35xx_usbhsotg_hwmod, | |
181 | .slave = &omap3xxx_l3_main_hwmod, | |
182 | .clk = "core_l3_ick", | |
183 | .user = OCP_USER_MPU, | |
184 | }; | |
7359154e PW |
185 | /* L4_CORE -> L4_WKUP interface */ |
186 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { | |
187 | .master = &omap3xxx_l4_core_hwmod, | |
188 | .slave = &omap3xxx_l4_wkup_hwmod, | |
189 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
190 | }; | |
191 | ||
b163605e | 192 | /* L4 CORE -> MMC1 interface */ |
b163605e PW |
193 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = { |
194 | .master = &omap3xxx_l4_core_hwmod, | |
195 | .slave = &omap3xxx_mmc1_hwmod, | |
196 | .clk = "mmchs1_ick", | |
ded11383 | 197 | .addr = omap2430_mmc1_addr_space, |
b163605e PW |
198 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
199 | .flags = OMAP_FIREWALL_L4 | |
200 | }; | |
201 | ||
202 | /* L4 CORE -> MMC2 interface */ | |
b163605e PW |
203 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = { |
204 | .master = &omap3xxx_l4_core_hwmod, | |
205 | .slave = &omap3xxx_mmc2_hwmod, | |
206 | .clk = "mmchs2_ick", | |
ded11383 | 207 | .addr = omap2430_mmc2_addr_space, |
b163605e PW |
208 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
209 | .flags = OMAP_FIREWALL_L4 | |
210 | }; | |
211 | ||
212 | /* L4 CORE -> MMC3 interface */ | |
213 | static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { | |
214 | { | |
215 | .pa_start = 0x480ad000, | |
216 | .pa_end = 0x480ad1ff, | |
217 | .flags = ADDR_TYPE_RT, | |
218 | }, | |
78183f3f | 219 | { } |
b163605e PW |
220 | }; |
221 | ||
222 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { | |
223 | .master = &omap3xxx_l4_core_hwmod, | |
224 | .slave = &omap3xxx_mmc3_hwmod, | |
225 | .clk = "mmchs3_ick", | |
226 | .addr = omap3xxx_mmc3_addr_space, | |
b163605e PW |
227 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
228 | .flags = OMAP_FIREWALL_L4 | |
229 | }; | |
230 | ||
046465b7 KH |
231 | /* L4 CORE -> UART1 interface */ |
232 | static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { | |
233 | { | |
234 | .pa_start = OMAP3_UART1_BASE, | |
235 | .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, | |
236 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
237 | }, | |
78183f3f | 238 | { } |
046465b7 KH |
239 | }; |
240 | ||
241 | static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { | |
242 | .master = &omap3xxx_l4_core_hwmod, | |
243 | .slave = &omap3xxx_uart1_hwmod, | |
244 | .clk = "uart1_ick", | |
245 | .addr = omap3xxx_uart1_addr_space, | |
046465b7 KH |
246 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
247 | }; | |
248 | ||
249 | /* L4 CORE -> UART2 interface */ | |
250 | static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { | |
251 | { | |
252 | .pa_start = OMAP3_UART2_BASE, | |
253 | .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, | |
254 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
255 | }, | |
78183f3f | 256 | { } |
046465b7 KH |
257 | }; |
258 | ||
259 | static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { | |
260 | .master = &omap3xxx_l4_core_hwmod, | |
261 | .slave = &omap3xxx_uart2_hwmod, | |
262 | .clk = "uart2_ick", | |
263 | .addr = omap3xxx_uart2_addr_space, | |
046465b7 KH |
264 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
265 | }; | |
266 | ||
267 | /* L4 PER -> UART3 interface */ | |
268 | static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { | |
269 | { | |
270 | .pa_start = OMAP3_UART3_BASE, | |
271 | .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, | |
272 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
273 | }, | |
78183f3f | 274 | { } |
046465b7 KH |
275 | }; |
276 | ||
277 | static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { | |
278 | .master = &omap3xxx_l4_per_hwmod, | |
279 | .slave = &omap3xxx_uart3_hwmod, | |
280 | .clk = "uart3_ick", | |
281 | .addr = omap3xxx_uart3_addr_space, | |
046465b7 KH |
282 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
283 | }; | |
284 | ||
285 | /* L4 PER -> UART4 interface */ | |
286 | static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = { | |
287 | { | |
288 | .pa_start = OMAP3_UART4_BASE, | |
289 | .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, | |
290 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
291 | }, | |
78183f3f | 292 | { } |
046465b7 KH |
293 | }; |
294 | ||
295 | static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { | |
296 | .master = &omap3xxx_l4_per_hwmod, | |
297 | .slave = &omap3xxx_uart4_hwmod, | |
298 | .clk = "uart4_ick", | |
299 | .addr = omap3xxx_uart4_addr_space, | |
046465b7 KH |
300 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
301 | }; | |
302 | ||
4fe20e97 | 303 | /* L4 CORE -> I2C1 interface */ |
4fe20e97 RN |
304 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { |
305 | .master = &omap3xxx_l4_core_hwmod, | |
306 | .slave = &omap3xxx_i2c1_hwmod, | |
307 | .clk = "i2c1_ick", | |
ded11383 | 308 | .addr = omap2_i2c1_addr_space, |
4fe20e97 RN |
309 | .fw = { |
310 | .omap2 = { | |
311 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, | |
312 | .l4_prot_group = 7, | |
313 | .flags = OMAP_FIREWALL_L4, | |
314 | } | |
315 | }, | |
316 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
317 | }; | |
318 | ||
319 | /* L4 CORE -> I2C2 interface */ | |
4fe20e97 RN |
320 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { |
321 | .master = &omap3xxx_l4_core_hwmod, | |
322 | .slave = &omap3xxx_i2c2_hwmod, | |
323 | .clk = "i2c2_ick", | |
ded11383 | 324 | .addr = omap2_i2c2_addr_space, |
4fe20e97 RN |
325 | .fw = { |
326 | .omap2 = { | |
327 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, | |
328 | .l4_prot_group = 7, | |
329 | .flags = OMAP_FIREWALL_L4, | |
330 | } | |
331 | }, | |
332 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
333 | }; | |
334 | ||
335 | /* L4 CORE -> I2C3 interface */ | |
336 | static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { | |
337 | { | |
338 | .pa_start = 0x48060000, | |
ded11383 | 339 | .pa_end = 0x48060000 + SZ_128 - 1, |
4fe20e97 RN |
340 | .flags = ADDR_TYPE_RT, |
341 | }, | |
78183f3f | 342 | { } |
4fe20e97 RN |
343 | }; |
344 | ||
345 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { | |
346 | .master = &omap3xxx_l4_core_hwmod, | |
347 | .slave = &omap3xxx_i2c3_hwmod, | |
348 | .clk = "i2c3_ick", | |
349 | .addr = omap3xxx_i2c3_addr_space, | |
4fe20e97 RN |
350 | .fw = { |
351 | .omap2 = { | |
352 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, | |
353 | .l4_prot_group = 7, | |
354 | .flags = OMAP_FIREWALL_L4, | |
355 | } | |
356 | }, | |
357 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
358 | }; | |
359 | ||
d3442726 TG |
360 | /* L4 CORE -> SR1 interface */ |
361 | static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { | |
362 | { | |
363 | .pa_start = OMAP34XX_SR1_BASE, | |
364 | .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, | |
365 | .flags = ADDR_TYPE_RT, | |
366 | }, | |
78183f3f | 367 | { } |
d3442726 TG |
368 | }; |
369 | ||
370 | static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = { | |
371 | .master = &omap3xxx_l4_core_hwmod, | |
372 | .slave = &omap34xx_sr1_hwmod, | |
373 | .clk = "sr_l4_ick", | |
374 | .addr = omap3_sr1_addr_space, | |
d3442726 TG |
375 | .user = OCP_USER_MPU, |
376 | }; | |
377 | ||
378 | /* L4 CORE -> SR1 interface */ | |
379 | static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { | |
380 | { | |
381 | .pa_start = OMAP34XX_SR2_BASE, | |
382 | .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, | |
383 | .flags = ADDR_TYPE_RT, | |
384 | }, | |
78183f3f | 385 | { } |
d3442726 TG |
386 | }; |
387 | ||
388 | static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = { | |
389 | .master = &omap3xxx_l4_core_hwmod, | |
390 | .slave = &omap34xx_sr2_hwmod, | |
391 | .clk = "sr_l4_ick", | |
392 | .addr = omap3_sr2_addr_space, | |
d3442726 TG |
393 | .user = OCP_USER_MPU, |
394 | }; | |
395 | ||
870ea2b8 HH |
396 | /* |
397 | * usbhsotg interface data | |
398 | */ | |
399 | ||
400 | static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { | |
401 | { | |
402 | .pa_start = OMAP34XX_HSUSB_OTG_BASE, | |
403 | .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, | |
404 | .flags = ADDR_TYPE_RT | |
405 | }, | |
78183f3f | 406 | { } |
870ea2b8 HH |
407 | }; |
408 | ||
409 | /* l4_core -> usbhsotg */ | |
410 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { | |
411 | .master = &omap3xxx_l4_core_hwmod, | |
412 | .slave = &omap3xxx_usbhsotg_hwmod, | |
413 | .clk = "l4_ick", | |
414 | .addr = omap3xxx_usbhsotg_addrs, | |
870ea2b8 HH |
415 | .user = OCP_USER_MPU, |
416 | }; | |
417 | ||
418 | static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = { | |
419 | &omap3xxx_usbhsotg__l3, | |
420 | }; | |
421 | ||
422 | static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = { | |
423 | &omap3xxx_l4_core__usbhsotg, | |
424 | }; | |
425 | ||
273ff8c3 HH |
426 | static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { |
427 | { | |
428 | .pa_start = AM35XX_IPSS_USBOTGSS_BASE, | |
429 | .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, | |
430 | .flags = ADDR_TYPE_RT | |
431 | }, | |
78183f3f | 432 | { } |
273ff8c3 HH |
433 | }; |
434 | ||
435 | /* l4_core -> usbhsotg */ | |
436 | static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { | |
437 | .master = &omap3xxx_l4_core_hwmod, | |
438 | .slave = &am35xx_usbhsotg_hwmod, | |
439 | .clk = "l4_ick", | |
440 | .addr = am35xx_usbhsotg_addrs, | |
273ff8c3 HH |
441 | .user = OCP_USER_MPU, |
442 | }; | |
443 | ||
444 | static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = { | |
445 | &am35xx_usbhsotg__l3, | |
446 | }; | |
447 | ||
448 | static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = { | |
449 | &am35xx_l4_core__usbhsotg, | |
450 | }; | |
7359154e PW |
451 | /* Slave interfaces on the L4_CORE interconnect */ |
452 | static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { | |
4a7cf90a | 453 | &omap3xxx_l3_main__l4_core, |
7359154e PW |
454 | }; |
455 | ||
456 | /* L4 CORE */ | |
457 | static struct omap_hwmod omap3xxx_l4_core_hwmod = { | |
fa98347e | 458 | .name = "l4_core", |
43b40992 | 459 | .class = &l4_hwmod_class, |
7359154e PW |
460 | .slaves = omap3xxx_l4_core_slaves, |
461 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves), | |
2eb1875d KH |
462 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
463 | .flags = HWMOD_NO_IDLEST, | |
7359154e PW |
464 | }; |
465 | ||
466 | /* Slave interfaces on the L4_PER interconnect */ | |
467 | static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = { | |
4a7cf90a | 468 | &omap3xxx_l3_main__l4_per, |
7359154e PW |
469 | }; |
470 | ||
7359154e PW |
471 | /* L4 PER */ |
472 | static struct omap_hwmod omap3xxx_l4_per_hwmod = { | |
fa98347e | 473 | .name = "l4_per", |
43b40992 | 474 | .class = &l4_hwmod_class, |
7359154e PW |
475 | .slaves = omap3xxx_l4_per_slaves, |
476 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves), | |
2eb1875d KH |
477 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
478 | .flags = HWMOD_NO_IDLEST, | |
7359154e PW |
479 | }; |
480 | ||
481 | /* Slave interfaces on the L4_WKUP interconnect */ | |
482 | static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = { | |
483 | &omap3xxx_l4_core__l4_wkup, | |
484 | }; | |
485 | ||
7359154e PW |
486 | /* L4 WKUP */ |
487 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { | |
fa98347e | 488 | .name = "l4_wkup", |
43b40992 | 489 | .class = &l4_hwmod_class, |
7359154e PW |
490 | .slaves = omap3xxx_l4_wkup_slaves, |
491 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves), | |
2eb1875d KH |
492 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
493 | .flags = HWMOD_NO_IDLEST, | |
7359154e PW |
494 | }; |
495 | ||
496 | /* Master interfaces on the MPU device */ | |
497 | static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = { | |
4a7cf90a | 498 | &omap3xxx_mpu__l3_main, |
7359154e PW |
499 | }; |
500 | ||
501 | /* MPU */ | |
502 | static struct omap_hwmod omap3xxx_mpu_hwmod = { | |
5c2c0296 | 503 | .name = "mpu", |
43b40992 | 504 | .class = &mpu_hwmod_class, |
7359154e PW |
505 | .main_clk = "arm_fck", |
506 | .masters = omap3xxx_mpu_masters, | |
507 | .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters), | |
508 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
509 | }; | |
510 | ||
540064bf KH |
511 | /* |
512 | * IVA2_2 interface data | |
513 | */ | |
514 | ||
515 | /* IVA2 <- L3 interface */ | |
516 | static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { | |
517 | .master = &omap3xxx_l3_main_hwmod, | |
518 | .slave = &omap3xxx_iva_hwmod, | |
519 | .clk = "iva2_ck", | |
520 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
521 | }; | |
522 | ||
523 | static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = { | |
524 | &omap3xxx_l3__iva, | |
525 | }; | |
526 | ||
527 | /* | |
528 | * IVA2 (IVA2) | |
529 | */ | |
530 | ||
531 | static struct omap_hwmod omap3xxx_iva_hwmod = { | |
532 | .name = "iva", | |
533 | .class = &iva_hwmod_class, | |
534 | .masters = omap3xxx_iva_masters, | |
535 | .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters), | |
536 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
537 | }; | |
538 | ||
ce722d26 TG |
539 | /* timer class */ |
540 | static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { | |
541 | .rev_offs = 0x0000, | |
542 | .sysc_offs = 0x0010, | |
543 | .syss_offs = 0x0014, | |
544 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
545 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
546 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), | |
547 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
548 | .sysc_fields = &omap_hwmod_sysc_type1, | |
6b667f88 VC |
549 | }; |
550 | ||
ce722d26 TG |
551 | static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { |
552 | .name = "timer", | |
553 | .sysc = &omap3xxx_timer_1ms_sysc, | |
554 | .rev = OMAP_TIMER_IP_VERSION_1, | |
6b667f88 VC |
555 | }; |
556 | ||
ce722d26 | 557 | static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { |
6b667f88 VC |
558 | .rev_offs = 0x0000, |
559 | .sysc_offs = 0x0010, | |
560 | .syss_offs = 0x0014, | |
ce722d26 TG |
561 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | |
562 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
6b667f88 | 563 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
ce722d26 | 564 | .sysc_fields = &omap_hwmod_sysc_type1, |
6b667f88 VC |
565 | }; |
566 | ||
ce722d26 TG |
567 | static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { |
568 | .name = "timer", | |
569 | .sysc = &omap3xxx_timer_sysc, | |
570 | .rev = OMAP_TIMER_IP_VERSION_1, | |
4fe20e97 RN |
571 | }; |
572 | ||
ce722d26 TG |
573 | /* timer1 */ |
574 | static struct omap_hwmod omap3xxx_timer1_hwmod; | |
6b667f88 | 575 | |
ce722d26 TG |
576 | static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { |
577 | { | |
578 | .pa_start = 0x48318000, | |
579 | .pa_end = 0x48318000 + SZ_1K - 1, | |
580 | .flags = ADDR_TYPE_RT | |
581 | }, | |
78183f3f | 582 | { } |
6b667f88 VC |
583 | }; |
584 | ||
ce722d26 TG |
585 | /* l4_wkup -> timer1 */ |
586 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { | |
587 | .master = &omap3xxx_l4_wkup_hwmod, | |
588 | .slave = &omap3xxx_timer1_hwmod, | |
589 | .clk = "gpt1_ick", | |
590 | .addr = omap3xxx_timer1_addrs, | |
ce722d26 TG |
591 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
592 | }; | |
593 | ||
594 | /* timer1 slave port */ | |
595 | static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = { | |
596 | &omap3xxx_l4_wkup__timer1, | |
597 | }; | |
598 | ||
599 | /* timer1 hwmod */ | |
600 | static struct omap_hwmod omap3xxx_timer1_hwmod = { | |
601 | .name = "timer1", | |
0d619a89 | 602 | .mpu_irqs = omap2_timer1_mpu_irqs, |
ce722d26 | 603 | .main_clk = "gpt1_fck", |
6b667f88 VC |
604 | .prcm = { |
605 | .omap2 = { | |
606 | .prcm_reg_id = 1, | |
ce722d26 | 607 | .module_bit = OMAP3430_EN_GPT1_SHIFT, |
6b667f88 VC |
608 | .module_offs = WKUP_MOD, |
609 | .idlest_reg_id = 1, | |
ce722d26 | 610 | .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, |
6b667f88 VC |
611 | }, |
612 | }, | |
ce722d26 TG |
613 | .slaves = omap3xxx_timer1_slaves, |
614 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves), | |
615 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
616 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
046465b7 KH |
617 | }; |
618 | ||
ce722d26 TG |
619 | /* timer2 */ |
620 | static struct omap_hwmod omap3xxx_timer2_hwmod; | |
046465b7 | 621 | |
ce722d26 TG |
622 | static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { |
623 | { | |
624 | .pa_start = 0x49032000, | |
625 | .pa_end = 0x49032000 + SZ_1K - 1, | |
626 | .flags = ADDR_TYPE_RT | |
627 | }, | |
78183f3f | 628 | { } |
046465b7 KH |
629 | }; |
630 | ||
ce722d26 TG |
631 | /* l4_per -> timer2 */ |
632 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { | |
633 | .master = &omap3xxx_l4_per_hwmod, | |
634 | .slave = &omap3xxx_timer2_hwmod, | |
635 | .clk = "gpt2_ick", | |
636 | .addr = omap3xxx_timer2_addrs, | |
ce722d26 | 637 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
046465b7 KH |
638 | }; |
639 | ||
ce722d26 TG |
640 | /* timer2 slave port */ |
641 | static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = { | |
642 | &omap3xxx_l4_per__timer2, | |
046465b7 KH |
643 | }; |
644 | ||
ce722d26 TG |
645 | /* timer2 hwmod */ |
646 | static struct omap_hwmod omap3xxx_timer2_hwmod = { | |
647 | .name = "timer2", | |
0d619a89 | 648 | .mpu_irqs = omap2_timer2_mpu_irqs, |
ce722d26 | 649 | .main_clk = "gpt2_fck", |
046465b7 KH |
650 | .prcm = { |
651 | .omap2 = { | |
046465b7 | 652 | .prcm_reg_id = 1, |
ce722d26 TG |
653 | .module_bit = OMAP3430_EN_GPT2_SHIFT, |
654 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 655 | .idlest_reg_id = 1, |
ce722d26 | 656 | .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, |
046465b7 KH |
657 | }, |
658 | }, | |
ce722d26 TG |
659 | .slaves = omap3xxx_timer2_slaves, |
660 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves), | |
661 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
662 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
046465b7 KH |
663 | }; |
664 | ||
ce722d26 TG |
665 | /* timer3 */ |
666 | static struct omap_hwmod omap3xxx_timer3_hwmod; | |
046465b7 | 667 | |
ce722d26 TG |
668 | static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { |
669 | { | |
670 | .pa_start = 0x49034000, | |
671 | .pa_end = 0x49034000 + SZ_1K - 1, | |
672 | .flags = ADDR_TYPE_RT | |
673 | }, | |
78183f3f | 674 | { } |
046465b7 KH |
675 | }; |
676 | ||
ce722d26 TG |
677 | /* l4_per -> timer3 */ |
678 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { | |
679 | .master = &omap3xxx_l4_per_hwmod, | |
680 | .slave = &omap3xxx_timer3_hwmod, | |
681 | .clk = "gpt3_ick", | |
682 | .addr = omap3xxx_timer3_addrs, | |
ce722d26 | 683 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
046465b7 KH |
684 | }; |
685 | ||
ce722d26 TG |
686 | /* timer3 slave port */ |
687 | static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = { | |
688 | &omap3xxx_l4_per__timer3, | |
046465b7 KH |
689 | }; |
690 | ||
ce722d26 TG |
691 | /* timer3 hwmod */ |
692 | static struct omap_hwmod omap3xxx_timer3_hwmod = { | |
693 | .name = "timer3", | |
0d619a89 | 694 | .mpu_irqs = omap2_timer3_mpu_irqs, |
ce722d26 | 695 | .main_clk = "gpt3_fck", |
046465b7 KH |
696 | .prcm = { |
697 | .omap2 = { | |
046465b7 | 698 | .prcm_reg_id = 1, |
ce722d26 TG |
699 | .module_bit = OMAP3430_EN_GPT3_SHIFT, |
700 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 701 | .idlest_reg_id = 1, |
ce722d26 | 702 | .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, |
046465b7 KH |
703 | }, |
704 | }, | |
ce722d26 TG |
705 | .slaves = omap3xxx_timer3_slaves, |
706 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves), | |
707 | .class = &omap3xxx_timer_hwmod_class, | |
708 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
046465b7 KH |
709 | }; |
710 | ||
ce722d26 TG |
711 | /* timer4 */ |
712 | static struct omap_hwmod omap3xxx_timer4_hwmod; | |
046465b7 | 713 | |
ce722d26 TG |
714 | static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { |
715 | { | |
716 | .pa_start = 0x49036000, | |
717 | .pa_end = 0x49036000 + SZ_1K - 1, | |
718 | .flags = ADDR_TYPE_RT | |
719 | }, | |
78183f3f | 720 | { } |
046465b7 KH |
721 | }; |
722 | ||
ce722d26 TG |
723 | /* l4_per -> timer4 */ |
724 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { | |
725 | .master = &omap3xxx_l4_per_hwmod, | |
726 | .slave = &omap3xxx_timer4_hwmod, | |
727 | .clk = "gpt4_ick", | |
728 | .addr = omap3xxx_timer4_addrs, | |
ce722d26 | 729 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
046465b7 KH |
730 | }; |
731 | ||
ce722d26 TG |
732 | /* timer4 slave port */ |
733 | static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = { | |
734 | &omap3xxx_l4_per__timer4, | |
046465b7 KH |
735 | }; |
736 | ||
ce722d26 TG |
737 | /* timer4 hwmod */ |
738 | static struct omap_hwmod omap3xxx_timer4_hwmod = { | |
739 | .name = "timer4", | |
0d619a89 | 740 | .mpu_irqs = omap2_timer4_mpu_irqs, |
ce722d26 | 741 | .main_clk = "gpt4_fck", |
046465b7 KH |
742 | .prcm = { |
743 | .omap2 = { | |
046465b7 | 744 | .prcm_reg_id = 1, |
ce722d26 TG |
745 | .module_bit = OMAP3430_EN_GPT4_SHIFT, |
746 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 747 | .idlest_reg_id = 1, |
ce722d26 | 748 | .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, |
046465b7 KH |
749 | }, |
750 | }, | |
ce722d26 TG |
751 | .slaves = omap3xxx_timer4_slaves, |
752 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves), | |
753 | .class = &omap3xxx_timer_hwmod_class, | |
754 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
046465b7 KH |
755 | }; |
756 | ||
ce722d26 TG |
757 | /* timer5 */ |
758 | static struct omap_hwmod omap3xxx_timer5_hwmod; | |
046465b7 | 759 | |
ce722d26 TG |
760 | static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { |
761 | { | |
762 | .pa_start = 0x49038000, | |
763 | .pa_end = 0x49038000 + SZ_1K - 1, | |
764 | .flags = ADDR_TYPE_RT | |
765 | }, | |
78183f3f | 766 | { } |
046465b7 KH |
767 | }; |
768 | ||
ce722d26 TG |
769 | /* l4_per -> timer5 */ |
770 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { | |
771 | .master = &omap3xxx_l4_per_hwmod, | |
772 | .slave = &omap3xxx_timer5_hwmod, | |
773 | .clk = "gpt5_ick", | |
774 | .addr = omap3xxx_timer5_addrs, | |
ce722d26 | 775 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
046465b7 KH |
776 | }; |
777 | ||
ce722d26 TG |
778 | /* timer5 slave port */ |
779 | static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = { | |
780 | &omap3xxx_l4_per__timer5, | |
046465b7 KH |
781 | }; |
782 | ||
ce722d26 TG |
783 | /* timer5 hwmod */ |
784 | static struct omap_hwmod omap3xxx_timer5_hwmod = { | |
785 | .name = "timer5", | |
0d619a89 | 786 | .mpu_irqs = omap2_timer5_mpu_irqs, |
ce722d26 | 787 | .main_clk = "gpt5_fck", |
046465b7 KH |
788 | .prcm = { |
789 | .omap2 = { | |
046465b7 | 790 | .prcm_reg_id = 1, |
ce722d26 TG |
791 | .module_bit = OMAP3430_EN_GPT5_SHIFT, |
792 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 793 | .idlest_reg_id = 1, |
ce722d26 | 794 | .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, |
046465b7 KH |
795 | }, |
796 | }, | |
ce722d26 TG |
797 | .slaves = omap3xxx_timer5_slaves, |
798 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves), | |
799 | .class = &omap3xxx_timer_hwmod_class, | |
800 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
4fe20e97 RN |
801 | }; |
802 | ||
ce722d26 TG |
803 | /* timer6 */ |
804 | static struct omap_hwmod omap3xxx_timer6_hwmod; | |
4fe20e97 | 805 | |
ce722d26 TG |
806 | static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { |
807 | { | |
808 | .pa_start = 0x4903A000, | |
809 | .pa_end = 0x4903A000 + SZ_1K - 1, | |
810 | .flags = ADDR_TYPE_RT | |
811 | }, | |
78183f3f | 812 | { } |
4fe20e97 RN |
813 | }; |
814 | ||
ce722d26 TG |
815 | /* l4_per -> timer6 */ |
816 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { | |
817 | .master = &omap3xxx_l4_per_hwmod, | |
818 | .slave = &omap3xxx_timer6_hwmod, | |
819 | .clk = "gpt6_ick", | |
820 | .addr = omap3xxx_timer6_addrs, | |
ce722d26 | 821 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4fe20e97 RN |
822 | }; |
823 | ||
ce722d26 TG |
824 | /* timer6 slave port */ |
825 | static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = { | |
826 | &omap3xxx_l4_per__timer6, | |
4fe20e97 RN |
827 | }; |
828 | ||
ce722d26 TG |
829 | /* timer6 hwmod */ |
830 | static struct omap_hwmod omap3xxx_timer6_hwmod = { | |
831 | .name = "timer6", | |
0d619a89 | 832 | .mpu_irqs = omap2_timer6_mpu_irqs, |
ce722d26 | 833 | .main_clk = "gpt6_fck", |
4fe20e97 RN |
834 | .prcm = { |
835 | .omap2 = { | |
4fe20e97 | 836 | .prcm_reg_id = 1, |
ce722d26 TG |
837 | .module_bit = OMAP3430_EN_GPT6_SHIFT, |
838 | .module_offs = OMAP3430_PER_MOD, | |
4fe20e97 | 839 | .idlest_reg_id = 1, |
ce722d26 | 840 | .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, |
4fe20e97 RN |
841 | }, |
842 | }, | |
ce722d26 TG |
843 | .slaves = omap3xxx_timer6_slaves, |
844 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves), | |
845 | .class = &omap3xxx_timer_hwmod_class, | |
846 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
4fe20e97 RN |
847 | }; |
848 | ||
ce722d26 TG |
849 | /* timer7 */ |
850 | static struct omap_hwmod omap3xxx_timer7_hwmod; | |
4fe20e97 | 851 | |
ce722d26 TG |
852 | static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { |
853 | { | |
854 | .pa_start = 0x4903C000, | |
855 | .pa_end = 0x4903C000 + SZ_1K - 1, | |
856 | .flags = ADDR_TYPE_RT | |
857 | }, | |
78183f3f | 858 | { } |
4fe20e97 RN |
859 | }; |
860 | ||
ce722d26 TG |
861 | /* l4_per -> timer7 */ |
862 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { | |
863 | .master = &omap3xxx_l4_per_hwmod, | |
864 | .slave = &omap3xxx_timer7_hwmod, | |
865 | .clk = "gpt7_ick", | |
866 | .addr = omap3xxx_timer7_addrs, | |
ce722d26 | 867 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4fe20e97 RN |
868 | }; |
869 | ||
ce722d26 TG |
870 | /* timer7 slave port */ |
871 | static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = { | |
872 | &omap3xxx_l4_per__timer7, | |
4fe20e97 RN |
873 | }; |
874 | ||
ce722d26 TG |
875 | /* timer7 hwmod */ |
876 | static struct omap_hwmod omap3xxx_timer7_hwmod = { | |
877 | .name = "timer7", | |
0d619a89 | 878 | .mpu_irqs = omap2_timer7_mpu_irqs, |
ce722d26 | 879 | .main_clk = "gpt7_fck", |
4fe20e97 RN |
880 | .prcm = { |
881 | .omap2 = { | |
4fe20e97 | 882 | .prcm_reg_id = 1, |
ce722d26 TG |
883 | .module_bit = OMAP3430_EN_GPT7_SHIFT, |
884 | .module_offs = OMAP3430_PER_MOD, | |
4fe20e97 | 885 | .idlest_reg_id = 1, |
ce722d26 | 886 | .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, |
4fe20e97 RN |
887 | }, |
888 | }, | |
ce722d26 TG |
889 | .slaves = omap3xxx_timer7_slaves, |
890 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves), | |
891 | .class = &omap3xxx_timer_hwmod_class, | |
892 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
4fe20e97 RN |
893 | }; |
894 | ||
ce722d26 TG |
895 | /* timer8 */ |
896 | static struct omap_hwmod omap3xxx_timer8_hwmod; | |
4fe20e97 | 897 | |
ce722d26 TG |
898 | static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { |
899 | { | |
900 | .pa_start = 0x4903E000, | |
901 | .pa_end = 0x4903E000 + SZ_1K - 1, | |
902 | .flags = ADDR_TYPE_RT | |
903 | }, | |
78183f3f | 904 | { } |
4fe20e97 RN |
905 | }; |
906 | ||
ce722d26 TG |
907 | /* l4_per -> timer8 */ |
908 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { | |
909 | .master = &omap3xxx_l4_per_hwmod, | |
910 | .slave = &omap3xxx_timer8_hwmod, | |
911 | .clk = "gpt8_ick", | |
912 | .addr = omap3xxx_timer8_addrs, | |
ce722d26 | 913 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
4fe20e97 RN |
914 | }; |
915 | ||
ce722d26 TG |
916 | /* timer8 slave port */ |
917 | static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = { | |
918 | &omap3xxx_l4_per__timer8, | |
4fe20e97 RN |
919 | }; |
920 | ||
ce722d26 TG |
921 | /* timer8 hwmod */ |
922 | static struct omap_hwmod omap3xxx_timer8_hwmod = { | |
923 | .name = "timer8", | |
0d619a89 | 924 | .mpu_irqs = omap2_timer8_mpu_irqs, |
ce722d26 | 925 | .main_clk = "gpt8_fck", |
4fe20e97 RN |
926 | .prcm = { |
927 | .omap2 = { | |
4fe20e97 | 928 | .prcm_reg_id = 1, |
ce722d26 TG |
929 | .module_bit = OMAP3430_EN_GPT8_SHIFT, |
930 | .module_offs = OMAP3430_PER_MOD, | |
4fe20e97 | 931 | .idlest_reg_id = 1, |
ce722d26 | 932 | .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, |
4fe20e97 RN |
933 | }, |
934 | }, | |
ce722d26 TG |
935 | .slaves = omap3xxx_timer8_slaves, |
936 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves), | |
937 | .class = &omap3xxx_timer_hwmod_class, | |
938 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
4fe20e97 RN |
939 | }; |
940 | ||
ce722d26 TG |
941 | /* timer9 */ |
942 | static struct omap_hwmod omap3xxx_timer9_hwmod; | |
ce722d26 TG |
943 | |
944 | static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { | |
70034d38 | 945 | { |
ce722d26 TG |
946 | .pa_start = 0x49040000, |
947 | .pa_end = 0x49040000 + SZ_1K - 1, | |
70034d38 VC |
948 | .flags = ADDR_TYPE_RT |
949 | }, | |
78183f3f | 950 | { } |
70034d38 VC |
951 | }; |
952 | ||
ce722d26 TG |
953 | /* l4_per -> timer9 */ |
954 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { | |
955 | .master = &omap3xxx_l4_per_hwmod, | |
956 | .slave = &omap3xxx_timer9_hwmod, | |
957 | .clk = "gpt9_ick", | |
958 | .addr = omap3xxx_timer9_addrs, | |
70034d38 VC |
959 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
960 | }; | |
961 | ||
ce722d26 TG |
962 | /* timer9 slave port */ |
963 | static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = { | |
964 | &omap3xxx_l4_per__timer9, | |
965 | }; | |
966 | ||
967 | /* timer9 hwmod */ | |
968 | static struct omap_hwmod omap3xxx_timer9_hwmod = { | |
969 | .name = "timer9", | |
0d619a89 | 970 | .mpu_irqs = omap2_timer9_mpu_irqs, |
ce722d26 TG |
971 | .main_clk = "gpt9_fck", |
972 | .prcm = { | |
973 | .omap2 = { | |
974 | .prcm_reg_id = 1, | |
975 | .module_bit = OMAP3430_EN_GPT9_SHIFT, | |
976 | .module_offs = OMAP3430_PER_MOD, | |
977 | .idlest_reg_id = 1, | |
978 | .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, | |
979 | }, | |
70034d38 | 980 | }, |
ce722d26 TG |
981 | .slaves = omap3xxx_timer9_slaves, |
982 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves), | |
983 | .class = &omap3xxx_timer_hwmod_class, | |
984 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
70034d38 VC |
985 | }; |
986 | ||
ce722d26 TG |
987 | /* timer10 */ |
988 | static struct omap_hwmod omap3xxx_timer10_hwmod; | |
70034d38 | 989 | |
ce722d26 TG |
990 | /* l4_core -> timer10 */ |
991 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { | |
992 | .master = &omap3xxx_l4_core_hwmod, | |
993 | .slave = &omap3xxx_timer10_hwmod, | |
994 | .clk = "gpt10_ick", | |
ded11383 | 995 | .addr = omap2_timer10_addrs, |
70034d38 VC |
996 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
997 | }; | |
998 | ||
ce722d26 TG |
999 | /* timer10 slave port */ |
1000 | static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = { | |
1001 | &omap3xxx_l4_core__timer10, | |
1002 | }; | |
1003 | ||
1004 | /* timer10 hwmod */ | |
1005 | static struct omap_hwmod omap3xxx_timer10_hwmod = { | |
1006 | .name = "timer10", | |
0d619a89 | 1007 | .mpu_irqs = omap2_timer10_mpu_irqs, |
ce722d26 TG |
1008 | .main_clk = "gpt10_fck", |
1009 | .prcm = { | |
1010 | .omap2 = { | |
1011 | .prcm_reg_id = 1, | |
1012 | .module_bit = OMAP3430_EN_GPT10_SHIFT, | |
1013 | .module_offs = CORE_MOD, | |
1014 | .idlest_reg_id = 1, | |
1015 | .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, | |
1016 | }, | |
70034d38 | 1017 | }, |
ce722d26 TG |
1018 | .slaves = omap3xxx_timer10_slaves, |
1019 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves), | |
1020 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
1021 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
70034d38 VC |
1022 | }; |
1023 | ||
ce722d26 TG |
1024 | /* timer11 */ |
1025 | static struct omap_hwmod omap3xxx_timer11_hwmod; | |
70034d38 | 1026 | |
ce722d26 TG |
1027 | /* l4_core -> timer11 */ |
1028 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { | |
1029 | .master = &omap3xxx_l4_core_hwmod, | |
1030 | .slave = &omap3xxx_timer11_hwmod, | |
1031 | .clk = "gpt11_ick", | |
ded11383 | 1032 | .addr = omap2_timer11_addrs, |
70034d38 VC |
1033 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1034 | }; | |
1035 | ||
ce722d26 TG |
1036 | /* timer11 slave port */ |
1037 | static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = { | |
1038 | &omap3xxx_l4_core__timer11, | |
1039 | }; | |
1040 | ||
1041 | /* timer11 hwmod */ | |
1042 | static struct omap_hwmod omap3xxx_timer11_hwmod = { | |
1043 | .name = "timer11", | |
0d619a89 | 1044 | .mpu_irqs = omap2_timer11_mpu_irqs, |
ce722d26 TG |
1045 | .main_clk = "gpt11_fck", |
1046 | .prcm = { | |
1047 | .omap2 = { | |
1048 | .prcm_reg_id = 1, | |
1049 | .module_bit = OMAP3430_EN_GPT11_SHIFT, | |
1050 | .module_offs = CORE_MOD, | |
1051 | .idlest_reg_id = 1, | |
1052 | .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, | |
1053 | }, | |
1054 | }, | |
1055 | .slaves = omap3xxx_timer11_slaves, | |
1056 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves), | |
1057 | .class = &omap3xxx_timer_hwmod_class, | |
1058 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
1059 | }; | |
1060 | ||
1061 | /* timer12*/ | |
1062 | static struct omap_hwmod omap3xxx_timer12_hwmod; | |
1063 | static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { | |
1064 | { .irq = 95, }, | |
212738a4 | 1065 | { .irq = -1 } |
ce722d26 TG |
1066 | }; |
1067 | ||
1068 | static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { | |
70034d38 | 1069 | { |
ce722d26 TG |
1070 | .pa_start = 0x48304000, |
1071 | .pa_end = 0x48304000 + SZ_1K - 1, | |
70034d38 VC |
1072 | .flags = ADDR_TYPE_RT |
1073 | }, | |
78183f3f | 1074 | { } |
70034d38 VC |
1075 | }; |
1076 | ||
ce722d26 TG |
1077 | /* l4_core -> timer12 */ |
1078 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = { | |
1079 | .master = &omap3xxx_l4_core_hwmod, | |
1080 | .slave = &omap3xxx_timer12_hwmod, | |
1081 | .clk = "gpt12_ick", | |
1082 | .addr = omap3xxx_timer12_addrs, | |
70034d38 VC |
1083 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1084 | }; | |
1085 | ||
ce722d26 TG |
1086 | /* timer12 slave port */ |
1087 | static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = { | |
1088 | &omap3xxx_l4_core__timer12, | |
1089 | }; | |
70034d38 | 1090 | |
ce722d26 TG |
1091 | /* timer12 hwmod */ |
1092 | static struct omap_hwmod omap3xxx_timer12_hwmod = { | |
1093 | .name = "timer12", | |
1094 | .mpu_irqs = omap3xxx_timer12_mpu_irqs, | |
ce722d26 TG |
1095 | .main_clk = "gpt12_fck", |
1096 | .prcm = { | |
1097 | .omap2 = { | |
1098 | .prcm_reg_id = 1, | |
1099 | .module_bit = OMAP3430_EN_GPT12_SHIFT, | |
1100 | .module_offs = WKUP_MOD, | |
1101 | .idlest_reg_id = 1, | |
1102 | .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, | |
1103 | }, | |
1104 | }, | |
1105 | .slaves = omap3xxx_timer12_slaves, | |
1106 | .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves), | |
1107 | .class = &omap3xxx_timer_hwmod_class, | |
1108 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
70034d38 VC |
1109 | }; |
1110 | ||
6b667f88 VC |
1111 | /* l4_wkup -> wd_timer2 */ |
1112 | static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { | |
1113 | { | |
1114 | .pa_start = 0x48314000, | |
1115 | .pa_end = 0x4831407f, | |
1116 | .flags = ADDR_TYPE_RT | |
1117 | }, | |
78183f3f | 1118 | { } |
70034d38 VC |
1119 | }; |
1120 | ||
6b667f88 VC |
1121 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { |
1122 | .master = &omap3xxx_l4_wkup_hwmod, | |
1123 | .slave = &omap3xxx_wd_timer2_hwmod, | |
1124 | .clk = "wdt2_ick", | |
1125 | .addr = omap3xxx_wd_timer2_addrs, | |
6b667f88 | 1126 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
1127 | }; |
1128 | ||
6b667f88 VC |
1129 | /* |
1130 | * 'wd_timer' class | |
1131 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
1132 | * overflow condition | |
1133 | */ | |
1134 | ||
1135 | static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { | |
1136 | .rev_offs = 0x0000, | |
1137 | .sysc_offs = 0x0010, | |
1138 | .syss_offs = 0x0014, | |
1139 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | | |
1140 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
2d403fe0 | 1141 | SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | |
d73d65fa | 1142 | SYSS_HAS_RESET_STATUS), |
6b667f88 VC |
1143 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
1144 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1145 | }; |
1146 | ||
4fe20e97 RN |
1147 | /* I2C common */ |
1148 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
1149 | .rev_offs = 0x00, | |
1150 | .sysc_offs = 0x20, | |
1151 | .syss_offs = 0x10, | |
1152 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1153 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
2d403fe0 | 1154 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
4fe20e97 RN |
1155 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
1156 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1157 | }; |
1158 | ||
6b667f88 | 1159 | static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { |
ff2516fb PW |
1160 | .name = "wd_timer", |
1161 | .sysc = &omap3xxx_wd_timer_sysc, | |
1162 | .pre_shutdown = &omap2_wd_timer_disable | |
70034d38 VC |
1163 | }; |
1164 | ||
6b667f88 VC |
1165 | /* wd_timer2 */ |
1166 | static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = { | |
1167 | &omap3xxx_l4_wkup__wd_timer2, | |
1168 | }; | |
1169 | ||
1170 | static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { | |
1171 | .name = "wd_timer2", | |
1172 | .class = &omap3xxx_wd_timer_hwmod_class, | |
1173 | .main_clk = "wdt2_fck", | |
70034d38 VC |
1174 | .prcm = { |
1175 | .omap2 = { | |
1176 | .prcm_reg_id = 1, | |
6b667f88 | 1177 | .module_bit = OMAP3430_EN_WDT2_SHIFT, |
70034d38 VC |
1178 | .module_offs = WKUP_MOD, |
1179 | .idlest_reg_id = 1, | |
6b667f88 | 1180 | .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, |
70034d38 VC |
1181 | }, |
1182 | }, | |
6b667f88 VC |
1183 | .slaves = omap3xxx_wd_timer2_slaves, |
1184 | .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves), | |
70034d38 | 1185 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
2f4dd595 PW |
1186 | /* |
1187 | * XXX: Use software supervised mode, HW supervised smartidle seems to | |
1188 | * block CORE power domain idle transitions. Maybe a HW bug in wdt2? | |
1189 | */ | |
1190 | .flags = HWMOD_SWSUP_SIDLE, | |
70034d38 VC |
1191 | }; |
1192 | ||
046465b7 KH |
1193 | /* UART1 */ |
1194 | ||
046465b7 KH |
1195 | static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { |
1196 | &omap3_l4_core__uart1, | |
1197 | }; | |
1198 | ||
1199 | static struct omap_hwmod omap3xxx_uart1_hwmod = { | |
1200 | .name = "uart1", | |
0d619a89 | 1201 | .mpu_irqs = omap2_uart1_mpu_irqs, |
d826ebfa | 1202 | .sdma_reqs = omap2_uart1_sdma_reqs, |
046465b7 | 1203 | .main_clk = "uart1_fck", |
70034d38 VC |
1204 | .prcm = { |
1205 | .omap2 = { | |
046465b7 | 1206 | .module_offs = CORE_MOD, |
70034d38 | 1207 | .prcm_reg_id = 1, |
046465b7 | 1208 | .module_bit = OMAP3430_EN_UART1_SHIFT, |
70034d38 | 1209 | .idlest_reg_id = 1, |
046465b7 | 1210 | .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, |
70034d38 VC |
1211 | }, |
1212 | }, | |
046465b7 KH |
1213 | .slaves = omap3xxx_uart1_slaves, |
1214 | .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), | |
273b9465 | 1215 | .class = &omap2_uart_class, |
70034d38 VC |
1216 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
1217 | }; | |
1218 | ||
046465b7 KH |
1219 | /* UART2 */ |
1220 | ||
046465b7 KH |
1221 | static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = { |
1222 | &omap3_l4_core__uart2, | |
70034d38 VC |
1223 | }; |
1224 | ||
046465b7 KH |
1225 | static struct omap_hwmod omap3xxx_uart2_hwmod = { |
1226 | .name = "uart2", | |
0d619a89 | 1227 | .mpu_irqs = omap2_uart2_mpu_irqs, |
d826ebfa | 1228 | .sdma_reqs = omap2_uart2_sdma_reqs, |
046465b7 | 1229 | .main_clk = "uart2_fck", |
70034d38 VC |
1230 | .prcm = { |
1231 | .omap2 = { | |
046465b7 | 1232 | .module_offs = CORE_MOD, |
70034d38 | 1233 | .prcm_reg_id = 1, |
046465b7 KH |
1234 | .module_bit = OMAP3430_EN_UART2_SHIFT, |
1235 | .idlest_reg_id = 1, | |
1236 | .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, | |
1237 | }, | |
1238 | }, | |
1239 | .slaves = omap3xxx_uart2_slaves, | |
1240 | .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), | |
273b9465 | 1241 | .class = &omap2_uart_class, |
046465b7 KH |
1242 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
1243 | }; | |
1244 | ||
1245 | /* UART3 */ | |
1246 | ||
046465b7 KH |
1247 | static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = { |
1248 | &omap3_l4_per__uart3, | |
1249 | }; | |
1250 | ||
1251 | static struct omap_hwmod omap3xxx_uart3_hwmod = { | |
1252 | .name = "uart3", | |
0d619a89 | 1253 | .mpu_irqs = omap2_uart3_mpu_irqs, |
d826ebfa | 1254 | .sdma_reqs = omap2_uart3_sdma_reqs, |
046465b7 KH |
1255 | .main_clk = "uart3_fck", |
1256 | .prcm = { | |
1257 | .omap2 = { | |
70034d38 | 1258 | .module_offs = OMAP3430_PER_MOD, |
046465b7 KH |
1259 | .prcm_reg_id = 1, |
1260 | .module_bit = OMAP3430_EN_UART3_SHIFT, | |
70034d38 | 1261 | .idlest_reg_id = 1, |
046465b7 | 1262 | .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, |
70034d38 VC |
1263 | }, |
1264 | }, | |
046465b7 KH |
1265 | .slaves = omap3xxx_uart3_slaves, |
1266 | .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), | |
273b9465 | 1267 | .class = &omap2_uart_class, |
70034d38 VC |
1268 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
1269 | }; | |
1270 | ||
046465b7 KH |
1271 | /* UART4 */ |
1272 | ||
1273 | static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { | |
1274 | { .irq = INT_36XX_UART4_IRQ, }, | |
212738a4 | 1275 | { .irq = -1 } |
70034d38 VC |
1276 | }; |
1277 | ||
046465b7 KH |
1278 | static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { |
1279 | { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, | |
1280 | { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, | |
bc614958 | 1281 | { .dma_req = -1 } |
70034d38 VC |
1282 | }; |
1283 | ||
046465b7 KH |
1284 | static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { |
1285 | &omap3_l4_per__uart4, | |
70034d38 VC |
1286 | }; |
1287 | ||
046465b7 KH |
1288 | static struct omap_hwmod omap3xxx_uart4_hwmod = { |
1289 | .name = "uart4", | |
1290 | .mpu_irqs = uart4_mpu_irqs, | |
046465b7 | 1291 | .sdma_reqs = uart4_sdma_reqs, |
046465b7 KH |
1292 | .main_clk = "uart4_fck", |
1293 | .prcm = { | |
1294 | .omap2 = { | |
1295 | .module_offs = OMAP3430_PER_MOD, | |
1296 | .prcm_reg_id = 1, | |
1297 | .module_bit = OMAP3630_EN_UART4_SHIFT, | |
1298 | .idlest_reg_id = 1, | |
1299 | .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, | |
1300 | }, | |
1301 | }, | |
1302 | .slaves = omap3xxx_uart4_slaves, | |
1303 | .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), | |
273b9465 | 1304 | .class = &omap2_uart_class, |
046465b7 KH |
1305 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), |
1306 | }; | |
1307 | ||
4fe20e97 RN |
1308 | static struct omap_hwmod_class i2c_class = { |
1309 | .name = "i2c", | |
1310 | .sysc = &i2c_sysc, | |
1311 | }; | |
1312 | ||
e04d9e1e SG |
1313 | static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { |
1314 | { .name = "dispc", .dma_req = 5 }, | |
1315 | { .name = "dsi1", .dma_req = 74 }, | |
bc614958 | 1316 | { .dma_req = -1 } |
e04d9e1e SG |
1317 | }; |
1318 | ||
1319 | /* dss */ | |
1320 | /* dss master ports */ | |
1321 | static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = { | |
1322 | &omap3xxx_dss__l3, | |
1323 | }; | |
1324 | ||
e04d9e1e SG |
1325 | /* l4_core -> dss */ |
1326 | static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { | |
1327 | .master = &omap3xxx_l4_core_hwmod, | |
1328 | .slave = &omap3430es1_dss_core_hwmod, | |
1329 | .clk = "dss_ick", | |
ded11383 | 1330 | .addr = omap2_dss_addrs, |
e04d9e1e SG |
1331 | .fw = { |
1332 | .omap2 = { | |
1333 | .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, | |
1334 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
1335 | .flags = OMAP_FIREWALL_L4, | |
1336 | } | |
1337 | }, | |
1338 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1339 | }; | |
1340 | ||
1341 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { | |
1342 | .master = &omap3xxx_l4_core_hwmod, | |
1343 | .slave = &omap3xxx_dss_core_hwmod, | |
1344 | .clk = "dss_ick", | |
ded11383 | 1345 | .addr = omap2_dss_addrs, |
e04d9e1e SG |
1346 | .fw = { |
1347 | .omap2 = { | |
1348 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, | |
1349 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
1350 | .flags = OMAP_FIREWALL_L4, | |
1351 | } | |
1352 | }, | |
1353 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1354 | }; | |
1355 | ||
1356 | /* dss slave ports */ | |
1357 | static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = { | |
1358 | &omap3430es1_l4_core__dss, | |
1359 | }; | |
1360 | ||
1361 | static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = { | |
1362 | &omap3xxx_l4_core__dss, | |
1363 | }; | |
1364 | ||
1365 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
1366 | { .role = "tv_clk", .clk = "dss_tv_fck" }, | |
872462cd | 1367 | { .role = "video_clk", .clk = "dss_96m_fck" }, |
e04d9e1e SG |
1368 | { .role = "sys_clk", .clk = "dss2_alwon_fck" }, |
1369 | }; | |
1370 | ||
1371 | static struct omap_hwmod omap3430es1_dss_core_hwmod = { | |
1372 | .name = "dss_core", | |
273b9465 | 1373 | .class = &omap2_dss_hwmod_class, |
e04d9e1e | 1374 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ |
e04d9e1e | 1375 | .sdma_reqs = omap3xxx_dss_sdma_chs, |
e04d9e1e SG |
1376 | .prcm = { |
1377 | .omap2 = { | |
1378 | .prcm_reg_id = 1, | |
1379 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
1380 | .module_offs = OMAP3430_DSS_MOD, | |
1381 | .idlest_reg_id = 1, | |
1382 | .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, | |
1383 | }, | |
1384 | }, | |
1385 | .opt_clks = dss_opt_clks, | |
1386 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
1387 | .slaves = omap3430es1_dss_slaves, | |
1388 | .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves), | |
1389 | .masters = omap3xxx_dss_masters, | |
1390 | .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), | |
1391 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), | |
1392 | .flags = HWMOD_NO_IDLEST, | |
1393 | }; | |
1394 | ||
1395 | static struct omap_hwmod omap3xxx_dss_core_hwmod = { | |
1396 | .name = "dss_core", | |
273b9465 | 1397 | .class = &omap2_dss_hwmod_class, |
e04d9e1e | 1398 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ |
e04d9e1e | 1399 | .sdma_reqs = omap3xxx_dss_sdma_chs, |
e04d9e1e SG |
1400 | .prcm = { |
1401 | .omap2 = { | |
1402 | .prcm_reg_id = 1, | |
1403 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
1404 | .module_offs = OMAP3430_DSS_MOD, | |
1405 | .idlest_reg_id = 1, | |
1406 | .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, | |
1407 | .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, | |
1408 | }, | |
1409 | }, | |
1410 | .opt_clks = dss_opt_clks, | |
1411 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
1412 | .slaves = omap3xxx_dss_slaves, | |
1413 | .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves), | |
1414 | .masters = omap3xxx_dss_masters, | |
1415 | .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), | |
1416 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 | | |
1417 | CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1), | |
1418 | }; | |
1419 | ||
e04d9e1e SG |
1420 | /* l4_core -> dss_dispc */ |
1421 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { | |
1422 | .master = &omap3xxx_l4_core_hwmod, | |
1423 | .slave = &omap3xxx_dss_dispc_hwmod, | |
1424 | .clk = "dss_ick", | |
ded11383 | 1425 | .addr = omap2_dss_dispc_addrs, |
e04d9e1e SG |
1426 | .fw = { |
1427 | .omap2 = { | |
1428 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, | |
1429 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
1430 | .flags = OMAP_FIREWALL_L4, | |
1431 | } | |
1432 | }, | |
1433 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1434 | }; | |
1435 | ||
1436 | /* dss_dispc slave ports */ | |
1437 | static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = { | |
1438 | &omap3xxx_l4_core__dss_dispc, | |
1439 | }; | |
1440 | ||
1441 | static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { | |
1442 | .name = "dss_dispc", | |
273b9465 | 1443 | .class = &omap2_dispc_hwmod_class, |
0d619a89 | 1444 | .mpu_irqs = omap2_dispc_irqs, |
e04d9e1e SG |
1445 | .main_clk = "dss1_alwon_fck", |
1446 | .prcm = { | |
1447 | .omap2 = { | |
1448 | .prcm_reg_id = 1, | |
1449 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
1450 | .module_offs = OMAP3430_DSS_MOD, | |
1451 | }, | |
1452 | }, | |
1453 | .slaves = omap3xxx_dss_dispc_slaves, | |
1454 | .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves), | |
1455 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | | |
1456 | CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | | |
1457 | CHIP_GE_OMAP3630ES1_1), | |
1458 | .flags = HWMOD_NO_IDLEST, | |
1459 | }; | |
1460 | ||
1461 | /* | |
1462 | * 'dsi' class | |
1463 | * display serial interface controller | |
1464 | */ | |
1465 | ||
1466 | static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { | |
1467 | .name = "dsi", | |
1468 | }; | |
1469 | ||
affe360d | 1470 | static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { |
1471 | { .irq = 25 }, | |
212738a4 | 1472 | { .irq = -1 } |
affe360d | 1473 | }; |
1474 | ||
e04d9e1e SG |
1475 | /* dss_dsi1 */ |
1476 | static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { | |
1477 | { | |
1478 | .pa_start = 0x4804FC00, | |
1479 | .pa_end = 0x4804FFFF, | |
1480 | .flags = ADDR_TYPE_RT | |
1481 | }, | |
78183f3f | 1482 | { } |
e04d9e1e SG |
1483 | }; |
1484 | ||
1485 | /* l4_core -> dss_dsi1 */ | |
1486 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { | |
1487 | .master = &omap3xxx_l4_core_hwmod, | |
1488 | .slave = &omap3xxx_dss_dsi1_hwmod, | |
1489 | .addr = omap3xxx_dss_dsi1_addrs, | |
e04d9e1e SG |
1490 | .fw = { |
1491 | .omap2 = { | |
1492 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, | |
1493 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
1494 | .flags = OMAP_FIREWALL_L4, | |
1495 | } | |
1496 | }, | |
1497 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1498 | }; | |
1499 | ||
1500 | /* dss_dsi1 slave ports */ | |
1501 | static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = { | |
1502 | &omap3xxx_l4_core__dss_dsi1, | |
1503 | }; | |
1504 | ||
1505 | static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { | |
1506 | .name = "dss_dsi1", | |
1507 | .class = &omap3xxx_dsi_hwmod_class, | |
affe360d | 1508 | .mpu_irqs = omap3xxx_dsi1_irqs, |
e04d9e1e SG |
1509 | .main_clk = "dss1_alwon_fck", |
1510 | .prcm = { | |
1511 | .omap2 = { | |
1512 | .prcm_reg_id = 1, | |
1513 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
1514 | .module_offs = OMAP3430_DSS_MOD, | |
1515 | }, | |
1516 | }, | |
1517 | .slaves = omap3xxx_dss_dsi1_slaves, | |
1518 | .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves), | |
1519 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | | |
1520 | CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | | |
1521 | CHIP_GE_OMAP3630ES1_1), | |
1522 | .flags = HWMOD_NO_IDLEST, | |
1523 | }; | |
1524 | ||
e04d9e1e SG |
1525 | /* l4_core -> dss_rfbi */ |
1526 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { | |
1527 | .master = &omap3xxx_l4_core_hwmod, | |
1528 | .slave = &omap3xxx_dss_rfbi_hwmod, | |
1529 | .clk = "dss_ick", | |
ded11383 | 1530 | .addr = omap2_dss_rfbi_addrs, |
e04d9e1e SG |
1531 | .fw = { |
1532 | .omap2 = { | |
1533 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, | |
1534 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , | |
1535 | .flags = OMAP_FIREWALL_L4, | |
1536 | } | |
1537 | }, | |
1538 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1539 | }; | |
1540 | ||
1541 | /* dss_rfbi slave ports */ | |
1542 | static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = { | |
1543 | &omap3xxx_l4_core__dss_rfbi, | |
1544 | }; | |
1545 | ||
1546 | static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { | |
1547 | .name = "dss_rfbi", | |
273b9465 | 1548 | .class = &omap2_rfbi_hwmod_class, |
e04d9e1e SG |
1549 | .main_clk = "dss1_alwon_fck", |
1550 | .prcm = { | |
1551 | .omap2 = { | |
1552 | .prcm_reg_id = 1, | |
1553 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
1554 | .module_offs = OMAP3430_DSS_MOD, | |
1555 | }, | |
1556 | }, | |
1557 | .slaves = omap3xxx_dss_rfbi_slaves, | |
1558 | .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves), | |
1559 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | | |
1560 | CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | | |
1561 | CHIP_GE_OMAP3630ES1_1), | |
1562 | .flags = HWMOD_NO_IDLEST, | |
1563 | }; | |
1564 | ||
e04d9e1e SG |
1565 | /* l4_core -> dss_venc */ |
1566 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { | |
1567 | .master = &omap3xxx_l4_core_hwmod, | |
1568 | .slave = &omap3xxx_dss_venc_hwmod, | |
1569 | .clk = "dss_tv_fck", | |
ded11383 | 1570 | .addr = omap2_dss_venc_addrs, |
e04d9e1e SG |
1571 | .fw = { |
1572 | .omap2 = { | |
1573 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, | |
1574 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
1575 | .flags = OMAP_FIREWALL_L4, | |
1576 | } | |
1577 | }, | |
c39bee8a | 1578 | .flags = OCPIF_SWSUP_IDLE, |
e04d9e1e SG |
1579 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1580 | }; | |
1581 | ||
1582 | /* dss_venc slave ports */ | |
1583 | static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = { | |
1584 | &omap3xxx_l4_core__dss_venc, | |
1585 | }; | |
1586 | ||
1587 | static struct omap_hwmod omap3xxx_dss_venc_hwmod = { | |
1588 | .name = "dss_venc", | |
273b9465 | 1589 | .class = &omap2_venc_hwmod_class, |
e04d9e1e SG |
1590 | .main_clk = "dss1_alwon_fck", |
1591 | .prcm = { | |
1592 | .omap2 = { | |
1593 | .prcm_reg_id = 1, | |
1594 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
1595 | .module_offs = OMAP3430_DSS_MOD, | |
1596 | }, | |
1597 | }, | |
1598 | .slaves = omap3xxx_dss_venc_slaves, | |
1599 | .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves), | |
1600 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | | |
1601 | CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | | |
1602 | CHIP_GE_OMAP3630ES1_1), | |
1603 | .flags = HWMOD_NO_IDLEST, | |
1604 | }; | |
1605 | ||
4fe20e97 RN |
1606 | /* I2C1 */ |
1607 | ||
1608 | static struct omap_i2c_dev_attr i2c1_dev_attr = { | |
1609 | .fifo_depth = 8, /* bytes */ | |
1610 | }; | |
1611 | ||
4fe20e97 RN |
1612 | static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = { |
1613 | &omap3_l4_core__i2c1, | |
1614 | }; | |
1615 | ||
1616 | static struct omap_hwmod omap3xxx_i2c1_hwmod = { | |
1617 | .name = "i2c1", | |
0d619a89 | 1618 | .mpu_irqs = omap2_i2c1_mpu_irqs, |
d826ebfa | 1619 | .sdma_reqs = omap2_i2c1_sdma_reqs, |
4fe20e97 RN |
1620 | .main_clk = "i2c1_fck", |
1621 | .prcm = { | |
1622 | .omap2 = { | |
1623 | .module_offs = CORE_MOD, | |
1624 | .prcm_reg_id = 1, | |
1625 | .module_bit = OMAP3430_EN_I2C1_SHIFT, | |
1626 | .idlest_reg_id = 1, | |
1627 | .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, | |
1628 | }, | |
1629 | }, | |
1630 | .slaves = omap3xxx_i2c1_slaves, | |
1631 | .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves), | |
1632 | .class = &i2c_class, | |
1633 | .dev_attr = &i2c1_dev_attr, | |
1634 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1635 | }; | |
1636 | ||
1637 | /* I2C2 */ | |
1638 | ||
1639 | static struct omap_i2c_dev_attr i2c2_dev_attr = { | |
1640 | .fifo_depth = 8, /* bytes */ | |
1641 | }; | |
1642 | ||
4fe20e97 RN |
1643 | static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = { |
1644 | &omap3_l4_core__i2c2, | |
1645 | }; | |
1646 | ||
1647 | static struct omap_hwmod omap3xxx_i2c2_hwmod = { | |
1648 | .name = "i2c2", | |
0d619a89 | 1649 | .mpu_irqs = omap2_i2c2_mpu_irqs, |
d826ebfa | 1650 | .sdma_reqs = omap2_i2c2_sdma_reqs, |
4fe20e97 RN |
1651 | .main_clk = "i2c2_fck", |
1652 | .prcm = { | |
1653 | .omap2 = { | |
1654 | .module_offs = CORE_MOD, | |
1655 | .prcm_reg_id = 1, | |
1656 | .module_bit = OMAP3430_EN_I2C2_SHIFT, | |
1657 | .idlest_reg_id = 1, | |
1658 | .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, | |
1659 | }, | |
1660 | }, | |
1661 | .slaves = omap3xxx_i2c2_slaves, | |
1662 | .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves), | |
1663 | .class = &i2c_class, | |
1664 | .dev_attr = &i2c2_dev_attr, | |
1665 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1666 | }; | |
1667 | ||
1668 | /* I2C3 */ | |
1669 | ||
1670 | static struct omap_i2c_dev_attr i2c3_dev_attr = { | |
1671 | .fifo_depth = 64, /* bytes */ | |
1672 | }; | |
1673 | ||
1674 | static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { | |
1675 | { .irq = INT_34XX_I2C3_IRQ, }, | |
212738a4 | 1676 | { .irq = -1 } |
4fe20e97 RN |
1677 | }; |
1678 | ||
1679 | static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { | |
1680 | { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, | |
1681 | { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, | |
bc614958 | 1682 | { .dma_req = -1 } |
4fe20e97 RN |
1683 | }; |
1684 | ||
1685 | static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = { | |
1686 | &omap3_l4_core__i2c3, | |
1687 | }; | |
1688 | ||
1689 | static struct omap_hwmod omap3xxx_i2c3_hwmod = { | |
1690 | .name = "i2c3", | |
1691 | .mpu_irqs = i2c3_mpu_irqs, | |
4fe20e97 | 1692 | .sdma_reqs = i2c3_sdma_reqs, |
4fe20e97 RN |
1693 | .main_clk = "i2c3_fck", |
1694 | .prcm = { | |
1695 | .omap2 = { | |
1696 | .module_offs = CORE_MOD, | |
1697 | .prcm_reg_id = 1, | |
1698 | .module_bit = OMAP3430_EN_I2C3_SHIFT, | |
1699 | .idlest_reg_id = 1, | |
1700 | .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, | |
1701 | }, | |
1702 | }, | |
1703 | .slaves = omap3xxx_i2c3_slaves, | |
1704 | .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves), | |
1705 | .class = &i2c_class, | |
1706 | .dev_attr = &i2c3_dev_attr, | |
1707 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1708 | }; | |
1709 | ||
70034d38 VC |
1710 | /* l4_wkup -> gpio1 */ |
1711 | static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { | |
1712 | { | |
1713 | .pa_start = 0x48310000, | |
1714 | .pa_end = 0x483101ff, | |
1715 | .flags = ADDR_TYPE_RT | |
1716 | }, | |
78183f3f | 1717 | { } |
70034d38 VC |
1718 | }; |
1719 | ||
1720 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { | |
1721 | .master = &omap3xxx_l4_wkup_hwmod, | |
1722 | .slave = &omap3xxx_gpio1_hwmod, | |
1723 | .addr = omap3xxx_gpio1_addrs, | |
70034d38 VC |
1724 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1725 | }; | |
1726 | ||
1727 | /* l4_per -> gpio2 */ | |
1728 | static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { | |
1729 | { | |
1730 | .pa_start = 0x49050000, | |
1731 | .pa_end = 0x490501ff, | |
1732 | .flags = ADDR_TYPE_RT | |
1733 | }, | |
78183f3f | 1734 | { } |
70034d38 VC |
1735 | }; |
1736 | ||
1737 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { | |
1738 | .master = &omap3xxx_l4_per_hwmod, | |
1739 | .slave = &omap3xxx_gpio2_hwmod, | |
1740 | .addr = omap3xxx_gpio2_addrs, | |
70034d38 VC |
1741 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1742 | }; | |
1743 | ||
1744 | /* l4_per -> gpio3 */ | |
1745 | static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { | |
1746 | { | |
1747 | .pa_start = 0x49052000, | |
1748 | .pa_end = 0x490521ff, | |
1749 | .flags = ADDR_TYPE_RT | |
1750 | }, | |
78183f3f | 1751 | { } |
70034d38 VC |
1752 | }; |
1753 | ||
1754 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { | |
1755 | .master = &omap3xxx_l4_per_hwmod, | |
1756 | .slave = &omap3xxx_gpio3_hwmod, | |
1757 | .addr = omap3xxx_gpio3_addrs, | |
70034d38 VC |
1758 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1759 | }; | |
1760 | ||
1761 | /* l4_per -> gpio4 */ | |
1762 | static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { | |
1763 | { | |
1764 | .pa_start = 0x49054000, | |
1765 | .pa_end = 0x490541ff, | |
1766 | .flags = ADDR_TYPE_RT | |
1767 | }, | |
78183f3f | 1768 | { } |
70034d38 VC |
1769 | }; |
1770 | ||
1771 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { | |
1772 | .master = &omap3xxx_l4_per_hwmod, | |
1773 | .slave = &omap3xxx_gpio4_hwmod, | |
1774 | .addr = omap3xxx_gpio4_addrs, | |
70034d38 VC |
1775 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1776 | }; | |
1777 | ||
1778 | /* l4_per -> gpio5 */ | |
1779 | static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { | |
1780 | { | |
1781 | .pa_start = 0x49056000, | |
1782 | .pa_end = 0x490561ff, | |
1783 | .flags = ADDR_TYPE_RT | |
1784 | }, | |
78183f3f | 1785 | { } |
70034d38 VC |
1786 | }; |
1787 | ||
1788 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { | |
1789 | .master = &omap3xxx_l4_per_hwmod, | |
1790 | .slave = &omap3xxx_gpio5_hwmod, | |
1791 | .addr = omap3xxx_gpio5_addrs, | |
70034d38 VC |
1792 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1793 | }; | |
1794 | ||
1795 | /* l4_per -> gpio6 */ | |
1796 | static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { | |
1797 | { | |
1798 | .pa_start = 0x49058000, | |
1799 | .pa_end = 0x490581ff, | |
1800 | .flags = ADDR_TYPE_RT | |
1801 | }, | |
78183f3f | 1802 | { } |
70034d38 VC |
1803 | }; |
1804 | ||
1805 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { | |
1806 | .master = &omap3xxx_l4_per_hwmod, | |
1807 | .slave = &omap3xxx_gpio6_hwmod, | |
1808 | .addr = omap3xxx_gpio6_addrs, | |
70034d38 VC |
1809 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1810 | }; | |
1811 | ||
1812 | /* | |
1813 | * 'gpio' class | |
1814 | * general purpose io module | |
1815 | */ | |
1816 | ||
1817 | static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { | |
1818 | .rev_offs = 0x0000, | |
1819 | .sysc_offs = 0x0010, | |
1820 | .syss_offs = 0x0014, | |
1821 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
2d403fe0 PW |
1822 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
1823 | SYSS_HAS_RESET_STATUS), | |
70034d38 VC |
1824 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
1825 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1826 | }; | |
1827 | ||
1828 | static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { | |
1829 | .name = "gpio", | |
1830 | .sysc = &omap3xxx_gpio_sysc, | |
1831 | .rev = 1, | |
1832 | }; | |
1833 | ||
1834 | /* gpio_dev_attr*/ | |
1835 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
1836 | .bank_width = 32, | |
1837 | .dbck_flag = true, | |
1838 | }; | |
1839 | ||
1840 | /* gpio1 */ | |
70034d38 VC |
1841 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
1842 | { .role = "dbclk", .clk = "gpio1_dbck", }, | |
1843 | }; | |
1844 | ||
1845 | static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = { | |
1846 | &omap3xxx_l4_wkup__gpio1, | |
1847 | }; | |
1848 | ||
1849 | static struct omap_hwmod omap3xxx_gpio1_hwmod = { | |
1850 | .name = "gpio1", | |
f95440ca | 1851 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 1852 | .mpu_irqs = omap2_gpio1_irqs, |
70034d38 VC |
1853 | .main_clk = "gpio1_ick", |
1854 | .opt_clks = gpio1_opt_clks, | |
1855 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
1856 | .prcm = { | |
1857 | .omap2 = { | |
1858 | .prcm_reg_id = 1, | |
1859 | .module_bit = OMAP3430_EN_GPIO1_SHIFT, | |
1860 | .module_offs = WKUP_MOD, | |
1861 | .idlest_reg_id = 1, | |
1862 | .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, | |
1863 | }, | |
1864 | }, | |
1865 | .slaves = omap3xxx_gpio1_slaves, | |
1866 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves), | |
1867 | .class = &omap3xxx_gpio_hwmod_class, | |
1868 | .dev_attr = &gpio_dev_attr, | |
1869 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1870 | }; | |
1871 | ||
1872 | /* gpio2 */ | |
70034d38 VC |
1873 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
1874 | { .role = "dbclk", .clk = "gpio2_dbck", }, | |
1875 | }; | |
1876 | ||
1877 | static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = { | |
1878 | &omap3xxx_l4_per__gpio2, | |
1879 | }; | |
1880 | ||
1881 | static struct omap_hwmod omap3xxx_gpio2_hwmod = { | |
1882 | .name = "gpio2", | |
f95440ca | 1883 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 1884 | .mpu_irqs = omap2_gpio2_irqs, |
70034d38 VC |
1885 | .main_clk = "gpio2_ick", |
1886 | .opt_clks = gpio2_opt_clks, | |
1887 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
1888 | .prcm = { | |
1889 | .omap2 = { | |
1890 | .prcm_reg_id = 1, | |
1891 | .module_bit = OMAP3430_EN_GPIO2_SHIFT, | |
1892 | .module_offs = OMAP3430_PER_MOD, | |
1893 | .idlest_reg_id = 1, | |
1894 | .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, | |
1895 | }, | |
1896 | }, | |
1897 | .slaves = omap3xxx_gpio2_slaves, | |
1898 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves), | |
1899 | .class = &omap3xxx_gpio_hwmod_class, | |
1900 | .dev_attr = &gpio_dev_attr, | |
1901 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1902 | }; | |
1903 | ||
1904 | /* gpio3 */ | |
70034d38 VC |
1905 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
1906 | { .role = "dbclk", .clk = "gpio3_dbck", }, | |
1907 | }; | |
1908 | ||
1909 | static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = { | |
1910 | &omap3xxx_l4_per__gpio3, | |
1911 | }; | |
1912 | ||
1913 | static struct omap_hwmod omap3xxx_gpio3_hwmod = { | |
1914 | .name = "gpio3", | |
f95440ca | 1915 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 1916 | .mpu_irqs = omap2_gpio3_irqs, |
70034d38 VC |
1917 | .main_clk = "gpio3_ick", |
1918 | .opt_clks = gpio3_opt_clks, | |
1919 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
1920 | .prcm = { | |
1921 | .omap2 = { | |
1922 | .prcm_reg_id = 1, | |
1923 | .module_bit = OMAP3430_EN_GPIO3_SHIFT, | |
1924 | .module_offs = OMAP3430_PER_MOD, | |
1925 | .idlest_reg_id = 1, | |
1926 | .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, | |
1927 | }, | |
1928 | }, | |
1929 | .slaves = omap3xxx_gpio3_slaves, | |
1930 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves), | |
1931 | .class = &omap3xxx_gpio_hwmod_class, | |
1932 | .dev_attr = &gpio_dev_attr, | |
1933 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1934 | }; | |
1935 | ||
1936 | /* gpio4 */ | |
70034d38 VC |
1937 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
1938 | { .role = "dbclk", .clk = "gpio4_dbck", }, | |
1939 | }; | |
1940 | ||
1941 | static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = { | |
1942 | &omap3xxx_l4_per__gpio4, | |
1943 | }; | |
1944 | ||
1945 | static struct omap_hwmod omap3xxx_gpio4_hwmod = { | |
1946 | .name = "gpio4", | |
f95440ca | 1947 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 1948 | .mpu_irqs = omap2_gpio4_irqs, |
70034d38 VC |
1949 | .main_clk = "gpio4_ick", |
1950 | .opt_clks = gpio4_opt_clks, | |
1951 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
1952 | .prcm = { | |
1953 | .omap2 = { | |
1954 | .prcm_reg_id = 1, | |
1955 | .module_bit = OMAP3430_EN_GPIO4_SHIFT, | |
1956 | .module_offs = OMAP3430_PER_MOD, | |
1957 | .idlest_reg_id = 1, | |
1958 | .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, | |
1959 | }, | |
1960 | }, | |
1961 | .slaves = omap3xxx_gpio4_slaves, | |
1962 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves), | |
1963 | .class = &omap3xxx_gpio_hwmod_class, | |
1964 | .dev_attr = &gpio_dev_attr, | |
1965 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1966 | }; | |
1967 | ||
1968 | /* gpio5 */ | |
1969 | static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { | |
1970 | { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ | |
212738a4 | 1971 | { .irq = -1 } |
70034d38 VC |
1972 | }; |
1973 | ||
1974 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { | |
1975 | { .role = "dbclk", .clk = "gpio5_dbck", }, | |
1976 | }; | |
1977 | ||
1978 | static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = { | |
1979 | &omap3xxx_l4_per__gpio5, | |
1980 | }; | |
1981 | ||
1982 | static struct omap_hwmod omap3xxx_gpio5_hwmod = { | |
1983 | .name = "gpio5", | |
f95440ca | 1984 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
70034d38 | 1985 | .mpu_irqs = omap3xxx_gpio5_irqs, |
70034d38 VC |
1986 | .main_clk = "gpio5_ick", |
1987 | .opt_clks = gpio5_opt_clks, | |
1988 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
1989 | .prcm = { | |
1990 | .omap2 = { | |
1991 | .prcm_reg_id = 1, | |
1992 | .module_bit = OMAP3430_EN_GPIO5_SHIFT, | |
1993 | .module_offs = OMAP3430_PER_MOD, | |
1994 | .idlest_reg_id = 1, | |
1995 | .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, | |
1996 | }, | |
1997 | }, | |
1998 | .slaves = omap3xxx_gpio5_slaves, | |
1999 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves), | |
2000 | .class = &omap3xxx_gpio_hwmod_class, | |
2001 | .dev_attr = &gpio_dev_attr, | |
2002 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
2003 | }; | |
2004 | ||
2005 | /* gpio6 */ | |
2006 | static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { | |
2007 | { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ | |
212738a4 | 2008 | { .irq = -1 } |
70034d38 VC |
2009 | }; |
2010 | ||
2011 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { | |
2012 | { .role = "dbclk", .clk = "gpio6_dbck", }, | |
2013 | }; | |
2014 | ||
2015 | static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = { | |
2016 | &omap3xxx_l4_per__gpio6, | |
2017 | }; | |
2018 | ||
2019 | static struct omap_hwmod omap3xxx_gpio6_hwmod = { | |
2020 | .name = "gpio6", | |
f95440ca | 2021 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
70034d38 | 2022 | .mpu_irqs = omap3xxx_gpio6_irqs, |
70034d38 VC |
2023 | .main_clk = "gpio6_ick", |
2024 | .opt_clks = gpio6_opt_clks, | |
2025 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
2026 | .prcm = { | |
2027 | .omap2 = { | |
2028 | .prcm_reg_id = 1, | |
2029 | .module_bit = OMAP3430_EN_GPIO6_SHIFT, | |
2030 | .module_offs = OMAP3430_PER_MOD, | |
2031 | .idlest_reg_id = 1, | |
2032 | .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, | |
2033 | }, | |
2034 | }, | |
2035 | .slaves = omap3xxx_gpio6_slaves, | |
2036 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves), | |
2037 | .class = &omap3xxx_gpio_hwmod_class, | |
2038 | .dev_attr = &gpio_dev_attr, | |
2039 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
2040 | }; | |
2041 | ||
01438ab6 MK |
2042 | /* dma_system -> L3 */ |
2043 | static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { | |
2044 | .master = &omap3xxx_dma_system_hwmod, | |
2045 | .slave = &omap3xxx_l3_main_hwmod, | |
2046 | .clk = "core_l3_ick", | |
2047 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2048 | }; | |
2049 | ||
2050 | /* dma attributes */ | |
2051 | static struct omap_dma_dev_attr dma_dev_attr = { | |
2052 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
2053 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
2054 | .lch_count = 32, | |
2055 | }; | |
2056 | ||
2057 | static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { | |
2058 | .rev_offs = 0x0000, | |
2059 | .sysc_offs = 0x002c, | |
2060 | .syss_offs = 0x0028, | |
2061 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
2062 | SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
2d403fe0 PW |
2063 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | |
2064 | SYSS_HAS_RESET_STATUS), | |
01438ab6 MK |
2065 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
2066 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
2067 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2068 | }; | |
2069 | ||
2070 | static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { | |
2071 | .name = "dma", | |
2072 | .sysc = &omap3xxx_dma_sysc, | |
2073 | }; | |
2074 | ||
2075 | /* dma_system */ | |
01438ab6 MK |
2076 | static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { |
2077 | { | |
2078 | .pa_start = 0x48056000, | |
1286eeb2 | 2079 | .pa_end = 0x48056fff, |
01438ab6 MK |
2080 | .flags = ADDR_TYPE_RT |
2081 | }, | |
78183f3f | 2082 | { } |
01438ab6 MK |
2083 | }; |
2084 | ||
2085 | /* dma_system master ports */ | |
2086 | static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = { | |
2087 | &omap3xxx_dma_system__l3, | |
2088 | }; | |
2089 | ||
2090 | /* l4_cfg -> dma_system */ | |
2091 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { | |
2092 | .master = &omap3xxx_l4_core_hwmod, | |
2093 | .slave = &omap3xxx_dma_system_hwmod, | |
2094 | .clk = "core_l4_ick", | |
2095 | .addr = omap3xxx_dma_system_addrs, | |
01438ab6 MK |
2096 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2097 | }; | |
2098 | ||
2099 | /* dma_system slave ports */ | |
2100 | static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = { | |
2101 | &omap3xxx_l4_core__dma_system, | |
2102 | }; | |
2103 | ||
2104 | static struct omap_hwmod omap3xxx_dma_system_hwmod = { | |
2105 | .name = "dma", | |
2106 | .class = &omap3xxx_dma_hwmod_class, | |
0d619a89 | 2107 | .mpu_irqs = omap2_dma_system_irqs, |
01438ab6 MK |
2108 | .main_clk = "core_l3_ick", |
2109 | .prcm = { | |
2110 | .omap2 = { | |
2111 | .module_offs = CORE_MOD, | |
2112 | .prcm_reg_id = 1, | |
2113 | .module_bit = OMAP3430_ST_SDMA_SHIFT, | |
2114 | .idlest_reg_id = 1, | |
2115 | .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, | |
2116 | }, | |
2117 | }, | |
2118 | .slaves = omap3xxx_dma_system_slaves, | |
2119 | .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves), | |
2120 | .masters = omap3xxx_dma_system_masters, | |
2121 | .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters), | |
2122 | .dev_attr = &dma_dev_attr, | |
2123 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
2124 | .flags = HWMOD_NO_IDLEST, | |
2125 | }; | |
2126 | ||
70034d38 | 2127 | /* |
dc48e5fc C |
2128 | * 'mcbsp' class |
2129 | * multi channel buffered serial port controller | |
70034d38 VC |
2130 | */ |
2131 | ||
dc48e5fc C |
2132 | static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { |
2133 | .sysc_offs = 0x008c, | |
2134 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
2135 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
70034d38 | 2136 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
dc48e5fc C |
2137 | .sysc_fields = &omap_hwmod_sysc_type1, |
2138 | .clockact = 0x2, | |
70034d38 VC |
2139 | }; |
2140 | ||
dc48e5fc C |
2141 | static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { |
2142 | .name = "mcbsp", | |
2143 | .sysc = &omap3xxx_mcbsp_sysc, | |
2144 | .rev = MCBSP_CONFIG_TYPE3, | |
70034d38 VC |
2145 | }; |
2146 | ||
dc48e5fc C |
2147 | /* mcbsp1 */ |
2148 | static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { | |
2149 | { .name = "irq", .irq = 16 }, | |
2150 | { .name = "tx", .irq = 59 }, | |
2151 | { .name = "rx", .irq = 60 }, | |
212738a4 | 2152 | { .irq = -1 } |
70034d38 VC |
2153 | }; |
2154 | ||
dc48e5fc C |
2155 | static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { |
2156 | { | |
2157 | .name = "mpu", | |
2158 | .pa_start = 0x48074000, | |
2159 | .pa_end = 0x480740ff, | |
2160 | .flags = ADDR_TYPE_RT | |
2161 | }, | |
78183f3f | 2162 | { } |
70034d38 VC |
2163 | }; |
2164 | ||
dc48e5fc C |
2165 | /* l4_core -> mcbsp1 */ |
2166 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { | |
2167 | .master = &omap3xxx_l4_core_hwmod, | |
2168 | .slave = &omap3xxx_mcbsp1_hwmod, | |
2169 | .clk = "mcbsp1_ick", | |
2170 | .addr = omap3xxx_mcbsp1_addrs, | |
dc48e5fc | 2171 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2172 | }; |
2173 | ||
dc48e5fc C |
2174 | /* mcbsp1 slave ports */ |
2175 | static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = { | |
2176 | &omap3xxx_l4_core__mcbsp1, | |
2177 | }; | |
2178 | ||
2179 | static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { | |
2180 | .name = "mcbsp1", | |
2181 | .class = &omap3xxx_mcbsp_hwmod_class, | |
2182 | .mpu_irqs = omap3xxx_mcbsp1_irqs, | |
d826ebfa | 2183 | .sdma_reqs = omap2_mcbsp1_sdma_reqs, |
dc48e5fc | 2184 | .main_clk = "mcbsp1_fck", |
70034d38 VC |
2185 | .prcm = { |
2186 | .omap2 = { | |
2187 | .prcm_reg_id = 1, | |
dc48e5fc C |
2188 | .module_bit = OMAP3430_EN_MCBSP1_SHIFT, |
2189 | .module_offs = CORE_MOD, | |
70034d38 | 2190 | .idlest_reg_id = 1, |
dc48e5fc | 2191 | .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, |
70034d38 VC |
2192 | }, |
2193 | }, | |
dc48e5fc C |
2194 | .slaves = omap3xxx_mcbsp1_slaves, |
2195 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves), | |
70034d38 VC |
2196 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
2197 | }; | |
2198 | ||
dc48e5fc C |
2199 | /* mcbsp2 */ |
2200 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { | |
2201 | { .name = "irq", .irq = 17 }, | |
2202 | { .name = "tx", .irq = 62 }, | |
2203 | { .name = "rx", .irq = 63 }, | |
212738a4 | 2204 | { .irq = -1 } |
70034d38 VC |
2205 | }; |
2206 | ||
dc48e5fc C |
2207 | static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { |
2208 | { | |
2209 | .name = "mpu", | |
2210 | .pa_start = 0x49022000, | |
2211 | .pa_end = 0x490220ff, | |
2212 | .flags = ADDR_TYPE_RT | |
70034d38 | 2213 | }, |
78183f3f | 2214 | { } |
70034d38 VC |
2215 | }; |
2216 | ||
dc48e5fc C |
2217 | /* l4_per -> mcbsp2 */ |
2218 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { | |
2219 | .master = &omap3xxx_l4_per_hwmod, | |
2220 | .slave = &omap3xxx_mcbsp2_hwmod, | |
2221 | .clk = "mcbsp2_ick", | |
2222 | .addr = omap3xxx_mcbsp2_addrs, | |
dc48e5fc | 2223 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2224 | }; |
2225 | ||
dc48e5fc C |
2226 | /* mcbsp2 slave ports */ |
2227 | static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = { | |
2228 | &omap3xxx_l4_per__mcbsp2, | |
70034d38 VC |
2229 | }; |
2230 | ||
8b1906f1 KVA |
2231 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { |
2232 | .sidetone = "mcbsp2_sidetone", | |
70034d38 VC |
2233 | }; |
2234 | ||
dc48e5fc C |
2235 | static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { |
2236 | .name = "mcbsp2", | |
2237 | .class = &omap3xxx_mcbsp_hwmod_class, | |
2238 | .mpu_irqs = omap3xxx_mcbsp2_irqs, | |
d826ebfa | 2239 | .sdma_reqs = omap2_mcbsp2_sdma_reqs, |
dc48e5fc | 2240 | .main_clk = "mcbsp2_fck", |
70034d38 VC |
2241 | .prcm = { |
2242 | .omap2 = { | |
2243 | .prcm_reg_id = 1, | |
dc48e5fc | 2244 | .module_bit = OMAP3430_EN_MCBSP2_SHIFT, |
70034d38 VC |
2245 | .module_offs = OMAP3430_PER_MOD, |
2246 | .idlest_reg_id = 1, | |
dc48e5fc | 2247 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, |
70034d38 VC |
2248 | }, |
2249 | }, | |
dc48e5fc C |
2250 | .slaves = omap3xxx_mcbsp2_slaves, |
2251 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves), | |
8b1906f1 | 2252 | .dev_attr = &omap34xx_mcbsp2_dev_attr, |
70034d38 VC |
2253 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
2254 | }; | |
2255 | ||
dc48e5fc C |
2256 | /* mcbsp3 */ |
2257 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { | |
2258 | { .name = "irq", .irq = 22 }, | |
2259 | { .name = "tx", .irq = 89 }, | |
2260 | { .name = "rx", .irq = 90 }, | |
212738a4 | 2261 | { .irq = -1 } |
70034d38 VC |
2262 | }; |
2263 | ||
dc48e5fc C |
2264 | static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { |
2265 | { | |
2266 | .name = "mpu", | |
2267 | .pa_start = 0x49024000, | |
2268 | .pa_end = 0x490240ff, | |
2269 | .flags = ADDR_TYPE_RT | |
2270 | }, | |
78183f3f | 2271 | { } |
70034d38 VC |
2272 | }; |
2273 | ||
dc48e5fc C |
2274 | /* l4_per -> mcbsp3 */ |
2275 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { | |
2276 | .master = &omap3xxx_l4_per_hwmod, | |
2277 | .slave = &omap3xxx_mcbsp3_hwmod, | |
2278 | .clk = "mcbsp3_ick", | |
2279 | .addr = omap3xxx_mcbsp3_addrs, | |
dc48e5fc C |
2280 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2281 | }; | |
2282 | ||
2283 | /* mcbsp3 slave ports */ | |
2284 | static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = { | |
2285 | &omap3xxx_l4_per__mcbsp3, | |
2286 | }; | |
2287 | ||
8b1906f1 KVA |
2288 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { |
2289 | .sidetone = "mcbsp3_sidetone", | |
2290 | }; | |
2291 | ||
dc48e5fc C |
2292 | static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { |
2293 | .name = "mcbsp3", | |
2294 | .class = &omap3xxx_mcbsp_hwmod_class, | |
2295 | .mpu_irqs = omap3xxx_mcbsp3_irqs, | |
d826ebfa | 2296 | .sdma_reqs = omap2_mcbsp3_sdma_reqs, |
dc48e5fc | 2297 | .main_clk = "mcbsp3_fck", |
70034d38 VC |
2298 | .prcm = { |
2299 | .omap2 = { | |
2300 | .prcm_reg_id = 1, | |
dc48e5fc | 2301 | .module_bit = OMAP3430_EN_MCBSP3_SHIFT, |
70034d38 VC |
2302 | .module_offs = OMAP3430_PER_MOD, |
2303 | .idlest_reg_id = 1, | |
dc48e5fc | 2304 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, |
70034d38 VC |
2305 | }, |
2306 | }, | |
dc48e5fc C |
2307 | .slaves = omap3xxx_mcbsp3_slaves, |
2308 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves), | |
8b1906f1 | 2309 | .dev_attr = &omap34xx_mcbsp3_dev_attr, |
70034d38 VC |
2310 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
2311 | }; | |
2312 | ||
dc48e5fc C |
2313 | /* mcbsp4 */ |
2314 | static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { | |
2315 | { .name = "irq", .irq = 23 }, | |
2316 | { .name = "tx", .irq = 54 }, | |
2317 | { .name = "rx", .irq = 55 }, | |
212738a4 | 2318 | { .irq = -1 } |
70034d38 VC |
2319 | }; |
2320 | ||
dc48e5fc C |
2321 | static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { |
2322 | { .name = "rx", .dma_req = 20 }, | |
2323 | { .name = "tx", .dma_req = 19 }, | |
bc614958 | 2324 | { .dma_req = -1 } |
70034d38 VC |
2325 | }; |
2326 | ||
dc48e5fc C |
2327 | static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { |
2328 | { | |
2329 | .name = "mpu", | |
2330 | .pa_start = 0x49026000, | |
2331 | .pa_end = 0x490260ff, | |
2332 | .flags = ADDR_TYPE_RT | |
2333 | }, | |
78183f3f | 2334 | { } |
70034d38 VC |
2335 | }; |
2336 | ||
dc48e5fc C |
2337 | /* l4_per -> mcbsp4 */ |
2338 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { | |
2339 | .master = &omap3xxx_l4_per_hwmod, | |
2340 | .slave = &omap3xxx_mcbsp4_hwmod, | |
2341 | .clk = "mcbsp4_ick", | |
2342 | .addr = omap3xxx_mcbsp4_addrs, | |
dc48e5fc | 2343 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2344 | }; |
2345 | ||
dc48e5fc C |
2346 | /* mcbsp4 slave ports */ |
2347 | static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = { | |
2348 | &omap3xxx_l4_per__mcbsp4, | |
70034d38 VC |
2349 | }; |
2350 | ||
dc48e5fc C |
2351 | static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { |
2352 | .name = "mcbsp4", | |
2353 | .class = &omap3xxx_mcbsp_hwmod_class, | |
2354 | .mpu_irqs = omap3xxx_mcbsp4_irqs, | |
dc48e5fc | 2355 | .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, |
dc48e5fc | 2356 | .main_clk = "mcbsp4_fck", |
70034d38 VC |
2357 | .prcm = { |
2358 | .omap2 = { | |
2359 | .prcm_reg_id = 1, | |
dc48e5fc | 2360 | .module_bit = OMAP3430_EN_MCBSP4_SHIFT, |
70034d38 VC |
2361 | .module_offs = OMAP3430_PER_MOD, |
2362 | .idlest_reg_id = 1, | |
dc48e5fc | 2363 | .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, |
70034d38 VC |
2364 | }, |
2365 | }, | |
dc48e5fc C |
2366 | .slaves = omap3xxx_mcbsp4_slaves, |
2367 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves), | |
70034d38 VC |
2368 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
2369 | }; | |
2370 | ||
dc48e5fc C |
2371 | /* mcbsp5 */ |
2372 | static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { | |
2373 | { .name = "irq", .irq = 27 }, | |
2374 | { .name = "tx", .irq = 81 }, | |
2375 | { .name = "rx", .irq = 82 }, | |
212738a4 | 2376 | { .irq = -1 } |
70034d38 VC |
2377 | }; |
2378 | ||
dc48e5fc C |
2379 | static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { |
2380 | { .name = "rx", .dma_req = 22 }, | |
2381 | { .name = "tx", .dma_req = 21 }, | |
bc614958 | 2382 | { .dma_req = -1 } |
70034d38 VC |
2383 | }; |
2384 | ||
dc48e5fc C |
2385 | static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { |
2386 | { | |
2387 | .name = "mpu", | |
2388 | .pa_start = 0x48096000, | |
2389 | .pa_end = 0x480960ff, | |
2390 | .flags = ADDR_TYPE_RT | |
2391 | }, | |
78183f3f | 2392 | { } |
70034d38 VC |
2393 | }; |
2394 | ||
dc48e5fc C |
2395 | /* l4_core -> mcbsp5 */ |
2396 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { | |
2397 | .master = &omap3xxx_l4_core_hwmod, | |
2398 | .slave = &omap3xxx_mcbsp5_hwmod, | |
2399 | .clk = "mcbsp5_ick", | |
2400 | .addr = omap3xxx_mcbsp5_addrs, | |
dc48e5fc C |
2401 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2402 | }; | |
2403 | ||
2404 | /* mcbsp5 slave ports */ | |
2405 | static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = { | |
2406 | &omap3xxx_l4_core__mcbsp5, | |
2407 | }; | |
2408 | ||
2409 | static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { | |
2410 | .name = "mcbsp5", | |
2411 | .class = &omap3xxx_mcbsp_hwmod_class, | |
2412 | .mpu_irqs = omap3xxx_mcbsp5_irqs, | |
dc48e5fc | 2413 | .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, |
dc48e5fc | 2414 | .main_clk = "mcbsp5_fck", |
70034d38 VC |
2415 | .prcm = { |
2416 | .omap2 = { | |
2417 | .prcm_reg_id = 1, | |
dc48e5fc C |
2418 | .module_bit = OMAP3430_EN_MCBSP5_SHIFT, |
2419 | .module_offs = CORE_MOD, | |
70034d38 | 2420 | .idlest_reg_id = 1, |
dc48e5fc | 2421 | .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, |
70034d38 VC |
2422 | }, |
2423 | }, | |
dc48e5fc C |
2424 | .slaves = omap3xxx_mcbsp5_slaves, |
2425 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves), | |
70034d38 VC |
2426 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
2427 | }; | |
dc48e5fc | 2428 | /* 'mcbsp sidetone' class */ |
70034d38 | 2429 | |
dc48e5fc C |
2430 | static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { |
2431 | .sysc_offs = 0x0010, | |
2432 | .sysc_flags = SYSC_HAS_AUTOIDLE, | |
2433 | .sysc_fields = &omap_hwmod_sysc_type1, | |
01438ab6 MK |
2434 | }; |
2435 | ||
dc48e5fc C |
2436 | static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { |
2437 | .name = "mcbsp_sidetone", | |
2438 | .sysc = &omap3xxx_mcbsp_sidetone_sysc, | |
01438ab6 MK |
2439 | }; |
2440 | ||
dc48e5fc C |
2441 | /* mcbsp2_sidetone */ |
2442 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { | |
2443 | { .name = "irq", .irq = 4 }, | |
212738a4 | 2444 | { .irq = -1 } |
01438ab6 MK |
2445 | }; |
2446 | ||
dc48e5fc C |
2447 | static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { |
2448 | { | |
2449 | .name = "sidetone", | |
2450 | .pa_start = 0x49028000, | |
2451 | .pa_end = 0x490280ff, | |
2452 | .flags = ADDR_TYPE_RT | |
2453 | }, | |
78183f3f | 2454 | { } |
01438ab6 MK |
2455 | }; |
2456 | ||
dc48e5fc C |
2457 | /* l4_per -> mcbsp2_sidetone */ |
2458 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { | |
2459 | .master = &omap3xxx_l4_per_hwmod, | |
2460 | .slave = &omap3xxx_mcbsp2_sidetone_hwmod, | |
2461 | .clk = "mcbsp2_ick", | |
2462 | .addr = omap3xxx_mcbsp2_sidetone_addrs, | |
dc48e5fc | 2463 | .user = OCP_USER_MPU, |
01438ab6 MK |
2464 | }; |
2465 | ||
dc48e5fc C |
2466 | /* mcbsp2_sidetone slave ports */ |
2467 | static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = { | |
2468 | &omap3xxx_l4_per__mcbsp2_sidetone, | |
2469 | }; | |
2470 | ||
2471 | static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { | |
2472 | .name = "mcbsp2_sidetone", | |
2473 | .class = &omap3xxx_mcbsp_sidetone_hwmod_class, | |
2474 | .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, | |
dc48e5fc C |
2475 | .main_clk = "mcbsp2_fck", |
2476 | .prcm = { | |
2477 | .omap2 = { | |
2478 | .prcm_reg_id = 1, | |
2479 | .module_bit = OMAP3430_EN_MCBSP2_SHIFT, | |
2480 | .module_offs = OMAP3430_PER_MOD, | |
2481 | .idlest_reg_id = 1, | |
2482 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, | |
2483 | }, | |
01438ab6 | 2484 | }, |
dc48e5fc C |
2485 | .slaves = omap3xxx_mcbsp2_sidetone_slaves, |
2486 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves), | |
2487 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
01438ab6 MK |
2488 | }; |
2489 | ||
dc48e5fc C |
2490 | /* mcbsp3_sidetone */ |
2491 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { | |
2492 | { .name = "irq", .irq = 5 }, | |
212738a4 | 2493 | { .irq = -1 } |
01438ab6 MK |
2494 | }; |
2495 | ||
dc48e5fc C |
2496 | static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { |
2497 | { | |
2498 | .name = "sidetone", | |
2499 | .pa_start = 0x4902A000, | |
2500 | .pa_end = 0x4902A0ff, | |
2501 | .flags = ADDR_TYPE_RT | |
2502 | }, | |
78183f3f | 2503 | { } |
01438ab6 MK |
2504 | }; |
2505 | ||
dc48e5fc C |
2506 | /* l4_per -> mcbsp3_sidetone */ |
2507 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { | |
2508 | .master = &omap3xxx_l4_per_hwmod, | |
2509 | .slave = &omap3xxx_mcbsp3_sidetone_hwmod, | |
2510 | .clk = "mcbsp3_ick", | |
2511 | .addr = omap3xxx_mcbsp3_sidetone_addrs, | |
dc48e5fc | 2512 | .user = OCP_USER_MPU, |
01438ab6 MK |
2513 | }; |
2514 | ||
dc48e5fc C |
2515 | /* mcbsp3_sidetone slave ports */ |
2516 | static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = { | |
2517 | &omap3xxx_l4_per__mcbsp3_sidetone, | |
2518 | }; | |
2519 | ||
2520 | static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { | |
2521 | .name = "mcbsp3_sidetone", | |
2522 | .class = &omap3xxx_mcbsp_sidetone_hwmod_class, | |
2523 | .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, | |
dc48e5fc C |
2524 | .main_clk = "mcbsp3_fck", |
2525 | .prcm = { | |
01438ab6 | 2526 | .omap2 = { |
dc48e5fc C |
2527 | .prcm_reg_id = 1, |
2528 | .module_bit = OMAP3430_EN_MCBSP3_SHIFT, | |
2529 | .module_offs = OMAP3430_PER_MOD, | |
2530 | .idlest_reg_id = 1, | |
2531 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, | |
01438ab6 MK |
2532 | }, |
2533 | }, | |
dc48e5fc C |
2534 | .slaves = omap3xxx_mcbsp3_sidetone_slaves, |
2535 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves), | |
01438ab6 | 2536 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
01438ab6 MK |
2537 | }; |
2538 | ||
dc48e5fc | 2539 | |
d3442726 TG |
2540 | /* SR common */ |
2541 | static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { | |
2542 | .clkact_shift = 20, | |
2543 | }; | |
2544 | ||
2545 | static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { | |
2546 | .sysc_offs = 0x24, | |
2547 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), | |
2548 | .clockact = CLOCKACT_TEST_ICLK, | |
2549 | .sysc_fields = &omap34xx_sr_sysc_fields, | |
2550 | }; | |
2551 | ||
2552 | static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { | |
2553 | .name = "smartreflex", | |
2554 | .sysc = &omap34xx_sr_sysc, | |
2555 | .rev = 1, | |
2556 | }; | |
2557 | ||
2558 | static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { | |
2559 | .sidle_shift = 24, | |
2560 | .enwkup_shift = 26 | |
2561 | }; | |
2562 | ||
2563 | static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { | |
2564 | .sysc_offs = 0x38, | |
2565 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2566 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
2567 | SYSC_NO_CACHE), | |
2568 | .sysc_fields = &omap36xx_sr_sysc_fields, | |
2569 | }; | |
2570 | ||
2571 | static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { | |
2572 | .name = "smartreflex", | |
2573 | .sysc = &omap36xx_sr_sysc, | |
2574 | .rev = 2, | |
2575 | }; | |
2576 | ||
2577 | /* SR1 */ | |
2578 | static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = { | |
2579 | &omap3_l4_core__sr1, | |
2580 | }; | |
2581 | ||
2582 | static struct omap_hwmod omap34xx_sr1_hwmod = { | |
2583 | .name = "sr1_hwmod", | |
2584 | .class = &omap34xx_smartreflex_hwmod_class, | |
2585 | .main_clk = "sr1_fck", | |
2586 | .vdd_name = "mpu", | |
2587 | .prcm = { | |
2588 | .omap2 = { | |
2589 | .prcm_reg_id = 1, | |
2590 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
2591 | .module_offs = WKUP_MOD, | |
2592 | .idlest_reg_id = 1, | |
2593 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
2594 | }, | |
2595 | }, | |
2596 | .slaves = omap3_sr1_slaves, | |
2597 | .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), | |
2598 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 | | |
2599 | CHIP_IS_OMAP3430ES3_0 | | |
2600 | CHIP_IS_OMAP3430ES3_1), | |
2601 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
2602 | }; | |
2603 | ||
2604 | static struct omap_hwmod omap36xx_sr1_hwmod = { | |
2605 | .name = "sr1_hwmod", | |
2606 | .class = &omap36xx_smartreflex_hwmod_class, | |
2607 | .main_clk = "sr1_fck", | |
2608 | .vdd_name = "mpu", | |
2609 | .prcm = { | |
2610 | .omap2 = { | |
2611 | .prcm_reg_id = 1, | |
2612 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
2613 | .module_offs = WKUP_MOD, | |
2614 | .idlest_reg_id = 1, | |
2615 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
2616 | }, | |
2617 | }, | |
2618 | .slaves = omap3_sr1_slaves, | |
2619 | .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), | |
2620 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), | |
2621 | }; | |
2622 | ||
2623 | /* SR2 */ | |
2624 | static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = { | |
2625 | &omap3_l4_core__sr2, | |
2626 | }; | |
2627 | ||
2628 | static struct omap_hwmod omap34xx_sr2_hwmod = { | |
2629 | .name = "sr2_hwmod", | |
2630 | .class = &omap34xx_smartreflex_hwmod_class, | |
2631 | .main_clk = "sr2_fck", | |
2632 | .vdd_name = "core", | |
2633 | .prcm = { | |
2634 | .omap2 = { | |
2635 | .prcm_reg_id = 1, | |
2636 | .module_bit = OMAP3430_EN_SR2_SHIFT, | |
2637 | .module_offs = WKUP_MOD, | |
2638 | .idlest_reg_id = 1, | |
2639 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, | |
2640 | }, | |
2641 | }, | |
2642 | .slaves = omap3_sr2_slaves, | |
2643 | .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), | |
2644 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 | | |
2645 | CHIP_IS_OMAP3430ES3_0 | | |
2646 | CHIP_IS_OMAP3430ES3_1), | |
2647 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
2648 | }; | |
2649 | ||
2650 | static struct omap_hwmod omap36xx_sr2_hwmod = { | |
2651 | .name = "sr2_hwmod", | |
2652 | .class = &omap36xx_smartreflex_hwmod_class, | |
2653 | .main_clk = "sr2_fck", | |
2654 | .vdd_name = "core", | |
2655 | .prcm = { | |
2656 | .omap2 = { | |
2657 | .prcm_reg_id = 1, | |
2658 | .module_bit = OMAP3430_EN_SR2_SHIFT, | |
2659 | .module_offs = WKUP_MOD, | |
2660 | .idlest_reg_id = 1, | |
2661 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, | |
2662 | }, | |
2663 | }, | |
2664 | .slaves = omap3_sr2_slaves, | |
2665 | .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), | |
2666 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), | |
2667 | }; | |
2668 | ||
0f9dfdd3 FC |
2669 | /* |
2670 | * 'mailbox' class | |
2671 | * mailbox module allowing communication between the on-chip processors | |
2672 | * using a queued mailbox-interrupt mechanism. | |
2673 | */ | |
2674 | ||
2675 | static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { | |
2676 | .rev_offs = 0x000, | |
2677 | .sysc_offs = 0x010, | |
2678 | .syss_offs = 0x014, | |
2679 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
2680 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
2681 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2682 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2683 | }; | |
2684 | ||
2685 | static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { | |
2686 | .name = "mailbox", | |
2687 | .sysc = &omap3xxx_mailbox_sysc, | |
2688 | }; | |
2689 | ||
2690 | static struct omap_hwmod omap3xxx_mailbox_hwmod; | |
2691 | static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { | |
2692 | { .irq = 26 }, | |
212738a4 | 2693 | { .irq = -1 } |
0f9dfdd3 FC |
2694 | }; |
2695 | ||
2696 | static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { | |
2697 | { | |
2698 | .pa_start = 0x48094000, | |
2699 | .pa_end = 0x480941ff, | |
2700 | .flags = ADDR_TYPE_RT, | |
2701 | }, | |
78183f3f | 2702 | { } |
0f9dfdd3 FC |
2703 | }; |
2704 | ||
2705 | /* l4_core -> mailbox */ | |
2706 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { | |
2707 | .master = &omap3xxx_l4_core_hwmod, | |
2708 | .slave = &omap3xxx_mailbox_hwmod, | |
2709 | .addr = omap3xxx_mailbox_addrs, | |
0f9dfdd3 FC |
2710 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2711 | }; | |
2712 | ||
2713 | /* mailbox slave ports */ | |
2714 | static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = { | |
2715 | &omap3xxx_l4_core__mailbox, | |
2716 | }; | |
2717 | ||
2718 | static struct omap_hwmod omap3xxx_mailbox_hwmod = { | |
2719 | .name = "mailbox", | |
2720 | .class = &omap3xxx_mailbox_hwmod_class, | |
2721 | .mpu_irqs = omap3xxx_mailbox_irqs, | |
0f9dfdd3 FC |
2722 | .main_clk = "mailboxes_ick", |
2723 | .prcm = { | |
2724 | .omap2 = { | |
2725 | .prcm_reg_id = 1, | |
2726 | .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, | |
2727 | .module_offs = CORE_MOD, | |
2728 | .idlest_reg_id = 1, | |
2729 | .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, | |
2730 | }, | |
2731 | }, | |
2732 | .slaves = omap3xxx_mailbox_slaves, | |
2733 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves), | |
2734 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
2735 | }; | |
2736 | ||
0f616a4e | 2737 | /* l4 core -> mcspi1 interface */ |
0f616a4e C |
2738 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { |
2739 | .master = &omap3xxx_l4_core_hwmod, | |
2740 | .slave = &omap34xx_mcspi1, | |
2741 | .clk = "mcspi1_ick", | |
ded11383 | 2742 | .addr = omap2_mcspi1_addr_space, |
0f616a4e C |
2743 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2744 | }; | |
2745 | ||
2746 | /* l4 core -> mcspi2 interface */ | |
0f616a4e C |
2747 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { |
2748 | .master = &omap3xxx_l4_core_hwmod, | |
2749 | .slave = &omap34xx_mcspi2, | |
2750 | .clk = "mcspi2_ick", | |
ded11383 | 2751 | .addr = omap2_mcspi2_addr_space, |
0f616a4e C |
2752 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2753 | }; | |
2754 | ||
2755 | /* l4 core -> mcspi3 interface */ | |
0f616a4e C |
2756 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { |
2757 | .master = &omap3xxx_l4_core_hwmod, | |
2758 | .slave = &omap34xx_mcspi3, | |
2759 | .clk = "mcspi3_ick", | |
ded11383 | 2760 | .addr = omap2430_mcspi3_addr_space, |
0f616a4e C |
2761 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2762 | }; | |
2763 | ||
2764 | /* l4 core -> mcspi4 interface */ | |
2765 | static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { | |
2766 | { | |
2767 | .pa_start = 0x480ba000, | |
2768 | .pa_end = 0x480ba0ff, | |
2769 | .flags = ADDR_TYPE_RT, | |
2770 | }, | |
78183f3f | 2771 | { } |
0f616a4e C |
2772 | }; |
2773 | ||
2774 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { | |
2775 | .master = &omap3xxx_l4_core_hwmod, | |
2776 | .slave = &omap34xx_mcspi4, | |
2777 | .clk = "mcspi4_ick", | |
2778 | .addr = omap34xx_mcspi4_addr_space, | |
0f616a4e C |
2779 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2780 | }; | |
2781 | ||
2782 | /* | |
2783 | * 'mcspi' class | |
2784 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
2785 | * bus | |
2786 | */ | |
2787 | ||
2788 | static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { | |
2789 | .rev_offs = 0x0000, | |
2790 | .sysc_offs = 0x0010, | |
2791 | .syss_offs = 0x0014, | |
2792 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
2793 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
2794 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
2795 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2796 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2797 | }; | |
2798 | ||
2799 | static struct omap_hwmod_class omap34xx_mcspi_class = { | |
2800 | .name = "mcspi", | |
2801 | .sysc = &omap34xx_mcspi_sysc, | |
2802 | .rev = OMAP3_MCSPI_REV, | |
2803 | }; | |
2804 | ||
2805 | /* mcspi1 */ | |
0f616a4e C |
2806 | static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = { |
2807 | &omap34xx_l4_core__mcspi1, | |
2808 | }; | |
2809 | ||
2810 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { | |
2811 | .num_chipselect = 4, | |
2812 | }; | |
2813 | ||
2814 | static struct omap_hwmod omap34xx_mcspi1 = { | |
2815 | .name = "mcspi1", | |
0d619a89 | 2816 | .mpu_irqs = omap2_mcspi1_mpu_irqs, |
d826ebfa | 2817 | .sdma_reqs = omap2_mcspi1_sdma_reqs, |
0f616a4e C |
2818 | .main_clk = "mcspi1_fck", |
2819 | .prcm = { | |
2820 | .omap2 = { | |
2821 | .module_offs = CORE_MOD, | |
2822 | .prcm_reg_id = 1, | |
2823 | .module_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
2824 | .idlest_reg_id = 1, | |
2825 | .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, | |
2826 | }, | |
2827 | }, | |
2828 | .slaves = omap34xx_mcspi1_slaves, | |
2829 | .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves), | |
2830 | .class = &omap34xx_mcspi_class, | |
2831 | .dev_attr = &omap_mcspi1_dev_attr, | |
2832 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
2833 | }; | |
2834 | ||
2835 | /* mcspi2 */ | |
0f616a4e C |
2836 | static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = { |
2837 | &omap34xx_l4_core__mcspi2, | |
2838 | }; | |
2839 | ||
2840 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { | |
2841 | .num_chipselect = 2, | |
2842 | }; | |
2843 | ||
2844 | static struct omap_hwmod omap34xx_mcspi2 = { | |
2845 | .name = "mcspi2", | |
0d619a89 | 2846 | .mpu_irqs = omap2_mcspi2_mpu_irqs, |
d826ebfa | 2847 | .sdma_reqs = omap2_mcspi2_sdma_reqs, |
0f616a4e | 2848 | .main_clk = "mcspi2_fck", |
70034d38 VC |
2849 | .prcm = { |
2850 | .omap2 = { | |
0f616a4e | 2851 | .module_offs = CORE_MOD, |
70034d38 | 2852 | .prcm_reg_id = 1, |
0f616a4e | 2853 | .module_bit = OMAP3430_EN_MCSPI2_SHIFT, |
70034d38 | 2854 | .idlest_reg_id = 1, |
0f616a4e | 2855 | .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, |
70034d38 VC |
2856 | }, |
2857 | }, | |
0f616a4e C |
2858 | .slaves = omap34xx_mcspi2_slaves, |
2859 | .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves), | |
2860 | .class = &omap34xx_mcspi_class, | |
2861 | .dev_attr = &omap_mcspi2_dev_attr, | |
70034d38 VC |
2862 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
2863 | }; | |
2864 | ||
0f616a4e C |
2865 | /* mcspi3 */ |
2866 | static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { | |
2867 | { .name = "irq", .irq = 91 }, /* 91 */ | |
212738a4 | 2868 | { .irq = -1 } |
70034d38 VC |
2869 | }; |
2870 | ||
0f616a4e C |
2871 | static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { |
2872 | { .name = "tx0", .dma_req = 15 }, | |
2873 | { .name = "rx0", .dma_req = 16 }, | |
2874 | { .name = "tx1", .dma_req = 23 }, | |
2875 | { .name = "rx1", .dma_req = 24 }, | |
bc614958 | 2876 | { .dma_req = -1 } |
70034d38 VC |
2877 | }; |
2878 | ||
0f616a4e C |
2879 | static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = { |
2880 | &omap34xx_l4_core__mcspi3, | |
70034d38 VC |
2881 | }; |
2882 | ||
0f616a4e C |
2883 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { |
2884 | .num_chipselect = 2, | |
2885 | }; | |
2886 | ||
2887 | static struct omap_hwmod omap34xx_mcspi3 = { | |
2888 | .name = "mcspi3", | |
2889 | .mpu_irqs = omap34xx_mcspi3_mpu_irqs, | |
0f616a4e | 2890 | .sdma_reqs = omap34xx_mcspi3_sdma_reqs, |
0f616a4e | 2891 | .main_clk = "mcspi3_fck", |
70034d38 VC |
2892 | .prcm = { |
2893 | .omap2 = { | |
0f616a4e | 2894 | .module_offs = CORE_MOD, |
70034d38 | 2895 | .prcm_reg_id = 1, |
0f616a4e | 2896 | .module_bit = OMAP3430_EN_MCSPI3_SHIFT, |
70034d38 | 2897 | .idlest_reg_id = 1, |
0f616a4e | 2898 | .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, |
70034d38 VC |
2899 | }, |
2900 | }, | |
0f616a4e C |
2901 | .slaves = omap34xx_mcspi3_slaves, |
2902 | .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves), | |
2903 | .class = &omap34xx_mcspi_class, | |
2904 | .dev_attr = &omap_mcspi3_dev_attr, | |
70034d38 VC |
2905 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
2906 | }; | |
2907 | ||
0f616a4e C |
2908 | /* SPI4 */ |
2909 | static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { | |
2910 | { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ | |
212738a4 | 2911 | { .irq = -1 } |
70034d38 VC |
2912 | }; |
2913 | ||
0f616a4e C |
2914 | static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { |
2915 | { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ | |
2916 | { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ | |
bc614958 | 2917 | { .dma_req = -1 } |
70034d38 VC |
2918 | }; |
2919 | ||
0f616a4e C |
2920 | static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = { |
2921 | &omap34xx_l4_core__mcspi4, | |
70034d38 VC |
2922 | }; |
2923 | ||
0f616a4e C |
2924 | static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { |
2925 | .num_chipselect = 1, | |
2926 | }; | |
2927 | ||
2928 | static struct omap_hwmod omap34xx_mcspi4 = { | |
2929 | .name = "mcspi4", | |
2930 | .mpu_irqs = omap34xx_mcspi4_mpu_irqs, | |
0f616a4e | 2931 | .sdma_reqs = omap34xx_mcspi4_sdma_reqs, |
0f616a4e | 2932 | .main_clk = "mcspi4_fck", |
70034d38 VC |
2933 | .prcm = { |
2934 | .omap2 = { | |
0f616a4e | 2935 | .module_offs = CORE_MOD, |
70034d38 | 2936 | .prcm_reg_id = 1, |
0f616a4e | 2937 | .module_bit = OMAP3430_EN_MCSPI4_SHIFT, |
70034d38 | 2938 | .idlest_reg_id = 1, |
0f616a4e | 2939 | .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, |
70034d38 VC |
2940 | }, |
2941 | }, | |
0f616a4e C |
2942 | .slaves = omap34xx_mcspi4_slaves, |
2943 | .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves), | |
2944 | .class = &omap34xx_mcspi_class, | |
2945 | .dev_attr = &omap_mcspi4_dev_attr, | |
70034d38 VC |
2946 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
2947 | }; | |
2948 | ||
870ea2b8 HH |
2949 | /* |
2950 | * usbhsotg | |
2951 | */ | |
2952 | static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { | |
2953 | .rev_offs = 0x0400, | |
2954 | .sysc_offs = 0x0404, | |
2955 | .syss_offs = 0x0408, | |
2956 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| | |
2957 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
2958 | SYSC_HAS_AUTOIDLE), | |
01438ab6 | 2959 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
870ea2b8 | 2960 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
01438ab6 MK |
2961 | .sysc_fields = &omap_hwmod_sysc_type1, |
2962 | }; | |
2963 | ||
870ea2b8 HH |
2964 | static struct omap_hwmod_class usbotg_class = { |
2965 | .name = "usbotg", | |
2966 | .sysc = &omap3xxx_usbhsotg_sysc, | |
01438ab6 | 2967 | }; |
870ea2b8 HH |
2968 | /* usb_otg_hs */ |
2969 | static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { | |
01438ab6 | 2970 | |
870ea2b8 HH |
2971 | { .name = "mc", .irq = 92 }, |
2972 | { .name = "dma", .irq = 93 }, | |
212738a4 | 2973 | { .irq = -1 } |
01438ab6 MK |
2974 | }; |
2975 | ||
870ea2b8 HH |
2976 | static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { |
2977 | .name = "usb_otg_hs", | |
2978 | .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, | |
870ea2b8 HH |
2979 | .main_clk = "hsotgusb_ick", |
2980 | .prcm = { | |
2981 | .omap2 = { | |
2982 | .prcm_reg_id = 1, | |
2983 | .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, | |
2984 | .module_offs = CORE_MOD, | |
2985 | .idlest_reg_id = 1, | |
2986 | .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, | |
2987 | .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT | |
2988 | }, | |
01438ab6 | 2989 | }, |
870ea2b8 HH |
2990 | .masters = omap3xxx_usbhsotg_masters, |
2991 | .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters), | |
2992 | .slaves = omap3xxx_usbhsotg_slaves, | |
2993 | .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves), | |
2994 | .class = &usbotg_class, | |
2995 | ||
2996 | /* | |
2997 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially | |
2998 | * broken when autoidle is enabled | |
2999 | * workaround is to disable the autoidle bit at module level. | |
3000 | */ | |
3001 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | |
3002 | | HWMOD_SWSUP_MSTANDBY, | |
3003 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
01438ab6 MK |
3004 | }; |
3005 | ||
273ff8c3 HH |
3006 | /* usb_otg_hs */ |
3007 | static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { | |
01438ab6 | 3008 | |
273ff8c3 | 3009 | { .name = "mc", .irq = 71 }, |
212738a4 | 3010 | { .irq = -1 } |
01438ab6 MK |
3011 | }; |
3012 | ||
273ff8c3 HH |
3013 | static struct omap_hwmod_class am35xx_usbotg_class = { |
3014 | .name = "am35xx_usbotg", | |
3015 | .sysc = NULL, | |
01438ab6 MK |
3016 | }; |
3017 | ||
273ff8c3 HH |
3018 | static struct omap_hwmod am35xx_usbhsotg_hwmod = { |
3019 | .name = "am35x_otg_hs", | |
3020 | .mpu_irqs = am35xx_usbhsotg_mpu_irqs, | |
273ff8c3 | 3021 | .main_clk = NULL, |
01438ab6 MK |
3022 | .prcm = { |
3023 | .omap2 = { | |
01438ab6 MK |
3024 | }, |
3025 | }, | |
273ff8c3 HH |
3026 | .masters = am35xx_usbhsotg_masters, |
3027 | .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters), | |
3028 | .slaves = am35xx_usbhsotg_slaves, | |
3029 | .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves), | |
3030 | .class = &am35xx_usbotg_class, | |
3031 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1) | |
01438ab6 MK |
3032 | }; |
3033 | ||
b163605e PW |
3034 | /* MMC/SD/SDIO common */ |
3035 | ||
3036 | static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { | |
3037 | .rev_offs = 0x1fc, | |
3038 | .sysc_offs = 0x10, | |
3039 | .syss_offs = 0x14, | |
3040 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
3041 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
3042 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
3043 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
3044 | .sysc_fields = &omap_hwmod_sysc_type1, | |
d3442726 TG |
3045 | }; |
3046 | ||
b163605e PW |
3047 | static struct omap_hwmod_class omap34xx_mmc_class = { |
3048 | .name = "mmc", | |
3049 | .sysc = &omap34xx_mmc_sysc, | |
d3442726 TG |
3050 | }; |
3051 | ||
b163605e PW |
3052 | /* MMC/SD/SDIO1 */ |
3053 | ||
3054 | static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { | |
3055 | { .irq = 83, }, | |
212738a4 | 3056 | { .irq = -1 } |
d3442726 TG |
3057 | }; |
3058 | ||
b163605e PW |
3059 | static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { |
3060 | { .name = "tx", .dma_req = 61, }, | |
3061 | { .name = "rx", .dma_req = 62, }, | |
bc614958 | 3062 | { .dma_req = -1 } |
d3442726 TG |
3063 | }; |
3064 | ||
b163605e PW |
3065 | static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { |
3066 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
d3442726 TG |
3067 | }; |
3068 | ||
b163605e PW |
3069 | static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = { |
3070 | &omap3xxx_l4_core__mmc1, | |
d3442726 TG |
3071 | }; |
3072 | ||
6ab8946f KK |
3073 | static struct omap_mmc_dev_attr mmc1_dev_attr = { |
3074 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
d3442726 TG |
3075 | }; |
3076 | ||
b163605e PW |
3077 | static struct omap_hwmod omap3xxx_mmc1_hwmod = { |
3078 | .name = "mmc1", | |
3079 | .mpu_irqs = omap34xx_mmc1_mpu_irqs, | |
b163605e | 3080 | .sdma_reqs = omap34xx_mmc1_sdma_reqs, |
b163605e PW |
3081 | .opt_clks = omap34xx_mmc1_opt_clks, |
3082 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), | |
3083 | .main_clk = "mmchs1_fck", | |
d3442726 TG |
3084 | .prcm = { |
3085 | .omap2 = { | |
b163605e | 3086 | .module_offs = CORE_MOD, |
d3442726 | 3087 | .prcm_reg_id = 1, |
b163605e | 3088 | .module_bit = OMAP3430_EN_MMC1_SHIFT, |
d3442726 | 3089 | .idlest_reg_id = 1, |
b163605e | 3090 | .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, |
d3442726 TG |
3091 | }, |
3092 | }, | |
6ab8946f | 3093 | .dev_attr = &mmc1_dev_attr, |
b163605e PW |
3094 | .slaves = omap3xxx_mmc1_slaves, |
3095 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves), | |
3096 | .class = &omap34xx_mmc_class, | |
3097 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
d3442726 TG |
3098 | }; |
3099 | ||
b163605e PW |
3100 | /* MMC/SD/SDIO2 */ |
3101 | ||
3102 | static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { | |
3103 | { .irq = INT_24XX_MMC2_IRQ, }, | |
212738a4 | 3104 | { .irq = -1 } |
d3442726 TG |
3105 | }; |
3106 | ||
b163605e PW |
3107 | static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { |
3108 | { .name = "tx", .dma_req = 47, }, | |
3109 | { .name = "rx", .dma_req = 48, }, | |
bc614958 | 3110 | { .dma_req = -1 } |
d3442726 TG |
3111 | }; |
3112 | ||
b163605e PW |
3113 | static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { |
3114 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
3115 | }; | |
3116 | ||
3117 | static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = { | |
3118 | &omap3xxx_l4_core__mmc2, | |
3119 | }; | |
3120 | ||
3121 | static struct omap_hwmod omap3xxx_mmc2_hwmod = { | |
3122 | .name = "mmc2", | |
3123 | .mpu_irqs = omap34xx_mmc2_mpu_irqs, | |
b163605e | 3124 | .sdma_reqs = omap34xx_mmc2_sdma_reqs, |
b163605e PW |
3125 | .opt_clks = omap34xx_mmc2_opt_clks, |
3126 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), | |
3127 | .main_clk = "mmchs2_fck", | |
d3442726 TG |
3128 | .prcm = { |
3129 | .omap2 = { | |
b163605e | 3130 | .module_offs = CORE_MOD, |
d3442726 | 3131 | .prcm_reg_id = 1, |
b163605e | 3132 | .module_bit = OMAP3430_EN_MMC2_SHIFT, |
d3442726 | 3133 | .idlest_reg_id = 1, |
b163605e | 3134 | .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, |
d3442726 TG |
3135 | }, |
3136 | }, | |
b163605e PW |
3137 | .slaves = omap3xxx_mmc2_slaves, |
3138 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves), | |
3139 | .class = &omap34xx_mmc_class, | |
3140 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
d3442726 TG |
3141 | }; |
3142 | ||
b163605e PW |
3143 | /* MMC/SD/SDIO3 */ |
3144 | ||
3145 | static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { | |
3146 | { .irq = 94, }, | |
212738a4 | 3147 | { .irq = -1 } |
b163605e PW |
3148 | }; |
3149 | ||
3150 | static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { | |
3151 | { .name = "tx", .dma_req = 77, }, | |
3152 | { .name = "rx", .dma_req = 78, }, | |
bc614958 | 3153 | { .dma_req = -1 } |
b163605e PW |
3154 | }; |
3155 | ||
3156 | static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { | |
3157 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
3158 | }; | |
3159 | ||
3160 | static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = { | |
3161 | &omap3xxx_l4_core__mmc3, | |
3162 | }; | |
3163 | ||
3164 | static struct omap_hwmod omap3xxx_mmc3_hwmod = { | |
3165 | .name = "mmc3", | |
3166 | .mpu_irqs = omap34xx_mmc3_mpu_irqs, | |
b163605e | 3167 | .sdma_reqs = omap34xx_mmc3_sdma_reqs, |
b163605e PW |
3168 | .opt_clks = omap34xx_mmc3_opt_clks, |
3169 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), | |
3170 | .main_clk = "mmchs3_fck", | |
d3442726 TG |
3171 | .prcm = { |
3172 | .omap2 = { | |
3173 | .prcm_reg_id = 1, | |
b163605e | 3174 | .module_bit = OMAP3430_EN_MMC3_SHIFT, |
d3442726 | 3175 | .idlest_reg_id = 1, |
b163605e | 3176 | .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, |
d3442726 TG |
3177 | }, |
3178 | }, | |
b163605e PW |
3179 | .slaves = omap3xxx_mmc3_slaves, |
3180 | .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves), | |
3181 | .class = &omap34xx_mmc_class, | |
3182 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
d3442726 TG |
3183 | }; |
3184 | ||
7359154e | 3185 | static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { |
4a7cf90a | 3186 | &omap3xxx_l3_main_hwmod, |
7359154e PW |
3187 | &omap3xxx_l4_core_hwmod, |
3188 | &omap3xxx_l4_per_hwmod, | |
3189 | &omap3xxx_l4_wkup_hwmod, | |
b163605e PW |
3190 | &omap3xxx_mmc1_hwmod, |
3191 | &omap3xxx_mmc2_hwmod, | |
3192 | &omap3xxx_mmc3_hwmod, | |
7359154e | 3193 | &omap3xxx_mpu_hwmod, |
540064bf | 3194 | &omap3xxx_iva_hwmod, |
ce722d26 TG |
3195 | |
3196 | &omap3xxx_timer1_hwmod, | |
3197 | &omap3xxx_timer2_hwmod, | |
3198 | &omap3xxx_timer3_hwmod, | |
3199 | &omap3xxx_timer4_hwmod, | |
3200 | &omap3xxx_timer5_hwmod, | |
3201 | &omap3xxx_timer6_hwmod, | |
3202 | &omap3xxx_timer7_hwmod, | |
3203 | &omap3xxx_timer8_hwmod, | |
3204 | &omap3xxx_timer9_hwmod, | |
3205 | &omap3xxx_timer10_hwmod, | |
3206 | &omap3xxx_timer11_hwmod, | |
3207 | &omap3xxx_timer12_hwmod, | |
3208 | ||
6b667f88 | 3209 | &omap3xxx_wd_timer2_hwmod, |
046465b7 KH |
3210 | &omap3xxx_uart1_hwmod, |
3211 | &omap3xxx_uart2_hwmod, | |
3212 | &omap3xxx_uart3_hwmod, | |
3213 | &omap3xxx_uart4_hwmod, | |
e04d9e1e SG |
3214 | /* dss class */ |
3215 | &omap3430es1_dss_core_hwmod, | |
3216 | &omap3xxx_dss_core_hwmod, | |
3217 | &omap3xxx_dss_dispc_hwmod, | |
3218 | &omap3xxx_dss_dsi1_hwmod, | |
3219 | &omap3xxx_dss_rfbi_hwmod, | |
3220 | &omap3xxx_dss_venc_hwmod, | |
3221 | ||
3222 | /* i2c class */ | |
4fe20e97 RN |
3223 | &omap3xxx_i2c1_hwmod, |
3224 | &omap3xxx_i2c2_hwmod, | |
3225 | &omap3xxx_i2c3_hwmod, | |
d3442726 TG |
3226 | &omap34xx_sr1_hwmod, |
3227 | &omap34xx_sr2_hwmod, | |
3228 | &omap36xx_sr1_hwmod, | |
3229 | &omap36xx_sr2_hwmod, | |
3230 | ||
70034d38 VC |
3231 | |
3232 | /* gpio class */ | |
3233 | &omap3xxx_gpio1_hwmod, | |
3234 | &omap3xxx_gpio2_hwmod, | |
3235 | &omap3xxx_gpio3_hwmod, | |
3236 | &omap3xxx_gpio4_hwmod, | |
3237 | &omap3xxx_gpio5_hwmod, | |
3238 | &omap3xxx_gpio6_hwmod, | |
01438ab6 MK |
3239 | |
3240 | /* dma_system class*/ | |
3241 | &omap3xxx_dma_system_hwmod, | |
0f616a4e | 3242 | |
dc48e5fc C |
3243 | /* mcbsp class */ |
3244 | &omap3xxx_mcbsp1_hwmod, | |
3245 | &omap3xxx_mcbsp2_hwmod, | |
3246 | &omap3xxx_mcbsp3_hwmod, | |
3247 | &omap3xxx_mcbsp4_hwmod, | |
3248 | &omap3xxx_mcbsp5_hwmod, | |
3249 | &omap3xxx_mcbsp2_sidetone_hwmod, | |
3250 | &omap3xxx_mcbsp3_sidetone_hwmod, | |
3251 | ||
0f9dfdd3 FC |
3252 | /* mailbox class */ |
3253 | &omap3xxx_mailbox_hwmod, | |
3254 | ||
0f616a4e C |
3255 | /* mcspi class */ |
3256 | &omap34xx_mcspi1, | |
3257 | &omap34xx_mcspi2, | |
3258 | &omap34xx_mcspi3, | |
3259 | &omap34xx_mcspi4, | |
04aa67de | 3260 | |
870ea2b8 HH |
3261 | /* usbotg class */ |
3262 | &omap3xxx_usbhsotg_hwmod, | |
3263 | ||
273ff8c3 HH |
3264 | /* usbotg for am35x */ |
3265 | &am35xx_usbhsotg_hwmod, | |
3266 | ||
7359154e PW |
3267 | NULL, |
3268 | }; | |
3269 | ||
3270 | int __init omap3xxx_hwmod_init(void) | |
3271 | { | |
550c8092 | 3272 | return omap_hwmod_register(omap3xxx_hwmods); |
7359154e | 3273 | } |