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7359154e PW |
1 | /* |
2 | * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips | |
3 | * | |
4 | * Copyright (C) 2009-2010 Nokia Corporation | |
5 | * Paul Walmsley | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * The data in this file should be completely autogeneratable from | |
12 | * the TI hardware database or other technical documentation. | |
13 | * | |
14 | * XXX these should be marked initdata for multi-OMAP kernels | |
15 | */ | |
16 | #include <plat/omap_hwmod.h> | |
17 | #include <mach/irqs.h> | |
18 | #include <plat/cpu.h> | |
19 | #include <plat/dma.h> | |
046465b7 | 20 | #include <plat/serial.h> |
4fe20e97 RN |
21 | #include <plat/l4_3xxx.h> |
22 | #include <plat/i2c.h> | |
70034d38 | 23 | #include <plat/gpio.h> |
d3442726 | 24 | #include <plat/smartreflex.h> |
0f616a4e | 25 | #include <plat/mcspi.h> |
7359154e | 26 | |
43b40992 PW |
27 | #include "omap_hwmod_common_data.h" |
28 | ||
7359154e | 29 | #include "prm-regbits-34xx.h" |
6b667f88 | 30 | #include "cm-regbits-34xx.h" |
ff2516fb | 31 | #include "wd_timer.h" |
273ff8c3 | 32 | #include <mach/am35xx.h> |
7359154e PW |
33 | |
34 | /* | |
35 | * OMAP3xxx hardware module integration data | |
36 | * | |
37 | * ALl of the data in this section should be autogeneratable from the | |
38 | * TI hardware database or other technical documentation. Data that | |
39 | * is driver-specific or driver-kernel integration-specific belongs | |
40 | * elsewhere. | |
41 | */ | |
42 | ||
43 | static struct omap_hwmod omap3xxx_mpu_hwmod; | |
540064bf | 44 | static struct omap_hwmod omap3xxx_iva_hwmod; |
4a7cf90a | 45 | static struct omap_hwmod omap3xxx_l3_main_hwmod; |
7359154e PW |
46 | static struct omap_hwmod omap3xxx_l4_core_hwmod; |
47 | static struct omap_hwmod omap3xxx_l4_per_hwmod; | |
6b667f88 | 48 | static struct omap_hwmod omap3xxx_wd_timer2_hwmod; |
4fe20e97 RN |
49 | static struct omap_hwmod omap3xxx_i2c1_hwmod; |
50 | static struct omap_hwmod omap3xxx_i2c2_hwmod; | |
51 | static struct omap_hwmod omap3xxx_i2c3_hwmod; | |
70034d38 VC |
52 | static struct omap_hwmod omap3xxx_gpio1_hwmod; |
53 | static struct omap_hwmod omap3xxx_gpio2_hwmod; | |
54 | static struct omap_hwmod omap3xxx_gpio3_hwmod; | |
55 | static struct omap_hwmod omap3xxx_gpio4_hwmod; | |
56 | static struct omap_hwmod omap3xxx_gpio5_hwmod; | |
57 | static struct omap_hwmod omap3xxx_gpio6_hwmod; | |
d3442726 TG |
58 | static struct omap_hwmod omap34xx_sr1_hwmod; |
59 | static struct omap_hwmod omap34xx_sr2_hwmod; | |
0f616a4e C |
60 | static struct omap_hwmod omap34xx_mcspi1; |
61 | static struct omap_hwmod omap34xx_mcspi2; | |
62 | static struct omap_hwmod omap34xx_mcspi3; | |
63 | static struct omap_hwmod omap34xx_mcspi4; | |
273ff8c3 | 64 | static struct omap_hwmod am35xx_usbhsotg_hwmod; |
7359154e | 65 | |
01438ab6 MK |
66 | static struct omap_hwmod omap3xxx_dma_system_hwmod; |
67 | ||
7359154e | 68 | /* L3 -> L4_CORE interface */ |
4a7cf90a KH |
69 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { |
70 | .master = &omap3xxx_l3_main_hwmod, | |
7359154e PW |
71 | .slave = &omap3xxx_l4_core_hwmod, |
72 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
73 | }; | |
74 | ||
75 | /* L3 -> L4_PER interface */ | |
4a7cf90a KH |
76 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { |
77 | .master = &omap3xxx_l3_main_hwmod, | |
7359154e PW |
78 | .slave = &omap3xxx_l4_per_hwmod, |
79 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
80 | }; | |
81 | ||
82 | /* MPU -> L3 interface */ | |
4a7cf90a | 83 | static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { |
7359154e | 84 | .master = &omap3xxx_mpu_hwmod, |
4a7cf90a | 85 | .slave = &omap3xxx_l3_main_hwmod, |
7359154e PW |
86 | .user = OCP_USER_MPU, |
87 | }; | |
88 | ||
89 | /* Slave interfaces on the L3 interconnect */ | |
4a7cf90a KH |
90 | static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = { |
91 | &omap3xxx_mpu__l3_main, | |
7359154e PW |
92 | }; |
93 | ||
94 | /* Master interfaces on the L3 interconnect */ | |
4a7cf90a KH |
95 | static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = { |
96 | &omap3xxx_l3_main__l4_core, | |
97 | &omap3xxx_l3_main__l4_per, | |
7359154e PW |
98 | }; |
99 | ||
100 | /* L3 */ | |
4a7cf90a | 101 | static struct omap_hwmod omap3xxx_l3_main_hwmod = { |
fa98347e | 102 | .name = "l3_main", |
43b40992 | 103 | .class = &l3_hwmod_class, |
4a7cf90a KH |
104 | .masters = omap3xxx_l3_main_masters, |
105 | .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), | |
106 | .slaves = omap3xxx_l3_main_slaves, | |
107 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves), | |
2eb1875d KH |
108 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
109 | .flags = HWMOD_NO_IDLEST, | |
7359154e PW |
110 | }; |
111 | ||
112 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod; | |
046465b7 KH |
113 | static struct omap_hwmod omap3xxx_uart1_hwmod; |
114 | static struct omap_hwmod omap3xxx_uart2_hwmod; | |
115 | static struct omap_hwmod omap3xxx_uart3_hwmod; | |
116 | static struct omap_hwmod omap3xxx_uart4_hwmod; | |
870ea2b8 | 117 | static struct omap_hwmod omap3xxx_usbhsotg_hwmod; |
7359154e | 118 | |
870ea2b8 HH |
119 | /* l3_core -> usbhsotg interface */ |
120 | static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { | |
121 | .master = &omap3xxx_usbhsotg_hwmod, | |
122 | .slave = &omap3xxx_l3_main_hwmod, | |
123 | .clk = "core_l3_ick", | |
124 | .user = OCP_USER_MPU, | |
125 | }; | |
7359154e | 126 | |
273ff8c3 HH |
127 | /* l3_core -> am35xx_usbhsotg interface */ |
128 | static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { | |
129 | .master = &am35xx_usbhsotg_hwmod, | |
130 | .slave = &omap3xxx_l3_main_hwmod, | |
131 | .clk = "core_l3_ick", | |
132 | .user = OCP_USER_MPU, | |
133 | }; | |
7359154e PW |
134 | /* L4_CORE -> L4_WKUP interface */ |
135 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { | |
136 | .master = &omap3xxx_l4_core_hwmod, | |
137 | .slave = &omap3xxx_l4_wkup_hwmod, | |
138 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
139 | }; | |
140 | ||
046465b7 KH |
141 | /* L4 CORE -> UART1 interface */ |
142 | static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { | |
143 | { | |
144 | .pa_start = OMAP3_UART1_BASE, | |
145 | .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, | |
146 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
147 | }, | |
148 | }; | |
149 | ||
150 | static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { | |
151 | .master = &omap3xxx_l4_core_hwmod, | |
152 | .slave = &omap3xxx_uart1_hwmod, | |
153 | .clk = "uart1_ick", | |
154 | .addr = omap3xxx_uart1_addr_space, | |
155 | .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space), | |
156 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
157 | }; | |
158 | ||
159 | /* L4 CORE -> UART2 interface */ | |
160 | static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { | |
161 | { | |
162 | .pa_start = OMAP3_UART2_BASE, | |
163 | .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, | |
164 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
165 | }, | |
166 | }; | |
167 | ||
168 | static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { | |
169 | .master = &omap3xxx_l4_core_hwmod, | |
170 | .slave = &omap3xxx_uart2_hwmod, | |
171 | .clk = "uart2_ick", | |
172 | .addr = omap3xxx_uart2_addr_space, | |
173 | .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space), | |
174 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
175 | }; | |
176 | ||
177 | /* L4 PER -> UART3 interface */ | |
178 | static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { | |
179 | { | |
180 | .pa_start = OMAP3_UART3_BASE, | |
181 | .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, | |
182 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
183 | }, | |
184 | }; | |
185 | ||
186 | static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { | |
187 | .master = &omap3xxx_l4_per_hwmod, | |
188 | .slave = &omap3xxx_uart3_hwmod, | |
189 | .clk = "uart3_ick", | |
190 | .addr = omap3xxx_uart3_addr_space, | |
191 | .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space), | |
192 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
193 | }; | |
194 | ||
195 | /* L4 PER -> UART4 interface */ | |
196 | static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = { | |
197 | { | |
198 | .pa_start = OMAP3_UART4_BASE, | |
199 | .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, | |
200 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
201 | }, | |
202 | }; | |
203 | ||
204 | static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { | |
205 | .master = &omap3xxx_l4_per_hwmod, | |
206 | .slave = &omap3xxx_uart4_hwmod, | |
207 | .clk = "uart4_ick", | |
208 | .addr = omap3xxx_uart4_addr_space, | |
209 | .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space), | |
210 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
211 | }; | |
212 | ||
4fe20e97 RN |
213 | /* I2C IP block address space length (in bytes) */ |
214 | #define OMAP2_I2C_AS_LEN 128 | |
215 | ||
216 | /* L4 CORE -> I2C1 interface */ | |
217 | static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = { | |
218 | { | |
219 | .pa_start = 0x48070000, | |
220 | .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, | |
221 | .flags = ADDR_TYPE_RT, | |
222 | }, | |
223 | }; | |
224 | ||
225 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { | |
226 | .master = &omap3xxx_l4_core_hwmod, | |
227 | .slave = &omap3xxx_i2c1_hwmod, | |
228 | .clk = "i2c1_ick", | |
229 | .addr = omap3xxx_i2c1_addr_space, | |
230 | .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space), | |
231 | .fw = { | |
232 | .omap2 = { | |
233 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, | |
234 | .l4_prot_group = 7, | |
235 | .flags = OMAP_FIREWALL_L4, | |
236 | } | |
237 | }, | |
238 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
239 | }; | |
240 | ||
241 | /* L4 CORE -> I2C2 interface */ | |
242 | static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = { | |
243 | { | |
244 | .pa_start = 0x48072000, | |
245 | .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, | |
246 | .flags = ADDR_TYPE_RT, | |
247 | }, | |
248 | }; | |
249 | ||
250 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { | |
251 | .master = &omap3xxx_l4_core_hwmod, | |
252 | .slave = &omap3xxx_i2c2_hwmod, | |
253 | .clk = "i2c2_ick", | |
254 | .addr = omap3xxx_i2c2_addr_space, | |
255 | .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space), | |
256 | .fw = { | |
257 | .omap2 = { | |
258 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, | |
259 | .l4_prot_group = 7, | |
260 | .flags = OMAP_FIREWALL_L4, | |
261 | } | |
262 | }, | |
263 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
264 | }; | |
265 | ||
266 | /* L4 CORE -> I2C3 interface */ | |
267 | static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { | |
268 | { | |
269 | .pa_start = 0x48060000, | |
270 | .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1, | |
271 | .flags = ADDR_TYPE_RT, | |
272 | }, | |
273 | }; | |
274 | ||
275 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { | |
276 | .master = &omap3xxx_l4_core_hwmod, | |
277 | .slave = &omap3xxx_i2c3_hwmod, | |
278 | .clk = "i2c3_ick", | |
279 | .addr = omap3xxx_i2c3_addr_space, | |
280 | .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space), | |
281 | .fw = { | |
282 | .omap2 = { | |
283 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, | |
284 | .l4_prot_group = 7, | |
285 | .flags = OMAP_FIREWALL_L4, | |
286 | } | |
287 | }, | |
288 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
289 | }; | |
290 | ||
d3442726 TG |
291 | /* L4 CORE -> SR1 interface */ |
292 | static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { | |
293 | { | |
294 | .pa_start = OMAP34XX_SR1_BASE, | |
295 | .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, | |
296 | .flags = ADDR_TYPE_RT, | |
297 | }, | |
298 | }; | |
299 | ||
300 | static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = { | |
301 | .master = &omap3xxx_l4_core_hwmod, | |
302 | .slave = &omap34xx_sr1_hwmod, | |
303 | .clk = "sr_l4_ick", | |
304 | .addr = omap3_sr1_addr_space, | |
305 | .addr_cnt = ARRAY_SIZE(omap3_sr1_addr_space), | |
306 | .user = OCP_USER_MPU, | |
307 | }; | |
308 | ||
309 | /* L4 CORE -> SR1 interface */ | |
310 | static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { | |
311 | { | |
312 | .pa_start = OMAP34XX_SR2_BASE, | |
313 | .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, | |
314 | .flags = ADDR_TYPE_RT, | |
315 | }, | |
316 | }; | |
317 | ||
318 | static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = { | |
319 | .master = &omap3xxx_l4_core_hwmod, | |
320 | .slave = &omap34xx_sr2_hwmod, | |
321 | .clk = "sr_l4_ick", | |
322 | .addr = omap3_sr2_addr_space, | |
323 | .addr_cnt = ARRAY_SIZE(omap3_sr2_addr_space), | |
324 | .user = OCP_USER_MPU, | |
325 | }; | |
326 | ||
870ea2b8 HH |
327 | /* |
328 | * usbhsotg interface data | |
329 | */ | |
330 | ||
331 | static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { | |
332 | { | |
333 | .pa_start = OMAP34XX_HSUSB_OTG_BASE, | |
334 | .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, | |
335 | .flags = ADDR_TYPE_RT | |
336 | }, | |
337 | }; | |
338 | ||
339 | /* l4_core -> usbhsotg */ | |
340 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { | |
341 | .master = &omap3xxx_l4_core_hwmod, | |
342 | .slave = &omap3xxx_usbhsotg_hwmod, | |
343 | .clk = "l4_ick", | |
344 | .addr = omap3xxx_usbhsotg_addrs, | |
345 | .addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs), | |
346 | .user = OCP_USER_MPU, | |
347 | }; | |
348 | ||
349 | static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = { | |
350 | &omap3xxx_usbhsotg__l3, | |
351 | }; | |
352 | ||
353 | static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = { | |
354 | &omap3xxx_l4_core__usbhsotg, | |
355 | }; | |
356 | ||
273ff8c3 HH |
357 | static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { |
358 | { | |
359 | .pa_start = AM35XX_IPSS_USBOTGSS_BASE, | |
360 | .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, | |
361 | .flags = ADDR_TYPE_RT | |
362 | }, | |
363 | }; | |
364 | ||
365 | /* l4_core -> usbhsotg */ | |
366 | static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { | |
367 | .master = &omap3xxx_l4_core_hwmod, | |
368 | .slave = &am35xx_usbhsotg_hwmod, | |
369 | .clk = "l4_ick", | |
370 | .addr = am35xx_usbhsotg_addrs, | |
371 | .addr_cnt = ARRAY_SIZE(am35xx_usbhsotg_addrs), | |
372 | .user = OCP_USER_MPU, | |
373 | }; | |
374 | ||
375 | static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = { | |
376 | &am35xx_usbhsotg__l3, | |
377 | }; | |
378 | ||
379 | static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = { | |
380 | &am35xx_l4_core__usbhsotg, | |
381 | }; | |
7359154e PW |
382 | /* Slave interfaces on the L4_CORE interconnect */ |
383 | static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { | |
4a7cf90a | 384 | &omap3xxx_l3_main__l4_core, |
d3442726 TG |
385 | &omap3_l4_core__sr1, |
386 | &omap3_l4_core__sr2, | |
7359154e PW |
387 | }; |
388 | ||
389 | /* Master interfaces on the L4_CORE interconnect */ | |
390 | static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = { | |
391 | &omap3xxx_l4_core__l4_wkup, | |
046465b7 KH |
392 | &omap3_l4_core__uart1, |
393 | &omap3_l4_core__uart2, | |
4fe20e97 RN |
394 | &omap3_l4_core__i2c1, |
395 | &omap3_l4_core__i2c2, | |
396 | &omap3_l4_core__i2c3, | |
7359154e PW |
397 | }; |
398 | ||
399 | /* L4 CORE */ | |
400 | static struct omap_hwmod omap3xxx_l4_core_hwmod = { | |
fa98347e | 401 | .name = "l4_core", |
43b40992 | 402 | .class = &l4_hwmod_class, |
7359154e PW |
403 | .masters = omap3xxx_l4_core_masters, |
404 | .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters), | |
405 | .slaves = omap3xxx_l4_core_slaves, | |
406 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves), | |
2eb1875d KH |
407 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
408 | .flags = HWMOD_NO_IDLEST, | |
7359154e PW |
409 | }; |
410 | ||
411 | /* Slave interfaces on the L4_PER interconnect */ | |
412 | static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = { | |
4a7cf90a | 413 | &omap3xxx_l3_main__l4_per, |
7359154e PW |
414 | }; |
415 | ||
416 | /* Master interfaces on the L4_PER interconnect */ | |
417 | static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = { | |
046465b7 KH |
418 | &omap3_l4_per__uart3, |
419 | &omap3_l4_per__uart4, | |
7359154e PW |
420 | }; |
421 | ||
422 | /* L4 PER */ | |
423 | static struct omap_hwmod omap3xxx_l4_per_hwmod = { | |
fa98347e | 424 | .name = "l4_per", |
43b40992 | 425 | .class = &l4_hwmod_class, |
7359154e PW |
426 | .masters = omap3xxx_l4_per_masters, |
427 | .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters), | |
428 | .slaves = omap3xxx_l4_per_slaves, | |
429 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves), | |
2eb1875d KH |
430 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
431 | .flags = HWMOD_NO_IDLEST, | |
7359154e PW |
432 | }; |
433 | ||
434 | /* Slave interfaces on the L4_WKUP interconnect */ | |
435 | static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = { | |
436 | &omap3xxx_l4_core__l4_wkup, | |
437 | }; | |
438 | ||
439 | /* Master interfaces on the L4_WKUP interconnect */ | |
440 | static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = { | |
441 | }; | |
442 | ||
443 | /* L4 WKUP */ | |
444 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { | |
fa98347e | 445 | .name = "l4_wkup", |
43b40992 | 446 | .class = &l4_hwmod_class, |
7359154e PW |
447 | .masters = omap3xxx_l4_wkup_masters, |
448 | .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters), | |
449 | .slaves = omap3xxx_l4_wkup_slaves, | |
450 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves), | |
2eb1875d KH |
451 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
452 | .flags = HWMOD_NO_IDLEST, | |
7359154e PW |
453 | }; |
454 | ||
455 | /* Master interfaces on the MPU device */ | |
456 | static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = { | |
4a7cf90a | 457 | &omap3xxx_mpu__l3_main, |
7359154e PW |
458 | }; |
459 | ||
460 | /* MPU */ | |
461 | static struct omap_hwmod omap3xxx_mpu_hwmod = { | |
5c2c0296 | 462 | .name = "mpu", |
43b40992 | 463 | .class = &mpu_hwmod_class, |
7359154e PW |
464 | .main_clk = "arm_fck", |
465 | .masters = omap3xxx_mpu_masters, | |
466 | .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters), | |
467 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
468 | }; | |
469 | ||
540064bf KH |
470 | /* |
471 | * IVA2_2 interface data | |
472 | */ | |
473 | ||
474 | /* IVA2 <- L3 interface */ | |
475 | static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { | |
476 | .master = &omap3xxx_l3_main_hwmod, | |
477 | .slave = &omap3xxx_iva_hwmod, | |
478 | .clk = "iva2_ck", | |
479 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
480 | }; | |
481 | ||
482 | static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = { | |
483 | &omap3xxx_l3__iva, | |
484 | }; | |
485 | ||
486 | /* | |
487 | * IVA2 (IVA2) | |
488 | */ | |
489 | ||
490 | static struct omap_hwmod omap3xxx_iva_hwmod = { | |
491 | .name = "iva", | |
492 | .class = &iva_hwmod_class, | |
493 | .masters = omap3xxx_iva_masters, | |
494 | .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters), | |
495 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
496 | }; | |
497 | ||
6b667f88 VC |
498 | /* l4_wkup -> wd_timer2 */ |
499 | static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { | |
500 | { | |
501 | .pa_start = 0x48314000, | |
502 | .pa_end = 0x4831407f, | |
503 | .flags = ADDR_TYPE_RT | |
504 | }, | |
505 | }; | |
506 | ||
507 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { | |
508 | .master = &omap3xxx_l4_wkup_hwmod, | |
509 | .slave = &omap3xxx_wd_timer2_hwmod, | |
510 | .clk = "wdt2_ick", | |
511 | .addr = omap3xxx_wd_timer2_addrs, | |
512 | .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs), | |
513 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
514 | }; | |
515 | ||
516 | /* | |
517 | * 'wd_timer' class | |
518 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
519 | * overflow condition | |
520 | */ | |
521 | ||
522 | static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { | |
523 | .rev_offs = 0x0000, | |
524 | .sysc_offs = 0x0010, | |
525 | .syss_offs = 0x0014, | |
526 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | | |
527 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
528 | SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY), | |
529 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
530 | .sysc_fields = &omap_hwmod_sysc_type1, | |
531 | }; | |
532 | ||
4fe20e97 RN |
533 | /* I2C common */ |
534 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
535 | .rev_offs = 0x00, | |
536 | .sysc_offs = 0x20, | |
537 | .syss_offs = 0x10, | |
538 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
539 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
540 | SYSC_HAS_AUTOIDLE), | |
541 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
542 | .sysc_fields = &omap_hwmod_sysc_type1, | |
543 | }; | |
544 | ||
6b667f88 | 545 | static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { |
ff2516fb PW |
546 | .name = "wd_timer", |
547 | .sysc = &omap3xxx_wd_timer_sysc, | |
548 | .pre_shutdown = &omap2_wd_timer_disable | |
6b667f88 VC |
549 | }; |
550 | ||
551 | /* wd_timer2 */ | |
552 | static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = { | |
553 | &omap3xxx_l4_wkup__wd_timer2, | |
554 | }; | |
555 | ||
556 | static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { | |
557 | .name = "wd_timer2", | |
558 | .class = &omap3xxx_wd_timer_hwmod_class, | |
559 | .main_clk = "wdt2_fck", | |
560 | .prcm = { | |
561 | .omap2 = { | |
562 | .prcm_reg_id = 1, | |
563 | .module_bit = OMAP3430_EN_WDT2_SHIFT, | |
564 | .module_offs = WKUP_MOD, | |
565 | .idlest_reg_id = 1, | |
566 | .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, | |
567 | }, | |
568 | }, | |
569 | .slaves = omap3xxx_wd_timer2_slaves, | |
570 | .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves), | |
571 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
572 | }; | |
573 | ||
046465b7 KH |
574 | /* UART common */ |
575 | ||
576 | static struct omap_hwmod_class_sysconfig uart_sysc = { | |
577 | .rev_offs = 0x50, | |
578 | .sysc_offs = 0x54, | |
579 | .syss_offs = 0x58, | |
580 | .sysc_flags = (SYSC_HAS_SIDLEMODE | | |
581 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
582 | SYSC_HAS_AUTOIDLE), | |
583 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
584 | .sysc_fields = &omap_hwmod_sysc_type1, | |
585 | }; | |
586 | ||
587 | static struct omap_hwmod_class uart_class = { | |
588 | .name = "uart", | |
589 | .sysc = &uart_sysc, | |
590 | }; | |
591 | ||
592 | /* UART1 */ | |
593 | ||
594 | static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { | |
595 | { .irq = INT_24XX_UART1_IRQ, }, | |
596 | }; | |
597 | ||
598 | static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { | |
599 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, | |
600 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, | |
601 | }; | |
602 | ||
603 | static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { | |
604 | &omap3_l4_core__uart1, | |
605 | }; | |
606 | ||
607 | static struct omap_hwmod omap3xxx_uart1_hwmod = { | |
608 | .name = "uart1", | |
609 | .mpu_irqs = uart1_mpu_irqs, | |
610 | .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), | |
611 | .sdma_reqs = uart1_sdma_reqs, | |
612 | .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), | |
613 | .main_clk = "uart1_fck", | |
614 | .prcm = { | |
615 | .omap2 = { | |
616 | .module_offs = CORE_MOD, | |
617 | .prcm_reg_id = 1, | |
618 | .module_bit = OMAP3430_EN_UART1_SHIFT, | |
619 | .idlest_reg_id = 1, | |
620 | .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, | |
621 | }, | |
622 | }, | |
623 | .slaves = omap3xxx_uart1_slaves, | |
624 | .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), | |
625 | .class = &uart_class, | |
626 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
627 | }; | |
628 | ||
629 | /* UART2 */ | |
630 | ||
631 | static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { | |
632 | { .irq = INT_24XX_UART2_IRQ, }, | |
633 | }; | |
634 | ||
635 | static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { | |
636 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, | |
637 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, | |
638 | }; | |
639 | ||
640 | static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = { | |
641 | &omap3_l4_core__uart2, | |
642 | }; | |
643 | ||
644 | static struct omap_hwmod omap3xxx_uart2_hwmod = { | |
645 | .name = "uart2", | |
646 | .mpu_irqs = uart2_mpu_irqs, | |
647 | .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), | |
648 | .sdma_reqs = uart2_sdma_reqs, | |
649 | .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), | |
650 | .main_clk = "uart2_fck", | |
651 | .prcm = { | |
652 | .omap2 = { | |
653 | .module_offs = CORE_MOD, | |
654 | .prcm_reg_id = 1, | |
655 | .module_bit = OMAP3430_EN_UART2_SHIFT, | |
656 | .idlest_reg_id = 1, | |
657 | .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, | |
658 | }, | |
659 | }, | |
660 | .slaves = omap3xxx_uart2_slaves, | |
661 | .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), | |
662 | .class = &uart_class, | |
663 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
664 | }; | |
665 | ||
666 | /* UART3 */ | |
667 | ||
668 | static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { | |
669 | { .irq = INT_24XX_UART3_IRQ, }, | |
670 | }; | |
671 | ||
672 | static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { | |
673 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, | |
674 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, | |
675 | }; | |
676 | ||
677 | static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = { | |
678 | &omap3_l4_per__uart3, | |
679 | }; | |
680 | ||
681 | static struct omap_hwmod omap3xxx_uart3_hwmod = { | |
682 | .name = "uart3", | |
683 | .mpu_irqs = uart3_mpu_irqs, | |
684 | .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), | |
685 | .sdma_reqs = uart3_sdma_reqs, | |
686 | .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), | |
687 | .main_clk = "uart3_fck", | |
688 | .prcm = { | |
689 | .omap2 = { | |
690 | .module_offs = OMAP3430_PER_MOD, | |
691 | .prcm_reg_id = 1, | |
692 | .module_bit = OMAP3430_EN_UART3_SHIFT, | |
693 | .idlest_reg_id = 1, | |
694 | .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, | |
695 | }, | |
696 | }, | |
697 | .slaves = omap3xxx_uart3_slaves, | |
698 | .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), | |
699 | .class = &uart_class, | |
700 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
701 | }; | |
702 | ||
703 | /* UART4 */ | |
704 | ||
705 | static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { | |
706 | { .irq = INT_36XX_UART4_IRQ, }, | |
707 | }; | |
708 | ||
709 | static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { | |
710 | { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, | |
711 | { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, | |
712 | }; | |
713 | ||
714 | static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { | |
715 | &omap3_l4_per__uart4, | |
716 | }; | |
717 | ||
718 | static struct omap_hwmod omap3xxx_uart4_hwmod = { | |
719 | .name = "uart4", | |
720 | .mpu_irqs = uart4_mpu_irqs, | |
721 | .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs), | |
722 | .sdma_reqs = uart4_sdma_reqs, | |
723 | .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs), | |
724 | .main_clk = "uart4_fck", | |
725 | .prcm = { | |
726 | .omap2 = { | |
727 | .module_offs = OMAP3430_PER_MOD, | |
728 | .prcm_reg_id = 1, | |
729 | .module_bit = OMAP3630_EN_UART4_SHIFT, | |
730 | .idlest_reg_id = 1, | |
731 | .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, | |
732 | }, | |
733 | }, | |
734 | .slaves = omap3xxx_uart4_slaves, | |
735 | .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), | |
736 | .class = &uart_class, | |
737 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), | |
738 | }; | |
739 | ||
4fe20e97 RN |
740 | static struct omap_hwmod_class i2c_class = { |
741 | .name = "i2c", | |
742 | .sysc = &i2c_sysc, | |
743 | }; | |
744 | ||
745 | /* I2C1 */ | |
746 | ||
747 | static struct omap_i2c_dev_attr i2c1_dev_attr = { | |
748 | .fifo_depth = 8, /* bytes */ | |
749 | }; | |
750 | ||
751 | static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { | |
752 | { .irq = INT_24XX_I2C1_IRQ, }, | |
753 | }; | |
754 | ||
755 | static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { | |
756 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, | |
757 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, | |
758 | }; | |
759 | ||
760 | static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = { | |
761 | &omap3_l4_core__i2c1, | |
762 | }; | |
763 | ||
764 | static struct omap_hwmod omap3xxx_i2c1_hwmod = { | |
765 | .name = "i2c1", | |
766 | .mpu_irqs = i2c1_mpu_irqs, | |
767 | .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), | |
768 | .sdma_reqs = i2c1_sdma_reqs, | |
769 | .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), | |
770 | .main_clk = "i2c1_fck", | |
771 | .prcm = { | |
772 | .omap2 = { | |
773 | .module_offs = CORE_MOD, | |
774 | .prcm_reg_id = 1, | |
775 | .module_bit = OMAP3430_EN_I2C1_SHIFT, | |
776 | .idlest_reg_id = 1, | |
777 | .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, | |
778 | }, | |
779 | }, | |
780 | .slaves = omap3xxx_i2c1_slaves, | |
781 | .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves), | |
782 | .class = &i2c_class, | |
783 | .dev_attr = &i2c1_dev_attr, | |
784 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
785 | }; | |
786 | ||
787 | /* I2C2 */ | |
788 | ||
789 | static struct omap_i2c_dev_attr i2c2_dev_attr = { | |
790 | .fifo_depth = 8, /* bytes */ | |
791 | }; | |
792 | ||
793 | static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { | |
794 | { .irq = INT_24XX_I2C2_IRQ, }, | |
795 | }; | |
796 | ||
797 | static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { | |
798 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, | |
799 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, | |
800 | }; | |
801 | ||
802 | static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = { | |
803 | &omap3_l4_core__i2c2, | |
804 | }; | |
805 | ||
806 | static struct omap_hwmod omap3xxx_i2c2_hwmod = { | |
807 | .name = "i2c2", | |
808 | .mpu_irqs = i2c2_mpu_irqs, | |
809 | .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), | |
810 | .sdma_reqs = i2c2_sdma_reqs, | |
811 | .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), | |
812 | .main_clk = "i2c2_fck", | |
813 | .prcm = { | |
814 | .omap2 = { | |
815 | .module_offs = CORE_MOD, | |
816 | .prcm_reg_id = 1, | |
817 | .module_bit = OMAP3430_EN_I2C2_SHIFT, | |
818 | .idlest_reg_id = 1, | |
819 | .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, | |
820 | }, | |
821 | }, | |
822 | .slaves = omap3xxx_i2c2_slaves, | |
823 | .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves), | |
824 | .class = &i2c_class, | |
825 | .dev_attr = &i2c2_dev_attr, | |
826 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
827 | }; | |
828 | ||
829 | /* I2C3 */ | |
830 | ||
831 | static struct omap_i2c_dev_attr i2c3_dev_attr = { | |
832 | .fifo_depth = 64, /* bytes */ | |
833 | }; | |
834 | ||
835 | static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { | |
836 | { .irq = INT_34XX_I2C3_IRQ, }, | |
837 | }; | |
838 | ||
839 | static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { | |
840 | { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, | |
841 | { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, | |
842 | }; | |
843 | ||
844 | static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = { | |
845 | &omap3_l4_core__i2c3, | |
846 | }; | |
847 | ||
848 | static struct omap_hwmod omap3xxx_i2c3_hwmod = { | |
849 | .name = "i2c3", | |
850 | .mpu_irqs = i2c3_mpu_irqs, | |
851 | .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs), | |
852 | .sdma_reqs = i2c3_sdma_reqs, | |
853 | .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs), | |
854 | .main_clk = "i2c3_fck", | |
855 | .prcm = { | |
856 | .omap2 = { | |
857 | .module_offs = CORE_MOD, | |
858 | .prcm_reg_id = 1, | |
859 | .module_bit = OMAP3430_EN_I2C3_SHIFT, | |
860 | .idlest_reg_id = 1, | |
861 | .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, | |
862 | }, | |
863 | }, | |
864 | .slaves = omap3xxx_i2c3_slaves, | |
865 | .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves), | |
866 | .class = &i2c_class, | |
867 | .dev_attr = &i2c3_dev_attr, | |
868 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
869 | }; | |
870 | ||
70034d38 VC |
871 | /* l4_wkup -> gpio1 */ |
872 | static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { | |
873 | { | |
874 | .pa_start = 0x48310000, | |
875 | .pa_end = 0x483101ff, | |
876 | .flags = ADDR_TYPE_RT | |
877 | }, | |
878 | }; | |
879 | ||
880 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { | |
881 | .master = &omap3xxx_l4_wkup_hwmod, | |
882 | .slave = &omap3xxx_gpio1_hwmod, | |
883 | .addr = omap3xxx_gpio1_addrs, | |
884 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs), | |
885 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
886 | }; | |
887 | ||
888 | /* l4_per -> gpio2 */ | |
889 | static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { | |
890 | { | |
891 | .pa_start = 0x49050000, | |
892 | .pa_end = 0x490501ff, | |
893 | .flags = ADDR_TYPE_RT | |
894 | }, | |
895 | }; | |
896 | ||
897 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { | |
898 | .master = &omap3xxx_l4_per_hwmod, | |
899 | .slave = &omap3xxx_gpio2_hwmod, | |
900 | .addr = omap3xxx_gpio2_addrs, | |
901 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs), | |
902 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
903 | }; | |
904 | ||
905 | /* l4_per -> gpio3 */ | |
906 | static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { | |
907 | { | |
908 | .pa_start = 0x49052000, | |
909 | .pa_end = 0x490521ff, | |
910 | .flags = ADDR_TYPE_RT | |
911 | }, | |
912 | }; | |
913 | ||
914 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { | |
915 | .master = &omap3xxx_l4_per_hwmod, | |
916 | .slave = &omap3xxx_gpio3_hwmod, | |
917 | .addr = omap3xxx_gpio3_addrs, | |
918 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs), | |
919 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
920 | }; | |
921 | ||
922 | /* l4_per -> gpio4 */ | |
923 | static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { | |
924 | { | |
925 | .pa_start = 0x49054000, | |
926 | .pa_end = 0x490541ff, | |
927 | .flags = ADDR_TYPE_RT | |
928 | }, | |
929 | }; | |
930 | ||
931 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { | |
932 | .master = &omap3xxx_l4_per_hwmod, | |
933 | .slave = &omap3xxx_gpio4_hwmod, | |
934 | .addr = omap3xxx_gpio4_addrs, | |
935 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs), | |
936 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
937 | }; | |
938 | ||
939 | /* l4_per -> gpio5 */ | |
940 | static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { | |
941 | { | |
942 | .pa_start = 0x49056000, | |
943 | .pa_end = 0x490561ff, | |
944 | .flags = ADDR_TYPE_RT | |
945 | }, | |
946 | }; | |
947 | ||
948 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { | |
949 | .master = &omap3xxx_l4_per_hwmod, | |
950 | .slave = &omap3xxx_gpio5_hwmod, | |
951 | .addr = omap3xxx_gpio5_addrs, | |
952 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs), | |
953 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
954 | }; | |
955 | ||
956 | /* l4_per -> gpio6 */ | |
957 | static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { | |
958 | { | |
959 | .pa_start = 0x49058000, | |
960 | .pa_end = 0x490581ff, | |
961 | .flags = ADDR_TYPE_RT | |
962 | }, | |
963 | }; | |
964 | ||
965 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { | |
966 | .master = &omap3xxx_l4_per_hwmod, | |
967 | .slave = &omap3xxx_gpio6_hwmod, | |
968 | .addr = omap3xxx_gpio6_addrs, | |
969 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs), | |
970 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
971 | }; | |
972 | ||
973 | /* | |
974 | * 'gpio' class | |
975 | * general purpose io module | |
976 | */ | |
977 | ||
978 | static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { | |
979 | .rev_offs = 0x0000, | |
980 | .sysc_offs = 0x0010, | |
981 | .syss_offs = 0x0014, | |
982 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
983 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
984 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
985 | .sysc_fields = &omap_hwmod_sysc_type1, | |
986 | }; | |
987 | ||
988 | static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { | |
989 | .name = "gpio", | |
990 | .sysc = &omap3xxx_gpio_sysc, | |
991 | .rev = 1, | |
992 | }; | |
993 | ||
994 | /* gpio_dev_attr*/ | |
995 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
996 | .bank_width = 32, | |
997 | .dbck_flag = true, | |
998 | }; | |
999 | ||
1000 | /* gpio1 */ | |
1001 | static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = { | |
1002 | { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */ | |
1003 | }; | |
1004 | ||
1005 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | |
1006 | { .role = "dbclk", .clk = "gpio1_dbck", }, | |
1007 | }; | |
1008 | ||
1009 | static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = { | |
1010 | &omap3xxx_l4_wkup__gpio1, | |
1011 | }; | |
1012 | ||
1013 | static struct omap_hwmod omap3xxx_gpio1_hwmod = { | |
1014 | .name = "gpio1", | |
1015 | .mpu_irqs = omap3xxx_gpio1_irqs, | |
1016 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs), | |
1017 | .main_clk = "gpio1_ick", | |
1018 | .opt_clks = gpio1_opt_clks, | |
1019 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
1020 | .prcm = { | |
1021 | .omap2 = { | |
1022 | .prcm_reg_id = 1, | |
1023 | .module_bit = OMAP3430_EN_GPIO1_SHIFT, | |
1024 | .module_offs = WKUP_MOD, | |
1025 | .idlest_reg_id = 1, | |
1026 | .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, | |
1027 | }, | |
1028 | }, | |
1029 | .slaves = omap3xxx_gpio1_slaves, | |
1030 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves), | |
1031 | .class = &omap3xxx_gpio_hwmod_class, | |
1032 | .dev_attr = &gpio_dev_attr, | |
1033 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1034 | }; | |
1035 | ||
1036 | /* gpio2 */ | |
1037 | static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = { | |
1038 | { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */ | |
1039 | }; | |
1040 | ||
1041 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | |
1042 | { .role = "dbclk", .clk = "gpio2_dbck", }, | |
1043 | }; | |
1044 | ||
1045 | static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = { | |
1046 | &omap3xxx_l4_per__gpio2, | |
1047 | }; | |
1048 | ||
1049 | static struct omap_hwmod omap3xxx_gpio2_hwmod = { | |
1050 | .name = "gpio2", | |
1051 | .mpu_irqs = omap3xxx_gpio2_irqs, | |
1052 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs), | |
1053 | .main_clk = "gpio2_ick", | |
1054 | .opt_clks = gpio2_opt_clks, | |
1055 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
1056 | .prcm = { | |
1057 | .omap2 = { | |
1058 | .prcm_reg_id = 1, | |
1059 | .module_bit = OMAP3430_EN_GPIO2_SHIFT, | |
1060 | .module_offs = OMAP3430_PER_MOD, | |
1061 | .idlest_reg_id = 1, | |
1062 | .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, | |
1063 | }, | |
1064 | }, | |
1065 | .slaves = omap3xxx_gpio2_slaves, | |
1066 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves), | |
1067 | .class = &omap3xxx_gpio_hwmod_class, | |
1068 | .dev_attr = &gpio_dev_attr, | |
1069 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1070 | }; | |
1071 | ||
1072 | /* gpio3 */ | |
1073 | static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = { | |
1074 | { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */ | |
1075 | }; | |
1076 | ||
1077 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { | |
1078 | { .role = "dbclk", .clk = "gpio3_dbck", }, | |
1079 | }; | |
1080 | ||
1081 | static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = { | |
1082 | &omap3xxx_l4_per__gpio3, | |
1083 | }; | |
1084 | ||
1085 | static struct omap_hwmod omap3xxx_gpio3_hwmod = { | |
1086 | .name = "gpio3", | |
1087 | .mpu_irqs = omap3xxx_gpio3_irqs, | |
1088 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs), | |
1089 | .main_clk = "gpio3_ick", | |
1090 | .opt_clks = gpio3_opt_clks, | |
1091 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
1092 | .prcm = { | |
1093 | .omap2 = { | |
1094 | .prcm_reg_id = 1, | |
1095 | .module_bit = OMAP3430_EN_GPIO3_SHIFT, | |
1096 | .module_offs = OMAP3430_PER_MOD, | |
1097 | .idlest_reg_id = 1, | |
1098 | .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, | |
1099 | }, | |
1100 | }, | |
1101 | .slaves = omap3xxx_gpio3_slaves, | |
1102 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves), | |
1103 | .class = &omap3xxx_gpio_hwmod_class, | |
1104 | .dev_attr = &gpio_dev_attr, | |
1105 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1106 | }; | |
1107 | ||
1108 | /* gpio4 */ | |
1109 | static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = { | |
1110 | { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */ | |
1111 | }; | |
1112 | ||
1113 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { | |
1114 | { .role = "dbclk", .clk = "gpio4_dbck", }, | |
1115 | }; | |
1116 | ||
1117 | static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = { | |
1118 | &omap3xxx_l4_per__gpio4, | |
1119 | }; | |
1120 | ||
1121 | static struct omap_hwmod omap3xxx_gpio4_hwmod = { | |
1122 | .name = "gpio4", | |
1123 | .mpu_irqs = omap3xxx_gpio4_irqs, | |
1124 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs), | |
1125 | .main_clk = "gpio4_ick", | |
1126 | .opt_clks = gpio4_opt_clks, | |
1127 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
1128 | .prcm = { | |
1129 | .omap2 = { | |
1130 | .prcm_reg_id = 1, | |
1131 | .module_bit = OMAP3430_EN_GPIO4_SHIFT, | |
1132 | .module_offs = OMAP3430_PER_MOD, | |
1133 | .idlest_reg_id = 1, | |
1134 | .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, | |
1135 | }, | |
1136 | }, | |
1137 | .slaves = omap3xxx_gpio4_slaves, | |
1138 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves), | |
1139 | .class = &omap3xxx_gpio_hwmod_class, | |
1140 | .dev_attr = &gpio_dev_attr, | |
1141 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1142 | }; | |
1143 | ||
1144 | /* gpio5 */ | |
1145 | static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { | |
1146 | { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ | |
1147 | }; | |
1148 | ||
1149 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { | |
1150 | { .role = "dbclk", .clk = "gpio5_dbck", }, | |
1151 | }; | |
1152 | ||
1153 | static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = { | |
1154 | &omap3xxx_l4_per__gpio5, | |
1155 | }; | |
1156 | ||
1157 | static struct omap_hwmod omap3xxx_gpio5_hwmod = { | |
1158 | .name = "gpio5", | |
1159 | .mpu_irqs = omap3xxx_gpio5_irqs, | |
1160 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs), | |
1161 | .main_clk = "gpio5_ick", | |
1162 | .opt_clks = gpio5_opt_clks, | |
1163 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
1164 | .prcm = { | |
1165 | .omap2 = { | |
1166 | .prcm_reg_id = 1, | |
1167 | .module_bit = OMAP3430_EN_GPIO5_SHIFT, | |
1168 | .module_offs = OMAP3430_PER_MOD, | |
1169 | .idlest_reg_id = 1, | |
1170 | .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, | |
1171 | }, | |
1172 | }, | |
1173 | .slaves = omap3xxx_gpio5_slaves, | |
1174 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves), | |
1175 | .class = &omap3xxx_gpio_hwmod_class, | |
1176 | .dev_attr = &gpio_dev_attr, | |
1177 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1178 | }; | |
1179 | ||
1180 | /* gpio6 */ | |
1181 | static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { | |
1182 | { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ | |
1183 | }; | |
1184 | ||
1185 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { | |
1186 | { .role = "dbclk", .clk = "gpio6_dbck", }, | |
1187 | }; | |
1188 | ||
1189 | static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = { | |
1190 | &omap3xxx_l4_per__gpio6, | |
1191 | }; | |
1192 | ||
1193 | static struct omap_hwmod omap3xxx_gpio6_hwmod = { | |
1194 | .name = "gpio6", | |
1195 | .mpu_irqs = omap3xxx_gpio6_irqs, | |
1196 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs), | |
1197 | .main_clk = "gpio6_ick", | |
1198 | .opt_clks = gpio6_opt_clks, | |
1199 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
1200 | .prcm = { | |
1201 | .omap2 = { | |
1202 | .prcm_reg_id = 1, | |
1203 | .module_bit = OMAP3430_EN_GPIO6_SHIFT, | |
1204 | .module_offs = OMAP3430_PER_MOD, | |
1205 | .idlest_reg_id = 1, | |
1206 | .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, | |
1207 | }, | |
1208 | }, | |
1209 | .slaves = omap3xxx_gpio6_slaves, | |
1210 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves), | |
1211 | .class = &omap3xxx_gpio_hwmod_class, | |
1212 | .dev_attr = &gpio_dev_attr, | |
1213 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1214 | }; | |
1215 | ||
01438ab6 MK |
1216 | /* dma_system -> L3 */ |
1217 | static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { | |
1218 | .master = &omap3xxx_dma_system_hwmod, | |
1219 | .slave = &omap3xxx_l3_main_hwmod, | |
1220 | .clk = "core_l3_ick", | |
1221 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1222 | }; | |
1223 | ||
1224 | /* dma attributes */ | |
1225 | static struct omap_dma_dev_attr dma_dev_attr = { | |
1226 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
1227 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
1228 | .lch_count = 32, | |
1229 | }; | |
1230 | ||
1231 | static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { | |
1232 | .rev_offs = 0x0000, | |
1233 | .sysc_offs = 0x002c, | |
1234 | .syss_offs = 0x0028, | |
1235 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1236 | SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
1237 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), | |
1238 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1239 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1240 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1241 | }; | |
1242 | ||
1243 | static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { | |
1244 | .name = "dma", | |
1245 | .sysc = &omap3xxx_dma_sysc, | |
1246 | }; | |
1247 | ||
1248 | /* dma_system */ | |
1249 | static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = { | |
1250 | { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ | |
1251 | { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ | |
1252 | { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ | |
1253 | { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ | |
1254 | }; | |
1255 | ||
1256 | static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { | |
1257 | { | |
1258 | .pa_start = 0x48056000, | |
1259 | .pa_end = 0x4a0560ff, | |
1260 | .flags = ADDR_TYPE_RT | |
1261 | }, | |
1262 | }; | |
1263 | ||
1264 | /* dma_system master ports */ | |
1265 | static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = { | |
1266 | &omap3xxx_dma_system__l3, | |
1267 | }; | |
1268 | ||
1269 | /* l4_cfg -> dma_system */ | |
1270 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { | |
1271 | .master = &omap3xxx_l4_core_hwmod, | |
1272 | .slave = &omap3xxx_dma_system_hwmod, | |
1273 | .clk = "core_l4_ick", | |
1274 | .addr = omap3xxx_dma_system_addrs, | |
1275 | .addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs), | |
1276 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1277 | }; | |
1278 | ||
1279 | /* dma_system slave ports */ | |
1280 | static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = { | |
1281 | &omap3xxx_l4_core__dma_system, | |
1282 | }; | |
1283 | ||
1284 | static struct omap_hwmod omap3xxx_dma_system_hwmod = { | |
1285 | .name = "dma", | |
1286 | .class = &omap3xxx_dma_hwmod_class, | |
1287 | .mpu_irqs = omap3xxx_dma_system_irqs, | |
1288 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs), | |
1289 | .main_clk = "core_l3_ick", | |
1290 | .prcm = { | |
1291 | .omap2 = { | |
1292 | .module_offs = CORE_MOD, | |
1293 | .prcm_reg_id = 1, | |
1294 | .module_bit = OMAP3430_ST_SDMA_SHIFT, | |
1295 | .idlest_reg_id = 1, | |
1296 | .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, | |
1297 | }, | |
1298 | }, | |
1299 | .slaves = omap3xxx_dma_system_slaves, | |
1300 | .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves), | |
1301 | .masters = omap3xxx_dma_system_masters, | |
1302 | .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters), | |
1303 | .dev_attr = &dma_dev_attr, | |
1304 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1305 | .flags = HWMOD_NO_IDLEST, | |
1306 | }; | |
1307 | ||
d3442726 TG |
1308 | /* SR common */ |
1309 | static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { | |
1310 | .clkact_shift = 20, | |
1311 | }; | |
1312 | ||
1313 | static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { | |
1314 | .sysc_offs = 0x24, | |
1315 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), | |
1316 | .clockact = CLOCKACT_TEST_ICLK, | |
1317 | .sysc_fields = &omap34xx_sr_sysc_fields, | |
1318 | }; | |
1319 | ||
1320 | static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { | |
1321 | .name = "smartreflex", | |
1322 | .sysc = &omap34xx_sr_sysc, | |
1323 | .rev = 1, | |
1324 | }; | |
1325 | ||
1326 | static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { | |
1327 | .sidle_shift = 24, | |
1328 | .enwkup_shift = 26 | |
1329 | }; | |
1330 | ||
1331 | static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { | |
1332 | .sysc_offs = 0x38, | |
1333 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1334 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
1335 | SYSC_NO_CACHE), | |
1336 | .sysc_fields = &omap36xx_sr_sysc_fields, | |
1337 | }; | |
1338 | ||
1339 | static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { | |
1340 | .name = "smartreflex", | |
1341 | .sysc = &omap36xx_sr_sysc, | |
1342 | .rev = 2, | |
1343 | }; | |
1344 | ||
1345 | /* SR1 */ | |
1346 | static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = { | |
1347 | &omap3_l4_core__sr1, | |
1348 | }; | |
1349 | ||
1350 | static struct omap_hwmod omap34xx_sr1_hwmod = { | |
1351 | .name = "sr1_hwmod", | |
1352 | .class = &omap34xx_smartreflex_hwmod_class, | |
1353 | .main_clk = "sr1_fck", | |
1354 | .vdd_name = "mpu", | |
1355 | .prcm = { | |
1356 | .omap2 = { | |
1357 | .prcm_reg_id = 1, | |
1358 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
1359 | .module_offs = WKUP_MOD, | |
1360 | .idlest_reg_id = 1, | |
1361 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
1362 | }, | |
1363 | }, | |
1364 | .slaves = omap3_sr1_slaves, | |
1365 | .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), | |
1366 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 | | |
1367 | CHIP_IS_OMAP3430ES3_0 | | |
1368 | CHIP_IS_OMAP3430ES3_1), | |
1369 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
1370 | }; | |
1371 | ||
1372 | static struct omap_hwmod omap36xx_sr1_hwmod = { | |
1373 | .name = "sr1_hwmod", | |
1374 | .class = &omap36xx_smartreflex_hwmod_class, | |
1375 | .main_clk = "sr1_fck", | |
1376 | .vdd_name = "mpu", | |
1377 | .prcm = { | |
1378 | .omap2 = { | |
1379 | .prcm_reg_id = 1, | |
1380 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
1381 | .module_offs = WKUP_MOD, | |
1382 | .idlest_reg_id = 1, | |
1383 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
1384 | }, | |
1385 | }, | |
1386 | .slaves = omap3_sr1_slaves, | |
1387 | .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), | |
1388 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), | |
1389 | }; | |
1390 | ||
1391 | /* SR2 */ | |
1392 | static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = { | |
1393 | &omap3_l4_core__sr2, | |
1394 | }; | |
1395 | ||
1396 | static struct omap_hwmod omap34xx_sr2_hwmod = { | |
1397 | .name = "sr2_hwmod", | |
1398 | .class = &omap34xx_smartreflex_hwmod_class, | |
1399 | .main_clk = "sr2_fck", | |
1400 | .vdd_name = "core", | |
1401 | .prcm = { | |
1402 | .omap2 = { | |
1403 | .prcm_reg_id = 1, | |
1404 | .module_bit = OMAP3430_EN_SR2_SHIFT, | |
1405 | .module_offs = WKUP_MOD, | |
1406 | .idlest_reg_id = 1, | |
1407 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, | |
1408 | }, | |
1409 | }, | |
1410 | .slaves = omap3_sr2_slaves, | |
1411 | .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), | |
1412 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 | | |
1413 | CHIP_IS_OMAP3430ES3_0 | | |
1414 | CHIP_IS_OMAP3430ES3_1), | |
1415 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
1416 | }; | |
1417 | ||
1418 | static struct omap_hwmod omap36xx_sr2_hwmod = { | |
1419 | .name = "sr2_hwmod", | |
1420 | .class = &omap36xx_smartreflex_hwmod_class, | |
1421 | .main_clk = "sr2_fck", | |
1422 | .vdd_name = "core", | |
1423 | .prcm = { | |
1424 | .omap2 = { | |
1425 | .prcm_reg_id = 1, | |
1426 | .module_bit = OMAP3430_EN_SR2_SHIFT, | |
1427 | .module_offs = WKUP_MOD, | |
1428 | .idlest_reg_id = 1, | |
1429 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, | |
1430 | }, | |
1431 | }, | |
1432 | .slaves = omap3_sr2_slaves, | |
1433 | .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), | |
1434 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), | |
1435 | }; | |
1436 | ||
0f616a4e C |
1437 | /* l4 core -> mcspi1 interface */ |
1438 | static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = { | |
1439 | { | |
1440 | .pa_start = 0x48098000, | |
1441 | .pa_end = 0x480980ff, | |
1442 | .flags = ADDR_TYPE_RT, | |
1443 | }, | |
1444 | }; | |
1445 | ||
1446 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { | |
1447 | .master = &omap3xxx_l4_core_hwmod, | |
1448 | .slave = &omap34xx_mcspi1, | |
1449 | .clk = "mcspi1_ick", | |
1450 | .addr = omap34xx_mcspi1_addr_space, | |
1451 | .addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space), | |
1452 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1453 | }; | |
1454 | ||
1455 | /* l4 core -> mcspi2 interface */ | |
1456 | static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = { | |
1457 | { | |
1458 | .pa_start = 0x4809a000, | |
1459 | .pa_end = 0x4809a0ff, | |
1460 | .flags = ADDR_TYPE_RT, | |
1461 | }, | |
1462 | }; | |
1463 | ||
1464 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { | |
1465 | .master = &omap3xxx_l4_core_hwmod, | |
1466 | .slave = &omap34xx_mcspi2, | |
1467 | .clk = "mcspi2_ick", | |
1468 | .addr = omap34xx_mcspi2_addr_space, | |
1469 | .addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space), | |
1470 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1471 | }; | |
1472 | ||
1473 | /* l4 core -> mcspi3 interface */ | |
1474 | static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = { | |
1475 | { | |
1476 | .pa_start = 0x480b8000, | |
1477 | .pa_end = 0x480b80ff, | |
1478 | .flags = ADDR_TYPE_RT, | |
1479 | }, | |
1480 | }; | |
1481 | ||
1482 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { | |
1483 | .master = &omap3xxx_l4_core_hwmod, | |
1484 | .slave = &omap34xx_mcspi3, | |
1485 | .clk = "mcspi3_ick", | |
1486 | .addr = omap34xx_mcspi3_addr_space, | |
1487 | .addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space), | |
1488 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1489 | }; | |
1490 | ||
1491 | /* l4 core -> mcspi4 interface */ | |
1492 | static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { | |
1493 | { | |
1494 | .pa_start = 0x480ba000, | |
1495 | .pa_end = 0x480ba0ff, | |
1496 | .flags = ADDR_TYPE_RT, | |
1497 | }, | |
1498 | }; | |
1499 | ||
1500 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { | |
1501 | .master = &omap3xxx_l4_core_hwmod, | |
1502 | .slave = &omap34xx_mcspi4, | |
1503 | .clk = "mcspi4_ick", | |
1504 | .addr = omap34xx_mcspi4_addr_space, | |
1505 | .addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space), | |
1506 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1507 | }; | |
1508 | ||
1509 | /* | |
1510 | * 'mcspi' class | |
1511 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
1512 | * bus | |
1513 | */ | |
1514 | ||
1515 | static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { | |
1516 | .rev_offs = 0x0000, | |
1517 | .sysc_offs = 0x0010, | |
1518 | .syss_offs = 0x0014, | |
1519 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1520 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1521 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1522 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1523 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1524 | }; | |
1525 | ||
1526 | static struct omap_hwmod_class omap34xx_mcspi_class = { | |
1527 | .name = "mcspi", | |
1528 | .sysc = &omap34xx_mcspi_sysc, | |
1529 | .rev = OMAP3_MCSPI_REV, | |
1530 | }; | |
1531 | ||
1532 | /* mcspi1 */ | |
1533 | static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = { | |
1534 | { .name = "irq", .irq = 65 }, | |
1535 | }; | |
1536 | ||
1537 | static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = { | |
1538 | { .name = "tx0", .dma_req = 35 }, | |
1539 | { .name = "rx0", .dma_req = 36 }, | |
1540 | { .name = "tx1", .dma_req = 37 }, | |
1541 | { .name = "rx1", .dma_req = 38 }, | |
1542 | { .name = "tx2", .dma_req = 39 }, | |
1543 | { .name = "rx2", .dma_req = 40 }, | |
1544 | { .name = "tx3", .dma_req = 41 }, | |
1545 | { .name = "rx3", .dma_req = 42 }, | |
1546 | }; | |
1547 | ||
1548 | static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = { | |
1549 | &omap34xx_l4_core__mcspi1, | |
1550 | }; | |
1551 | ||
1552 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { | |
1553 | .num_chipselect = 4, | |
1554 | }; | |
1555 | ||
1556 | static struct omap_hwmod omap34xx_mcspi1 = { | |
1557 | .name = "mcspi1", | |
1558 | .mpu_irqs = omap34xx_mcspi1_mpu_irqs, | |
1559 | .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs), | |
1560 | .sdma_reqs = omap34xx_mcspi1_sdma_reqs, | |
1561 | .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs), | |
1562 | .main_clk = "mcspi1_fck", | |
1563 | .prcm = { | |
1564 | .omap2 = { | |
1565 | .module_offs = CORE_MOD, | |
1566 | .prcm_reg_id = 1, | |
1567 | .module_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
1568 | .idlest_reg_id = 1, | |
1569 | .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, | |
1570 | }, | |
1571 | }, | |
1572 | .slaves = omap34xx_mcspi1_slaves, | |
1573 | .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves), | |
1574 | .class = &omap34xx_mcspi_class, | |
1575 | .dev_attr = &omap_mcspi1_dev_attr, | |
1576 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1577 | }; | |
1578 | ||
1579 | /* mcspi2 */ | |
1580 | static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = { | |
1581 | { .name = "irq", .irq = 66 }, | |
1582 | }; | |
1583 | ||
1584 | static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = { | |
1585 | { .name = "tx0", .dma_req = 43 }, | |
1586 | { .name = "rx0", .dma_req = 44 }, | |
1587 | { .name = "tx1", .dma_req = 45 }, | |
1588 | { .name = "rx1", .dma_req = 46 }, | |
1589 | }; | |
1590 | ||
1591 | static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = { | |
1592 | &omap34xx_l4_core__mcspi2, | |
1593 | }; | |
1594 | ||
1595 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { | |
1596 | .num_chipselect = 2, | |
1597 | }; | |
1598 | ||
1599 | static struct omap_hwmod omap34xx_mcspi2 = { | |
1600 | .name = "mcspi2", | |
1601 | .mpu_irqs = omap34xx_mcspi2_mpu_irqs, | |
1602 | .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs), | |
1603 | .sdma_reqs = omap34xx_mcspi2_sdma_reqs, | |
1604 | .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs), | |
1605 | .main_clk = "mcspi2_fck", | |
1606 | .prcm = { | |
1607 | .omap2 = { | |
1608 | .module_offs = CORE_MOD, | |
1609 | .prcm_reg_id = 1, | |
1610 | .module_bit = OMAP3430_EN_MCSPI2_SHIFT, | |
1611 | .idlest_reg_id = 1, | |
1612 | .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, | |
1613 | }, | |
1614 | }, | |
1615 | .slaves = omap34xx_mcspi2_slaves, | |
1616 | .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves), | |
1617 | .class = &omap34xx_mcspi_class, | |
1618 | .dev_attr = &omap_mcspi2_dev_attr, | |
1619 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1620 | }; | |
1621 | ||
1622 | /* mcspi3 */ | |
1623 | static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { | |
1624 | { .name = "irq", .irq = 91 }, /* 91 */ | |
1625 | }; | |
1626 | ||
1627 | static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { | |
1628 | { .name = "tx0", .dma_req = 15 }, | |
1629 | { .name = "rx0", .dma_req = 16 }, | |
1630 | { .name = "tx1", .dma_req = 23 }, | |
1631 | { .name = "rx1", .dma_req = 24 }, | |
1632 | }; | |
1633 | ||
1634 | static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = { | |
1635 | &omap34xx_l4_core__mcspi3, | |
1636 | }; | |
1637 | ||
1638 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { | |
1639 | .num_chipselect = 2, | |
1640 | }; | |
1641 | ||
1642 | static struct omap_hwmod omap34xx_mcspi3 = { | |
1643 | .name = "mcspi3", | |
1644 | .mpu_irqs = omap34xx_mcspi3_mpu_irqs, | |
1645 | .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs), | |
1646 | .sdma_reqs = omap34xx_mcspi3_sdma_reqs, | |
1647 | .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs), | |
1648 | .main_clk = "mcspi3_fck", | |
1649 | .prcm = { | |
1650 | .omap2 = { | |
1651 | .module_offs = CORE_MOD, | |
1652 | .prcm_reg_id = 1, | |
1653 | .module_bit = OMAP3430_EN_MCSPI3_SHIFT, | |
1654 | .idlest_reg_id = 1, | |
1655 | .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, | |
1656 | }, | |
1657 | }, | |
1658 | .slaves = omap34xx_mcspi3_slaves, | |
1659 | .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves), | |
1660 | .class = &omap34xx_mcspi_class, | |
1661 | .dev_attr = &omap_mcspi3_dev_attr, | |
1662 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1663 | }; | |
1664 | ||
1665 | /* SPI4 */ | |
1666 | static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { | |
1667 | { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ | |
1668 | }; | |
1669 | ||
1670 | static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { | |
1671 | { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ | |
1672 | { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ | |
1673 | }; | |
1674 | ||
1675 | static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = { | |
1676 | &omap34xx_l4_core__mcspi4, | |
1677 | }; | |
1678 | ||
1679 | static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { | |
1680 | .num_chipselect = 1, | |
1681 | }; | |
1682 | ||
1683 | static struct omap_hwmod omap34xx_mcspi4 = { | |
1684 | .name = "mcspi4", | |
1685 | .mpu_irqs = omap34xx_mcspi4_mpu_irqs, | |
1686 | .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs), | |
1687 | .sdma_reqs = omap34xx_mcspi4_sdma_reqs, | |
1688 | .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs), | |
1689 | .main_clk = "mcspi4_fck", | |
1690 | .prcm = { | |
1691 | .omap2 = { | |
1692 | .module_offs = CORE_MOD, | |
1693 | .prcm_reg_id = 1, | |
1694 | .module_bit = OMAP3430_EN_MCSPI4_SHIFT, | |
1695 | .idlest_reg_id = 1, | |
1696 | .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, | |
1697 | }, | |
1698 | }, | |
1699 | .slaves = omap34xx_mcspi4_slaves, | |
1700 | .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves), | |
1701 | .class = &omap34xx_mcspi_class, | |
1702 | .dev_attr = &omap_mcspi4_dev_attr, | |
1703 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1704 | }; | |
1705 | ||
870ea2b8 HH |
1706 | /* |
1707 | * usbhsotg | |
1708 | */ | |
1709 | static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { | |
1710 | .rev_offs = 0x0400, | |
1711 | .sysc_offs = 0x0404, | |
1712 | .syss_offs = 0x0408, | |
1713 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| | |
1714 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1715 | SYSC_HAS_AUTOIDLE), | |
1716 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1717 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1718 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1719 | }; | |
1720 | ||
1721 | static struct omap_hwmod_class usbotg_class = { | |
1722 | .name = "usbotg", | |
1723 | .sysc = &omap3xxx_usbhsotg_sysc, | |
1724 | }; | |
870ea2b8 HH |
1725 | /* usb_otg_hs */ |
1726 | static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { | |
1727 | ||
1728 | { .name = "mc", .irq = 92 }, | |
1729 | { .name = "dma", .irq = 93 }, | |
1730 | }; | |
1731 | ||
1732 | static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { | |
1733 | .name = "usb_otg_hs", | |
1734 | .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, | |
1735 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs), | |
1736 | .main_clk = "hsotgusb_ick", | |
1737 | .prcm = { | |
1738 | .omap2 = { | |
1739 | .prcm_reg_id = 1, | |
1740 | .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, | |
1741 | .module_offs = CORE_MOD, | |
1742 | .idlest_reg_id = 1, | |
1743 | .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, | |
1744 | .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT | |
1745 | }, | |
1746 | }, | |
1747 | .masters = omap3xxx_usbhsotg_masters, | |
1748 | .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters), | |
1749 | .slaves = omap3xxx_usbhsotg_slaves, | |
1750 | .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves), | |
1751 | .class = &usbotg_class, | |
1752 | ||
1753 | /* | |
1754 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially | |
1755 | * broken when autoidle is enabled | |
1756 | * workaround is to disable the autoidle bit at module level. | |
1757 | */ | |
1758 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | |
1759 | | HWMOD_SWSUP_MSTANDBY, | |
1760 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
1761 | }; | |
04aa67de | 1762 | |
273ff8c3 HH |
1763 | /* usb_otg_hs */ |
1764 | static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { | |
1765 | ||
1766 | { .name = "mc", .irq = 71 }, | |
1767 | }; | |
1768 | ||
1769 | static struct omap_hwmod_class am35xx_usbotg_class = { | |
1770 | .name = "am35xx_usbotg", | |
1771 | .sysc = NULL, | |
1772 | }; | |
1773 | ||
1774 | static struct omap_hwmod am35xx_usbhsotg_hwmod = { | |
1775 | .name = "am35x_otg_hs", | |
1776 | .mpu_irqs = am35xx_usbhsotg_mpu_irqs, | |
1777 | .mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs), | |
1778 | .main_clk = NULL, | |
1779 | .prcm = { | |
1780 | .omap2 = { | |
1781 | }, | |
1782 | }, | |
1783 | .masters = am35xx_usbhsotg_masters, | |
1784 | .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters), | |
1785 | .slaves = am35xx_usbhsotg_slaves, | |
1786 | .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves), | |
1787 | .class = &am35xx_usbotg_class, | |
1788 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1) | |
1789 | }; | |
870ea2b8 | 1790 | |
7359154e | 1791 | static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { |
4a7cf90a | 1792 | &omap3xxx_l3_main_hwmod, |
7359154e PW |
1793 | &omap3xxx_l4_core_hwmod, |
1794 | &omap3xxx_l4_per_hwmod, | |
1795 | &omap3xxx_l4_wkup_hwmod, | |
1796 | &omap3xxx_mpu_hwmod, | |
540064bf | 1797 | &omap3xxx_iva_hwmod, |
6b667f88 | 1798 | &omap3xxx_wd_timer2_hwmod, |
046465b7 KH |
1799 | &omap3xxx_uart1_hwmod, |
1800 | &omap3xxx_uart2_hwmod, | |
1801 | &omap3xxx_uart3_hwmod, | |
1802 | &omap3xxx_uart4_hwmod, | |
4fe20e97 RN |
1803 | &omap3xxx_i2c1_hwmod, |
1804 | &omap3xxx_i2c2_hwmod, | |
1805 | &omap3xxx_i2c3_hwmod, | |
d3442726 TG |
1806 | &omap34xx_sr1_hwmod, |
1807 | &omap34xx_sr2_hwmod, | |
1808 | &omap36xx_sr1_hwmod, | |
1809 | &omap36xx_sr2_hwmod, | |
1810 | ||
70034d38 VC |
1811 | |
1812 | /* gpio class */ | |
1813 | &omap3xxx_gpio1_hwmod, | |
1814 | &omap3xxx_gpio2_hwmod, | |
1815 | &omap3xxx_gpio3_hwmod, | |
1816 | &omap3xxx_gpio4_hwmod, | |
1817 | &omap3xxx_gpio5_hwmod, | |
1818 | &omap3xxx_gpio6_hwmod, | |
01438ab6 MK |
1819 | |
1820 | /* dma_system class*/ | |
1821 | &omap3xxx_dma_system_hwmod, | |
0f616a4e C |
1822 | |
1823 | /* mcspi class */ | |
1824 | &omap34xx_mcspi1, | |
1825 | &omap34xx_mcspi2, | |
1826 | &omap34xx_mcspi3, | |
1827 | &omap34xx_mcspi4, | |
04aa67de | 1828 | |
870ea2b8 HH |
1829 | /* usbotg class */ |
1830 | &omap3xxx_usbhsotg_hwmod, | |
1831 | ||
273ff8c3 HH |
1832 | /* usbotg for am35x */ |
1833 | &am35xx_usbhsotg_hwmod, | |
1834 | ||
7359154e PW |
1835 | NULL, |
1836 | }; | |
1837 | ||
1838 | int __init omap3xxx_hwmod_init(void) | |
1839 | { | |
1840 | return omap_hwmod_init(omap3xxx_hwmods); | |
1841 | } |