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55d2cb08 BC |
1 | /* |
2 | * Hardware modules present on the OMAP44xx chips | |
3 | * | |
0a78c5c5 | 4 | * Copyright (C) 2009-2012 Texas Instruments, Inc. |
55d2cb08 BC |
5 | * Copyright (C) 2009-2010 Nokia Corporation |
6 | * | |
7 | * Paul Walmsley | |
8 | * Benoit Cousson | |
9 | * | |
10 | * This file is automatically generated from the OMAP hardware databases. | |
11 | * We respectfully ask that any modifications to this file be coordinated | |
12 | * with the public linux-omap@vger.kernel.org mailing list and the | |
13 | * authors above to ensure that the autogeneration scripts are kept | |
14 | * up-to-date with the file contents. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/io.h> | |
b86aeafc | 22 | #include <linux/power/smartreflex.h> |
55d2cb08 BC |
23 | |
24 | #include <plat/omap_hwmod.h> | |
25 | #include <plat/cpu.h> | |
6d3c55fd | 26 | #include <plat/i2c.h> |
9780a9cf | 27 | #include <plat/gpio.h> |
531ce0d5 | 28 | #include <plat/dma.h> |
905a74d9 | 29 | #include <plat/mcspi.h> |
cb7e9ded | 30 | #include <plat/mcbsp.h> |
6ab8946f | 31 | #include <plat/mmc.h> |
c345c8b0 | 32 | #include <plat/dmtimer.h> |
13662dc5 | 33 | #include <plat/common.h> |
55d2cb08 BC |
34 | |
35 | #include "omap_hwmod_common_data.h" | |
d198b514 PW |
36 | #include "cm1_44xx.h" |
37 | #include "cm2_44xx.h" | |
38 | #include "prm44xx.h" | |
55d2cb08 | 39 | #include "prm-regbits-44xx.h" |
ff2516fb | 40 | #include "wd_timer.h" |
55d2cb08 BC |
41 | |
42 | /* Base offset for all OMAP4 interrupts external to MPUSS */ | |
43 | #define OMAP44XX_IRQ_GIC_START 32 | |
44 | ||
45 | /* Base offset for all OMAP4 dma requests */ | |
844a3b63 | 46 | #define OMAP44XX_DMA_REQ_START 1 |
55d2cb08 BC |
47 | |
48 | /* | |
844a3b63 | 49 | * IP blocks |
55d2cb08 BC |
50 | */ |
51 | ||
42b9e387 PW |
52 | /* |
53 | * 'c2c_target_fw' class | |
54 | * instance(s): c2c_target_fw | |
55 | */ | |
56 | static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = { | |
57 | .name = "c2c_target_fw", | |
58 | }; | |
59 | ||
60 | /* c2c_target_fw */ | |
61 | static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = { | |
62 | .name = "c2c_target_fw", | |
63 | .class = &omap44xx_c2c_target_fw_hwmod_class, | |
64 | .clkdm_name = "d2d_clkdm", | |
65 | .prcm = { | |
66 | .omap4 = { | |
67 | .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET, | |
68 | .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET, | |
69 | }, | |
70 | }, | |
71 | }; | |
72 | ||
55d2cb08 BC |
73 | /* |
74 | * 'dmm' class | |
75 | * instance(s): dmm | |
76 | */ | |
77 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { | |
fe13471c | 78 | .name = "dmm", |
55d2cb08 BC |
79 | }; |
80 | ||
7e69ed97 BC |
81 | /* dmm */ |
82 | static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { | |
83 | { .irq = 113 + OMAP44XX_IRQ_GIC_START }, | |
84 | { .irq = -1 } | |
85 | }; | |
86 | ||
55d2cb08 BC |
87 | static struct omap_hwmod omap44xx_dmm_hwmod = { |
88 | .name = "dmm", | |
89 | .class = &omap44xx_dmm_hwmod_class, | |
a5322c6f | 90 | .clkdm_name = "l3_emif_clkdm", |
844a3b63 | 91 | .mpu_irqs = omap44xx_dmm_irqs, |
d0f0631d BC |
92 | .prcm = { |
93 | .omap4 = { | |
94 | .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, | |
27bb00b5 | 95 | .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, |
d0f0631d BC |
96 | }, |
97 | }, | |
55d2cb08 BC |
98 | }; |
99 | ||
100 | /* | |
101 | * 'emif_fw' class | |
102 | * instance(s): emif_fw | |
103 | */ | |
104 | static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { | |
fe13471c | 105 | .name = "emif_fw", |
55d2cb08 BC |
106 | }; |
107 | ||
7e69ed97 | 108 | /* emif_fw */ |
55d2cb08 BC |
109 | static struct omap_hwmod omap44xx_emif_fw_hwmod = { |
110 | .name = "emif_fw", | |
111 | .class = &omap44xx_emif_fw_hwmod_class, | |
a5322c6f | 112 | .clkdm_name = "l3_emif_clkdm", |
d0f0631d BC |
113 | .prcm = { |
114 | .omap4 = { | |
115 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET, | |
27bb00b5 | 116 | .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET, |
d0f0631d BC |
117 | }, |
118 | }, | |
55d2cb08 BC |
119 | }; |
120 | ||
121 | /* | |
122 | * 'l3' class | |
123 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 | |
124 | */ | |
125 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { | |
fe13471c | 126 | .name = "l3", |
55d2cb08 BC |
127 | }; |
128 | ||
7e69ed97 | 129 | /* l3_instr */ |
55d2cb08 BC |
130 | static struct omap_hwmod omap44xx_l3_instr_hwmod = { |
131 | .name = "l3_instr", | |
132 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 133 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
134 | .prcm = { |
135 | .omap4 = { | |
136 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, | |
27bb00b5 | 137 | .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, |
03fdefe5 | 138 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
139 | }, |
140 | }, | |
55d2cb08 BC |
141 | }; |
142 | ||
7e69ed97 | 143 | /* l3_main_1 */ |
9b4021be BC |
144 | static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = { |
145 | { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START }, | |
146 | { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START }, | |
147 | { .irq = -1 } | |
148 | }; | |
149 | ||
55d2cb08 BC |
150 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { |
151 | .name = "l3_main_1", | |
152 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 153 | .clkdm_name = "l3_1_clkdm", |
7e69ed97 | 154 | .mpu_irqs = omap44xx_l3_main_1_irqs, |
d0f0631d BC |
155 | .prcm = { |
156 | .omap4 = { | |
157 | .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, | |
27bb00b5 | 158 | .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, |
d0f0631d BC |
159 | }, |
160 | }, | |
55d2cb08 BC |
161 | }; |
162 | ||
7e69ed97 | 163 | /* l3_main_2 */ |
55d2cb08 BC |
164 | static struct omap_hwmod omap44xx_l3_main_2_hwmod = { |
165 | .name = "l3_main_2", | |
166 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 167 | .clkdm_name = "l3_2_clkdm", |
d0f0631d BC |
168 | .prcm = { |
169 | .omap4 = { | |
170 | .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET, | |
27bb00b5 | 171 | .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, |
d0f0631d BC |
172 | }, |
173 | }, | |
55d2cb08 BC |
174 | }; |
175 | ||
7e69ed97 | 176 | /* l3_main_3 */ |
55d2cb08 BC |
177 | static struct omap_hwmod omap44xx_l3_main_3_hwmod = { |
178 | .name = "l3_main_3", | |
179 | .class = &omap44xx_l3_hwmod_class, | |
a5322c6f | 180 | .clkdm_name = "l3_instr_clkdm", |
d0f0631d BC |
181 | .prcm = { |
182 | .omap4 = { | |
183 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, | |
27bb00b5 | 184 | .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET, |
03fdefe5 | 185 | .modulemode = MODULEMODE_HWCTRL, |
d0f0631d BC |
186 | }, |
187 | }, | |
55d2cb08 BC |
188 | }; |
189 | ||
190 | /* | |
191 | * 'l4' class | |
192 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup | |
193 | */ | |
194 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { | |
fe13471c | 195 | .name = "l4", |
55d2cb08 BC |
196 | }; |
197 | ||
7e69ed97 | 198 | /* l4_abe */ |
55d2cb08 BC |
199 | static struct omap_hwmod omap44xx_l4_abe_hwmod = { |
200 | .name = "l4_abe", | |
201 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 202 | .clkdm_name = "abe_clkdm", |
d0f0631d BC |
203 | .prcm = { |
204 | .omap4 = { | |
205 | .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, | |
206 | }, | |
207 | }, | |
55d2cb08 BC |
208 | }; |
209 | ||
7e69ed97 | 210 | /* l4_cfg */ |
55d2cb08 BC |
211 | static struct omap_hwmod omap44xx_l4_cfg_hwmod = { |
212 | .name = "l4_cfg", | |
213 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 214 | .clkdm_name = "l4_cfg_clkdm", |
d0f0631d BC |
215 | .prcm = { |
216 | .omap4 = { | |
217 | .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, | |
27bb00b5 | 218 | .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, |
d0f0631d BC |
219 | }, |
220 | }, | |
55d2cb08 BC |
221 | }; |
222 | ||
7e69ed97 | 223 | /* l4_per */ |
55d2cb08 BC |
224 | static struct omap_hwmod omap44xx_l4_per_hwmod = { |
225 | .name = "l4_per", | |
226 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 227 | .clkdm_name = "l4_per_clkdm", |
d0f0631d BC |
228 | .prcm = { |
229 | .omap4 = { | |
230 | .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET, | |
27bb00b5 | 231 | .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, |
d0f0631d BC |
232 | }, |
233 | }, | |
55d2cb08 BC |
234 | }; |
235 | ||
7e69ed97 | 236 | /* l4_wkup */ |
55d2cb08 BC |
237 | static struct omap_hwmod omap44xx_l4_wkup_hwmod = { |
238 | .name = "l4_wkup", | |
239 | .class = &omap44xx_l4_hwmod_class, | |
a5322c6f | 240 | .clkdm_name = "l4_wkup_clkdm", |
d0f0631d BC |
241 | .prcm = { |
242 | .omap4 = { | |
243 | .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, | |
27bb00b5 | 244 | .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, |
d0f0631d BC |
245 | }, |
246 | }, | |
55d2cb08 BC |
247 | }; |
248 | ||
f776471f | 249 | /* |
3b54baad BC |
250 | * 'mpu_bus' class |
251 | * instance(s): mpu_private | |
f776471f | 252 | */ |
3b54baad | 253 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
fe13471c | 254 | .name = "mpu_bus", |
3b54baad | 255 | }; |
f776471f | 256 | |
7e69ed97 | 257 | /* mpu_private */ |
3b54baad BC |
258 | static struct omap_hwmod omap44xx_mpu_private_hwmod = { |
259 | .name = "mpu_private", | |
260 | .class = &omap44xx_mpu_bus_hwmod_class, | |
a5322c6f | 261 | .clkdm_name = "mpuss_clkdm", |
3b54baad BC |
262 | }; |
263 | ||
9a817bc8 BC |
264 | /* |
265 | * 'ocp_wp_noc' class | |
266 | * instance(s): ocp_wp_noc | |
267 | */ | |
268 | static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = { | |
269 | .name = "ocp_wp_noc", | |
270 | }; | |
271 | ||
272 | /* ocp_wp_noc */ | |
273 | static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = { | |
274 | .name = "ocp_wp_noc", | |
275 | .class = &omap44xx_ocp_wp_noc_hwmod_class, | |
276 | .clkdm_name = "l3_instr_clkdm", | |
277 | .prcm = { | |
278 | .omap4 = { | |
279 | .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET, | |
280 | .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET, | |
281 | .modulemode = MODULEMODE_HWCTRL, | |
282 | }, | |
283 | }, | |
284 | }; | |
285 | ||
3b54baad BC |
286 | /* |
287 | * Modules omap_hwmod structures | |
288 | * | |
289 | * The following IPs are excluded for the moment because: | |
290 | * - They do not need an explicit SW control using omap_hwmod API. | |
291 | * - They still need to be validated with the driver | |
292 | * properly adapted to omap_hwmod / omap_device | |
293 | * | |
96566043 | 294 | * usim |
3b54baad BC |
295 | */ |
296 | ||
407a6888 BC |
297 | /* |
298 | * 'aess' class | |
299 | * audio engine sub system | |
300 | */ | |
301 | ||
302 | static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { | |
303 | .rev_offs = 0x0000, | |
304 | .sysc_offs = 0x0010, | |
305 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
306 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
c614ebf6 BC |
307 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART | |
308 | MSTANDBY_SMART_WKUP), | |
407a6888 BC |
309 | .sysc_fields = &omap_hwmod_sysc_type2, |
310 | }; | |
311 | ||
312 | static struct omap_hwmod_class omap44xx_aess_hwmod_class = { | |
313 | .name = "aess", | |
314 | .sysc = &omap44xx_aess_sysc, | |
315 | }; | |
316 | ||
317 | /* aess */ | |
318 | static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { | |
319 | { .irq = 99 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 320 | { .irq = -1 } |
407a6888 BC |
321 | }; |
322 | ||
323 | static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { | |
324 | { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START }, | |
325 | { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START }, | |
326 | { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START }, | |
327 | { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START }, | |
328 | { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START }, | |
329 | { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START }, | |
330 | { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START }, | |
331 | { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 332 | { .dma_req = -1 } |
407a6888 BC |
333 | }; |
334 | ||
407a6888 BC |
335 | static struct omap_hwmod omap44xx_aess_hwmod = { |
336 | .name = "aess", | |
337 | .class = &omap44xx_aess_hwmod_class, | |
a5322c6f | 338 | .clkdm_name = "abe_clkdm", |
407a6888 | 339 | .mpu_irqs = omap44xx_aess_irqs, |
407a6888 | 340 | .sdma_reqs = omap44xx_aess_sdma_reqs, |
407a6888 | 341 | .main_clk = "aess_fck", |
00fe610b | 342 | .prcm = { |
407a6888 | 343 | .omap4 = { |
d0f0631d | 344 | .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, |
27bb00b5 | 345 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
03fdefe5 | 346 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
347 | }, |
348 | }, | |
407a6888 BC |
349 | }; |
350 | ||
42b9e387 PW |
351 | /* |
352 | * 'c2c' class | |
353 | * chip 2 chip interface used to plug the ape soc (omap) with an external modem | |
354 | * soc | |
355 | */ | |
356 | ||
357 | static struct omap_hwmod_class omap44xx_c2c_hwmod_class = { | |
358 | .name = "c2c", | |
359 | }; | |
360 | ||
361 | /* c2c */ | |
362 | static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = { | |
363 | { .irq = 88 + OMAP44XX_IRQ_GIC_START }, | |
364 | { .irq = -1 } | |
365 | }; | |
366 | ||
367 | static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = { | |
368 | { .dma_req = 68 + OMAP44XX_DMA_REQ_START }, | |
369 | { .dma_req = -1 } | |
370 | }; | |
371 | ||
372 | static struct omap_hwmod omap44xx_c2c_hwmod = { | |
373 | .name = "c2c", | |
374 | .class = &omap44xx_c2c_hwmod_class, | |
375 | .clkdm_name = "d2d_clkdm", | |
376 | .mpu_irqs = omap44xx_c2c_irqs, | |
377 | .sdma_reqs = omap44xx_c2c_sdma_reqs, | |
378 | .prcm = { | |
379 | .omap4 = { | |
380 | .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET, | |
381 | .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET, | |
382 | }, | |
383 | }, | |
384 | }; | |
385 | ||
407a6888 BC |
386 | /* |
387 | * 'counter' class | |
388 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
389 | */ | |
390 | ||
391 | static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = { | |
392 | .rev_offs = 0x0000, | |
393 | .sysc_offs = 0x0004, | |
394 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
252a4c54 | 395 | .idlemodes = (SIDLE_FORCE | SIDLE_NO), |
407a6888 BC |
396 | .sysc_fields = &omap_hwmod_sysc_type1, |
397 | }; | |
398 | ||
399 | static struct omap_hwmod_class omap44xx_counter_hwmod_class = { | |
400 | .name = "counter", | |
401 | .sysc = &omap44xx_counter_sysc, | |
402 | }; | |
403 | ||
404 | /* counter_32k */ | |
407a6888 BC |
405 | static struct omap_hwmod omap44xx_counter_32k_hwmod = { |
406 | .name = "counter_32k", | |
407 | .class = &omap44xx_counter_hwmod_class, | |
a5322c6f | 408 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 BC |
409 | .flags = HWMOD_SWSUP_SIDLE, |
410 | .main_clk = "sys_32k_ck", | |
00fe610b | 411 | .prcm = { |
407a6888 | 412 | .omap4 = { |
d0f0631d | 413 | .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, |
27bb00b5 | 414 | .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, |
407a6888 BC |
415 | }, |
416 | }, | |
407a6888 BC |
417 | }; |
418 | ||
a0b5d813 PW |
419 | /* |
420 | * 'ctrl_module' class | |
421 | * attila core control module + core pad control module + wkup pad control | |
422 | * module + attila wkup control module | |
423 | */ | |
424 | ||
425 | static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = { | |
426 | .rev_offs = 0x0000, | |
427 | .sysc_offs = 0x0010, | |
428 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
429 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
430 | SIDLE_SMART_WKUP), | |
431 | .sysc_fields = &omap_hwmod_sysc_type2, | |
432 | }; | |
433 | ||
434 | static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = { | |
435 | .name = "ctrl_module", | |
436 | .sysc = &omap44xx_ctrl_module_sysc, | |
437 | }; | |
438 | ||
439 | /* ctrl_module_core */ | |
440 | static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = { | |
441 | { .irq = 8 + OMAP44XX_IRQ_GIC_START }, | |
442 | { .irq = -1 } | |
443 | }; | |
444 | ||
445 | static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = { | |
446 | .name = "ctrl_module_core", | |
447 | .class = &omap44xx_ctrl_module_hwmod_class, | |
448 | .clkdm_name = "l4_cfg_clkdm", | |
449 | .mpu_irqs = omap44xx_ctrl_module_core_irqs, | |
450 | }; | |
451 | ||
452 | /* ctrl_module_pad_core */ | |
453 | static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = { | |
454 | .name = "ctrl_module_pad_core", | |
455 | .class = &omap44xx_ctrl_module_hwmod_class, | |
456 | .clkdm_name = "l4_cfg_clkdm", | |
457 | }; | |
458 | ||
459 | /* ctrl_module_wkup */ | |
460 | static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = { | |
461 | .name = "ctrl_module_wkup", | |
462 | .class = &omap44xx_ctrl_module_hwmod_class, | |
463 | .clkdm_name = "l4_wkup_clkdm", | |
464 | }; | |
465 | ||
466 | /* ctrl_module_pad_wkup */ | |
467 | static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = { | |
468 | .name = "ctrl_module_pad_wkup", | |
469 | .class = &omap44xx_ctrl_module_hwmod_class, | |
470 | .clkdm_name = "l4_wkup_clkdm", | |
471 | }; | |
472 | ||
96566043 BC |
473 | /* |
474 | * 'debugss' class | |
475 | * debug and emulation sub system | |
476 | */ | |
477 | ||
478 | static struct omap_hwmod_class omap44xx_debugss_hwmod_class = { | |
479 | .name = "debugss", | |
480 | }; | |
481 | ||
482 | /* debugss */ | |
483 | static struct omap_hwmod omap44xx_debugss_hwmod = { | |
484 | .name = "debugss", | |
485 | .class = &omap44xx_debugss_hwmod_class, | |
486 | .clkdm_name = "emu_sys_clkdm", | |
487 | .main_clk = "trace_clk_div_ck", | |
488 | .prcm = { | |
489 | .omap4 = { | |
490 | .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET, | |
491 | .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET, | |
492 | }, | |
493 | }, | |
494 | }; | |
495 | ||
d7cf5f33 BC |
496 | /* |
497 | * 'dma' class | |
498 | * dma controller for data exchange between memory to memory (i.e. internal or | |
499 | * external memory) and gp peripherals to memory or memory to gp peripherals | |
500 | */ | |
501 | ||
502 | static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { | |
503 | .rev_offs = 0x0000, | |
504 | .sysc_offs = 0x002c, | |
505 | .syss_offs = 0x0028, | |
506 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
507 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
508 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
509 | SYSS_HAS_RESET_STATUS), | |
510 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
511 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
512 | .sysc_fields = &omap_hwmod_sysc_type1, | |
513 | }; | |
514 | ||
515 | static struct omap_hwmod_class omap44xx_dma_hwmod_class = { | |
516 | .name = "dma", | |
517 | .sysc = &omap44xx_dma_sysc, | |
518 | }; | |
519 | ||
520 | /* dma dev_attr */ | |
521 | static struct omap_dma_dev_attr dma_dev_attr = { | |
522 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
523 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
524 | .lch_count = 32, | |
525 | }; | |
526 | ||
527 | /* dma_system */ | |
528 | static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { | |
529 | { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, | |
530 | { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, | |
531 | { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, | |
532 | { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 533 | { .irq = -1 } |
d7cf5f33 BC |
534 | }; |
535 | ||
d7cf5f33 BC |
536 | static struct omap_hwmod omap44xx_dma_system_hwmod = { |
537 | .name = "dma_system", | |
538 | .class = &omap44xx_dma_hwmod_class, | |
a5322c6f | 539 | .clkdm_name = "l3_dma_clkdm", |
d7cf5f33 | 540 | .mpu_irqs = omap44xx_dma_system_irqs, |
d7cf5f33 BC |
541 | .main_clk = "l3_div_ck", |
542 | .prcm = { | |
543 | .omap4 = { | |
d0f0631d | 544 | .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, |
27bb00b5 | 545 | .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, |
d7cf5f33 BC |
546 | }, |
547 | }, | |
548 | .dev_attr = &dma_dev_attr, | |
d7cf5f33 BC |
549 | }; |
550 | ||
8ca476da BC |
551 | /* |
552 | * 'dmic' class | |
553 | * digital microphone controller | |
554 | */ | |
555 | ||
556 | static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = { | |
557 | .rev_offs = 0x0000, | |
558 | .sysc_offs = 0x0010, | |
559 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
560 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
561 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
562 | SIDLE_SMART_WKUP), | |
563 | .sysc_fields = &omap_hwmod_sysc_type2, | |
564 | }; | |
565 | ||
566 | static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { | |
567 | .name = "dmic", | |
568 | .sysc = &omap44xx_dmic_sysc, | |
569 | }; | |
570 | ||
571 | /* dmic */ | |
8ca476da BC |
572 | static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { |
573 | { .irq = 114 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 574 | { .irq = -1 } |
8ca476da BC |
575 | }; |
576 | ||
577 | static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { | |
578 | { .dma_req = 66 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 579 | { .dma_req = -1 } |
8ca476da BC |
580 | }; |
581 | ||
8ca476da BC |
582 | static struct omap_hwmod omap44xx_dmic_hwmod = { |
583 | .name = "dmic", | |
584 | .class = &omap44xx_dmic_hwmod_class, | |
a5322c6f | 585 | .clkdm_name = "abe_clkdm", |
8ca476da | 586 | .mpu_irqs = omap44xx_dmic_irqs, |
8ca476da | 587 | .sdma_reqs = omap44xx_dmic_sdma_reqs, |
8ca476da | 588 | .main_clk = "dmic_fck", |
00fe610b | 589 | .prcm = { |
8ca476da | 590 | .omap4 = { |
d0f0631d | 591 | .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, |
27bb00b5 | 592 | .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET, |
03fdefe5 | 593 | .modulemode = MODULEMODE_SWCTRL, |
8ca476da BC |
594 | }, |
595 | }, | |
8ca476da BC |
596 | }; |
597 | ||
8f25bdc5 BC |
598 | /* |
599 | * 'dsp' class | |
600 | * dsp sub-system | |
601 | */ | |
602 | ||
603 | static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { | |
fe13471c | 604 | .name = "dsp", |
8f25bdc5 BC |
605 | }; |
606 | ||
607 | /* dsp */ | |
608 | static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { | |
609 | { .irq = 28 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 610 | { .irq = -1 } |
8f25bdc5 BC |
611 | }; |
612 | ||
613 | static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { | |
8f25bdc5 | 614 | { .name = "dsp", .rst_shift = 0 }, |
f2f5736c | 615 | { .name = "mmu_cache", .rst_shift = 1 }, |
8f25bdc5 BC |
616 | }; |
617 | ||
8f25bdc5 BC |
618 | static struct omap_hwmod omap44xx_dsp_hwmod = { |
619 | .name = "dsp", | |
620 | .class = &omap44xx_dsp_hwmod_class, | |
a5322c6f | 621 | .clkdm_name = "tesla_clkdm", |
8f25bdc5 | 622 | .mpu_irqs = omap44xx_dsp_irqs, |
8f25bdc5 BC |
623 | .rst_lines = omap44xx_dsp_resets, |
624 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), | |
625 | .main_clk = "dsp_fck", | |
626 | .prcm = { | |
627 | .omap4 = { | |
d0f0631d | 628 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, |
eaac329d | 629 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, |
27bb00b5 | 630 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, |
03fdefe5 | 631 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
632 | }, |
633 | }, | |
8f25bdc5 BC |
634 | }; |
635 | ||
d63bd74f BC |
636 | /* |
637 | * 'dss' class | |
638 | * display sub-system | |
639 | */ | |
640 | ||
641 | static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = { | |
642 | .rev_offs = 0x0000, | |
643 | .syss_offs = 0x0014, | |
644 | .sysc_flags = SYSS_HAS_RESET_STATUS, | |
645 | }; | |
646 | ||
647 | static struct omap_hwmod_class omap44xx_dss_hwmod_class = { | |
648 | .name = "dss", | |
649 | .sysc = &omap44xx_dss_sysc, | |
13662dc5 | 650 | .reset = omap_dss_reset, |
d63bd74f BC |
651 | }; |
652 | ||
653 | /* dss */ | |
d63bd74f BC |
654 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { |
655 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
656 | { .role = "tv_clk", .clk = "dss_tv_clk" }, | |
4d0698d9 | 657 | { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, |
d63bd74f BC |
658 | }; |
659 | ||
660 | static struct omap_hwmod omap44xx_dss_hwmod = { | |
661 | .name = "dss_core", | |
37ad0855 | 662 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
d63bd74f | 663 | .class = &omap44xx_dss_hwmod_class, |
a5322c6f | 664 | .clkdm_name = "l3_dss_clkdm", |
da7cdfac | 665 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
666 | .prcm = { |
667 | .omap4 = { | |
d0f0631d | 668 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 669 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
670 | }, |
671 | }, | |
672 | .opt_clks = dss_opt_clks, | |
673 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
d63bd74f BC |
674 | }; |
675 | ||
676 | /* | |
677 | * 'dispc' class | |
678 | * display controller | |
679 | */ | |
680 | ||
681 | static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = { | |
682 | .rev_offs = 0x0000, | |
683 | .sysc_offs = 0x0010, | |
684 | .syss_offs = 0x0014, | |
685 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
686 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | | |
687 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
688 | SYSS_HAS_RESET_STATUS), | |
689 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
690 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
691 | .sysc_fields = &omap_hwmod_sysc_type1, | |
692 | }; | |
693 | ||
694 | static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { | |
695 | .name = "dispc", | |
696 | .sysc = &omap44xx_dispc_sysc, | |
697 | }; | |
698 | ||
699 | /* dss_dispc */ | |
d63bd74f BC |
700 | static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { |
701 | { .irq = 25 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 702 | { .irq = -1 } |
d63bd74f BC |
703 | }; |
704 | ||
705 | static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { | |
706 | { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 707 | { .dma_req = -1 } |
d63bd74f BC |
708 | }; |
709 | ||
b923d40d AT |
710 | static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { |
711 | .manager_count = 3, | |
712 | .has_framedonetv_irq = 1 | |
713 | }; | |
714 | ||
d63bd74f BC |
715 | static struct omap_hwmod omap44xx_dss_dispc_hwmod = { |
716 | .name = "dss_dispc", | |
717 | .class = &omap44xx_dispc_hwmod_class, | |
a5322c6f | 718 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 719 | .mpu_irqs = omap44xx_dss_dispc_irqs, |
d63bd74f | 720 | .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, |
da7cdfac | 721 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
722 | .prcm = { |
723 | .omap4 = { | |
d0f0631d | 724 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 725 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
726 | }, |
727 | }, | |
b923d40d | 728 | .dev_attr = &omap44xx_dss_dispc_dev_attr |
d63bd74f BC |
729 | }; |
730 | ||
731 | /* | |
732 | * 'dsi' class | |
733 | * display serial interface controller | |
734 | */ | |
735 | ||
736 | static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = { | |
737 | .rev_offs = 0x0000, | |
738 | .sysc_offs = 0x0010, | |
739 | .syss_offs = 0x0014, | |
740 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
741 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
742 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
743 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
744 | .sysc_fields = &omap_hwmod_sysc_type1, | |
745 | }; | |
746 | ||
747 | static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { | |
748 | .name = "dsi", | |
749 | .sysc = &omap44xx_dsi_sysc, | |
750 | }; | |
751 | ||
752 | /* dss_dsi1 */ | |
d63bd74f BC |
753 | static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { |
754 | { .irq = 53 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 755 | { .irq = -1 } |
d63bd74f BC |
756 | }; |
757 | ||
758 | static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { | |
759 | { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 760 | { .dma_req = -1 } |
d63bd74f BC |
761 | }; |
762 | ||
3a23aafc TV |
763 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { |
764 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
765 | }; | |
766 | ||
d63bd74f BC |
767 | static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { |
768 | .name = "dss_dsi1", | |
769 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 770 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 771 | .mpu_irqs = omap44xx_dss_dsi1_irqs, |
d63bd74f | 772 | .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, |
da7cdfac | 773 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
774 | .prcm = { |
775 | .omap4 = { | |
d0f0631d | 776 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 777 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
778 | }, |
779 | }, | |
3a23aafc TV |
780 | .opt_clks = dss_dsi1_opt_clks, |
781 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
d63bd74f BC |
782 | }; |
783 | ||
784 | /* dss_dsi2 */ | |
d63bd74f BC |
785 | static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { |
786 | { .irq = 84 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 787 | { .irq = -1 } |
d63bd74f BC |
788 | }; |
789 | ||
790 | static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { | |
791 | { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 792 | { .dma_req = -1 } |
d63bd74f BC |
793 | }; |
794 | ||
3a23aafc TV |
795 | static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { |
796 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
797 | }; | |
798 | ||
d63bd74f BC |
799 | static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { |
800 | .name = "dss_dsi2", | |
801 | .class = &omap44xx_dsi_hwmod_class, | |
a5322c6f | 802 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 803 | .mpu_irqs = omap44xx_dss_dsi2_irqs, |
d63bd74f | 804 | .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, |
da7cdfac | 805 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
806 | .prcm = { |
807 | .omap4 = { | |
d0f0631d | 808 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 809 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
810 | }, |
811 | }, | |
3a23aafc TV |
812 | .opt_clks = dss_dsi2_opt_clks, |
813 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), | |
d63bd74f BC |
814 | }; |
815 | ||
816 | /* | |
817 | * 'hdmi' class | |
818 | * hdmi controller | |
819 | */ | |
820 | ||
821 | static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = { | |
822 | .rev_offs = 0x0000, | |
823 | .sysc_offs = 0x0010, | |
824 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
825 | SYSC_HAS_SOFTRESET), | |
826 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
827 | SIDLE_SMART_WKUP), | |
828 | .sysc_fields = &omap_hwmod_sysc_type2, | |
829 | }; | |
830 | ||
831 | static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { | |
832 | .name = "hdmi", | |
833 | .sysc = &omap44xx_hdmi_sysc, | |
834 | }; | |
835 | ||
836 | /* dss_hdmi */ | |
d63bd74f BC |
837 | static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { |
838 | { .irq = 101 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 839 | { .irq = -1 } |
d63bd74f BC |
840 | }; |
841 | ||
842 | static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { | |
843 | { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 844 | { .dma_req = -1 } |
d63bd74f BC |
845 | }; |
846 | ||
3a23aafc TV |
847 | static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { |
848 | { .role = "sys_clk", .clk = "dss_sys_clk" }, | |
849 | }; | |
850 | ||
d63bd74f BC |
851 | static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { |
852 | .name = "dss_hdmi", | |
853 | .class = &omap44xx_hdmi_hwmod_class, | |
a5322c6f | 854 | .clkdm_name = "l3_dss_clkdm", |
dc57aef5 RN |
855 | /* |
856 | * HDMI audio requires to use no-idle mode. Hence, | |
857 | * set idle mode by software. | |
858 | */ | |
859 | .flags = HWMOD_SWSUP_SIDLE, | |
d63bd74f | 860 | .mpu_irqs = omap44xx_dss_hdmi_irqs, |
d63bd74f | 861 | .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, |
4d0698d9 | 862 | .main_clk = "dss_48mhz_clk", |
d63bd74f BC |
863 | .prcm = { |
864 | .omap4 = { | |
d0f0631d | 865 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 866 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
867 | }, |
868 | }, | |
3a23aafc TV |
869 | .opt_clks = dss_hdmi_opt_clks, |
870 | .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), | |
d63bd74f BC |
871 | }; |
872 | ||
873 | /* | |
874 | * 'rfbi' class | |
875 | * remote frame buffer interface | |
876 | */ | |
877 | ||
878 | static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = { | |
879 | .rev_offs = 0x0000, | |
880 | .sysc_offs = 0x0010, | |
881 | .syss_offs = 0x0014, | |
882 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
883 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
884 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
885 | .sysc_fields = &omap_hwmod_sysc_type1, | |
886 | }; | |
887 | ||
888 | static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { | |
889 | .name = "rfbi", | |
890 | .sysc = &omap44xx_rfbi_sysc, | |
891 | }; | |
892 | ||
893 | /* dss_rfbi */ | |
d63bd74f BC |
894 | static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { |
895 | { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 896 | { .dma_req = -1 } |
d63bd74f BC |
897 | }; |
898 | ||
3a23aafc TV |
899 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
900 | { .role = "ick", .clk = "dss_fck" }, | |
901 | }; | |
902 | ||
d63bd74f BC |
903 | static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { |
904 | .name = "dss_rfbi", | |
905 | .class = &omap44xx_rfbi_hwmod_class, | |
a5322c6f | 906 | .clkdm_name = "l3_dss_clkdm", |
d63bd74f | 907 | .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, |
da7cdfac | 908 | .main_clk = "dss_dss_clk", |
d63bd74f BC |
909 | .prcm = { |
910 | .omap4 = { | |
d0f0631d | 911 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 912 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
913 | }, |
914 | }, | |
3a23aafc TV |
915 | .opt_clks = dss_rfbi_opt_clks, |
916 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
d63bd74f BC |
917 | }; |
918 | ||
919 | /* | |
920 | * 'venc' class | |
921 | * video encoder | |
922 | */ | |
923 | ||
924 | static struct omap_hwmod_class omap44xx_venc_hwmod_class = { | |
925 | .name = "venc", | |
926 | }; | |
927 | ||
928 | /* dss_venc */ | |
d63bd74f BC |
929 | static struct omap_hwmod omap44xx_dss_venc_hwmod = { |
930 | .name = "dss_venc", | |
931 | .class = &omap44xx_venc_hwmod_class, | |
a5322c6f | 932 | .clkdm_name = "l3_dss_clkdm", |
4d0698d9 | 933 | .main_clk = "dss_tv_clk", |
d63bd74f BC |
934 | .prcm = { |
935 | .omap4 = { | |
d0f0631d | 936 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
27bb00b5 | 937 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
d63bd74f BC |
938 | }, |
939 | }, | |
d63bd74f BC |
940 | }; |
941 | ||
42b9e387 PW |
942 | /* |
943 | * 'elm' class | |
944 | * bch error location module | |
945 | */ | |
946 | ||
947 | static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = { | |
948 | .rev_offs = 0x0000, | |
949 | .sysc_offs = 0x0010, | |
950 | .syss_offs = 0x0014, | |
951 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
952 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
953 | SYSS_HAS_RESET_STATUS), | |
954 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
955 | .sysc_fields = &omap_hwmod_sysc_type1, | |
956 | }; | |
957 | ||
958 | static struct omap_hwmod_class omap44xx_elm_hwmod_class = { | |
959 | .name = "elm", | |
960 | .sysc = &omap44xx_elm_sysc, | |
961 | }; | |
962 | ||
963 | /* elm */ | |
964 | static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = { | |
965 | { .irq = 4 + OMAP44XX_IRQ_GIC_START }, | |
966 | { .irq = -1 } | |
967 | }; | |
968 | ||
969 | static struct omap_hwmod omap44xx_elm_hwmod = { | |
970 | .name = "elm", | |
971 | .class = &omap44xx_elm_hwmod_class, | |
972 | .clkdm_name = "l4_per_clkdm", | |
973 | .mpu_irqs = omap44xx_elm_irqs, | |
974 | .prcm = { | |
975 | .omap4 = { | |
976 | .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET, | |
977 | .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET, | |
978 | }, | |
979 | }, | |
980 | }; | |
981 | ||
bf30f950 PW |
982 | /* |
983 | * 'emif' class | |
984 | * external memory interface no1 | |
985 | */ | |
986 | ||
987 | static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = { | |
988 | .rev_offs = 0x0000, | |
989 | }; | |
990 | ||
991 | static struct omap_hwmod_class omap44xx_emif_hwmod_class = { | |
992 | .name = "emif", | |
993 | .sysc = &omap44xx_emif_sysc, | |
994 | }; | |
995 | ||
996 | /* emif1 */ | |
997 | static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = { | |
998 | { .irq = 110 + OMAP44XX_IRQ_GIC_START }, | |
999 | { .irq = -1 } | |
1000 | }; | |
1001 | ||
1002 | static struct omap_hwmod omap44xx_emif1_hwmod = { | |
1003 | .name = "emif1", | |
1004 | .class = &omap44xx_emif_hwmod_class, | |
1005 | .clkdm_name = "l3_emif_clkdm", | |
1006 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | |
1007 | .mpu_irqs = omap44xx_emif1_irqs, | |
1008 | .main_clk = "ddrphy_ck", | |
1009 | .prcm = { | |
1010 | .omap4 = { | |
1011 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET, | |
1012 | .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET, | |
1013 | .modulemode = MODULEMODE_HWCTRL, | |
1014 | }, | |
1015 | }, | |
1016 | }; | |
1017 | ||
1018 | /* emif2 */ | |
1019 | static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = { | |
1020 | { .irq = 111 + OMAP44XX_IRQ_GIC_START }, | |
1021 | { .irq = -1 } | |
1022 | }; | |
1023 | ||
1024 | static struct omap_hwmod omap44xx_emif2_hwmod = { | |
1025 | .name = "emif2", | |
1026 | .class = &omap44xx_emif_hwmod_class, | |
1027 | .clkdm_name = "l3_emif_clkdm", | |
1028 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | |
1029 | .mpu_irqs = omap44xx_emif2_irqs, | |
1030 | .main_clk = "ddrphy_ck", | |
1031 | .prcm = { | |
1032 | .omap4 = { | |
1033 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET, | |
1034 | .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET, | |
1035 | .modulemode = MODULEMODE_HWCTRL, | |
1036 | }, | |
1037 | }, | |
1038 | }; | |
1039 | ||
b050f688 ML |
1040 | /* |
1041 | * 'fdif' class | |
1042 | * face detection hw accelerator module | |
1043 | */ | |
1044 | ||
1045 | static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = { | |
1046 | .rev_offs = 0x0000, | |
1047 | .sysc_offs = 0x0010, | |
1048 | /* | |
1049 | * FDIF needs 100 OCP clk cycles delay after a softreset before | |
1050 | * accessing sysconfig again. | |
1051 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
1052 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
1053 | * | |
1054 | * TODO: Indicate errata when available. | |
1055 | */ | |
1056 | .srst_udelay = 2, | |
1057 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | | |
1058 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1059 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1060 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1061 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1062 | }; | |
1063 | ||
1064 | static struct omap_hwmod_class omap44xx_fdif_hwmod_class = { | |
1065 | .name = "fdif", | |
1066 | .sysc = &omap44xx_fdif_sysc, | |
1067 | }; | |
1068 | ||
1069 | /* fdif */ | |
1070 | static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = { | |
1071 | { .irq = 69 + OMAP44XX_IRQ_GIC_START }, | |
1072 | { .irq = -1 } | |
1073 | }; | |
1074 | ||
1075 | static struct omap_hwmod omap44xx_fdif_hwmod = { | |
1076 | .name = "fdif", | |
1077 | .class = &omap44xx_fdif_hwmod_class, | |
1078 | .clkdm_name = "iss_clkdm", | |
1079 | .mpu_irqs = omap44xx_fdif_irqs, | |
1080 | .main_clk = "fdif_fck", | |
1081 | .prcm = { | |
1082 | .omap4 = { | |
1083 | .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET, | |
1084 | .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET, | |
1085 | .modulemode = MODULEMODE_SWCTRL, | |
1086 | }, | |
1087 | }, | |
1088 | }; | |
1089 | ||
3b54baad BC |
1090 | /* |
1091 | * 'gpio' class | |
1092 | * general purpose io module | |
1093 | */ | |
1094 | ||
1095 | static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { | |
1096 | .rev_offs = 0x0000, | |
f776471f | 1097 | .sysc_offs = 0x0010, |
3b54baad | 1098 | .syss_offs = 0x0114, |
0cfe8751 BC |
1099 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
1100 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1101 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
1102 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1103 | SIDLE_SMART_WKUP), | |
f776471f BC |
1104 | .sysc_fields = &omap_hwmod_sysc_type1, |
1105 | }; | |
1106 | ||
3b54baad | 1107 | static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { |
fe13471c BC |
1108 | .name = "gpio", |
1109 | .sysc = &omap44xx_gpio_sysc, | |
1110 | .rev = 2, | |
f776471f BC |
1111 | }; |
1112 | ||
3b54baad BC |
1113 | /* gpio dev_attr */ |
1114 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
fe13471c BC |
1115 | .bank_width = 32, |
1116 | .dbck_flag = true, | |
f776471f BC |
1117 | }; |
1118 | ||
3b54baad | 1119 | /* gpio1 */ |
3b54baad BC |
1120 | static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { |
1121 | { .irq = 29 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1122 | { .irq = -1 } |
f776471f BC |
1123 | }; |
1124 | ||
3b54baad | 1125 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
b399bca8 | 1126 | { .role = "dbclk", .clk = "gpio1_dbclk" }, |
3b54baad BC |
1127 | }; |
1128 | ||
1129 | static struct omap_hwmod omap44xx_gpio1_hwmod = { | |
1130 | .name = "gpio1", | |
1131 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1132 | .clkdm_name = "l4_wkup_clkdm", |
3b54baad | 1133 | .mpu_irqs = omap44xx_gpio1_irqs, |
3b54baad | 1134 | .main_clk = "gpio1_ick", |
f776471f BC |
1135 | .prcm = { |
1136 | .omap4 = { | |
d0f0631d | 1137 | .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, |
27bb00b5 | 1138 | .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET, |
03fdefe5 | 1139 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1140 | }, |
1141 | }, | |
3b54baad BC |
1142 | .opt_clks = gpio1_opt_clks, |
1143 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
1144 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1145 | }; |
1146 | ||
3b54baad | 1147 | /* gpio2 */ |
3b54baad BC |
1148 | static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { |
1149 | { .irq = 30 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1150 | { .irq = -1 } |
f776471f BC |
1151 | }; |
1152 | ||
3b54baad | 1153 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
b399bca8 | 1154 | { .role = "dbclk", .clk = "gpio2_dbclk" }, |
3b54baad BC |
1155 | }; |
1156 | ||
1157 | static struct omap_hwmod omap44xx_gpio2_hwmod = { | |
1158 | .name = "gpio2", | |
1159 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1160 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1161 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1162 | .mpu_irqs = omap44xx_gpio2_irqs, |
3b54baad | 1163 | .main_clk = "gpio2_ick", |
f776471f BC |
1164 | .prcm = { |
1165 | .omap4 = { | |
d0f0631d | 1166 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, |
27bb00b5 | 1167 | .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET, |
03fdefe5 | 1168 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1169 | }, |
1170 | }, | |
3b54baad BC |
1171 | .opt_clks = gpio2_opt_clks, |
1172 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
1173 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1174 | }; |
1175 | ||
3b54baad | 1176 | /* gpio3 */ |
3b54baad BC |
1177 | static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { |
1178 | { .irq = 31 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1179 | { .irq = -1 } |
f776471f BC |
1180 | }; |
1181 | ||
3b54baad | 1182 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
b399bca8 | 1183 | { .role = "dbclk", .clk = "gpio3_dbclk" }, |
3b54baad BC |
1184 | }; |
1185 | ||
1186 | static struct omap_hwmod omap44xx_gpio3_hwmod = { | |
1187 | .name = "gpio3", | |
1188 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1189 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1190 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1191 | .mpu_irqs = omap44xx_gpio3_irqs, |
3b54baad | 1192 | .main_clk = "gpio3_ick", |
f776471f BC |
1193 | .prcm = { |
1194 | .omap4 = { | |
d0f0631d | 1195 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, |
27bb00b5 | 1196 | .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET, |
03fdefe5 | 1197 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1198 | }, |
1199 | }, | |
3b54baad BC |
1200 | .opt_clks = gpio3_opt_clks, |
1201 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
1202 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1203 | }; |
1204 | ||
3b54baad | 1205 | /* gpio4 */ |
3b54baad BC |
1206 | static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { |
1207 | { .irq = 32 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1208 | { .irq = -1 } |
f776471f BC |
1209 | }; |
1210 | ||
3b54baad | 1211 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
b399bca8 | 1212 | { .role = "dbclk", .clk = "gpio4_dbclk" }, |
3b54baad BC |
1213 | }; |
1214 | ||
1215 | static struct omap_hwmod omap44xx_gpio4_hwmod = { | |
1216 | .name = "gpio4", | |
1217 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1218 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1219 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1220 | .mpu_irqs = omap44xx_gpio4_irqs, |
3b54baad | 1221 | .main_clk = "gpio4_ick", |
f776471f BC |
1222 | .prcm = { |
1223 | .omap4 = { | |
d0f0631d | 1224 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, |
27bb00b5 | 1225 | .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET, |
03fdefe5 | 1226 | .modulemode = MODULEMODE_HWCTRL, |
f776471f BC |
1227 | }, |
1228 | }, | |
3b54baad BC |
1229 | .opt_clks = gpio4_opt_clks, |
1230 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
1231 | .dev_attr = &gpio_dev_attr, | |
f776471f BC |
1232 | }; |
1233 | ||
3b54baad | 1234 | /* gpio5 */ |
3b54baad BC |
1235 | static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { |
1236 | { .irq = 33 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1237 | { .irq = -1 } |
55d2cb08 BC |
1238 | }; |
1239 | ||
844a3b63 PW |
1240 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
1241 | { .role = "dbclk", .clk = "gpio5_dbclk" }, | |
55d2cb08 BC |
1242 | }; |
1243 | ||
3b54baad BC |
1244 | static struct omap_hwmod omap44xx_gpio5_hwmod = { |
1245 | .name = "gpio5", | |
1246 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1247 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1248 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1249 | .mpu_irqs = omap44xx_gpio5_irqs, |
3b54baad | 1250 | .main_clk = "gpio5_ick", |
55d2cb08 BC |
1251 | .prcm = { |
1252 | .omap4 = { | |
d0f0631d | 1253 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, |
27bb00b5 | 1254 | .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET, |
03fdefe5 | 1255 | .modulemode = MODULEMODE_HWCTRL, |
55d2cb08 BC |
1256 | }, |
1257 | }, | |
3b54baad BC |
1258 | .opt_clks = gpio5_opt_clks, |
1259 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
1260 | .dev_attr = &gpio_dev_attr, | |
55d2cb08 BC |
1261 | }; |
1262 | ||
3b54baad | 1263 | /* gpio6 */ |
3b54baad BC |
1264 | static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { |
1265 | { .irq = 34 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1266 | { .irq = -1 } |
92b18d1c BC |
1267 | }; |
1268 | ||
3b54baad | 1269 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
b399bca8 | 1270 | { .role = "dbclk", .clk = "gpio6_dbclk" }, |
db12ba53 BC |
1271 | }; |
1272 | ||
3b54baad BC |
1273 | static struct omap_hwmod omap44xx_gpio6_hwmod = { |
1274 | .name = "gpio6", | |
1275 | .class = &omap44xx_gpio_hwmod_class, | |
a5322c6f | 1276 | .clkdm_name = "l4_per_clkdm", |
b399bca8 | 1277 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
3b54baad | 1278 | .mpu_irqs = omap44xx_gpio6_irqs, |
3b54baad BC |
1279 | .main_clk = "gpio6_ick", |
1280 | .prcm = { | |
1281 | .omap4 = { | |
d0f0631d | 1282 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, |
27bb00b5 | 1283 | .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET, |
03fdefe5 | 1284 | .modulemode = MODULEMODE_HWCTRL, |
3b54baad | 1285 | }, |
db12ba53 | 1286 | }, |
3b54baad BC |
1287 | .opt_clks = gpio6_opt_clks, |
1288 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
1289 | .dev_attr = &gpio_dev_attr, | |
db12ba53 BC |
1290 | }; |
1291 | ||
eb42b5d3 BC |
1292 | /* |
1293 | * 'gpmc' class | |
1294 | * general purpose memory controller | |
1295 | */ | |
1296 | ||
1297 | static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = { | |
1298 | .rev_offs = 0x0000, | |
1299 | .sysc_offs = 0x0010, | |
1300 | .syss_offs = 0x0014, | |
1301 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | | |
1302 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1303 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1304 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1305 | }; | |
1306 | ||
1307 | static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = { | |
1308 | .name = "gpmc", | |
1309 | .sysc = &omap44xx_gpmc_sysc, | |
1310 | }; | |
1311 | ||
1312 | /* gpmc */ | |
1313 | static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = { | |
1314 | { .irq = 20 + OMAP44XX_IRQ_GIC_START }, | |
1315 | { .irq = -1 } | |
1316 | }; | |
1317 | ||
1318 | static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = { | |
1319 | { .dma_req = 3 + OMAP44XX_DMA_REQ_START }, | |
1320 | { .dma_req = -1 } | |
1321 | }; | |
1322 | ||
1323 | static struct omap_hwmod omap44xx_gpmc_hwmod = { | |
1324 | .name = "gpmc", | |
1325 | .class = &omap44xx_gpmc_hwmod_class, | |
1326 | .clkdm_name = "l3_2_clkdm", | |
1327 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | |
1328 | .mpu_irqs = omap44xx_gpmc_irqs, | |
1329 | .sdma_reqs = omap44xx_gpmc_sdma_reqs, | |
1330 | .prcm = { | |
1331 | .omap4 = { | |
1332 | .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET, | |
1333 | .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET, | |
1334 | .modulemode = MODULEMODE_HWCTRL, | |
1335 | }, | |
1336 | }, | |
1337 | }; | |
1338 | ||
9def390e PW |
1339 | /* |
1340 | * 'gpu' class | |
1341 | * 2d/3d graphics accelerator | |
1342 | */ | |
1343 | ||
1344 | static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = { | |
1345 | .rev_offs = 0x1fc00, | |
1346 | .sysc_offs = 0x1fc10, | |
1347 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), | |
1348 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1349 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
1350 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), | |
1351 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1352 | }; | |
1353 | ||
1354 | static struct omap_hwmod_class omap44xx_gpu_hwmod_class = { | |
1355 | .name = "gpu", | |
1356 | .sysc = &omap44xx_gpu_sysc, | |
1357 | }; | |
1358 | ||
1359 | /* gpu */ | |
1360 | static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = { | |
1361 | { .irq = 21 + OMAP44XX_IRQ_GIC_START }, | |
1362 | { .irq = -1 } | |
1363 | }; | |
1364 | ||
1365 | static struct omap_hwmod omap44xx_gpu_hwmod = { | |
1366 | .name = "gpu", | |
1367 | .class = &omap44xx_gpu_hwmod_class, | |
1368 | .clkdm_name = "l3_gfx_clkdm", | |
1369 | .mpu_irqs = omap44xx_gpu_irqs, | |
1370 | .main_clk = "gpu_fck", | |
1371 | .prcm = { | |
1372 | .omap4 = { | |
1373 | .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET, | |
1374 | .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET, | |
1375 | .modulemode = MODULEMODE_SWCTRL, | |
1376 | }, | |
1377 | }, | |
1378 | }; | |
1379 | ||
a091c08e PW |
1380 | /* |
1381 | * 'hdq1w' class | |
1382 | * hdq / 1-wire serial interface controller | |
1383 | */ | |
1384 | ||
1385 | static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = { | |
1386 | .rev_offs = 0x0000, | |
1387 | .sysc_offs = 0x0014, | |
1388 | .syss_offs = 0x0018, | |
1389 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | | |
1390 | SYSS_HAS_RESET_STATUS), | |
1391 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1392 | }; | |
1393 | ||
1394 | static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = { | |
1395 | .name = "hdq1w", | |
1396 | .sysc = &omap44xx_hdq1w_sysc, | |
1397 | }; | |
1398 | ||
1399 | /* hdq1w */ | |
1400 | static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = { | |
1401 | { .irq = 58 + OMAP44XX_IRQ_GIC_START }, | |
1402 | { .irq = -1 } | |
1403 | }; | |
1404 | ||
1405 | static struct omap_hwmod omap44xx_hdq1w_hwmod = { | |
1406 | .name = "hdq1w", | |
1407 | .class = &omap44xx_hdq1w_hwmod_class, | |
1408 | .clkdm_name = "l4_per_clkdm", | |
1409 | .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ | |
1410 | .mpu_irqs = omap44xx_hdq1w_irqs, | |
1411 | .main_clk = "hdq1w_fck", | |
1412 | .prcm = { | |
1413 | .omap4 = { | |
1414 | .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, | |
1415 | .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET, | |
1416 | .modulemode = MODULEMODE_SWCTRL, | |
1417 | }, | |
1418 | }, | |
1419 | }; | |
1420 | ||
407a6888 BC |
1421 | /* |
1422 | * 'hsi' class | |
1423 | * mipi high-speed synchronous serial interface (multichannel and full-duplex | |
1424 | * serial if) | |
1425 | */ | |
1426 | ||
1427 | static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = { | |
1428 | .rev_offs = 0x0000, | |
1429 | .sysc_offs = 0x0010, | |
1430 | .syss_offs = 0x0014, | |
1431 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | | |
1432 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
1433 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
1434 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1435 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1436 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1437 | .sysc_fields = &omap_hwmod_sysc_type1, |
1438 | }; | |
1439 | ||
1440 | static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { | |
1441 | .name = "hsi", | |
1442 | .sysc = &omap44xx_hsi_sysc, | |
1443 | }; | |
1444 | ||
1445 | /* hsi */ | |
1446 | static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { | |
1447 | { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, | |
1448 | { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, | |
1449 | { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1450 | { .irq = -1 } |
407a6888 BC |
1451 | }; |
1452 | ||
407a6888 BC |
1453 | static struct omap_hwmod omap44xx_hsi_hwmod = { |
1454 | .name = "hsi", | |
1455 | .class = &omap44xx_hsi_hwmod_class, | |
a5322c6f | 1456 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 1457 | .mpu_irqs = omap44xx_hsi_irqs, |
407a6888 | 1458 | .main_clk = "hsi_fck", |
00fe610b | 1459 | .prcm = { |
407a6888 | 1460 | .omap4 = { |
d0f0631d | 1461 | .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET, |
27bb00b5 | 1462 | .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET, |
03fdefe5 | 1463 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1464 | }, |
1465 | }, | |
407a6888 BC |
1466 | }; |
1467 | ||
3b54baad BC |
1468 | /* |
1469 | * 'i2c' class | |
1470 | * multimaster high-speed i2c controller | |
1471 | */ | |
db12ba53 | 1472 | |
3b54baad BC |
1473 | static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { |
1474 | .sysc_offs = 0x0010, | |
1475 | .syss_offs = 0x0090, | |
1476 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1477 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 1478 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
1479 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
1480 | SIDLE_SMART_WKUP), | |
3e47dc6a | 1481 | .clockact = CLOCKACT_TEST_ICLK, |
3b54baad | 1482 | .sysc_fields = &omap_hwmod_sysc_type1, |
db12ba53 BC |
1483 | }; |
1484 | ||
3b54baad | 1485 | static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { |
fe13471c BC |
1486 | .name = "i2c", |
1487 | .sysc = &omap44xx_i2c_sysc, | |
db791a75 | 1488 | .rev = OMAP_I2C_IP_VERSION_2, |
6d3c55fd | 1489 | .reset = &omap_i2c_reset, |
db12ba53 BC |
1490 | }; |
1491 | ||
4d4441a6 | 1492 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
aa8f6cef S |
1493 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE | |
1494 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE, | |
4d4441a6 AG |
1495 | }; |
1496 | ||
3b54baad | 1497 | /* i2c1 */ |
3b54baad BC |
1498 | static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { |
1499 | { .irq = 56 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1500 | { .irq = -1 } |
db12ba53 BC |
1501 | }; |
1502 | ||
3b54baad BC |
1503 | static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { |
1504 | { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, | |
1505 | { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1506 | { .dma_req = -1 } |
db12ba53 BC |
1507 | }; |
1508 | ||
3b54baad BC |
1509 | static struct omap_hwmod omap44xx_i2c1_hwmod = { |
1510 | .name = "i2c1", | |
1511 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1512 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1513 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1514 | .mpu_irqs = omap44xx_i2c1_irqs, |
3b54baad | 1515 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, |
3b54baad | 1516 | .main_clk = "i2c1_fck", |
92b18d1c BC |
1517 | .prcm = { |
1518 | .omap4 = { | |
d0f0631d | 1519 | .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, |
27bb00b5 | 1520 | .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET, |
03fdefe5 | 1521 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
1522 | }, |
1523 | }, | |
4d4441a6 | 1524 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
1525 | }; |
1526 | ||
3b54baad | 1527 | /* i2c2 */ |
3b54baad BC |
1528 | static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { |
1529 | { .irq = 57 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1530 | { .irq = -1 } |
92b18d1c BC |
1531 | }; |
1532 | ||
3b54baad BC |
1533 | static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { |
1534 | { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, | |
1535 | { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1536 | { .dma_req = -1 } |
3b54baad BC |
1537 | }; |
1538 | ||
3b54baad BC |
1539 | static struct omap_hwmod omap44xx_i2c2_hwmod = { |
1540 | .name = "i2c2", | |
1541 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1542 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1543 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1544 | .mpu_irqs = omap44xx_i2c2_irqs, |
3b54baad | 1545 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, |
3b54baad | 1546 | .main_clk = "i2c2_fck", |
db12ba53 BC |
1547 | .prcm = { |
1548 | .omap4 = { | |
d0f0631d | 1549 | .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, |
27bb00b5 | 1550 | .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET, |
03fdefe5 | 1551 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
1552 | }, |
1553 | }, | |
4d4441a6 | 1554 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
1555 | }; |
1556 | ||
3b54baad | 1557 | /* i2c3 */ |
3b54baad BC |
1558 | static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { |
1559 | { .irq = 61 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1560 | { .irq = -1 } |
db12ba53 BC |
1561 | }; |
1562 | ||
3b54baad BC |
1563 | static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { |
1564 | { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, | |
1565 | { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1566 | { .dma_req = -1 } |
92b18d1c BC |
1567 | }; |
1568 | ||
3b54baad BC |
1569 | static struct omap_hwmod omap44xx_i2c3_hwmod = { |
1570 | .name = "i2c3", | |
1571 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1572 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1573 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1574 | .mpu_irqs = omap44xx_i2c3_irqs, |
3b54baad | 1575 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, |
3b54baad | 1576 | .main_clk = "i2c3_fck", |
db12ba53 BC |
1577 | .prcm = { |
1578 | .omap4 = { | |
d0f0631d | 1579 | .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, |
27bb00b5 | 1580 | .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET, |
03fdefe5 | 1581 | .modulemode = MODULEMODE_SWCTRL, |
db12ba53 BC |
1582 | }, |
1583 | }, | |
4d4441a6 | 1584 | .dev_attr = &i2c_dev_attr, |
db12ba53 BC |
1585 | }; |
1586 | ||
3b54baad | 1587 | /* i2c4 */ |
3b54baad BC |
1588 | static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { |
1589 | { .irq = 62 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1590 | { .irq = -1 } |
db12ba53 BC |
1591 | }; |
1592 | ||
3b54baad BC |
1593 | static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { |
1594 | { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, | |
1595 | { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1596 | { .dma_req = -1 } |
db12ba53 BC |
1597 | }; |
1598 | ||
3b54baad BC |
1599 | static struct omap_hwmod omap44xx_i2c4_hwmod = { |
1600 | .name = "i2c4", | |
1601 | .class = &omap44xx_i2c_hwmod_class, | |
a5322c6f | 1602 | .clkdm_name = "l4_per_clkdm", |
3e47dc6a | 1603 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
3b54baad | 1604 | .mpu_irqs = omap44xx_i2c4_irqs, |
3b54baad | 1605 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, |
3b54baad | 1606 | .main_clk = "i2c4_fck", |
92b18d1c BC |
1607 | .prcm = { |
1608 | .omap4 = { | |
d0f0631d | 1609 | .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, |
27bb00b5 | 1610 | .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET, |
03fdefe5 | 1611 | .modulemode = MODULEMODE_SWCTRL, |
92b18d1c BC |
1612 | }, |
1613 | }, | |
4d4441a6 | 1614 | .dev_attr = &i2c_dev_attr, |
92b18d1c BC |
1615 | }; |
1616 | ||
407a6888 BC |
1617 | /* |
1618 | * 'ipu' class | |
1619 | * imaging processor unit | |
1620 | */ | |
1621 | ||
1622 | static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { | |
1623 | .name = "ipu", | |
1624 | }; | |
1625 | ||
1626 | /* ipu */ | |
1627 | static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { | |
1628 | { .irq = 100 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1629 | { .irq = -1 } |
407a6888 BC |
1630 | }; |
1631 | ||
f2f5736c | 1632 | static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { |
407a6888 | 1633 | { .name = "cpu0", .rst_shift = 0 }, |
407a6888 | 1634 | { .name = "cpu1", .rst_shift = 1 }, |
407a6888 BC |
1635 | { .name = "mmu_cache", .rst_shift = 2 }, |
1636 | }; | |
1637 | ||
407a6888 BC |
1638 | static struct omap_hwmod omap44xx_ipu_hwmod = { |
1639 | .name = "ipu", | |
1640 | .class = &omap44xx_ipu_hwmod_class, | |
a5322c6f | 1641 | .clkdm_name = "ducati_clkdm", |
407a6888 | 1642 | .mpu_irqs = omap44xx_ipu_irqs, |
407a6888 BC |
1643 | .rst_lines = omap44xx_ipu_resets, |
1644 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), | |
1645 | .main_clk = "ipu_fck", | |
00fe610b | 1646 | .prcm = { |
407a6888 | 1647 | .omap4 = { |
d0f0631d | 1648 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, |
eaac329d | 1649 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, |
27bb00b5 | 1650 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, |
03fdefe5 | 1651 | .modulemode = MODULEMODE_HWCTRL, |
407a6888 BC |
1652 | }, |
1653 | }, | |
407a6888 BC |
1654 | }; |
1655 | ||
1656 | /* | |
1657 | * 'iss' class | |
1658 | * external images sensor pixel data processor | |
1659 | */ | |
1660 | ||
1661 | static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { | |
1662 | .rev_offs = 0x0000, | |
1663 | .sysc_offs = 0x0010, | |
d99de7f5 FGL |
1664 | /* |
1665 | * ISS needs 100 OCP clk cycles delay after a softreset before | |
1666 | * accessing sysconfig again. | |
1667 | * The lowest frequency at the moment for L3 bus is 100 MHz, so | |
1668 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). | |
1669 | * | |
1670 | * TODO: Indicate errata when available. | |
1671 | */ | |
1672 | .srst_udelay = 2, | |
407a6888 BC |
1673 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | |
1674 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1675 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1676 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 1677 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
1678 | .sysc_fields = &omap_hwmod_sysc_type2, |
1679 | }; | |
1680 | ||
1681 | static struct omap_hwmod_class omap44xx_iss_hwmod_class = { | |
1682 | .name = "iss", | |
1683 | .sysc = &omap44xx_iss_sysc, | |
1684 | }; | |
1685 | ||
1686 | /* iss */ | |
1687 | static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { | |
1688 | { .irq = 24 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1689 | { .irq = -1 } |
407a6888 BC |
1690 | }; |
1691 | ||
1692 | static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { | |
1693 | { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START }, | |
1694 | { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START }, | |
1695 | { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START }, | |
1696 | { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1697 | { .dma_req = -1 } |
407a6888 BC |
1698 | }; |
1699 | ||
407a6888 BC |
1700 | static struct omap_hwmod_opt_clk iss_opt_clks[] = { |
1701 | { .role = "ctrlclk", .clk = "iss_ctrlclk" }, | |
1702 | }; | |
1703 | ||
1704 | static struct omap_hwmod omap44xx_iss_hwmod = { | |
1705 | .name = "iss", | |
1706 | .class = &omap44xx_iss_hwmod_class, | |
a5322c6f | 1707 | .clkdm_name = "iss_clkdm", |
407a6888 | 1708 | .mpu_irqs = omap44xx_iss_irqs, |
407a6888 | 1709 | .sdma_reqs = omap44xx_iss_sdma_reqs, |
407a6888 | 1710 | .main_clk = "iss_fck", |
00fe610b | 1711 | .prcm = { |
407a6888 | 1712 | .omap4 = { |
d0f0631d | 1713 | .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, |
27bb00b5 | 1714 | .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET, |
03fdefe5 | 1715 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1716 | }, |
1717 | }, | |
1718 | .opt_clks = iss_opt_clks, | |
1719 | .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), | |
407a6888 BC |
1720 | }; |
1721 | ||
8f25bdc5 BC |
1722 | /* |
1723 | * 'iva' class | |
1724 | * multi-standard video encoder/decoder hardware accelerator | |
1725 | */ | |
1726 | ||
1727 | static struct omap_hwmod_class omap44xx_iva_hwmod_class = { | |
fe13471c | 1728 | .name = "iva", |
8f25bdc5 BC |
1729 | }; |
1730 | ||
1731 | /* iva */ | |
1732 | static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { | |
1733 | { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, | |
1734 | { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, | |
1735 | { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1736 | { .irq = -1 } |
8f25bdc5 BC |
1737 | }; |
1738 | ||
1739 | static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { | |
8f25bdc5 | 1740 | { .name = "seq0", .rst_shift = 0 }, |
8f25bdc5 | 1741 | { .name = "seq1", .rst_shift = 1 }, |
f2f5736c | 1742 | { .name = "logic", .rst_shift = 2 }, |
8f25bdc5 BC |
1743 | }; |
1744 | ||
8f25bdc5 BC |
1745 | static struct omap_hwmod omap44xx_iva_hwmod = { |
1746 | .name = "iva", | |
1747 | .class = &omap44xx_iva_hwmod_class, | |
a5322c6f | 1748 | .clkdm_name = "ivahd_clkdm", |
8f25bdc5 | 1749 | .mpu_irqs = omap44xx_iva_irqs, |
8f25bdc5 BC |
1750 | .rst_lines = omap44xx_iva_resets, |
1751 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), | |
1752 | .main_clk = "iva_fck", | |
1753 | .prcm = { | |
1754 | .omap4 = { | |
d0f0631d | 1755 | .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, |
eaac329d | 1756 | .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, |
27bb00b5 | 1757 | .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET, |
03fdefe5 | 1758 | .modulemode = MODULEMODE_HWCTRL, |
8f25bdc5 BC |
1759 | }, |
1760 | }, | |
8f25bdc5 BC |
1761 | }; |
1762 | ||
407a6888 BC |
1763 | /* |
1764 | * 'kbd' class | |
1765 | * keyboard controller | |
1766 | */ | |
1767 | ||
1768 | static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = { | |
1769 | .rev_offs = 0x0000, | |
1770 | .sysc_offs = 0x0010, | |
1771 | .syss_offs = 0x0014, | |
1772 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
1773 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
1774 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1775 | SYSS_HAS_RESET_STATUS), | |
1776 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1777 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1778 | }; | |
1779 | ||
1780 | static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { | |
1781 | .name = "kbd", | |
1782 | .sysc = &omap44xx_kbd_sysc, | |
1783 | }; | |
1784 | ||
1785 | /* kbd */ | |
407a6888 BC |
1786 | static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { |
1787 | { .irq = 120 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1788 | { .irq = -1 } |
407a6888 BC |
1789 | }; |
1790 | ||
407a6888 BC |
1791 | static struct omap_hwmod omap44xx_kbd_hwmod = { |
1792 | .name = "kbd", | |
1793 | .class = &omap44xx_kbd_hwmod_class, | |
a5322c6f | 1794 | .clkdm_name = "l4_wkup_clkdm", |
407a6888 | 1795 | .mpu_irqs = omap44xx_kbd_irqs, |
407a6888 | 1796 | .main_clk = "kbd_fck", |
00fe610b | 1797 | .prcm = { |
407a6888 | 1798 | .omap4 = { |
d0f0631d | 1799 | .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, |
27bb00b5 | 1800 | .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET, |
03fdefe5 | 1801 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
1802 | }, |
1803 | }, | |
407a6888 BC |
1804 | }; |
1805 | ||
ec5df927 BC |
1806 | /* |
1807 | * 'mailbox' class | |
1808 | * mailbox module allowing communication between the on-chip processors using a | |
1809 | * queued mailbox-interrupt mechanism. | |
1810 | */ | |
1811 | ||
1812 | static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = { | |
1813 | .rev_offs = 0x0000, | |
1814 | .sysc_offs = 0x0010, | |
1815 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
1816 | SYSC_HAS_SOFTRESET), | |
1817 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1818 | .sysc_fields = &omap_hwmod_sysc_type2, | |
1819 | }; | |
1820 | ||
1821 | static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { | |
1822 | .name = "mailbox", | |
1823 | .sysc = &omap44xx_mailbox_sysc, | |
1824 | }; | |
1825 | ||
1826 | /* mailbox */ | |
ec5df927 BC |
1827 | static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { |
1828 | { .irq = 26 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 1829 | { .irq = -1 } |
ec5df927 BC |
1830 | }; |
1831 | ||
ec5df927 BC |
1832 | static struct omap_hwmod omap44xx_mailbox_hwmod = { |
1833 | .name = "mailbox", | |
1834 | .class = &omap44xx_mailbox_hwmod_class, | |
a5322c6f | 1835 | .clkdm_name = "l4_cfg_clkdm", |
ec5df927 | 1836 | .mpu_irqs = omap44xx_mailbox_irqs, |
00fe610b | 1837 | .prcm = { |
ec5df927 | 1838 | .omap4 = { |
d0f0631d | 1839 | .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, |
27bb00b5 | 1840 | .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, |
ec5df927 BC |
1841 | }, |
1842 | }, | |
ec5df927 BC |
1843 | }; |
1844 | ||
896d4e98 BC |
1845 | /* |
1846 | * 'mcasp' class | |
1847 | * multi-channel audio serial port controller | |
1848 | */ | |
1849 | ||
1850 | /* The IP is not compliant to type1 / type2 scheme */ | |
1851 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = { | |
1852 | .sidle_shift = 0, | |
1853 | }; | |
1854 | ||
1855 | static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = { | |
1856 | .sysc_offs = 0x0004, | |
1857 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
1858 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1859 | SIDLE_SMART_WKUP), | |
1860 | .sysc_fields = &omap_hwmod_sysc_type_mcasp, | |
1861 | }; | |
1862 | ||
1863 | static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = { | |
1864 | .name = "mcasp", | |
1865 | .sysc = &omap44xx_mcasp_sysc, | |
1866 | }; | |
1867 | ||
1868 | /* mcasp */ | |
1869 | static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = { | |
1870 | { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START }, | |
1871 | { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START }, | |
1872 | { .irq = -1 } | |
1873 | }; | |
1874 | ||
1875 | static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = { | |
1876 | { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START }, | |
1877 | { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START }, | |
1878 | { .dma_req = -1 } | |
1879 | }; | |
1880 | ||
1881 | static struct omap_hwmod omap44xx_mcasp_hwmod = { | |
1882 | .name = "mcasp", | |
1883 | .class = &omap44xx_mcasp_hwmod_class, | |
1884 | .clkdm_name = "abe_clkdm", | |
1885 | .mpu_irqs = omap44xx_mcasp_irqs, | |
1886 | .sdma_reqs = omap44xx_mcasp_sdma_reqs, | |
1887 | .main_clk = "mcasp_fck", | |
1888 | .prcm = { | |
1889 | .omap4 = { | |
1890 | .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET, | |
1891 | .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET, | |
1892 | .modulemode = MODULEMODE_SWCTRL, | |
1893 | }, | |
1894 | }, | |
1895 | }; | |
1896 | ||
4ddff493 BC |
1897 | /* |
1898 | * 'mcbsp' class | |
1899 | * multi channel buffered serial port controller | |
1900 | */ | |
1901 | ||
1902 | static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { | |
1903 | .sysc_offs = 0x008c, | |
1904 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
1905 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1906 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1907 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1908 | }; | |
1909 | ||
1910 | static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { | |
1911 | .name = "mcbsp", | |
1912 | .sysc = &omap44xx_mcbsp_sysc, | |
cb7e9ded | 1913 | .rev = MCBSP_CONFIG_TYPE4, |
4ddff493 BC |
1914 | }; |
1915 | ||
1916 | /* mcbsp1 */ | |
4ddff493 | 1917 | static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { |
437e8970 | 1918 | { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START }, |
212738a4 | 1919 | { .irq = -1 } |
4ddff493 BC |
1920 | }; |
1921 | ||
1922 | static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { | |
1923 | { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, | |
1924 | { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1925 | { .dma_req = -1 } |
4ddff493 BC |
1926 | }; |
1927 | ||
503d0ea2 PW |
1928 | static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { |
1929 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 1930 | { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" }, |
503d0ea2 PW |
1931 | }; |
1932 | ||
4ddff493 BC |
1933 | static struct omap_hwmod omap44xx_mcbsp1_hwmod = { |
1934 | .name = "mcbsp1", | |
1935 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1936 | .clkdm_name = "abe_clkdm", |
4ddff493 | 1937 | .mpu_irqs = omap44xx_mcbsp1_irqs, |
4ddff493 | 1938 | .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, |
4ddff493 BC |
1939 | .main_clk = "mcbsp1_fck", |
1940 | .prcm = { | |
1941 | .omap4 = { | |
d0f0631d | 1942 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, |
27bb00b5 | 1943 | .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET, |
03fdefe5 | 1944 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1945 | }, |
1946 | }, | |
503d0ea2 PW |
1947 | .opt_clks = mcbsp1_opt_clks, |
1948 | .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks), | |
4ddff493 BC |
1949 | }; |
1950 | ||
1951 | /* mcbsp2 */ | |
4ddff493 | 1952 | static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { |
437e8970 | 1953 | { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START }, |
212738a4 | 1954 | { .irq = -1 } |
4ddff493 BC |
1955 | }; |
1956 | ||
1957 | static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { | |
1958 | { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START }, | |
1959 | { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1960 | { .dma_req = -1 } |
4ddff493 BC |
1961 | }; |
1962 | ||
844a3b63 PW |
1963 | static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { |
1964 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 1965 | { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" }, |
503d0ea2 PW |
1966 | }; |
1967 | ||
4ddff493 BC |
1968 | static struct omap_hwmod omap44xx_mcbsp2_hwmod = { |
1969 | .name = "mcbsp2", | |
1970 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 1971 | .clkdm_name = "abe_clkdm", |
4ddff493 | 1972 | .mpu_irqs = omap44xx_mcbsp2_irqs, |
4ddff493 | 1973 | .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, |
4ddff493 BC |
1974 | .main_clk = "mcbsp2_fck", |
1975 | .prcm = { | |
1976 | .omap4 = { | |
d0f0631d | 1977 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, |
27bb00b5 | 1978 | .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET, |
03fdefe5 | 1979 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
1980 | }, |
1981 | }, | |
503d0ea2 PW |
1982 | .opt_clks = mcbsp2_opt_clks, |
1983 | .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks), | |
4ddff493 BC |
1984 | }; |
1985 | ||
1986 | /* mcbsp3 */ | |
4ddff493 | 1987 | static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { |
437e8970 | 1988 | { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START }, |
212738a4 | 1989 | { .irq = -1 } |
4ddff493 BC |
1990 | }; |
1991 | ||
1992 | static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { | |
1993 | { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START }, | |
1994 | { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 1995 | { .dma_req = -1 } |
4ddff493 BC |
1996 | }; |
1997 | ||
503d0ea2 PW |
1998 | static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { |
1999 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 2000 | { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" }, |
503d0ea2 PW |
2001 | }; |
2002 | ||
4ddff493 BC |
2003 | static struct omap_hwmod omap44xx_mcbsp3_hwmod = { |
2004 | .name = "mcbsp3", | |
2005 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 2006 | .clkdm_name = "abe_clkdm", |
4ddff493 | 2007 | .mpu_irqs = omap44xx_mcbsp3_irqs, |
4ddff493 | 2008 | .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, |
4ddff493 BC |
2009 | .main_clk = "mcbsp3_fck", |
2010 | .prcm = { | |
2011 | .omap4 = { | |
d0f0631d | 2012 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, |
27bb00b5 | 2013 | .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET, |
03fdefe5 | 2014 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
2015 | }, |
2016 | }, | |
503d0ea2 PW |
2017 | .opt_clks = mcbsp3_opt_clks, |
2018 | .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks), | |
4ddff493 BC |
2019 | }; |
2020 | ||
2021 | /* mcbsp4 */ | |
4ddff493 | 2022 | static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { |
437e8970 | 2023 | { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START }, |
212738a4 | 2024 | { .irq = -1 } |
4ddff493 BC |
2025 | }; |
2026 | ||
2027 | static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { | |
2028 | { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START }, | |
2029 | { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2030 | { .dma_req = -1 } |
4ddff493 BC |
2031 | }; |
2032 | ||
503d0ea2 PW |
2033 | static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { |
2034 | { .role = "pad_fck", .clk = "pad_clks_ck" }, | |
d7a0b513 | 2035 | { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" }, |
503d0ea2 PW |
2036 | }; |
2037 | ||
4ddff493 BC |
2038 | static struct omap_hwmod omap44xx_mcbsp4_hwmod = { |
2039 | .name = "mcbsp4", | |
2040 | .class = &omap44xx_mcbsp_hwmod_class, | |
a5322c6f | 2041 | .clkdm_name = "l4_per_clkdm", |
4ddff493 | 2042 | .mpu_irqs = omap44xx_mcbsp4_irqs, |
4ddff493 | 2043 | .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, |
4ddff493 BC |
2044 | .main_clk = "mcbsp4_fck", |
2045 | .prcm = { | |
2046 | .omap4 = { | |
d0f0631d | 2047 | .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, |
27bb00b5 | 2048 | .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET, |
03fdefe5 | 2049 | .modulemode = MODULEMODE_SWCTRL, |
4ddff493 BC |
2050 | }, |
2051 | }, | |
503d0ea2 PW |
2052 | .opt_clks = mcbsp4_opt_clks, |
2053 | .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks), | |
4ddff493 BC |
2054 | }; |
2055 | ||
407a6888 BC |
2056 | /* |
2057 | * 'mcpdm' class | |
2058 | * multi channel pdm controller (proprietary interface with phoenix power | |
2059 | * ic) | |
2060 | */ | |
2061 | ||
2062 | static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = { | |
2063 | .rev_offs = 0x0000, | |
2064 | .sysc_offs = 0x0010, | |
2065 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2066 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2067 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2068 | SIDLE_SMART_WKUP), | |
2069 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2070 | }; | |
2071 | ||
2072 | static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { | |
2073 | .name = "mcpdm", | |
2074 | .sysc = &omap44xx_mcpdm_sysc, | |
2075 | }; | |
2076 | ||
2077 | /* mcpdm */ | |
407a6888 BC |
2078 | static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { |
2079 | { .irq = 112 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2080 | { .irq = -1 } |
407a6888 BC |
2081 | }; |
2082 | ||
2083 | static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { | |
2084 | { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START }, | |
2085 | { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2086 | { .dma_req = -1 } |
407a6888 BC |
2087 | }; |
2088 | ||
407a6888 BC |
2089 | static struct omap_hwmod omap44xx_mcpdm_hwmod = { |
2090 | .name = "mcpdm", | |
2091 | .class = &omap44xx_mcpdm_hwmod_class, | |
a5322c6f | 2092 | .clkdm_name = "abe_clkdm", |
407a6888 | 2093 | .mpu_irqs = omap44xx_mcpdm_irqs, |
407a6888 | 2094 | .sdma_reqs = omap44xx_mcpdm_sdma_reqs, |
407a6888 | 2095 | .main_clk = "mcpdm_fck", |
00fe610b | 2096 | .prcm = { |
407a6888 | 2097 | .omap4 = { |
d0f0631d | 2098 | .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, |
27bb00b5 | 2099 | .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET, |
03fdefe5 | 2100 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2101 | }, |
2102 | }, | |
407a6888 BC |
2103 | }; |
2104 | ||
9bcbd7f0 BC |
2105 | /* |
2106 | * 'mcspi' class | |
2107 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
2108 | * bus | |
2109 | */ | |
2110 | ||
2111 | static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { | |
2112 | .rev_offs = 0x0000, | |
2113 | .sysc_offs = 0x0010, | |
2114 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2115 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2116 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2117 | SIDLE_SMART_WKUP), | |
2118 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2119 | }; | |
2120 | ||
2121 | static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { | |
2122 | .name = "mcspi", | |
2123 | .sysc = &omap44xx_mcspi_sysc, | |
905a74d9 | 2124 | .rev = OMAP4_MCSPI_REV, |
9bcbd7f0 BC |
2125 | }; |
2126 | ||
2127 | /* mcspi1 */ | |
9bcbd7f0 BC |
2128 | static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { |
2129 | { .irq = 65 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2130 | { .irq = -1 } |
9bcbd7f0 BC |
2131 | }; |
2132 | ||
2133 | static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { | |
2134 | { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, | |
2135 | { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, | |
2136 | { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START }, | |
2137 | { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START }, | |
2138 | { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START }, | |
2139 | { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, | |
2140 | { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, | |
2141 | { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2142 | { .dma_req = -1 } |
9bcbd7f0 BC |
2143 | }; |
2144 | ||
905a74d9 BC |
2145 | /* mcspi1 dev_attr */ |
2146 | static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { | |
2147 | .num_chipselect = 4, | |
2148 | }; | |
2149 | ||
9bcbd7f0 BC |
2150 | static struct omap_hwmod omap44xx_mcspi1_hwmod = { |
2151 | .name = "mcspi1", | |
2152 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2153 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2154 | .mpu_irqs = omap44xx_mcspi1_irqs, |
9bcbd7f0 | 2155 | .sdma_reqs = omap44xx_mcspi1_sdma_reqs, |
9bcbd7f0 BC |
2156 | .main_clk = "mcspi1_fck", |
2157 | .prcm = { | |
2158 | .omap4 = { | |
d0f0631d | 2159 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, |
27bb00b5 | 2160 | .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET, |
03fdefe5 | 2161 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2162 | }, |
2163 | }, | |
905a74d9 | 2164 | .dev_attr = &mcspi1_dev_attr, |
9bcbd7f0 BC |
2165 | }; |
2166 | ||
2167 | /* mcspi2 */ | |
9bcbd7f0 BC |
2168 | static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { |
2169 | { .irq = 66 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2170 | { .irq = -1 } |
9bcbd7f0 BC |
2171 | }; |
2172 | ||
2173 | static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { | |
2174 | { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, | |
2175 | { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, | |
2176 | { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, | |
2177 | { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2178 | { .dma_req = -1 } |
9bcbd7f0 BC |
2179 | }; |
2180 | ||
905a74d9 BC |
2181 | /* mcspi2 dev_attr */ |
2182 | static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { | |
2183 | .num_chipselect = 2, | |
2184 | }; | |
2185 | ||
9bcbd7f0 BC |
2186 | static struct omap_hwmod omap44xx_mcspi2_hwmod = { |
2187 | .name = "mcspi2", | |
2188 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2189 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2190 | .mpu_irqs = omap44xx_mcspi2_irqs, |
9bcbd7f0 | 2191 | .sdma_reqs = omap44xx_mcspi2_sdma_reqs, |
9bcbd7f0 BC |
2192 | .main_clk = "mcspi2_fck", |
2193 | .prcm = { | |
2194 | .omap4 = { | |
d0f0631d | 2195 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, |
27bb00b5 | 2196 | .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET, |
03fdefe5 | 2197 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2198 | }, |
2199 | }, | |
905a74d9 | 2200 | .dev_attr = &mcspi2_dev_attr, |
9bcbd7f0 BC |
2201 | }; |
2202 | ||
2203 | /* mcspi3 */ | |
9bcbd7f0 BC |
2204 | static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { |
2205 | { .irq = 91 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2206 | { .irq = -1 } |
9bcbd7f0 BC |
2207 | }; |
2208 | ||
2209 | static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { | |
2210 | { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, | |
2211 | { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, | |
2212 | { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, | |
2213 | { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2214 | { .dma_req = -1 } |
9bcbd7f0 BC |
2215 | }; |
2216 | ||
905a74d9 BC |
2217 | /* mcspi3 dev_attr */ |
2218 | static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { | |
2219 | .num_chipselect = 2, | |
2220 | }; | |
2221 | ||
9bcbd7f0 BC |
2222 | static struct omap_hwmod omap44xx_mcspi3_hwmod = { |
2223 | .name = "mcspi3", | |
2224 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2225 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2226 | .mpu_irqs = omap44xx_mcspi3_irqs, |
9bcbd7f0 | 2227 | .sdma_reqs = omap44xx_mcspi3_sdma_reqs, |
9bcbd7f0 BC |
2228 | .main_clk = "mcspi3_fck", |
2229 | .prcm = { | |
2230 | .omap4 = { | |
d0f0631d | 2231 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, |
27bb00b5 | 2232 | .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET, |
03fdefe5 | 2233 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2234 | }, |
2235 | }, | |
905a74d9 | 2236 | .dev_attr = &mcspi3_dev_attr, |
9bcbd7f0 BC |
2237 | }; |
2238 | ||
2239 | /* mcspi4 */ | |
9bcbd7f0 BC |
2240 | static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { |
2241 | { .irq = 48 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2242 | { .irq = -1 } |
9bcbd7f0 BC |
2243 | }; |
2244 | ||
2245 | static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { | |
2246 | { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, | |
2247 | { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2248 | { .dma_req = -1 } |
9bcbd7f0 BC |
2249 | }; |
2250 | ||
905a74d9 BC |
2251 | /* mcspi4 dev_attr */ |
2252 | static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { | |
2253 | .num_chipselect = 1, | |
2254 | }; | |
2255 | ||
9bcbd7f0 BC |
2256 | static struct omap_hwmod omap44xx_mcspi4_hwmod = { |
2257 | .name = "mcspi4", | |
2258 | .class = &omap44xx_mcspi_hwmod_class, | |
a5322c6f | 2259 | .clkdm_name = "l4_per_clkdm", |
9bcbd7f0 | 2260 | .mpu_irqs = omap44xx_mcspi4_irqs, |
9bcbd7f0 | 2261 | .sdma_reqs = omap44xx_mcspi4_sdma_reqs, |
9bcbd7f0 BC |
2262 | .main_clk = "mcspi4_fck", |
2263 | .prcm = { | |
2264 | .omap4 = { | |
d0f0631d | 2265 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, |
27bb00b5 | 2266 | .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET, |
03fdefe5 | 2267 | .modulemode = MODULEMODE_SWCTRL, |
9bcbd7f0 BC |
2268 | }, |
2269 | }, | |
905a74d9 | 2270 | .dev_attr = &mcspi4_dev_attr, |
9bcbd7f0 BC |
2271 | }; |
2272 | ||
407a6888 BC |
2273 | /* |
2274 | * 'mmc' class | |
2275 | * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller | |
2276 | */ | |
2277 | ||
2278 | static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = { | |
2279 | .rev_offs = 0x0000, | |
2280 | .sysc_offs = 0x0010, | |
2281 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | |
2282 | SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
2283 | SYSC_HAS_SOFTRESET), | |
2284 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2285 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
c614ebf6 | 2286 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
407a6888 BC |
2287 | .sysc_fields = &omap_hwmod_sysc_type2, |
2288 | }; | |
2289 | ||
2290 | static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { | |
2291 | .name = "mmc", | |
2292 | .sysc = &omap44xx_mmc_sysc, | |
2293 | }; | |
2294 | ||
2295 | /* mmc1 */ | |
2296 | static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { | |
2297 | { .irq = 83 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2298 | { .irq = -1 } |
407a6888 BC |
2299 | }; |
2300 | ||
2301 | static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { | |
2302 | { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, | |
2303 | { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2304 | { .dma_req = -1 } |
407a6888 BC |
2305 | }; |
2306 | ||
6ab8946f KK |
2307 | /* mmc1 dev_attr */ |
2308 | static struct omap_mmc_dev_attr mmc1_dev_attr = { | |
2309 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
2310 | }; | |
2311 | ||
407a6888 BC |
2312 | static struct omap_hwmod omap44xx_mmc1_hwmod = { |
2313 | .name = "mmc1", | |
2314 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2315 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 2316 | .mpu_irqs = omap44xx_mmc1_irqs, |
407a6888 | 2317 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, |
407a6888 | 2318 | .main_clk = "mmc1_fck", |
00fe610b | 2319 | .prcm = { |
407a6888 | 2320 | .omap4 = { |
d0f0631d | 2321 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, |
27bb00b5 | 2322 | .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET, |
03fdefe5 | 2323 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2324 | }, |
2325 | }, | |
6ab8946f | 2326 | .dev_attr = &mmc1_dev_attr, |
407a6888 BC |
2327 | }; |
2328 | ||
2329 | /* mmc2 */ | |
2330 | static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { | |
2331 | { .irq = 86 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2332 | { .irq = -1 } |
407a6888 BC |
2333 | }; |
2334 | ||
2335 | static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { | |
2336 | { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, | |
2337 | { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2338 | { .dma_req = -1 } |
407a6888 BC |
2339 | }; |
2340 | ||
407a6888 BC |
2341 | static struct omap_hwmod omap44xx_mmc2_hwmod = { |
2342 | .name = "mmc2", | |
2343 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2344 | .clkdm_name = "l3_init_clkdm", |
407a6888 | 2345 | .mpu_irqs = omap44xx_mmc2_irqs, |
407a6888 | 2346 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, |
407a6888 | 2347 | .main_clk = "mmc2_fck", |
00fe610b | 2348 | .prcm = { |
407a6888 | 2349 | .omap4 = { |
d0f0631d | 2350 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, |
27bb00b5 | 2351 | .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET, |
03fdefe5 | 2352 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2353 | }, |
2354 | }, | |
407a6888 BC |
2355 | }; |
2356 | ||
2357 | /* mmc3 */ | |
407a6888 BC |
2358 | static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { |
2359 | { .irq = 94 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2360 | { .irq = -1 } |
407a6888 BC |
2361 | }; |
2362 | ||
2363 | static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { | |
2364 | { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, | |
2365 | { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2366 | { .dma_req = -1 } |
407a6888 BC |
2367 | }; |
2368 | ||
407a6888 BC |
2369 | static struct omap_hwmod omap44xx_mmc3_hwmod = { |
2370 | .name = "mmc3", | |
2371 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2372 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2373 | .mpu_irqs = omap44xx_mmc3_irqs, |
407a6888 | 2374 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, |
407a6888 | 2375 | .main_clk = "mmc3_fck", |
00fe610b | 2376 | .prcm = { |
407a6888 | 2377 | .omap4 = { |
d0f0631d | 2378 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, |
27bb00b5 | 2379 | .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET, |
03fdefe5 | 2380 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2381 | }, |
2382 | }, | |
407a6888 BC |
2383 | }; |
2384 | ||
2385 | /* mmc4 */ | |
407a6888 BC |
2386 | static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { |
2387 | { .irq = 96 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2388 | { .irq = -1 } |
407a6888 BC |
2389 | }; |
2390 | ||
2391 | static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { | |
2392 | { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, | |
2393 | { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2394 | { .dma_req = -1 } |
407a6888 BC |
2395 | }; |
2396 | ||
407a6888 BC |
2397 | static struct omap_hwmod omap44xx_mmc4_hwmod = { |
2398 | .name = "mmc4", | |
2399 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2400 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2401 | .mpu_irqs = omap44xx_mmc4_irqs, |
407a6888 | 2402 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, |
407a6888 | 2403 | .main_clk = "mmc4_fck", |
00fe610b | 2404 | .prcm = { |
407a6888 | 2405 | .omap4 = { |
d0f0631d | 2406 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, |
27bb00b5 | 2407 | .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET, |
03fdefe5 | 2408 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2409 | }, |
2410 | }, | |
407a6888 BC |
2411 | }; |
2412 | ||
2413 | /* mmc5 */ | |
407a6888 BC |
2414 | static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { |
2415 | { .irq = 59 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2416 | { .irq = -1 } |
407a6888 BC |
2417 | }; |
2418 | ||
2419 | static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { | |
2420 | { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, | |
2421 | { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 2422 | { .dma_req = -1 } |
407a6888 BC |
2423 | }; |
2424 | ||
407a6888 BC |
2425 | static struct omap_hwmod omap44xx_mmc5_hwmod = { |
2426 | .name = "mmc5", | |
2427 | .class = &omap44xx_mmc_hwmod_class, | |
a5322c6f | 2428 | .clkdm_name = "l4_per_clkdm", |
407a6888 | 2429 | .mpu_irqs = omap44xx_mmc5_irqs, |
407a6888 | 2430 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, |
407a6888 | 2431 | .main_clk = "mmc5_fck", |
00fe610b | 2432 | .prcm = { |
407a6888 | 2433 | .omap4 = { |
d0f0631d | 2434 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, |
27bb00b5 | 2435 | .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET, |
03fdefe5 | 2436 | .modulemode = MODULEMODE_SWCTRL, |
407a6888 BC |
2437 | }, |
2438 | }, | |
407a6888 BC |
2439 | }; |
2440 | ||
3b54baad BC |
2441 | /* |
2442 | * 'mpu' class | |
2443 | * mpu sub-system | |
2444 | */ | |
2445 | ||
2446 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { | |
fe13471c | 2447 | .name = "mpu", |
db12ba53 BC |
2448 | }; |
2449 | ||
3b54baad BC |
2450 | /* mpu */ |
2451 | static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { | |
2452 | { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, | |
2453 | { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, | |
2454 | { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2455 | { .irq = -1 } |
db12ba53 BC |
2456 | }; |
2457 | ||
3b54baad BC |
2458 | static struct omap_hwmod omap44xx_mpu_hwmod = { |
2459 | .name = "mpu", | |
2460 | .class = &omap44xx_mpu_hwmod_class, | |
a5322c6f | 2461 | .clkdm_name = "mpuss_clkdm", |
7ecc5373 | 2462 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3b54baad | 2463 | .mpu_irqs = omap44xx_mpu_irqs, |
3b54baad | 2464 | .main_clk = "dpll_mpu_m2_ck", |
db12ba53 BC |
2465 | .prcm = { |
2466 | .omap4 = { | |
d0f0631d | 2467 | .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 2468 | .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, |
db12ba53 BC |
2469 | }, |
2470 | }, | |
db12ba53 BC |
2471 | }; |
2472 | ||
e17f18c0 PW |
2473 | /* |
2474 | * 'ocmc_ram' class | |
2475 | * top-level core on-chip ram | |
2476 | */ | |
2477 | ||
2478 | static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = { | |
2479 | .name = "ocmc_ram", | |
2480 | }; | |
2481 | ||
2482 | /* ocmc_ram */ | |
2483 | static struct omap_hwmod omap44xx_ocmc_ram_hwmod = { | |
2484 | .name = "ocmc_ram", | |
2485 | .class = &omap44xx_ocmc_ram_hwmod_class, | |
2486 | .clkdm_name = "l3_2_clkdm", | |
2487 | .prcm = { | |
2488 | .omap4 = { | |
2489 | .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET, | |
2490 | .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET, | |
2491 | }, | |
2492 | }, | |
2493 | }; | |
2494 | ||
0c668875 BC |
2495 | /* |
2496 | * 'ocp2scp' class | |
2497 | * bridge to transform ocp interface protocol to scp (serial control port) | |
2498 | * protocol | |
2499 | */ | |
2500 | ||
2501 | static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = { | |
2502 | .name = "ocp2scp", | |
2503 | }; | |
2504 | ||
2505 | /* ocp2scp_usb_phy */ | |
2506 | static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = { | |
2507 | { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" }, | |
2508 | }; | |
2509 | ||
2510 | static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { | |
2511 | .name = "ocp2scp_usb_phy", | |
2512 | .class = &omap44xx_ocp2scp_hwmod_class, | |
2513 | .clkdm_name = "l3_init_clkdm", | |
2514 | .prcm = { | |
2515 | .omap4 = { | |
2516 | .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, | |
2517 | .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET, | |
2518 | .modulemode = MODULEMODE_HWCTRL, | |
2519 | }, | |
2520 | }, | |
2521 | .opt_clks = ocp2scp_usb_phy_opt_clks, | |
2522 | .opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks), | |
2523 | }; | |
2524 | ||
794b480a PW |
2525 | /* |
2526 | * 'prcm' class | |
2527 | * power and reset manager (part of the prcm infrastructure) + clock manager 2 | |
2528 | * + clock manager 1 (in always on power domain) + local prm in mpu | |
2529 | */ | |
2530 | ||
2531 | static struct omap_hwmod_class omap44xx_prcm_hwmod_class = { | |
2532 | .name = "prcm", | |
2533 | }; | |
2534 | ||
2535 | /* prcm_mpu */ | |
2536 | static struct omap_hwmod omap44xx_prcm_mpu_hwmod = { | |
2537 | .name = "prcm_mpu", | |
2538 | .class = &omap44xx_prcm_hwmod_class, | |
2539 | .clkdm_name = "l4_wkup_clkdm", | |
2540 | }; | |
2541 | ||
2542 | /* cm_core_aon */ | |
2543 | static struct omap_hwmod omap44xx_cm_core_aon_hwmod = { | |
2544 | .name = "cm_core_aon", | |
2545 | .class = &omap44xx_prcm_hwmod_class, | |
794b480a PW |
2546 | }; |
2547 | ||
2548 | /* cm_core */ | |
2549 | static struct omap_hwmod omap44xx_cm_core_hwmod = { | |
2550 | .name = "cm_core", | |
2551 | .class = &omap44xx_prcm_hwmod_class, | |
794b480a PW |
2552 | }; |
2553 | ||
2554 | /* prm */ | |
2555 | static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = { | |
2556 | { .irq = 11 + OMAP44XX_IRQ_GIC_START }, | |
2557 | { .irq = -1 } | |
2558 | }; | |
2559 | ||
2560 | static struct omap_hwmod_rst_info omap44xx_prm_resets[] = { | |
2561 | { .name = "rst_global_warm_sw", .rst_shift = 0 }, | |
2562 | { .name = "rst_global_cold_sw", .rst_shift = 1 }, | |
2563 | }; | |
2564 | ||
2565 | static struct omap_hwmod omap44xx_prm_hwmod = { | |
2566 | .name = "prm", | |
2567 | .class = &omap44xx_prcm_hwmod_class, | |
794b480a PW |
2568 | .mpu_irqs = omap44xx_prm_irqs, |
2569 | .rst_lines = omap44xx_prm_resets, | |
2570 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets), | |
2571 | }; | |
2572 | ||
2573 | /* | |
2574 | * 'scrm' class | |
2575 | * system clock and reset manager | |
2576 | */ | |
2577 | ||
2578 | static struct omap_hwmod_class omap44xx_scrm_hwmod_class = { | |
2579 | .name = "scrm", | |
2580 | }; | |
2581 | ||
2582 | /* scrm */ | |
2583 | static struct omap_hwmod omap44xx_scrm_hwmod = { | |
2584 | .name = "scrm", | |
2585 | .class = &omap44xx_scrm_hwmod_class, | |
2586 | .clkdm_name = "l4_wkup_clkdm", | |
2587 | }; | |
2588 | ||
42b9e387 PW |
2589 | /* |
2590 | * 'sl2if' class | |
2591 | * shared level 2 memory interface | |
2592 | */ | |
2593 | ||
2594 | static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = { | |
2595 | .name = "sl2if", | |
2596 | }; | |
2597 | ||
2598 | /* sl2if */ | |
2599 | static struct omap_hwmod omap44xx_sl2if_hwmod = { | |
2600 | .name = "sl2if", | |
2601 | .class = &omap44xx_sl2if_hwmod_class, | |
2602 | .clkdm_name = "ivahd_clkdm", | |
2603 | .prcm = { | |
2604 | .omap4 = { | |
2605 | .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET, | |
2606 | .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET, | |
2607 | .modulemode = MODULEMODE_HWCTRL, | |
2608 | }, | |
2609 | }, | |
2610 | }; | |
2611 | ||
1e3b5e59 BC |
2612 | /* |
2613 | * 'slimbus' class | |
2614 | * bidirectional, multi-drop, multi-channel two-line serial interface between | |
2615 | * the device and external components | |
2616 | */ | |
2617 | ||
2618 | static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = { | |
2619 | .rev_offs = 0x0000, | |
2620 | .sysc_offs = 0x0010, | |
2621 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | | |
2622 | SYSC_HAS_SOFTRESET), | |
2623 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2624 | SIDLE_SMART_WKUP), | |
2625 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2626 | }; | |
2627 | ||
2628 | static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = { | |
2629 | .name = "slimbus", | |
2630 | .sysc = &omap44xx_slimbus_sysc, | |
2631 | }; | |
2632 | ||
2633 | /* slimbus1 */ | |
2634 | static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = { | |
2635 | { .irq = 97 + OMAP44XX_IRQ_GIC_START }, | |
2636 | { .irq = -1 } | |
2637 | }; | |
2638 | ||
2639 | static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = { | |
2640 | { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START }, | |
2641 | { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START }, | |
2642 | { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START }, | |
2643 | { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START }, | |
2644 | { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START }, | |
2645 | { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START }, | |
2646 | { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START }, | |
2647 | { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START }, | |
2648 | { .dma_req = -1 } | |
2649 | }; | |
2650 | ||
2651 | static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = { | |
2652 | { .role = "fclk_1", .clk = "slimbus1_fclk_1" }, | |
2653 | { .role = "fclk_0", .clk = "slimbus1_fclk_0" }, | |
2654 | { .role = "fclk_2", .clk = "slimbus1_fclk_2" }, | |
2655 | { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" }, | |
2656 | }; | |
2657 | ||
2658 | static struct omap_hwmod omap44xx_slimbus1_hwmod = { | |
2659 | .name = "slimbus1", | |
2660 | .class = &omap44xx_slimbus_hwmod_class, | |
2661 | .clkdm_name = "abe_clkdm", | |
2662 | .mpu_irqs = omap44xx_slimbus1_irqs, | |
2663 | .sdma_reqs = omap44xx_slimbus1_sdma_reqs, | |
2664 | .prcm = { | |
2665 | .omap4 = { | |
2666 | .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET, | |
2667 | .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET, | |
2668 | .modulemode = MODULEMODE_SWCTRL, | |
2669 | }, | |
2670 | }, | |
2671 | .opt_clks = slimbus1_opt_clks, | |
2672 | .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks), | |
2673 | }; | |
2674 | ||
2675 | /* slimbus2 */ | |
2676 | static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = { | |
2677 | { .irq = 98 + OMAP44XX_IRQ_GIC_START }, | |
2678 | { .irq = -1 } | |
2679 | }; | |
2680 | ||
2681 | static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = { | |
2682 | { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START }, | |
2683 | { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START }, | |
2684 | { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START }, | |
2685 | { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START }, | |
2686 | { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START }, | |
2687 | { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START }, | |
2688 | { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START }, | |
2689 | { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START }, | |
2690 | { .dma_req = -1 } | |
2691 | }; | |
2692 | ||
2693 | static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = { | |
2694 | { .role = "fclk_1", .clk = "slimbus2_fclk_1" }, | |
2695 | { .role = "fclk_0", .clk = "slimbus2_fclk_0" }, | |
2696 | { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" }, | |
2697 | }; | |
2698 | ||
2699 | static struct omap_hwmod omap44xx_slimbus2_hwmod = { | |
2700 | .name = "slimbus2", | |
2701 | .class = &omap44xx_slimbus_hwmod_class, | |
2702 | .clkdm_name = "l4_per_clkdm", | |
2703 | .mpu_irqs = omap44xx_slimbus2_irqs, | |
2704 | .sdma_reqs = omap44xx_slimbus2_sdma_reqs, | |
2705 | .prcm = { | |
2706 | .omap4 = { | |
2707 | .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET, | |
2708 | .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET, | |
2709 | .modulemode = MODULEMODE_SWCTRL, | |
2710 | }, | |
2711 | }, | |
2712 | .opt_clks = slimbus2_opt_clks, | |
2713 | .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks), | |
2714 | }; | |
2715 | ||
1f6a717f BC |
2716 | /* |
2717 | * 'smartreflex' class | |
2718 | * smartreflex module (monitor silicon performance and outputs a measure of | |
2719 | * performance error) | |
2720 | */ | |
2721 | ||
2722 | /* The IP is not compliant to type1 / type2 scheme */ | |
2723 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { | |
2724 | .sidle_shift = 24, | |
2725 | .enwkup_shift = 26, | |
2726 | }; | |
2727 | ||
2728 | static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { | |
2729 | .sysc_offs = 0x0038, | |
2730 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), | |
2731 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2732 | SIDLE_SMART_WKUP), | |
2733 | .sysc_fields = &omap_hwmod_sysc_type_smartreflex, | |
2734 | }; | |
2735 | ||
2736 | static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { | |
fe13471c BC |
2737 | .name = "smartreflex", |
2738 | .sysc = &omap44xx_smartreflex_sysc, | |
2739 | .rev = 2, | |
1f6a717f BC |
2740 | }; |
2741 | ||
2742 | /* smartreflex_core */ | |
cea6b942 SG |
2743 | static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { |
2744 | .sensor_voltdm_name = "core", | |
2745 | }; | |
2746 | ||
1f6a717f BC |
2747 | static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { |
2748 | { .irq = 19 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2749 | { .irq = -1 } |
1f6a717f BC |
2750 | }; |
2751 | ||
1f6a717f BC |
2752 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { |
2753 | .name = "smartreflex_core", | |
2754 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2755 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2756 | .mpu_irqs = omap44xx_smartreflex_core_irqs, |
212738a4 | 2757 | |
1f6a717f | 2758 | .main_clk = "smartreflex_core_fck", |
1f6a717f BC |
2759 | .prcm = { |
2760 | .omap4 = { | |
d0f0631d | 2761 | .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET, |
27bb00b5 | 2762 | .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET, |
03fdefe5 | 2763 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2764 | }, |
2765 | }, | |
cea6b942 | 2766 | .dev_attr = &smartreflex_core_dev_attr, |
1f6a717f BC |
2767 | }; |
2768 | ||
2769 | /* smartreflex_iva */ | |
cea6b942 SG |
2770 | static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { |
2771 | .sensor_voltdm_name = "iva", | |
2772 | }; | |
2773 | ||
1f6a717f BC |
2774 | static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { |
2775 | { .irq = 102 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2776 | { .irq = -1 } |
1f6a717f BC |
2777 | }; |
2778 | ||
1f6a717f BC |
2779 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { |
2780 | .name = "smartreflex_iva", | |
2781 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2782 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2783 | .mpu_irqs = omap44xx_smartreflex_iva_irqs, |
1f6a717f | 2784 | .main_clk = "smartreflex_iva_fck", |
1f6a717f BC |
2785 | .prcm = { |
2786 | .omap4 = { | |
d0f0631d | 2787 | .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET, |
27bb00b5 | 2788 | .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET, |
03fdefe5 | 2789 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2790 | }, |
2791 | }, | |
cea6b942 | 2792 | .dev_attr = &smartreflex_iva_dev_attr, |
1f6a717f BC |
2793 | }; |
2794 | ||
2795 | /* smartreflex_mpu */ | |
cea6b942 SG |
2796 | static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { |
2797 | .sensor_voltdm_name = "mpu", | |
2798 | }; | |
2799 | ||
1f6a717f BC |
2800 | static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { |
2801 | { .irq = 18 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2802 | { .irq = -1 } |
1f6a717f BC |
2803 | }; |
2804 | ||
1f6a717f BC |
2805 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { |
2806 | .name = "smartreflex_mpu", | |
2807 | .class = &omap44xx_smartreflex_hwmod_class, | |
a5322c6f | 2808 | .clkdm_name = "l4_ao_clkdm", |
1f6a717f | 2809 | .mpu_irqs = omap44xx_smartreflex_mpu_irqs, |
1f6a717f | 2810 | .main_clk = "smartreflex_mpu_fck", |
1f6a717f BC |
2811 | .prcm = { |
2812 | .omap4 = { | |
d0f0631d | 2813 | .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET, |
27bb00b5 | 2814 | .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET, |
03fdefe5 | 2815 | .modulemode = MODULEMODE_SWCTRL, |
1f6a717f BC |
2816 | }, |
2817 | }, | |
cea6b942 | 2818 | .dev_attr = &smartreflex_mpu_dev_attr, |
1f6a717f BC |
2819 | }; |
2820 | ||
d11c217f BC |
2821 | /* |
2822 | * 'spinlock' class | |
2823 | * spinlock provides hardware assistance for synchronizing the processes | |
2824 | * running on multiple processors | |
2825 | */ | |
2826 | ||
2827 | static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = { | |
2828 | .rev_offs = 0x0000, | |
2829 | .sysc_offs = 0x0010, | |
2830 | .syss_offs = 0x0014, | |
2831 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2832 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
2833 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
2834 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2835 | SIDLE_SMART_WKUP), | |
2836 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2837 | }; | |
2838 | ||
2839 | static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { | |
2840 | .name = "spinlock", | |
2841 | .sysc = &omap44xx_spinlock_sysc, | |
2842 | }; | |
2843 | ||
2844 | /* spinlock */ | |
d11c217f BC |
2845 | static struct omap_hwmod omap44xx_spinlock_hwmod = { |
2846 | .name = "spinlock", | |
2847 | .class = &omap44xx_spinlock_hwmod_class, | |
a5322c6f | 2848 | .clkdm_name = "l4_cfg_clkdm", |
d11c217f BC |
2849 | .prcm = { |
2850 | .omap4 = { | |
d0f0631d | 2851 | .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET, |
27bb00b5 | 2852 | .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, |
d11c217f BC |
2853 | }, |
2854 | }, | |
d11c217f BC |
2855 | }; |
2856 | ||
35d1a66a BC |
2857 | /* |
2858 | * 'timer' class | |
2859 | * general purpose timer module with accurate 1ms tick | |
2860 | * This class contains several variants: ['timer_1ms', 'timer'] | |
2861 | */ | |
2862 | ||
2863 | static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { | |
2864 | .rev_offs = 0x0000, | |
2865 | .sysc_offs = 0x0010, | |
2866 | .syss_offs = 0x0014, | |
2867 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
2868 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | | |
2869 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
2870 | SYSS_HAS_RESET_STATUS), | |
2871 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2872 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2873 | }; | |
2874 | ||
2875 | static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { | |
2876 | .name = "timer", | |
2877 | .sysc = &omap44xx_timer_1ms_sysc, | |
2878 | }; | |
2879 | ||
2880 | static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = { | |
2881 | .rev_offs = 0x0000, | |
2882 | .sysc_offs = 0x0010, | |
2883 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | | |
2884 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
2885 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2886 | SIDLE_SMART_WKUP), | |
2887 | .sysc_fields = &omap_hwmod_sysc_type2, | |
2888 | }; | |
2889 | ||
2890 | static struct omap_hwmod_class omap44xx_timer_hwmod_class = { | |
2891 | .name = "timer", | |
2892 | .sysc = &omap44xx_timer_sysc, | |
2893 | }; | |
2894 | ||
c345c8b0 TKD |
2895 | /* always-on timers dev attribute */ |
2896 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
2897 | .timer_capability = OMAP_TIMER_ALWON, | |
2898 | }; | |
2899 | ||
2900 | /* pwm timers dev attribute */ | |
2901 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
2902 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
2903 | }; | |
2904 | ||
35d1a66a | 2905 | /* timer1 */ |
35d1a66a BC |
2906 | static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { |
2907 | { .irq = 37 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2908 | { .irq = -1 } |
35d1a66a BC |
2909 | }; |
2910 | ||
35d1a66a BC |
2911 | static struct omap_hwmod omap44xx_timer1_hwmod = { |
2912 | .name = "timer1", | |
2913 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2914 | .clkdm_name = "l4_wkup_clkdm", |
35d1a66a | 2915 | .mpu_irqs = omap44xx_timer1_irqs, |
35d1a66a BC |
2916 | .main_clk = "timer1_fck", |
2917 | .prcm = { | |
2918 | .omap4 = { | |
d0f0631d | 2919 | .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, |
27bb00b5 | 2920 | .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET, |
03fdefe5 | 2921 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2922 | }, |
2923 | }, | |
c345c8b0 | 2924 | .dev_attr = &capability_alwon_dev_attr, |
35d1a66a BC |
2925 | }; |
2926 | ||
2927 | /* timer2 */ | |
35d1a66a BC |
2928 | static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { |
2929 | { .irq = 38 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2930 | { .irq = -1 } |
35d1a66a BC |
2931 | }; |
2932 | ||
35d1a66a BC |
2933 | static struct omap_hwmod omap44xx_timer2_hwmod = { |
2934 | .name = "timer2", | |
2935 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 2936 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2937 | .mpu_irqs = omap44xx_timer2_irqs, |
35d1a66a BC |
2938 | .main_clk = "timer2_fck", |
2939 | .prcm = { | |
2940 | .omap4 = { | |
d0f0631d | 2941 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, |
27bb00b5 | 2942 | .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET, |
03fdefe5 | 2943 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2944 | }, |
2945 | }, | |
35d1a66a BC |
2946 | }; |
2947 | ||
2948 | /* timer3 */ | |
35d1a66a BC |
2949 | static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { |
2950 | { .irq = 39 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2951 | { .irq = -1 } |
35d1a66a BC |
2952 | }; |
2953 | ||
35d1a66a BC |
2954 | static struct omap_hwmod omap44xx_timer3_hwmod = { |
2955 | .name = "timer3", | |
2956 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2957 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2958 | .mpu_irqs = omap44xx_timer3_irqs, |
35d1a66a BC |
2959 | .main_clk = "timer3_fck", |
2960 | .prcm = { | |
2961 | .omap4 = { | |
d0f0631d | 2962 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, |
27bb00b5 | 2963 | .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET, |
03fdefe5 | 2964 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2965 | }, |
2966 | }, | |
35d1a66a BC |
2967 | }; |
2968 | ||
2969 | /* timer4 */ | |
35d1a66a BC |
2970 | static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { |
2971 | { .irq = 40 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2972 | { .irq = -1 } |
35d1a66a BC |
2973 | }; |
2974 | ||
35d1a66a BC |
2975 | static struct omap_hwmod omap44xx_timer4_hwmod = { |
2976 | .name = "timer4", | |
2977 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2978 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 2979 | .mpu_irqs = omap44xx_timer4_irqs, |
35d1a66a BC |
2980 | .main_clk = "timer4_fck", |
2981 | .prcm = { | |
2982 | .omap4 = { | |
d0f0631d | 2983 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, |
27bb00b5 | 2984 | .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET, |
03fdefe5 | 2985 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
2986 | }, |
2987 | }, | |
35d1a66a BC |
2988 | }; |
2989 | ||
2990 | /* timer5 */ | |
35d1a66a BC |
2991 | static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { |
2992 | { .irq = 41 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 2993 | { .irq = -1 } |
35d1a66a BC |
2994 | }; |
2995 | ||
35d1a66a BC |
2996 | static struct omap_hwmod omap44xx_timer5_hwmod = { |
2997 | .name = "timer5", | |
2998 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 2999 | .clkdm_name = "abe_clkdm", |
35d1a66a | 3000 | .mpu_irqs = omap44xx_timer5_irqs, |
35d1a66a BC |
3001 | .main_clk = "timer5_fck", |
3002 | .prcm = { | |
3003 | .omap4 = { | |
d0f0631d | 3004 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, |
27bb00b5 | 3005 | .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET, |
03fdefe5 | 3006 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3007 | }, |
3008 | }, | |
35d1a66a BC |
3009 | }; |
3010 | ||
3011 | /* timer6 */ | |
35d1a66a BC |
3012 | static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { |
3013 | { .irq = 42 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3014 | { .irq = -1 } |
35d1a66a BC |
3015 | }; |
3016 | ||
35d1a66a BC |
3017 | static struct omap_hwmod omap44xx_timer6_hwmod = { |
3018 | .name = "timer6", | |
3019 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3020 | .clkdm_name = "abe_clkdm", |
35d1a66a | 3021 | .mpu_irqs = omap44xx_timer6_irqs, |
212738a4 | 3022 | |
35d1a66a BC |
3023 | .main_clk = "timer6_fck", |
3024 | .prcm = { | |
3025 | .omap4 = { | |
d0f0631d | 3026 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, |
27bb00b5 | 3027 | .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET, |
03fdefe5 | 3028 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3029 | }, |
3030 | }, | |
35d1a66a BC |
3031 | }; |
3032 | ||
3033 | /* timer7 */ | |
35d1a66a BC |
3034 | static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { |
3035 | { .irq = 43 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3036 | { .irq = -1 } |
35d1a66a BC |
3037 | }; |
3038 | ||
35d1a66a BC |
3039 | static struct omap_hwmod omap44xx_timer7_hwmod = { |
3040 | .name = "timer7", | |
3041 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3042 | .clkdm_name = "abe_clkdm", |
35d1a66a | 3043 | .mpu_irqs = omap44xx_timer7_irqs, |
35d1a66a BC |
3044 | .main_clk = "timer7_fck", |
3045 | .prcm = { | |
3046 | .omap4 = { | |
d0f0631d | 3047 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, |
27bb00b5 | 3048 | .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET, |
03fdefe5 | 3049 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3050 | }, |
3051 | }, | |
35d1a66a BC |
3052 | }; |
3053 | ||
3054 | /* timer8 */ | |
35d1a66a BC |
3055 | static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { |
3056 | { .irq = 44 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3057 | { .irq = -1 } |
35d1a66a BC |
3058 | }; |
3059 | ||
35d1a66a BC |
3060 | static struct omap_hwmod omap44xx_timer8_hwmod = { |
3061 | .name = "timer8", | |
3062 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3063 | .clkdm_name = "abe_clkdm", |
35d1a66a | 3064 | .mpu_irqs = omap44xx_timer8_irqs, |
35d1a66a BC |
3065 | .main_clk = "timer8_fck", |
3066 | .prcm = { | |
3067 | .omap4 = { | |
d0f0631d | 3068 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, |
27bb00b5 | 3069 | .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET, |
03fdefe5 | 3070 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3071 | }, |
3072 | }, | |
c345c8b0 | 3073 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
3074 | }; |
3075 | ||
3076 | /* timer9 */ | |
35d1a66a BC |
3077 | static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { |
3078 | { .irq = 45 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3079 | { .irq = -1 } |
35d1a66a BC |
3080 | }; |
3081 | ||
35d1a66a BC |
3082 | static struct omap_hwmod omap44xx_timer9_hwmod = { |
3083 | .name = "timer9", | |
3084 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3085 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 3086 | .mpu_irqs = omap44xx_timer9_irqs, |
35d1a66a BC |
3087 | .main_clk = "timer9_fck", |
3088 | .prcm = { | |
3089 | .omap4 = { | |
d0f0631d | 3090 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, |
27bb00b5 | 3091 | .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET, |
03fdefe5 | 3092 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3093 | }, |
3094 | }, | |
c345c8b0 | 3095 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
3096 | }; |
3097 | ||
3098 | /* timer10 */ | |
35d1a66a BC |
3099 | static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { |
3100 | { .irq = 46 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3101 | { .irq = -1 } |
35d1a66a BC |
3102 | }; |
3103 | ||
35d1a66a BC |
3104 | static struct omap_hwmod omap44xx_timer10_hwmod = { |
3105 | .name = "timer10", | |
3106 | .class = &omap44xx_timer_1ms_hwmod_class, | |
a5322c6f | 3107 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 3108 | .mpu_irqs = omap44xx_timer10_irqs, |
35d1a66a BC |
3109 | .main_clk = "timer10_fck", |
3110 | .prcm = { | |
3111 | .omap4 = { | |
d0f0631d | 3112 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, |
27bb00b5 | 3113 | .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET, |
03fdefe5 | 3114 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3115 | }, |
3116 | }, | |
c345c8b0 | 3117 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
3118 | }; |
3119 | ||
3120 | /* timer11 */ | |
35d1a66a BC |
3121 | static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { |
3122 | { .irq = 47 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3123 | { .irq = -1 } |
35d1a66a BC |
3124 | }; |
3125 | ||
35d1a66a BC |
3126 | static struct omap_hwmod omap44xx_timer11_hwmod = { |
3127 | .name = "timer11", | |
3128 | .class = &omap44xx_timer_hwmod_class, | |
a5322c6f | 3129 | .clkdm_name = "l4_per_clkdm", |
35d1a66a | 3130 | .mpu_irqs = omap44xx_timer11_irqs, |
35d1a66a BC |
3131 | .main_clk = "timer11_fck", |
3132 | .prcm = { | |
3133 | .omap4 = { | |
d0f0631d | 3134 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, |
27bb00b5 | 3135 | .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET, |
03fdefe5 | 3136 | .modulemode = MODULEMODE_SWCTRL, |
35d1a66a BC |
3137 | }, |
3138 | }, | |
c345c8b0 | 3139 | .dev_attr = &capability_pwm_dev_attr, |
35d1a66a BC |
3140 | }; |
3141 | ||
9780a9cf | 3142 | /* |
3b54baad BC |
3143 | * 'uart' class |
3144 | * universal asynchronous receiver/transmitter (uart) | |
9780a9cf BC |
3145 | */ |
3146 | ||
3b54baad BC |
3147 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { |
3148 | .rev_offs = 0x0050, | |
3149 | .sysc_offs = 0x0054, | |
3150 | .syss_offs = 0x0058, | |
3151 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
0cfe8751 BC |
3152 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
3153 | SYSS_HAS_RESET_STATUS), | |
7cffa6b8 BC |
3154 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3155 | SIDLE_SMART_WKUP), | |
9780a9cf BC |
3156 | .sysc_fields = &omap_hwmod_sysc_type1, |
3157 | }; | |
3158 | ||
3b54baad | 3159 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { |
fe13471c BC |
3160 | .name = "uart", |
3161 | .sysc = &omap44xx_uart_sysc, | |
9780a9cf BC |
3162 | }; |
3163 | ||
3b54baad | 3164 | /* uart1 */ |
3b54baad BC |
3165 | static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { |
3166 | { .irq = 72 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3167 | { .irq = -1 } |
9780a9cf BC |
3168 | }; |
3169 | ||
3b54baad BC |
3170 | static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { |
3171 | { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, | |
3172 | { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3173 | { .dma_req = -1 } |
9780a9cf BC |
3174 | }; |
3175 | ||
3b54baad BC |
3176 | static struct omap_hwmod omap44xx_uart1_hwmod = { |
3177 | .name = "uart1", | |
3178 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3179 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 3180 | .mpu_irqs = omap44xx_uart1_irqs, |
3b54baad | 3181 | .sdma_reqs = omap44xx_uart1_sdma_reqs, |
3b54baad | 3182 | .main_clk = "uart1_fck", |
9780a9cf BC |
3183 | .prcm = { |
3184 | .omap4 = { | |
d0f0631d | 3185 | .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, |
27bb00b5 | 3186 | .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET, |
03fdefe5 | 3187 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3188 | }, |
3189 | }, | |
9780a9cf BC |
3190 | }; |
3191 | ||
3b54baad | 3192 | /* uart2 */ |
3b54baad BC |
3193 | static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { |
3194 | { .irq = 73 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3195 | { .irq = -1 } |
9780a9cf BC |
3196 | }; |
3197 | ||
3b54baad BC |
3198 | static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { |
3199 | { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, | |
3200 | { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3201 | { .dma_req = -1 } |
3b54baad BC |
3202 | }; |
3203 | ||
3b54baad BC |
3204 | static struct omap_hwmod omap44xx_uart2_hwmod = { |
3205 | .name = "uart2", | |
3206 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3207 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 3208 | .mpu_irqs = omap44xx_uart2_irqs, |
3b54baad | 3209 | .sdma_reqs = omap44xx_uart2_sdma_reqs, |
3b54baad | 3210 | .main_clk = "uart2_fck", |
9780a9cf BC |
3211 | .prcm = { |
3212 | .omap4 = { | |
d0f0631d | 3213 | .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, |
27bb00b5 | 3214 | .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET, |
03fdefe5 | 3215 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3216 | }, |
3217 | }, | |
9780a9cf BC |
3218 | }; |
3219 | ||
3b54baad | 3220 | /* uart3 */ |
3b54baad BC |
3221 | static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { |
3222 | { .irq = 74 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3223 | { .irq = -1 } |
9780a9cf BC |
3224 | }; |
3225 | ||
3b54baad BC |
3226 | static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { |
3227 | { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, | |
3228 | { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3229 | { .dma_req = -1 } |
3b54baad BC |
3230 | }; |
3231 | ||
3b54baad BC |
3232 | static struct omap_hwmod omap44xx_uart3_hwmod = { |
3233 | .name = "uart3", | |
3234 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3235 | .clkdm_name = "l4_per_clkdm", |
7ecc5373 | 3236 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3b54baad | 3237 | .mpu_irqs = omap44xx_uart3_irqs, |
3b54baad | 3238 | .sdma_reqs = omap44xx_uart3_sdma_reqs, |
3b54baad | 3239 | .main_clk = "uart3_fck", |
9780a9cf BC |
3240 | .prcm = { |
3241 | .omap4 = { | |
d0f0631d | 3242 | .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, |
27bb00b5 | 3243 | .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET, |
03fdefe5 | 3244 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3245 | }, |
3246 | }, | |
9780a9cf BC |
3247 | }; |
3248 | ||
3b54baad | 3249 | /* uart4 */ |
3b54baad BC |
3250 | static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { |
3251 | { .irq = 70 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3252 | { .irq = -1 } |
9780a9cf BC |
3253 | }; |
3254 | ||
3b54baad BC |
3255 | static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { |
3256 | { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, | |
3257 | { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, | |
bc614958 | 3258 | { .dma_req = -1 } |
3b54baad BC |
3259 | }; |
3260 | ||
3b54baad BC |
3261 | static struct omap_hwmod omap44xx_uart4_hwmod = { |
3262 | .name = "uart4", | |
3263 | .class = &omap44xx_uart_hwmod_class, | |
a5322c6f | 3264 | .clkdm_name = "l4_per_clkdm", |
3b54baad | 3265 | .mpu_irqs = omap44xx_uart4_irqs, |
3b54baad | 3266 | .sdma_reqs = omap44xx_uart4_sdma_reqs, |
3b54baad | 3267 | .main_clk = "uart4_fck", |
9780a9cf BC |
3268 | .prcm = { |
3269 | .omap4 = { | |
d0f0631d | 3270 | .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, |
27bb00b5 | 3271 | .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET, |
03fdefe5 | 3272 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3273 | }, |
3274 | }, | |
9780a9cf BC |
3275 | }; |
3276 | ||
0c668875 BC |
3277 | /* |
3278 | * 'usb_host_fs' class | |
3279 | * full-speed usb host controller | |
3280 | */ | |
3281 | ||
3282 | /* The IP is not compliant to type1 / type2 scheme */ | |
3283 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = { | |
3284 | .midle_shift = 4, | |
3285 | .sidle_shift = 2, | |
3286 | .srst_shift = 1, | |
3287 | }; | |
3288 | ||
3289 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = { | |
3290 | .rev_offs = 0x0000, | |
3291 | .sysc_offs = 0x0210, | |
3292 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3293 | SYSC_HAS_SOFTRESET), | |
3294 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3295 | SIDLE_SMART_WKUP), | |
3296 | .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs, | |
3297 | }; | |
3298 | ||
3299 | static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = { | |
3300 | .name = "usb_host_fs", | |
3301 | .sysc = &omap44xx_usb_host_fs_sysc, | |
3302 | }; | |
3303 | ||
3304 | /* usb_host_fs */ | |
3305 | static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = { | |
3306 | { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START }, | |
3307 | { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START }, | |
3308 | { .irq = -1 } | |
3309 | }; | |
3310 | ||
3311 | static struct omap_hwmod omap44xx_usb_host_fs_hwmod = { | |
3312 | .name = "usb_host_fs", | |
3313 | .class = &omap44xx_usb_host_fs_hwmod_class, | |
3314 | .clkdm_name = "l3_init_clkdm", | |
3315 | .mpu_irqs = omap44xx_usb_host_fs_irqs, | |
3316 | .main_clk = "usb_host_fs_fck", | |
3317 | .prcm = { | |
3318 | .omap4 = { | |
3319 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET, | |
3320 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET, | |
3321 | .modulemode = MODULEMODE_SWCTRL, | |
3322 | }, | |
3323 | }, | |
3324 | }; | |
3325 | ||
5844c4ea | 3326 | /* |
844a3b63 PW |
3327 | * 'usb_host_hs' class |
3328 | * high-speed multi-port usb host controller | |
5844c4ea BC |
3329 | */ |
3330 | ||
844a3b63 PW |
3331 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { |
3332 | .rev_offs = 0x0000, | |
3333 | .sysc_offs = 0x0010, | |
3334 | .syss_offs = 0x0014, | |
3335 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3336 | SYSC_HAS_SOFTRESET), | |
5844c4ea BC |
3337 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3338 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
844a3b63 PW |
3339 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
3340 | .sysc_fields = &omap_hwmod_sysc_type2, | |
5844c4ea BC |
3341 | }; |
3342 | ||
844a3b63 PW |
3343 | static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { |
3344 | .name = "usb_host_hs", | |
3345 | .sysc = &omap44xx_usb_host_hs_sysc, | |
5844c4ea BC |
3346 | }; |
3347 | ||
844a3b63 PW |
3348 | /* usb_host_hs */ |
3349 | static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { | |
3350 | { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, | |
3351 | { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3352 | { .irq = -1 } |
5844c4ea BC |
3353 | }; |
3354 | ||
844a3b63 PW |
3355 | static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { |
3356 | .name = "usb_host_hs", | |
3357 | .class = &omap44xx_usb_host_hs_hwmod_class, | |
a5322c6f | 3358 | .clkdm_name = "l3_init_clkdm", |
844a3b63 | 3359 | .main_clk = "usb_host_hs_fck", |
5844c4ea BC |
3360 | .prcm = { |
3361 | .omap4 = { | |
844a3b63 PW |
3362 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, |
3363 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, | |
3364 | .modulemode = MODULEMODE_SWCTRL, | |
3365 | }, | |
3366 | }, | |
3367 | .mpu_irqs = omap44xx_usb_host_hs_irqs, | |
3368 | ||
3369 | /* | |
3370 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
3371 | * id: i660 | |
3372 | * | |
3373 | * Description: | |
3374 | * In the following configuration : | |
3375 | * - USBHOST module is set to smart-idle mode | |
3376 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
3377 | * happens when the system is going to a low power mode : all ports | |
3378 | * have been suspended, the master part of the USBHOST module has | |
3379 | * entered the standby state, and SW has cut the functional clocks) | |
3380 | * - an USBHOST interrupt occurs before the module is able to answer | |
3381 | * idle_ack, typically a remote wakeup IRQ. | |
3382 | * Then the USB HOST module will enter a deadlock situation where it | |
3383 | * is no more accessible nor functional. | |
3384 | * | |
3385 | * Workaround: | |
3386 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
3387 | */ | |
3388 | ||
3389 | /* | |
3390 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
3391 | * Id: i571 | |
3392 | * | |
3393 | * Description: | |
3394 | * When the USBHOST module is set to smart-standby mode, and when it is | |
3395 | * ready to enter the standby state (i.e. all ports are suspended and | |
3396 | * all attached devices are in suspend mode), then it can wrongly assert | |
3397 | * the Mstandby signal too early while there are still some residual OCP | |
3398 | * transactions ongoing. If this condition occurs, the internal state | |
3399 | * machine may go to an undefined state and the USB link may be stuck | |
3400 | * upon the next resume. | |
3401 | * | |
3402 | * Workaround: | |
3403 | * Don't use smart standby; use only force standby, | |
3404 | * hence HWMOD_SWSUP_MSTANDBY | |
3405 | */ | |
3406 | ||
3407 | /* | |
3408 | * During system boot; If the hwmod framework resets the module | |
3409 | * the module will have smart idle settings; which can lead to deadlock | |
3410 | * (above Errata Id:i660); so, dont reset the module during boot; | |
3411 | * Use HWMOD_INIT_NO_RESET. | |
3412 | */ | |
3413 | ||
3414 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | | |
3415 | HWMOD_INIT_NO_RESET, | |
3416 | }; | |
3417 | ||
3418 | /* | |
3419 | * 'usb_otg_hs' class | |
3420 | * high-speed on-the-go universal serial bus (usb_otg_hs) controller | |
3421 | */ | |
3422 | ||
3423 | static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { | |
3424 | .rev_offs = 0x0400, | |
3425 | .sysc_offs = 0x0404, | |
3426 | .syss_offs = 0x0408, | |
3427 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | |
3428 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | | |
3429 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | |
3430 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
3431 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | | |
3432 | MSTANDBY_SMART), | |
3433 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3434 | }; | |
3435 | ||
3436 | static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { | |
3437 | .name = "usb_otg_hs", | |
3438 | .sysc = &omap44xx_usb_otg_hs_sysc, | |
3439 | }; | |
3440 | ||
3441 | /* usb_otg_hs */ | |
3442 | static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { | |
3443 | { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, | |
3444 | { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, | |
3445 | { .irq = -1 } | |
3446 | }; | |
3447 | ||
3448 | static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { | |
3449 | { .role = "xclk", .clk = "usb_otg_hs_xclk" }, | |
3450 | }; | |
3451 | ||
3452 | static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { | |
3453 | .name = "usb_otg_hs", | |
3454 | .class = &omap44xx_usb_otg_hs_hwmod_class, | |
3455 | .clkdm_name = "l3_init_clkdm", | |
3456 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, | |
3457 | .mpu_irqs = omap44xx_usb_otg_hs_irqs, | |
3458 | .main_clk = "usb_otg_hs_ick", | |
3459 | .prcm = { | |
3460 | .omap4 = { | |
3461 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET, | |
3462 | .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET, | |
3463 | .modulemode = MODULEMODE_HWCTRL, | |
3464 | }, | |
3465 | }, | |
3466 | .opt_clks = usb_otg_hs_opt_clks, | |
3467 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), | |
3468 | }; | |
3469 | ||
3470 | /* | |
3471 | * 'usb_tll_hs' class | |
3472 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
3473 | */ | |
3474 | ||
3475 | static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { | |
3476 | .rev_offs = 0x0000, | |
3477 | .sysc_offs = 0x0010, | |
3478 | .syss_offs = 0x0014, | |
3479 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
3480 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
3481 | SYSC_HAS_AUTOIDLE), | |
3482 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
3483 | .sysc_fields = &omap_hwmod_sysc_type1, | |
3484 | }; | |
3485 | ||
3486 | static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { | |
3487 | .name = "usb_tll_hs", | |
3488 | .sysc = &omap44xx_usb_tll_hs_sysc, | |
3489 | }; | |
3490 | ||
3491 | static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { | |
3492 | { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, | |
3493 | { .irq = -1 } | |
3494 | }; | |
3495 | ||
3496 | static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { | |
3497 | .name = "usb_tll_hs", | |
3498 | .class = &omap44xx_usb_tll_hs_hwmod_class, | |
3499 | .clkdm_name = "l3_init_clkdm", | |
3500 | .mpu_irqs = omap44xx_usb_tll_hs_irqs, | |
3501 | .main_clk = "usb_tll_hs_ick", | |
3502 | .prcm = { | |
3503 | .omap4 = { | |
3504 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, | |
3505 | .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, | |
3506 | .modulemode = MODULEMODE_HWCTRL, | |
5844c4ea BC |
3507 | }, |
3508 | }, | |
5844c4ea BC |
3509 | }; |
3510 | ||
3b54baad BC |
3511 | /* |
3512 | * 'wd_timer' class | |
3513 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
3514 | * overflow condition | |
3515 | */ | |
3516 | ||
3517 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { | |
3518 | .rev_offs = 0x0000, | |
3519 | .sysc_offs = 0x0010, | |
3520 | .syss_offs = 0x0014, | |
3521 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | |
0cfe8751 | 3522 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
7cffa6b8 BC |
3523 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
3524 | SIDLE_SMART_WKUP), | |
3b54baad | 3525 | .sysc_fields = &omap_hwmod_sysc_type1, |
9780a9cf BC |
3526 | }; |
3527 | ||
3b54baad BC |
3528 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { |
3529 | .name = "wd_timer", | |
3530 | .sysc = &omap44xx_wd_timer_sysc, | |
fe13471c | 3531 | .pre_shutdown = &omap2_wd_timer_disable, |
414e4128 | 3532 | .reset = &omap2_wd_timer_reset, |
3b54baad BC |
3533 | }; |
3534 | ||
3535 | /* wd_timer2 */ | |
3b54baad BC |
3536 | static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { |
3537 | { .irq = 80 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3538 | { .irq = -1 } |
3b54baad BC |
3539 | }; |
3540 | ||
3b54baad BC |
3541 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { |
3542 | .name = "wd_timer2", | |
3543 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 3544 | .clkdm_name = "l4_wkup_clkdm", |
3b54baad | 3545 | .mpu_irqs = omap44xx_wd_timer2_irqs, |
3b54baad | 3546 | .main_clk = "wd_timer2_fck", |
9780a9cf BC |
3547 | .prcm = { |
3548 | .omap4 = { | |
d0f0631d | 3549 | .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, |
27bb00b5 | 3550 | .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET, |
03fdefe5 | 3551 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3552 | }, |
3553 | }, | |
9780a9cf BC |
3554 | }; |
3555 | ||
3b54baad | 3556 | /* wd_timer3 */ |
3b54baad BC |
3557 | static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { |
3558 | { .irq = 36 + OMAP44XX_IRQ_GIC_START }, | |
212738a4 | 3559 | { .irq = -1 } |
9780a9cf BC |
3560 | }; |
3561 | ||
3b54baad BC |
3562 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { |
3563 | .name = "wd_timer3", | |
3564 | .class = &omap44xx_wd_timer_hwmod_class, | |
a5322c6f | 3565 | .clkdm_name = "abe_clkdm", |
3b54baad | 3566 | .mpu_irqs = omap44xx_wd_timer3_irqs, |
3b54baad | 3567 | .main_clk = "wd_timer3_fck", |
9780a9cf BC |
3568 | .prcm = { |
3569 | .omap4 = { | |
d0f0631d | 3570 | .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, |
27bb00b5 | 3571 | .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, |
03fdefe5 | 3572 | .modulemode = MODULEMODE_SWCTRL, |
9780a9cf BC |
3573 | }, |
3574 | }, | |
9780a9cf | 3575 | }; |
531ce0d5 | 3576 | |
844a3b63 | 3577 | |
af88fa9a | 3578 | /* |
844a3b63 | 3579 | * interfaces |
af88fa9a | 3580 | */ |
af88fa9a | 3581 | |
42b9e387 PW |
3582 | static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = { |
3583 | { | |
3584 | .pa_start = 0x4a204000, | |
3585 | .pa_end = 0x4a2040ff, | |
3586 | .flags = ADDR_TYPE_RT | |
3587 | }, | |
3588 | { } | |
3589 | }; | |
3590 | ||
3591 | /* c2c -> c2c_target_fw */ | |
3592 | static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = { | |
3593 | .master = &omap44xx_c2c_hwmod, | |
3594 | .slave = &omap44xx_c2c_target_fw_hwmod, | |
3595 | .clk = "div_core_ck", | |
3596 | .addr = omap44xx_c2c_target_fw_addrs, | |
3597 | .user = OCP_USER_MPU, | |
3598 | }; | |
3599 | ||
3600 | /* l4_cfg -> c2c_target_fw */ | |
3601 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = { | |
3602 | .master = &omap44xx_l4_cfg_hwmod, | |
3603 | .slave = &omap44xx_c2c_target_fw_hwmod, | |
3604 | .clk = "l4_div_ck", | |
3605 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3606 | }; | |
3607 | ||
844a3b63 PW |
3608 | /* l3_main_1 -> dmm */ |
3609 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { | |
3610 | .master = &omap44xx_l3_main_1_hwmod, | |
3611 | .slave = &omap44xx_dmm_hwmod, | |
3612 | .clk = "l3_div_ck", | |
3613 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
3614 | }; |
3615 | ||
844a3b63 | 3616 | static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { |
af88fa9a | 3617 | { |
844a3b63 PW |
3618 | .pa_start = 0x4e000000, |
3619 | .pa_end = 0x4e0007ff, | |
af88fa9a BC |
3620 | .flags = ADDR_TYPE_RT |
3621 | }, | |
844a3b63 | 3622 | { } |
af88fa9a BC |
3623 | }; |
3624 | ||
844a3b63 PW |
3625 | /* mpu -> dmm */ |
3626 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { | |
3627 | .master = &omap44xx_mpu_hwmod, | |
3628 | .slave = &omap44xx_dmm_hwmod, | |
3629 | .clk = "l3_div_ck", | |
3630 | .addr = omap44xx_dmm_addrs, | |
3631 | .user = OCP_USER_MPU, | |
af88fa9a BC |
3632 | }; |
3633 | ||
42b9e387 PW |
3634 | /* c2c -> emif_fw */ |
3635 | static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = { | |
3636 | .master = &omap44xx_c2c_hwmod, | |
3637 | .slave = &omap44xx_emif_fw_hwmod, | |
3638 | .clk = "div_core_ck", | |
3639 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3640 | }; | |
3641 | ||
844a3b63 PW |
3642 | /* dmm -> emif_fw */ |
3643 | static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { | |
3644 | .master = &omap44xx_dmm_hwmod, | |
3645 | .slave = &omap44xx_emif_fw_hwmod, | |
3646 | .clk = "l3_div_ck", | |
3647 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3648 | }; | |
3649 | ||
3650 | static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { | |
3651 | { | |
3652 | .pa_start = 0x4a20c000, | |
3653 | .pa_end = 0x4a20c0ff, | |
3654 | .flags = ADDR_TYPE_RT | |
3655 | }, | |
3656 | { } | |
3657 | }; | |
3658 | ||
3659 | /* l4_cfg -> emif_fw */ | |
3660 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { | |
3661 | .master = &omap44xx_l4_cfg_hwmod, | |
3662 | .slave = &omap44xx_emif_fw_hwmod, | |
3663 | .clk = "l4_div_ck", | |
3664 | .addr = omap44xx_emif_fw_addrs, | |
3665 | .user = OCP_USER_MPU, | |
3666 | }; | |
3667 | ||
3668 | /* iva -> l3_instr */ | |
3669 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { | |
3670 | .master = &omap44xx_iva_hwmod, | |
3671 | .slave = &omap44xx_l3_instr_hwmod, | |
3672 | .clk = "l3_div_ck", | |
3673 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3674 | }; | |
3675 | ||
3676 | /* l3_main_3 -> l3_instr */ | |
3677 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { | |
3678 | .master = &omap44xx_l3_main_3_hwmod, | |
3679 | .slave = &omap44xx_l3_instr_hwmod, | |
3680 | .clk = "l3_div_ck", | |
3681 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3682 | }; | |
3683 | ||
9a817bc8 BC |
3684 | /* ocp_wp_noc -> l3_instr */ |
3685 | static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = { | |
3686 | .master = &omap44xx_ocp_wp_noc_hwmod, | |
3687 | .slave = &omap44xx_l3_instr_hwmod, | |
3688 | .clk = "l3_div_ck", | |
3689 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3690 | }; | |
3691 | ||
844a3b63 PW |
3692 | /* dsp -> l3_main_1 */ |
3693 | static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { | |
3694 | .master = &omap44xx_dsp_hwmod, | |
3695 | .slave = &omap44xx_l3_main_1_hwmod, | |
3696 | .clk = "l3_div_ck", | |
3697 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3698 | }; | |
3699 | ||
3700 | /* dss -> l3_main_1 */ | |
3701 | static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { | |
3702 | .master = &omap44xx_dss_hwmod, | |
3703 | .slave = &omap44xx_l3_main_1_hwmod, | |
3704 | .clk = "l3_div_ck", | |
3705 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3706 | }; | |
3707 | ||
3708 | /* l3_main_2 -> l3_main_1 */ | |
3709 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { | |
3710 | .master = &omap44xx_l3_main_2_hwmod, | |
3711 | .slave = &omap44xx_l3_main_1_hwmod, | |
3712 | .clk = "l3_div_ck", | |
3713 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3714 | }; | |
3715 | ||
3716 | /* l4_cfg -> l3_main_1 */ | |
3717 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { | |
3718 | .master = &omap44xx_l4_cfg_hwmod, | |
3719 | .slave = &omap44xx_l3_main_1_hwmod, | |
3720 | .clk = "l4_div_ck", | |
3721 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3722 | }; | |
3723 | ||
3724 | /* mmc1 -> l3_main_1 */ | |
3725 | static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { | |
3726 | .master = &omap44xx_mmc1_hwmod, | |
3727 | .slave = &omap44xx_l3_main_1_hwmod, | |
3728 | .clk = "l3_div_ck", | |
3729 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3730 | }; | |
3731 | ||
3732 | /* mmc2 -> l3_main_1 */ | |
3733 | static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { | |
3734 | .master = &omap44xx_mmc2_hwmod, | |
3735 | .slave = &omap44xx_l3_main_1_hwmod, | |
3736 | .clk = "l3_div_ck", | |
3737 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3738 | }; | |
3739 | ||
3740 | static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { | |
3741 | { | |
3742 | .pa_start = 0x44000000, | |
3743 | .pa_end = 0x44000fff, | |
3744 | .flags = ADDR_TYPE_RT | |
3745 | }, | |
3746 | { } | |
3747 | }; | |
3748 | ||
3749 | /* mpu -> l3_main_1 */ | |
3750 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { | |
3751 | .master = &omap44xx_mpu_hwmod, | |
3752 | .slave = &omap44xx_l3_main_1_hwmod, | |
3753 | .clk = "l3_div_ck", | |
3754 | .addr = omap44xx_l3_main_1_addrs, | |
3755 | .user = OCP_USER_MPU, | |
3756 | }; | |
3757 | ||
42b9e387 PW |
3758 | /* c2c_target_fw -> l3_main_2 */ |
3759 | static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = { | |
3760 | .master = &omap44xx_c2c_target_fw_hwmod, | |
3761 | .slave = &omap44xx_l3_main_2_hwmod, | |
3762 | .clk = "l3_div_ck", | |
3763 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3764 | }; | |
3765 | ||
96566043 BC |
3766 | /* debugss -> l3_main_2 */ |
3767 | static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = { | |
3768 | .master = &omap44xx_debugss_hwmod, | |
3769 | .slave = &omap44xx_l3_main_2_hwmod, | |
3770 | .clk = "dbgclk_mux_ck", | |
3771 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3772 | }; | |
3773 | ||
844a3b63 PW |
3774 | /* dma_system -> l3_main_2 */ |
3775 | static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { | |
3776 | .master = &omap44xx_dma_system_hwmod, | |
3777 | .slave = &omap44xx_l3_main_2_hwmod, | |
3778 | .clk = "l3_div_ck", | |
3779 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3780 | }; | |
3781 | ||
b050f688 ML |
3782 | /* fdif -> l3_main_2 */ |
3783 | static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = { | |
3784 | .master = &omap44xx_fdif_hwmod, | |
3785 | .slave = &omap44xx_l3_main_2_hwmod, | |
3786 | .clk = "l3_div_ck", | |
3787 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3788 | }; | |
3789 | ||
9def390e PW |
3790 | /* gpu -> l3_main_2 */ |
3791 | static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = { | |
3792 | .master = &omap44xx_gpu_hwmod, | |
3793 | .slave = &omap44xx_l3_main_2_hwmod, | |
3794 | .clk = "l3_div_ck", | |
3795 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3796 | }; | |
3797 | ||
844a3b63 PW |
3798 | /* hsi -> l3_main_2 */ |
3799 | static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { | |
3800 | .master = &omap44xx_hsi_hwmod, | |
3801 | .slave = &omap44xx_l3_main_2_hwmod, | |
3802 | .clk = "l3_div_ck", | |
3803 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3804 | }; | |
3805 | ||
3806 | /* ipu -> l3_main_2 */ | |
3807 | static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { | |
3808 | .master = &omap44xx_ipu_hwmod, | |
3809 | .slave = &omap44xx_l3_main_2_hwmod, | |
3810 | .clk = "l3_div_ck", | |
3811 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3812 | }; | |
3813 | ||
3814 | /* iss -> l3_main_2 */ | |
3815 | static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { | |
3816 | .master = &omap44xx_iss_hwmod, | |
3817 | .slave = &omap44xx_l3_main_2_hwmod, | |
3818 | .clk = "l3_div_ck", | |
3819 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3820 | }; | |
3821 | ||
3822 | /* iva -> l3_main_2 */ | |
3823 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { | |
3824 | .master = &omap44xx_iva_hwmod, | |
3825 | .slave = &omap44xx_l3_main_2_hwmod, | |
3826 | .clk = "l3_div_ck", | |
3827 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3828 | }; | |
3829 | ||
3830 | static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { | |
3831 | { | |
3832 | .pa_start = 0x44800000, | |
3833 | .pa_end = 0x44801fff, | |
3834 | .flags = ADDR_TYPE_RT | |
3835 | }, | |
3836 | { } | |
3837 | }; | |
3838 | ||
3839 | /* l3_main_1 -> l3_main_2 */ | |
3840 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { | |
3841 | .master = &omap44xx_l3_main_1_hwmod, | |
3842 | .slave = &omap44xx_l3_main_2_hwmod, | |
3843 | .clk = "l3_div_ck", | |
3844 | .addr = omap44xx_l3_main_2_addrs, | |
3845 | .user = OCP_USER_MPU, | |
3846 | }; | |
3847 | ||
3848 | /* l4_cfg -> l3_main_2 */ | |
3849 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { | |
3850 | .master = &omap44xx_l4_cfg_hwmod, | |
3851 | .slave = &omap44xx_l3_main_2_hwmod, | |
3852 | .clk = "l4_div_ck", | |
3853 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3854 | }; | |
3855 | ||
0c668875 | 3856 | /* usb_host_fs -> l3_main_2 */ |
b0a70cc8 | 3857 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = { |
0c668875 BC |
3858 | .master = &omap44xx_usb_host_fs_hwmod, |
3859 | .slave = &omap44xx_l3_main_2_hwmod, | |
3860 | .clk = "l3_div_ck", | |
3861 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3862 | }; | |
3863 | ||
844a3b63 PW |
3864 | /* usb_host_hs -> l3_main_2 */ |
3865 | static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { | |
3866 | .master = &omap44xx_usb_host_hs_hwmod, | |
3867 | .slave = &omap44xx_l3_main_2_hwmod, | |
3868 | .clk = "l3_div_ck", | |
3869 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3870 | }; | |
3871 | ||
3872 | /* usb_otg_hs -> l3_main_2 */ | |
3873 | static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { | |
3874 | .master = &omap44xx_usb_otg_hs_hwmod, | |
3875 | .slave = &omap44xx_l3_main_2_hwmod, | |
3876 | .clk = "l3_div_ck", | |
3877 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3878 | }; | |
3879 | ||
3880 | static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { | |
3881 | { | |
3882 | .pa_start = 0x45000000, | |
3883 | .pa_end = 0x45000fff, | |
3884 | .flags = ADDR_TYPE_RT | |
3885 | }, | |
3886 | { } | |
3887 | }; | |
3888 | ||
3889 | /* l3_main_1 -> l3_main_3 */ | |
3890 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { | |
3891 | .master = &omap44xx_l3_main_1_hwmod, | |
3892 | .slave = &omap44xx_l3_main_3_hwmod, | |
3893 | .clk = "l3_div_ck", | |
3894 | .addr = omap44xx_l3_main_3_addrs, | |
3895 | .user = OCP_USER_MPU, | |
3896 | }; | |
3897 | ||
3898 | /* l3_main_2 -> l3_main_3 */ | |
3899 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { | |
3900 | .master = &omap44xx_l3_main_2_hwmod, | |
3901 | .slave = &omap44xx_l3_main_3_hwmod, | |
3902 | .clk = "l3_div_ck", | |
3903 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3904 | }; | |
3905 | ||
3906 | /* l4_cfg -> l3_main_3 */ | |
3907 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { | |
3908 | .master = &omap44xx_l4_cfg_hwmod, | |
3909 | .slave = &omap44xx_l3_main_3_hwmod, | |
3910 | .clk = "l4_div_ck", | |
3911 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3912 | }; | |
3913 | ||
3914 | /* aess -> l4_abe */ | |
b0a70cc8 | 3915 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = { |
844a3b63 PW |
3916 | .master = &omap44xx_aess_hwmod, |
3917 | .slave = &omap44xx_l4_abe_hwmod, | |
3918 | .clk = "ocp_abe_iclk", | |
3919 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3920 | }; | |
3921 | ||
3922 | /* dsp -> l4_abe */ | |
3923 | static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { | |
3924 | .master = &omap44xx_dsp_hwmod, | |
3925 | .slave = &omap44xx_l4_abe_hwmod, | |
3926 | .clk = "ocp_abe_iclk", | |
3927 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3928 | }; | |
3929 | ||
3930 | /* l3_main_1 -> l4_abe */ | |
3931 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { | |
3932 | .master = &omap44xx_l3_main_1_hwmod, | |
3933 | .slave = &omap44xx_l4_abe_hwmod, | |
3934 | .clk = "l3_div_ck", | |
3935 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3936 | }; | |
3937 | ||
3938 | /* mpu -> l4_abe */ | |
3939 | static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { | |
3940 | .master = &omap44xx_mpu_hwmod, | |
3941 | .slave = &omap44xx_l4_abe_hwmod, | |
3942 | .clk = "ocp_abe_iclk", | |
3943 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3944 | }; | |
3945 | ||
3946 | /* l3_main_1 -> l4_cfg */ | |
3947 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { | |
3948 | .master = &omap44xx_l3_main_1_hwmod, | |
3949 | .slave = &omap44xx_l4_cfg_hwmod, | |
3950 | .clk = "l3_div_ck", | |
3951 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3952 | }; | |
3953 | ||
3954 | /* l3_main_2 -> l4_per */ | |
3955 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { | |
3956 | .master = &omap44xx_l3_main_2_hwmod, | |
3957 | .slave = &omap44xx_l4_per_hwmod, | |
3958 | .clk = "l3_div_ck", | |
3959 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3960 | }; | |
3961 | ||
3962 | /* l4_cfg -> l4_wkup */ | |
3963 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { | |
3964 | .master = &omap44xx_l4_cfg_hwmod, | |
3965 | .slave = &omap44xx_l4_wkup_hwmod, | |
3966 | .clk = "l4_div_ck", | |
3967 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3968 | }; | |
3969 | ||
3970 | /* mpu -> mpu_private */ | |
3971 | static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { | |
3972 | .master = &omap44xx_mpu_hwmod, | |
3973 | .slave = &omap44xx_mpu_private_hwmod, | |
3974 | .clk = "l3_div_ck", | |
3975 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3976 | }; | |
3977 | ||
9a817bc8 BC |
3978 | static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = { |
3979 | { | |
3980 | .pa_start = 0x4a102000, | |
3981 | .pa_end = 0x4a10207f, | |
3982 | .flags = ADDR_TYPE_RT | |
3983 | }, | |
3984 | { } | |
3985 | }; | |
3986 | ||
3987 | /* l4_cfg -> ocp_wp_noc */ | |
3988 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = { | |
3989 | .master = &omap44xx_l4_cfg_hwmod, | |
3990 | .slave = &omap44xx_ocp_wp_noc_hwmod, | |
3991 | .clk = "l4_div_ck", | |
3992 | .addr = omap44xx_ocp_wp_noc_addrs, | |
3993 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3994 | }; | |
3995 | ||
844a3b63 PW |
3996 | static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { |
3997 | { | |
3998 | .pa_start = 0x401f1000, | |
3999 | .pa_end = 0x401f13ff, | |
4000 | .flags = ADDR_TYPE_RT | |
4001 | }, | |
4002 | { } | |
4003 | }; | |
4004 | ||
4005 | /* l4_abe -> aess */ | |
b0a70cc8 | 4006 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = { |
844a3b63 PW |
4007 | .master = &omap44xx_l4_abe_hwmod, |
4008 | .slave = &omap44xx_aess_hwmod, | |
4009 | .clk = "ocp_abe_iclk", | |
4010 | .addr = omap44xx_aess_addrs, | |
4011 | .user = OCP_USER_MPU, | |
4012 | }; | |
4013 | ||
4014 | static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { | |
4015 | { | |
4016 | .pa_start = 0x490f1000, | |
4017 | .pa_end = 0x490f13ff, | |
4018 | .flags = ADDR_TYPE_RT | |
4019 | }, | |
4020 | { } | |
4021 | }; | |
4022 | ||
4023 | /* l4_abe -> aess (dma) */ | |
b0a70cc8 | 4024 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = { |
844a3b63 PW |
4025 | .master = &omap44xx_l4_abe_hwmod, |
4026 | .slave = &omap44xx_aess_hwmod, | |
4027 | .clk = "ocp_abe_iclk", | |
4028 | .addr = omap44xx_aess_dma_addrs, | |
4029 | .user = OCP_USER_SDMA, | |
4030 | }; | |
4031 | ||
42b9e387 PW |
4032 | /* l3_main_2 -> c2c */ |
4033 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = { | |
4034 | .master = &omap44xx_l3_main_2_hwmod, | |
4035 | .slave = &omap44xx_c2c_hwmod, | |
4036 | .clk = "l3_div_ck", | |
4037 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4038 | }; | |
4039 | ||
844a3b63 PW |
4040 | static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { |
4041 | { | |
4042 | .pa_start = 0x4a304000, | |
4043 | .pa_end = 0x4a30401f, | |
4044 | .flags = ADDR_TYPE_RT | |
4045 | }, | |
4046 | { } | |
4047 | }; | |
4048 | ||
4049 | /* l4_wkup -> counter_32k */ | |
4050 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { | |
4051 | .master = &omap44xx_l4_wkup_hwmod, | |
4052 | .slave = &omap44xx_counter_32k_hwmod, | |
4053 | .clk = "l4_wkup_clk_mux_ck", | |
4054 | .addr = omap44xx_counter_32k_addrs, | |
4055 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4056 | }; | |
4057 | ||
a0b5d813 PW |
4058 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = { |
4059 | { | |
4060 | .pa_start = 0x4a002000, | |
4061 | .pa_end = 0x4a0027ff, | |
4062 | .flags = ADDR_TYPE_RT | |
4063 | }, | |
4064 | { } | |
4065 | }; | |
4066 | ||
4067 | /* l4_cfg -> ctrl_module_core */ | |
4068 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = { | |
4069 | .master = &omap44xx_l4_cfg_hwmod, | |
4070 | .slave = &omap44xx_ctrl_module_core_hwmod, | |
4071 | .clk = "l4_div_ck", | |
4072 | .addr = omap44xx_ctrl_module_core_addrs, | |
4073 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4074 | }; | |
4075 | ||
4076 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = { | |
4077 | { | |
4078 | .pa_start = 0x4a100000, | |
4079 | .pa_end = 0x4a1007ff, | |
4080 | .flags = ADDR_TYPE_RT | |
4081 | }, | |
4082 | { } | |
4083 | }; | |
4084 | ||
4085 | /* l4_cfg -> ctrl_module_pad_core */ | |
4086 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = { | |
4087 | .master = &omap44xx_l4_cfg_hwmod, | |
4088 | .slave = &omap44xx_ctrl_module_pad_core_hwmod, | |
4089 | .clk = "l4_div_ck", | |
4090 | .addr = omap44xx_ctrl_module_pad_core_addrs, | |
4091 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4092 | }; | |
4093 | ||
4094 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = { | |
4095 | { | |
4096 | .pa_start = 0x4a30c000, | |
4097 | .pa_end = 0x4a30c7ff, | |
4098 | .flags = ADDR_TYPE_RT | |
4099 | }, | |
4100 | { } | |
4101 | }; | |
4102 | ||
4103 | /* l4_wkup -> ctrl_module_wkup */ | |
4104 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = { | |
4105 | .master = &omap44xx_l4_wkup_hwmod, | |
4106 | .slave = &omap44xx_ctrl_module_wkup_hwmod, | |
4107 | .clk = "l4_wkup_clk_mux_ck", | |
4108 | .addr = omap44xx_ctrl_module_wkup_addrs, | |
4109 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4110 | }; | |
4111 | ||
4112 | static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = { | |
4113 | { | |
4114 | .pa_start = 0x4a31e000, | |
4115 | .pa_end = 0x4a31e7ff, | |
4116 | .flags = ADDR_TYPE_RT | |
4117 | }, | |
4118 | { } | |
4119 | }; | |
4120 | ||
4121 | /* l4_wkup -> ctrl_module_pad_wkup */ | |
4122 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = { | |
4123 | .master = &omap44xx_l4_wkup_hwmod, | |
4124 | .slave = &omap44xx_ctrl_module_pad_wkup_hwmod, | |
4125 | .clk = "l4_wkup_clk_mux_ck", | |
4126 | .addr = omap44xx_ctrl_module_pad_wkup_addrs, | |
4127 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4128 | }; | |
4129 | ||
96566043 BC |
4130 | static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = { |
4131 | { | |
4132 | .pa_start = 0x54160000, | |
4133 | .pa_end = 0x54167fff, | |
4134 | .flags = ADDR_TYPE_RT | |
4135 | }, | |
4136 | { } | |
4137 | }; | |
4138 | ||
4139 | /* l3_instr -> debugss */ | |
4140 | static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = { | |
4141 | .master = &omap44xx_l3_instr_hwmod, | |
4142 | .slave = &omap44xx_debugss_hwmod, | |
4143 | .clk = "l3_div_ck", | |
4144 | .addr = omap44xx_debugss_addrs, | |
4145 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4146 | }; | |
4147 | ||
844a3b63 PW |
4148 | static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { |
4149 | { | |
4150 | .pa_start = 0x4a056000, | |
4151 | .pa_end = 0x4a056fff, | |
4152 | .flags = ADDR_TYPE_RT | |
4153 | }, | |
4154 | { } | |
4155 | }; | |
4156 | ||
4157 | /* l4_cfg -> dma_system */ | |
4158 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { | |
4159 | .master = &omap44xx_l4_cfg_hwmod, | |
4160 | .slave = &omap44xx_dma_system_hwmod, | |
4161 | .clk = "l4_div_ck", | |
4162 | .addr = omap44xx_dma_system_addrs, | |
4163 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4164 | }; | |
4165 | ||
4166 | static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { | |
4167 | { | |
4168 | .name = "mpu", | |
4169 | .pa_start = 0x4012e000, | |
4170 | .pa_end = 0x4012e07f, | |
4171 | .flags = ADDR_TYPE_RT | |
4172 | }, | |
4173 | { } | |
4174 | }; | |
4175 | ||
4176 | /* l4_abe -> dmic */ | |
4177 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { | |
4178 | .master = &omap44xx_l4_abe_hwmod, | |
4179 | .slave = &omap44xx_dmic_hwmod, | |
4180 | .clk = "ocp_abe_iclk", | |
4181 | .addr = omap44xx_dmic_addrs, | |
4182 | .user = OCP_USER_MPU, | |
4183 | }; | |
4184 | ||
4185 | static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { | |
4186 | { | |
4187 | .name = "dma", | |
4188 | .pa_start = 0x4902e000, | |
4189 | .pa_end = 0x4902e07f, | |
4190 | .flags = ADDR_TYPE_RT | |
4191 | }, | |
4192 | { } | |
4193 | }; | |
4194 | ||
4195 | /* l4_abe -> dmic (dma) */ | |
4196 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { | |
4197 | .master = &omap44xx_l4_abe_hwmod, | |
4198 | .slave = &omap44xx_dmic_hwmod, | |
4199 | .clk = "ocp_abe_iclk", | |
4200 | .addr = omap44xx_dmic_dma_addrs, | |
4201 | .user = OCP_USER_SDMA, | |
4202 | }; | |
4203 | ||
4204 | /* dsp -> iva */ | |
4205 | static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { | |
4206 | .master = &omap44xx_dsp_hwmod, | |
4207 | .slave = &omap44xx_iva_hwmod, | |
4208 | .clk = "dpll_iva_m5x2_ck", | |
4209 | .user = OCP_USER_DSP, | |
4210 | }; | |
4211 | ||
42b9e387 PW |
4212 | /* dsp -> sl2if */ |
4213 | static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = { | |
4214 | .master = &omap44xx_dsp_hwmod, | |
4215 | .slave = &omap44xx_sl2if_hwmod, | |
4216 | .clk = "dpll_iva_m5x2_ck", | |
4217 | .user = OCP_USER_DSP, | |
4218 | }; | |
4219 | ||
844a3b63 PW |
4220 | /* l4_cfg -> dsp */ |
4221 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { | |
4222 | .master = &omap44xx_l4_cfg_hwmod, | |
4223 | .slave = &omap44xx_dsp_hwmod, | |
4224 | .clk = "l4_div_ck", | |
4225 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4226 | }; | |
4227 | ||
4228 | static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { | |
4229 | { | |
4230 | .pa_start = 0x58000000, | |
4231 | .pa_end = 0x5800007f, | |
4232 | .flags = ADDR_TYPE_RT | |
4233 | }, | |
4234 | { } | |
4235 | }; | |
4236 | ||
4237 | /* l3_main_2 -> dss */ | |
4238 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { | |
4239 | .master = &omap44xx_l3_main_2_hwmod, | |
4240 | .slave = &omap44xx_dss_hwmod, | |
4241 | .clk = "dss_fck", | |
4242 | .addr = omap44xx_dss_dma_addrs, | |
4243 | .user = OCP_USER_SDMA, | |
4244 | }; | |
4245 | ||
4246 | static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { | |
4247 | { | |
4248 | .pa_start = 0x48040000, | |
4249 | .pa_end = 0x4804007f, | |
4250 | .flags = ADDR_TYPE_RT | |
4251 | }, | |
4252 | { } | |
4253 | }; | |
4254 | ||
4255 | /* l4_per -> dss */ | |
4256 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { | |
4257 | .master = &omap44xx_l4_per_hwmod, | |
4258 | .slave = &omap44xx_dss_hwmod, | |
4259 | .clk = "l4_div_ck", | |
4260 | .addr = omap44xx_dss_addrs, | |
4261 | .user = OCP_USER_MPU, | |
4262 | }; | |
4263 | ||
4264 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { | |
4265 | { | |
4266 | .pa_start = 0x58001000, | |
4267 | .pa_end = 0x58001fff, | |
4268 | .flags = ADDR_TYPE_RT | |
4269 | }, | |
4270 | { } | |
4271 | }; | |
4272 | ||
4273 | /* l3_main_2 -> dss_dispc */ | |
4274 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { | |
4275 | .master = &omap44xx_l3_main_2_hwmod, | |
4276 | .slave = &omap44xx_dss_dispc_hwmod, | |
4277 | .clk = "dss_fck", | |
4278 | .addr = omap44xx_dss_dispc_dma_addrs, | |
4279 | .user = OCP_USER_SDMA, | |
4280 | }; | |
4281 | ||
4282 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { | |
4283 | { | |
4284 | .pa_start = 0x48041000, | |
4285 | .pa_end = 0x48041fff, | |
4286 | .flags = ADDR_TYPE_RT | |
4287 | }, | |
4288 | { } | |
4289 | }; | |
4290 | ||
4291 | /* l4_per -> dss_dispc */ | |
4292 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { | |
4293 | .master = &omap44xx_l4_per_hwmod, | |
4294 | .slave = &omap44xx_dss_dispc_hwmod, | |
4295 | .clk = "l4_div_ck", | |
4296 | .addr = omap44xx_dss_dispc_addrs, | |
4297 | .user = OCP_USER_MPU, | |
4298 | }; | |
4299 | ||
4300 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { | |
4301 | { | |
4302 | .pa_start = 0x58004000, | |
4303 | .pa_end = 0x580041ff, | |
4304 | .flags = ADDR_TYPE_RT | |
4305 | }, | |
4306 | { } | |
4307 | }; | |
4308 | ||
4309 | /* l3_main_2 -> dss_dsi1 */ | |
4310 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { | |
4311 | .master = &omap44xx_l3_main_2_hwmod, | |
4312 | .slave = &omap44xx_dss_dsi1_hwmod, | |
4313 | .clk = "dss_fck", | |
4314 | .addr = omap44xx_dss_dsi1_dma_addrs, | |
4315 | .user = OCP_USER_SDMA, | |
4316 | }; | |
4317 | ||
4318 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { | |
4319 | { | |
4320 | .pa_start = 0x48044000, | |
4321 | .pa_end = 0x480441ff, | |
4322 | .flags = ADDR_TYPE_RT | |
4323 | }, | |
4324 | { } | |
4325 | }; | |
4326 | ||
4327 | /* l4_per -> dss_dsi1 */ | |
4328 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { | |
4329 | .master = &omap44xx_l4_per_hwmod, | |
4330 | .slave = &omap44xx_dss_dsi1_hwmod, | |
4331 | .clk = "l4_div_ck", | |
4332 | .addr = omap44xx_dss_dsi1_addrs, | |
4333 | .user = OCP_USER_MPU, | |
4334 | }; | |
4335 | ||
4336 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { | |
4337 | { | |
4338 | .pa_start = 0x58005000, | |
4339 | .pa_end = 0x580051ff, | |
4340 | .flags = ADDR_TYPE_RT | |
4341 | }, | |
4342 | { } | |
4343 | }; | |
4344 | ||
4345 | /* l3_main_2 -> dss_dsi2 */ | |
4346 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { | |
4347 | .master = &omap44xx_l3_main_2_hwmod, | |
4348 | .slave = &omap44xx_dss_dsi2_hwmod, | |
4349 | .clk = "dss_fck", | |
4350 | .addr = omap44xx_dss_dsi2_dma_addrs, | |
4351 | .user = OCP_USER_SDMA, | |
4352 | }; | |
4353 | ||
4354 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { | |
4355 | { | |
4356 | .pa_start = 0x48045000, | |
4357 | .pa_end = 0x480451ff, | |
4358 | .flags = ADDR_TYPE_RT | |
4359 | }, | |
4360 | { } | |
4361 | }; | |
4362 | ||
4363 | /* l4_per -> dss_dsi2 */ | |
4364 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { | |
4365 | .master = &omap44xx_l4_per_hwmod, | |
4366 | .slave = &omap44xx_dss_dsi2_hwmod, | |
4367 | .clk = "l4_div_ck", | |
4368 | .addr = omap44xx_dss_dsi2_addrs, | |
4369 | .user = OCP_USER_MPU, | |
4370 | }; | |
4371 | ||
4372 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { | |
4373 | { | |
4374 | .pa_start = 0x58006000, | |
4375 | .pa_end = 0x58006fff, | |
4376 | .flags = ADDR_TYPE_RT | |
4377 | }, | |
4378 | { } | |
4379 | }; | |
4380 | ||
4381 | /* l3_main_2 -> dss_hdmi */ | |
4382 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { | |
4383 | .master = &omap44xx_l3_main_2_hwmod, | |
4384 | .slave = &omap44xx_dss_hdmi_hwmod, | |
4385 | .clk = "dss_fck", | |
4386 | .addr = omap44xx_dss_hdmi_dma_addrs, | |
4387 | .user = OCP_USER_SDMA, | |
4388 | }; | |
4389 | ||
4390 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { | |
4391 | { | |
4392 | .pa_start = 0x48046000, | |
4393 | .pa_end = 0x48046fff, | |
4394 | .flags = ADDR_TYPE_RT | |
4395 | }, | |
4396 | { } | |
4397 | }; | |
4398 | ||
4399 | /* l4_per -> dss_hdmi */ | |
4400 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { | |
4401 | .master = &omap44xx_l4_per_hwmod, | |
4402 | .slave = &omap44xx_dss_hdmi_hwmod, | |
4403 | .clk = "l4_div_ck", | |
4404 | .addr = omap44xx_dss_hdmi_addrs, | |
4405 | .user = OCP_USER_MPU, | |
4406 | }; | |
4407 | ||
4408 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { | |
4409 | { | |
4410 | .pa_start = 0x58002000, | |
4411 | .pa_end = 0x580020ff, | |
4412 | .flags = ADDR_TYPE_RT | |
4413 | }, | |
4414 | { } | |
4415 | }; | |
4416 | ||
4417 | /* l3_main_2 -> dss_rfbi */ | |
4418 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { | |
4419 | .master = &omap44xx_l3_main_2_hwmod, | |
4420 | .slave = &omap44xx_dss_rfbi_hwmod, | |
4421 | .clk = "dss_fck", | |
4422 | .addr = omap44xx_dss_rfbi_dma_addrs, | |
4423 | .user = OCP_USER_SDMA, | |
4424 | }; | |
4425 | ||
4426 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { | |
4427 | { | |
4428 | .pa_start = 0x48042000, | |
4429 | .pa_end = 0x480420ff, | |
4430 | .flags = ADDR_TYPE_RT | |
4431 | }, | |
4432 | { } | |
4433 | }; | |
4434 | ||
4435 | /* l4_per -> dss_rfbi */ | |
4436 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { | |
4437 | .master = &omap44xx_l4_per_hwmod, | |
4438 | .slave = &omap44xx_dss_rfbi_hwmod, | |
4439 | .clk = "l4_div_ck", | |
4440 | .addr = omap44xx_dss_rfbi_addrs, | |
4441 | .user = OCP_USER_MPU, | |
4442 | }; | |
4443 | ||
4444 | static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { | |
4445 | { | |
4446 | .pa_start = 0x58003000, | |
4447 | .pa_end = 0x580030ff, | |
4448 | .flags = ADDR_TYPE_RT | |
4449 | }, | |
4450 | { } | |
4451 | }; | |
4452 | ||
4453 | /* l3_main_2 -> dss_venc */ | |
4454 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { | |
4455 | .master = &omap44xx_l3_main_2_hwmod, | |
4456 | .slave = &omap44xx_dss_venc_hwmod, | |
4457 | .clk = "dss_fck", | |
4458 | .addr = omap44xx_dss_venc_dma_addrs, | |
4459 | .user = OCP_USER_SDMA, | |
4460 | }; | |
4461 | ||
4462 | static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { | |
4463 | { | |
4464 | .pa_start = 0x48043000, | |
4465 | .pa_end = 0x480430ff, | |
4466 | .flags = ADDR_TYPE_RT | |
4467 | }, | |
4468 | { } | |
4469 | }; | |
4470 | ||
4471 | /* l4_per -> dss_venc */ | |
4472 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { | |
4473 | .master = &omap44xx_l4_per_hwmod, | |
4474 | .slave = &omap44xx_dss_venc_hwmod, | |
4475 | .clk = "l4_div_ck", | |
4476 | .addr = omap44xx_dss_venc_addrs, | |
4477 | .user = OCP_USER_MPU, | |
4478 | }; | |
4479 | ||
42b9e387 PW |
4480 | static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = { |
4481 | { | |
4482 | .pa_start = 0x48078000, | |
4483 | .pa_end = 0x48078fff, | |
4484 | .flags = ADDR_TYPE_RT | |
4485 | }, | |
4486 | { } | |
4487 | }; | |
4488 | ||
4489 | /* l4_per -> elm */ | |
4490 | static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = { | |
4491 | .master = &omap44xx_l4_per_hwmod, | |
4492 | .slave = &omap44xx_elm_hwmod, | |
4493 | .clk = "l4_div_ck", | |
4494 | .addr = omap44xx_elm_addrs, | |
4495 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4496 | }; | |
4497 | ||
bf30f950 PW |
4498 | static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = { |
4499 | { | |
4500 | .pa_start = 0x4c000000, | |
4501 | .pa_end = 0x4c0000ff, | |
4502 | .flags = ADDR_TYPE_RT | |
4503 | }, | |
4504 | { } | |
4505 | }; | |
4506 | ||
4507 | /* emif_fw -> emif1 */ | |
4508 | static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = { | |
4509 | .master = &omap44xx_emif_fw_hwmod, | |
4510 | .slave = &omap44xx_emif1_hwmod, | |
4511 | .clk = "l3_div_ck", | |
4512 | .addr = omap44xx_emif1_addrs, | |
4513 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4514 | }; | |
4515 | ||
4516 | static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = { | |
4517 | { | |
4518 | .pa_start = 0x4d000000, | |
4519 | .pa_end = 0x4d0000ff, | |
4520 | .flags = ADDR_TYPE_RT | |
4521 | }, | |
4522 | { } | |
4523 | }; | |
4524 | ||
4525 | /* emif_fw -> emif2 */ | |
4526 | static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = { | |
4527 | .master = &omap44xx_emif_fw_hwmod, | |
4528 | .slave = &omap44xx_emif2_hwmod, | |
4529 | .clk = "l3_div_ck", | |
4530 | .addr = omap44xx_emif2_addrs, | |
4531 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4532 | }; | |
4533 | ||
b050f688 ML |
4534 | static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = { |
4535 | { | |
4536 | .pa_start = 0x4a10a000, | |
4537 | .pa_end = 0x4a10a1ff, | |
4538 | .flags = ADDR_TYPE_RT | |
4539 | }, | |
4540 | { } | |
4541 | }; | |
4542 | ||
4543 | /* l4_cfg -> fdif */ | |
4544 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = { | |
4545 | .master = &omap44xx_l4_cfg_hwmod, | |
4546 | .slave = &omap44xx_fdif_hwmod, | |
4547 | .clk = "l4_div_ck", | |
4548 | .addr = omap44xx_fdif_addrs, | |
4549 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4550 | }; | |
4551 | ||
844a3b63 PW |
4552 | static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { |
4553 | { | |
4554 | .pa_start = 0x4a310000, | |
4555 | .pa_end = 0x4a3101ff, | |
4556 | .flags = ADDR_TYPE_RT | |
4557 | }, | |
4558 | { } | |
4559 | }; | |
4560 | ||
4561 | /* l4_wkup -> gpio1 */ | |
4562 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { | |
4563 | .master = &omap44xx_l4_wkup_hwmod, | |
4564 | .slave = &omap44xx_gpio1_hwmod, | |
4565 | .clk = "l4_wkup_clk_mux_ck", | |
4566 | .addr = omap44xx_gpio1_addrs, | |
4567 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4568 | }; | |
4569 | ||
4570 | static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { | |
4571 | { | |
4572 | .pa_start = 0x48055000, | |
4573 | .pa_end = 0x480551ff, | |
4574 | .flags = ADDR_TYPE_RT | |
4575 | }, | |
4576 | { } | |
4577 | }; | |
4578 | ||
4579 | /* l4_per -> gpio2 */ | |
4580 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { | |
4581 | .master = &omap44xx_l4_per_hwmod, | |
4582 | .slave = &omap44xx_gpio2_hwmod, | |
4583 | .clk = "l4_div_ck", | |
4584 | .addr = omap44xx_gpio2_addrs, | |
4585 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4586 | }; | |
4587 | ||
4588 | static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { | |
4589 | { | |
4590 | .pa_start = 0x48057000, | |
4591 | .pa_end = 0x480571ff, | |
4592 | .flags = ADDR_TYPE_RT | |
4593 | }, | |
4594 | { } | |
4595 | }; | |
4596 | ||
4597 | /* l4_per -> gpio3 */ | |
4598 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { | |
4599 | .master = &omap44xx_l4_per_hwmod, | |
4600 | .slave = &omap44xx_gpio3_hwmod, | |
4601 | .clk = "l4_div_ck", | |
4602 | .addr = omap44xx_gpio3_addrs, | |
4603 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4604 | }; | |
4605 | ||
4606 | static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { | |
4607 | { | |
4608 | .pa_start = 0x48059000, | |
4609 | .pa_end = 0x480591ff, | |
4610 | .flags = ADDR_TYPE_RT | |
4611 | }, | |
4612 | { } | |
4613 | }; | |
4614 | ||
4615 | /* l4_per -> gpio4 */ | |
4616 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { | |
4617 | .master = &omap44xx_l4_per_hwmod, | |
4618 | .slave = &omap44xx_gpio4_hwmod, | |
4619 | .clk = "l4_div_ck", | |
4620 | .addr = omap44xx_gpio4_addrs, | |
4621 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4622 | }; | |
4623 | ||
4624 | static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { | |
4625 | { | |
4626 | .pa_start = 0x4805b000, | |
4627 | .pa_end = 0x4805b1ff, | |
4628 | .flags = ADDR_TYPE_RT | |
4629 | }, | |
4630 | { } | |
4631 | }; | |
4632 | ||
4633 | /* l4_per -> gpio5 */ | |
4634 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { | |
4635 | .master = &omap44xx_l4_per_hwmod, | |
4636 | .slave = &omap44xx_gpio5_hwmod, | |
4637 | .clk = "l4_div_ck", | |
4638 | .addr = omap44xx_gpio5_addrs, | |
4639 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4640 | }; | |
4641 | ||
4642 | static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { | |
4643 | { | |
4644 | .pa_start = 0x4805d000, | |
4645 | .pa_end = 0x4805d1ff, | |
4646 | .flags = ADDR_TYPE_RT | |
4647 | }, | |
4648 | { } | |
4649 | }; | |
4650 | ||
4651 | /* l4_per -> gpio6 */ | |
4652 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { | |
4653 | .master = &omap44xx_l4_per_hwmod, | |
4654 | .slave = &omap44xx_gpio6_hwmod, | |
4655 | .clk = "l4_div_ck", | |
4656 | .addr = omap44xx_gpio6_addrs, | |
4657 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4658 | }; | |
4659 | ||
eb42b5d3 BC |
4660 | static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = { |
4661 | { | |
4662 | .pa_start = 0x50000000, | |
4663 | .pa_end = 0x500003ff, | |
4664 | .flags = ADDR_TYPE_RT | |
4665 | }, | |
4666 | { } | |
4667 | }; | |
4668 | ||
4669 | /* l3_main_2 -> gpmc */ | |
4670 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { | |
4671 | .master = &omap44xx_l3_main_2_hwmod, | |
4672 | .slave = &omap44xx_gpmc_hwmod, | |
4673 | .clk = "l3_div_ck", | |
4674 | .addr = omap44xx_gpmc_addrs, | |
4675 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4676 | }; | |
4677 | ||
9def390e PW |
4678 | static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = { |
4679 | { | |
4680 | .pa_start = 0x56000000, | |
4681 | .pa_end = 0x5600ffff, | |
4682 | .flags = ADDR_TYPE_RT | |
4683 | }, | |
4684 | { } | |
4685 | }; | |
4686 | ||
4687 | /* l3_main_2 -> gpu */ | |
4688 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = { | |
4689 | .master = &omap44xx_l3_main_2_hwmod, | |
4690 | .slave = &omap44xx_gpu_hwmod, | |
4691 | .clk = "l3_div_ck", | |
4692 | .addr = omap44xx_gpu_addrs, | |
4693 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4694 | }; | |
4695 | ||
a091c08e PW |
4696 | static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = { |
4697 | { | |
4698 | .pa_start = 0x480b2000, | |
4699 | .pa_end = 0x480b201f, | |
4700 | .flags = ADDR_TYPE_RT | |
4701 | }, | |
4702 | { } | |
4703 | }; | |
4704 | ||
4705 | /* l4_per -> hdq1w */ | |
4706 | static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = { | |
4707 | .master = &omap44xx_l4_per_hwmod, | |
4708 | .slave = &omap44xx_hdq1w_hwmod, | |
4709 | .clk = "l4_div_ck", | |
4710 | .addr = omap44xx_hdq1w_addrs, | |
4711 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4712 | }; | |
4713 | ||
844a3b63 PW |
4714 | static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { |
4715 | { | |
4716 | .pa_start = 0x4a058000, | |
4717 | .pa_end = 0x4a05bfff, | |
4718 | .flags = ADDR_TYPE_RT | |
4719 | }, | |
4720 | { } | |
4721 | }; | |
4722 | ||
4723 | /* l4_cfg -> hsi */ | |
4724 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { | |
4725 | .master = &omap44xx_l4_cfg_hwmod, | |
4726 | .slave = &omap44xx_hsi_hwmod, | |
4727 | .clk = "l4_div_ck", | |
4728 | .addr = omap44xx_hsi_addrs, | |
4729 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4730 | }; | |
4731 | ||
4732 | static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { | |
4733 | { | |
4734 | .pa_start = 0x48070000, | |
4735 | .pa_end = 0x480700ff, | |
4736 | .flags = ADDR_TYPE_RT | |
4737 | }, | |
4738 | { } | |
4739 | }; | |
4740 | ||
4741 | /* l4_per -> i2c1 */ | |
4742 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { | |
4743 | .master = &omap44xx_l4_per_hwmod, | |
4744 | .slave = &omap44xx_i2c1_hwmod, | |
4745 | .clk = "l4_div_ck", | |
4746 | .addr = omap44xx_i2c1_addrs, | |
4747 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4748 | }; | |
4749 | ||
4750 | static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { | |
4751 | { | |
4752 | .pa_start = 0x48072000, | |
4753 | .pa_end = 0x480720ff, | |
4754 | .flags = ADDR_TYPE_RT | |
4755 | }, | |
4756 | { } | |
4757 | }; | |
4758 | ||
4759 | /* l4_per -> i2c2 */ | |
4760 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { | |
4761 | .master = &omap44xx_l4_per_hwmod, | |
4762 | .slave = &omap44xx_i2c2_hwmod, | |
4763 | .clk = "l4_div_ck", | |
4764 | .addr = omap44xx_i2c2_addrs, | |
4765 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4766 | }; | |
4767 | ||
4768 | static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { | |
4769 | { | |
4770 | .pa_start = 0x48060000, | |
4771 | .pa_end = 0x480600ff, | |
4772 | .flags = ADDR_TYPE_RT | |
4773 | }, | |
4774 | { } | |
4775 | }; | |
4776 | ||
4777 | /* l4_per -> i2c3 */ | |
4778 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { | |
4779 | .master = &omap44xx_l4_per_hwmod, | |
4780 | .slave = &omap44xx_i2c3_hwmod, | |
4781 | .clk = "l4_div_ck", | |
4782 | .addr = omap44xx_i2c3_addrs, | |
4783 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4784 | }; | |
4785 | ||
4786 | static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { | |
4787 | { | |
4788 | .pa_start = 0x48350000, | |
4789 | .pa_end = 0x483500ff, | |
4790 | .flags = ADDR_TYPE_RT | |
4791 | }, | |
4792 | { } | |
4793 | }; | |
4794 | ||
4795 | /* l4_per -> i2c4 */ | |
4796 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { | |
4797 | .master = &omap44xx_l4_per_hwmod, | |
4798 | .slave = &omap44xx_i2c4_hwmod, | |
4799 | .clk = "l4_div_ck", | |
4800 | .addr = omap44xx_i2c4_addrs, | |
4801 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4802 | }; | |
4803 | ||
4804 | /* l3_main_2 -> ipu */ | |
4805 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { | |
4806 | .master = &omap44xx_l3_main_2_hwmod, | |
4807 | .slave = &omap44xx_ipu_hwmod, | |
4808 | .clk = "l3_div_ck", | |
4809 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4810 | }; | |
4811 | ||
4812 | static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { | |
4813 | { | |
4814 | .pa_start = 0x52000000, | |
4815 | .pa_end = 0x520000ff, | |
4816 | .flags = ADDR_TYPE_RT | |
4817 | }, | |
4818 | { } | |
4819 | }; | |
4820 | ||
4821 | /* l3_main_2 -> iss */ | |
4822 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { | |
4823 | .master = &omap44xx_l3_main_2_hwmod, | |
4824 | .slave = &omap44xx_iss_hwmod, | |
4825 | .clk = "l3_div_ck", | |
4826 | .addr = omap44xx_iss_addrs, | |
4827 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4828 | }; | |
4829 | ||
42b9e387 PW |
4830 | /* iva -> sl2if */ |
4831 | static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = { | |
4832 | .master = &omap44xx_iva_hwmod, | |
4833 | .slave = &omap44xx_sl2if_hwmod, | |
4834 | .clk = "dpll_iva_m5x2_ck", | |
4835 | .user = OCP_USER_IVA, | |
4836 | }; | |
4837 | ||
844a3b63 PW |
4838 | static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { |
4839 | { | |
4840 | .pa_start = 0x5a000000, | |
4841 | .pa_end = 0x5a07ffff, | |
4842 | .flags = ADDR_TYPE_RT | |
4843 | }, | |
4844 | { } | |
4845 | }; | |
4846 | ||
4847 | /* l3_main_2 -> iva */ | |
4848 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { | |
4849 | .master = &omap44xx_l3_main_2_hwmod, | |
4850 | .slave = &omap44xx_iva_hwmod, | |
4851 | .clk = "l3_div_ck", | |
4852 | .addr = omap44xx_iva_addrs, | |
4853 | .user = OCP_USER_MPU, | |
4854 | }; | |
4855 | ||
4856 | static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { | |
4857 | { | |
4858 | .pa_start = 0x4a31c000, | |
4859 | .pa_end = 0x4a31c07f, | |
4860 | .flags = ADDR_TYPE_RT | |
4861 | }, | |
4862 | { } | |
4863 | }; | |
4864 | ||
4865 | /* l4_wkup -> kbd */ | |
4866 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { | |
4867 | .master = &omap44xx_l4_wkup_hwmod, | |
4868 | .slave = &omap44xx_kbd_hwmod, | |
4869 | .clk = "l4_wkup_clk_mux_ck", | |
4870 | .addr = omap44xx_kbd_addrs, | |
4871 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4872 | }; | |
4873 | ||
4874 | static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { | |
4875 | { | |
4876 | .pa_start = 0x4a0f4000, | |
4877 | .pa_end = 0x4a0f41ff, | |
4878 | .flags = ADDR_TYPE_RT | |
4879 | }, | |
4880 | { } | |
4881 | }; | |
4882 | ||
4883 | /* l4_cfg -> mailbox */ | |
4884 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { | |
4885 | .master = &omap44xx_l4_cfg_hwmod, | |
4886 | .slave = &omap44xx_mailbox_hwmod, | |
4887 | .clk = "l4_div_ck", | |
4888 | .addr = omap44xx_mailbox_addrs, | |
4889 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
4890 | }; | |
4891 | ||
896d4e98 BC |
4892 | static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = { |
4893 | { | |
4894 | .pa_start = 0x40128000, | |
4895 | .pa_end = 0x401283ff, | |
4896 | .flags = ADDR_TYPE_RT | |
4897 | }, | |
4898 | { } | |
4899 | }; | |
4900 | ||
4901 | /* l4_abe -> mcasp */ | |
4902 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = { | |
4903 | .master = &omap44xx_l4_abe_hwmod, | |
4904 | .slave = &omap44xx_mcasp_hwmod, | |
4905 | .clk = "ocp_abe_iclk", | |
4906 | .addr = omap44xx_mcasp_addrs, | |
4907 | .user = OCP_USER_MPU, | |
4908 | }; | |
4909 | ||
4910 | static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = { | |
4911 | { | |
4912 | .pa_start = 0x49028000, | |
4913 | .pa_end = 0x490283ff, | |
4914 | .flags = ADDR_TYPE_RT | |
4915 | }, | |
4916 | { } | |
4917 | }; | |
4918 | ||
4919 | /* l4_abe -> mcasp (dma) */ | |
4920 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = { | |
4921 | .master = &omap44xx_l4_abe_hwmod, | |
4922 | .slave = &omap44xx_mcasp_hwmod, | |
4923 | .clk = "ocp_abe_iclk", | |
4924 | .addr = omap44xx_mcasp_dma_addrs, | |
4925 | .user = OCP_USER_SDMA, | |
4926 | }; | |
4927 | ||
844a3b63 PW |
4928 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { |
4929 | { | |
4930 | .name = "mpu", | |
4931 | .pa_start = 0x40122000, | |
4932 | .pa_end = 0x401220ff, | |
4933 | .flags = ADDR_TYPE_RT | |
4934 | }, | |
4935 | { } | |
4936 | }; | |
4937 | ||
4938 | /* l4_abe -> mcbsp1 */ | |
4939 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { | |
4940 | .master = &omap44xx_l4_abe_hwmod, | |
4941 | .slave = &omap44xx_mcbsp1_hwmod, | |
4942 | .clk = "ocp_abe_iclk", | |
4943 | .addr = omap44xx_mcbsp1_addrs, | |
4944 | .user = OCP_USER_MPU, | |
4945 | }; | |
4946 | ||
4947 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { | |
4948 | { | |
4949 | .name = "dma", | |
4950 | .pa_start = 0x49022000, | |
4951 | .pa_end = 0x490220ff, | |
4952 | .flags = ADDR_TYPE_RT | |
4953 | }, | |
4954 | { } | |
4955 | }; | |
4956 | ||
4957 | /* l4_abe -> mcbsp1 (dma) */ | |
4958 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { | |
4959 | .master = &omap44xx_l4_abe_hwmod, | |
4960 | .slave = &omap44xx_mcbsp1_hwmod, | |
4961 | .clk = "ocp_abe_iclk", | |
4962 | .addr = omap44xx_mcbsp1_dma_addrs, | |
4963 | .user = OCP_USER_SDMA, | |
4964 | }; | |
4965 | ||
4966 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { | |
4967 | { | |
4968 | .name = "mpu", | |
4969 | .pa_start = 0x40124000, | |
4970 | .pa_end = 0x401240ff, | |
4971 | .flags = ADDR_TYPE_RT | |
4972 | }, | |
4973 | { } | |
4974 | }; | |
4975 | ||
4976 | /* l4_abe -> mcbsp2 */ | |
4977 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { | |
4978 | .master = &omap44xx_l4_abe_hwmod, | |
4979 | .slave = &omap44xx_mcbsp2_hwmod, | |
4980 | .clk = "ocp_abe_iclk", | |
4981 | .addr = omap44xx_mcbsp2_addrs, | |
4982 | .user = OCP_USER_MPU, | |
4983 | }; | |
4984 | ||
4985 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { | |
4986 | { | |
4987 | .name = "dma", | |
4988 | .pa_start = 0x49024000, | |
4989 | .pa_end = 0x490240ff, | |
4990 | .flags = ADDR_TYPE_RT | |
4991 | }, | |
4992 | { } | |
4993 | }; | |
4994 | ||
4995 | /* l4_abe -> mcbsp2 (dma) */ | |
4996 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { | |
4997 | .master = &omap44xx_l4_abe_hwmod, | |
4998 | .slave = &omap44xx_mcbsp2_hwmod, | |
4999 | .clk = "ocp_abe_iclk", | |
5000 | .addr = omap44xx_mcbsp2_dma_addrs, | |
5001 | .user = OCP_USER_SDMA, | |
5002 | }; | |
5003 | ||
5004 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { | |
5005 | { | |
5006 | .name = "mpu", | |
5007 | .pa_start = 0x40126000, | |
5008 | .pa_end = 0x401260ff, | |
5009 | .flags = ADDR_TYPE_RT | |
5010 | }, | |
5011 | { } | |
5012 | }; | |
5013 | ||
5014 | /* l4_abe -> mcbsp3 */ | |
5015 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { | |
5016 | .master = &omap44xx_l4_abe_hwmod, | |
5017 | .slave = &omap44xx_mcbsp3_hwmod, | |
5018 | .clk = "ocp_abe_iclk", | |
5019 | .addr = omap44xx_mcbsp3_addrs, | |
5020 | .user = OCP_USER_MPU, | |
5021 | }; | |
5022 | ||
5023 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { | |
5024 | { | |
5025 | .name = "dma", | |
5026 | .pa_start = 0x49026000, | |
5027 | .pa_end = 0x490260ff, | |
5028 | .flags = ADDR_TYPE_RT | |
5029 | }, | |
5030 | { } | |
5031 | }; | |
5032 | ||
5033 | /* l4_abe -> mcbsp3 (dma) */ | |
5034 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { | |
5035 | .master = &omap44xx_l4_abe_hwmod, | |
5036 | .slave = &omap44xx_mcbsp3_hwmod, | |
5037 | .clk = "ocp_abe_iclk", | |
5038 | .addr = omap44xx_mcbsp3_dma_addrs, | |
5039 | .user = OCP_USER_SDMA, | |
5040 | }; | |
5041 | ||
5042 | static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { | |
5043 | { | |
5044 | .pa_start = 0x48096000, | |
5045 | .pa_end = 0x480960ff, | |
5046 | .flags = ADDR_TYPE_RT | |
5047 | }, | |
5048 | { } | |
5049 | }; | |
5050 | ||
5051 | /* l4_per -> mcbsp4 */ | |
5052 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { | |
5053 | .master = &omap44xx_l4_per_hwmod, | |
5054 | .slave = &omap44xx_mcbsp4_hwmod, | |
5055 | .clk = "l4_div_ck", | |
5056 | .addr = omap44xx_mcbsp4_addrs, | |
5057 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5058 | }; | |
5059 | ||
5060 | static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { | |
5061 | { | |
5062 | .pa_start = 0x40132000, | |
5063 | .pa_end = 0x4013207f, | |
5064 | .flags = ADDR_TYPE_RT | |
5065 | }, | |
5066 | { } | |
5067 | }; | |
5068 | ||
5069 | /* l4_abe -> mcpdm */ | |
5070 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { | |
5071 | .master = &omap44xx_l4_abe_hwmod, | |
5072 | .slave = &omap44xx_mcpdm_hwmod, | |
5073 | .clk = "ocp_abe_iclk", | |
5074 | .addr = omap44xx_mcpdm_addrs, | |
5075 | .user = OCP_USER_MPU, | |
5076 | }; | |
5077 | ||
5078 | static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { | |
5079 | { | |
5080 | .pa_start = 0x49032000, | |
5081 | .pa_end = 0x4903207f, | |
5082 | .flags = ADDR_TYPE_RT | |
5083 | }, | |
5084 | { } | |
5085 | }; | |
5086 | ||
5087 | /* l4_abe -> mcpdm (dma) */ | |
5088 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { | |
5089 | .master = &omap44xx_l4_abe_hwmod, | |
5090 | .slave = &omap44xx_mcpdm_hwmod, | |
5091 | .clk = "ocp_abe_iclk", | |
5092 | .addr = omap44xx_mcpdm_dma_addrs, | |
5093 | .user = OCP_USER_SDMA, | |
5094 | }; | |
5095 | ||
5096 | static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { | |
5097 | { | |
5098 | .pa_start = 0x48098000, | |
5099 | .pa_end = 0x480981ff, | |
5100 | .flags = ADDR_TYPE_RT | |
5101 | }, | |
5102 | { } | |
5103 | }; | |
5104 | ||
5105 | /* l4_per -> mcspi1 */ | |
5106 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { | |
5107 | .master = &omap44xx_l4_per_hwmod, | |
5108 | .slave = &omap44xx_mcspi1_hwmod, | |
5109 | .clk = "l4_div_ck", | |
5110 | .addr = omap44xx_mcspi1_addrs, | |
5111 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5112 | }; | |
5113 | ||
5114 | static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { | |
5115 | { | |
5116 | .pa_start = 0x4809a000, | |
5117 | .pa_end = 0x4809a1ff, | |
5118 | .flags = ADDR_TYPE_RT | |
5119 | }, | |
5120 | { } | |
5121 | }; | |
5122 | ||
5123 | /* l4_per -> mcspi2 */ | |
5124 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { | |
5125 | .master = &omap44xx_l4_per_hwmod, | |
5126 | .slave = &omap44xx_mcspi2_hwmod, | |
5127 | .clk = "l4_div_ck", | |
5128 | .addr = omap44xx_mcspi2_addrs, | |
5129 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5130 | }; | |
5131 | ||
5132 | static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { | |
5133 | { | |
5134 | .pa_start = 0x480b8000, | |
5135 | .pa_end = 0x480b81ff, | |
5136 | .flags = ADDR_TYPE_RT | |
5137 | }, | |
5138 | { } | |
5139 | }; | |
5140 | ||
5141 | /* l4_per -> mcspi3 */ | |
5142 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { | |
5143 | .master = &omap44xx_l4_per_hwmod, | |
5144 | .slave = &omap44xx_mcspi3_hwmod, | |
5145 | .clk = "l4_div_ck", | |
5146 | .addr = omap44xx_mcspi3_addrs, | |
5147 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5148 | }; | |
5149 | ||
5150 | static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { | |
5151 | { | |
5152 | .pa_start = 0x480ba000, | |
5153 | .pa_end = 0x480ba1ff, | |
5154 | .flags = ADDR_TYPE_RT | |
5155 | }, | |
5156 | { } | |
5157 | }; | |
5158 | ||
5159 | /* l4_per -> mcspi4 */ | |
5160 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { | |
5161 | .master = &omap44xx_l4_per_hwmod, | |
5162 | .slave = &omap44xx_mcspi4_hwmod, | |
5163 | .clk = "l4_div_ck", | |
5164 | .addr = omap44xx_mcspi4_addrs, | |
5165 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5166 | }; | |
5167 | ||
5168 | static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { | |
5169 | { | |
5170 | .pa_start = 0x4809c000, | |
5171 | .pa_end = 0x4809c3ff, | |
5172 | .flags = ADDR_TYPE_RT | |
5173 | }, | |
5174 | { } | |
5175 | }; | |
5176 | ||
5177 | /* l4_per -> mmc1 */ | |
5178 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { | |
5179 | .master = &omap44xx_l4_per_hwmod, | |
5180 | .slave = &omap44xx_mmc1_hwmod, | |
5181 | .clk = "l4_div_ck", | |
5182 | .addr = omap44xx_mmc1_addrs, | |
5183 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5184 | }; | |
5185 | ||
5186 | static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { | |
5187 | { | |
5188 | .pa_start = 0x480b4000, | |
5189 | .pa_end = 0x480b43ff, | |
5190 | .flags = ADDR_TYPE_RT | |
5191 | }, | |
5192 | { } | |
5193 | }; | |
5194 | ||
5195 | /* l4_per -> mmc2 */ | |
5196 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { | |
5197 | .master = &omap44xx_l4_per_hwmod, | |
5198 | .slave = &omap44xx_mmc2_hwmod, | |
5199 | .clk = "l4_div_ck", | |
5200 | .addr = omap44xx_mmc2_addrs, | |
5201 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5202 | }; | |
5203 | ||
5204 | static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { | |
5205 | { | |
5206 | .pa_start = 0x480ad000, | |
5207 | .pa_end = 0x480ad3ff, | |
5208 | .flags = ADDR_TYPE_RT | |
5209 | }, | |
5210 | { } | |
5211 | }; | |
5212 | ||
5213 | /* l4_per -> mmc3 */ | |
5214 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { | |
5215 | .master = &omap44xx_l4_per_hwmod, | |
5216 | .slave = &omap44xx_mmc3_hwmod, | |
5217 | .clk = "l4_div_ck", | |
5218 | .addr = omap44xx_mmc3_addrs, | |
5219 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5220 | }; | |
5221 | ||
5222 | static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { | |
5223 | { | |
5224 | .pa_start = 0x480d1000, | |
5225 | .pa_end = 0x480d13ff, | |
5226 | .flags = ADDR_TYPE_RT | |
5227 | }, | |
5228 | { } | |
5229 | }; | |
5230 | ||
5231 | /* l4_per -> mmc4 */ | |
5232 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { | |
5233 | .master = &omap44xx_l4_per_hwmod, | |
5234 | .slave = &omap44xx_mmc4_hwmod, | |
5235 | .clk = "l4_div_ck", | |
5236 | .addr = omap44xx_mmc4_addrs, | |
5237 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5238 | }; | |
5239 | ||
5240 | static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { | |
5241 | { | |
5242 | .pa_start = 0x480d5000, | |
5243 | .pa_end = 0x480d53ff, | |
5244 | .flags = ADDR_TYPE_RT | |
5245 | }, | |
5246 | { } | |
5247 | }; | |
5248 | ||
5249 | /* l4_per -> mmc5 */ | |
5250 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { | |
5251 | .master = &omap44xx_l4_per_hwmod, | |
5252 | .slave = &omap44xx_mmc5_hwmod, | |
5253 | .clk = "l4_div_ck", | |
5254 | .addr = omap44xx_mmc5_addrs, | |
5255 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5256 | }; | |
5257 | ||
e17f18c0 PW |
5258 | /* l3_main_2 -> ocmc_ram */ |
5259 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = { | |
5260 | .master = &omap44xx_l3_main_2_hwmod, | |
5261 | .slave = &omap44xx_ocmc_ram_hwmod, | |
5262 | .clk = "l3_div_ck", | |
5263 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5264 | }; | |
5265 | ||
0c668875 BC |
5266 | /* l4_cfg -> ocp2scp_usb_phy */ |
5267 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = { | |
5268 | .master = &omap44xx_l4_cfg_hwmod, | |
5269 | .slave = &omap44xx_ocp2scp_usb_phy_hwmod, | |
5270 | .clk = "l4_div_ck", | |
5271 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5272 | }; | |
5273 | ||
794b480a PW |
5274 | static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = { |
5275 | { | |
5276 | .pa_start = 0x48243000, | |
5277 | .pa_end = 0x48243fff, | |
5278 | .flags = ADDR_TYPE_RT | |
5279 | }, | |
5280 | { } | |
5281 | }; | |
5282 | ||
5283 | /* mpu_private -> prcm_mpu */ | |
5284 | static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = { | |
5285 | .master = &omap44xx_mpu_private_hwmod, | |
5286 | .slave = &omap44xx_prcm_mpu_hwmod, | |
5287 | .clk = "l3_div_ck", | |
5288 | .addr = omap44xx_prcm_mpu_addrs, | |
5289 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5290 | }; | |
5291 | ||
5292 | static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = { | |
5293 | { | |
5294 | .pa_start = 0x4a004000, | |
5295 | .pa_end = 0x4a004fff, | |
5296 | .flags = ADDR_TYPE_RT | |
5297 | }, | |
5298 | { } | |
5299 | }; | |
5300 | ||
5301 | /* l4_wkup -> cm_core_aon */ | |
5302 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = { | |
5303 | .master = &omap44xx_l4_wkup_hwmod, | |
5304 | .slave = &omap44xx_cm_core_aon_hwmod, | |
5305 | .clk = "l4_wkup_clk_mux_ck", | |
5306 | .addr = omap44xx_cm_core_aon_addrs, | |
5307 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5308 | }; | |
5309 | ||
5310 | static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = { | |
5311 | { | |
5312 | .pa_start = 0x4a008000, | |
5313 | .pa_end = 0x4a009fff, | |
5314 | .flags = ADDR_TYPE_RT | |
5315 | }, | |
5316 | { } | |
5317 | }; | |
5318 | ||
5319 | /* l4_cfg -> cm_core */ | |
5320 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = { | |
5321 | .master = &omap44xx_l4_cfg_hwmod, | |
5322 | .slave = &omap44xx_cm_core_hwmod, | |
5323 | .clk = "l4_div_ck", | |
5324 | .addr = omap44xx_cm_core_addrs, | |
5325 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5326 | }; | |
5327 | ||
5328 | static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = { | |
5329 | { | |
5330 | .pa_start = 0x4a306000, | |
5331 | .pa_end = 0x4a307fff, | |
5332 | .flags = ADDR_TYPE_RT | |
5333 | }, | |
5334 | { } | |
5335 | }; | |
5336 | ||
5337 | /* l4_wkup -> prm */ | |
5338 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = { | |
5339 | .master = &omap44xx_l4_wkup_hwmod, | |
5340 | .slave = &omap44xx_prm_hwmod, | |
5341 | .clk = "l4_wkup_clk_mux_ck", | |
5342 | .addr = omap44xx_prm_addrs, | |
5343 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5344 | }; | |
5345 | ||
5346 | static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = { | |
5347 | { | |
5348 | .pa_start = 0x4a30a000, | |
5349 | .pa_end = 0x4a30a7ff, | |
5350 | .flags = ADDR_TYPE_RT | |
5351 | }, | |
5352 | { } | |
5353 | }; | |
5354 | ||
5355 | /* l4_wkup -> scrm */ | |
5356 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = { | |
5357 | .master = &omap44xx_l4_wkup_hwmod, | |
5358 | .slave = &omap44xx_scrm_hwmod, | |
5359 | .clk = "l4_wkup_clk_mux_ck", | |
5360 | .addr = omap44xx_scrm_addrs, | |
5361 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5362 | }; | |
5363 | ||
42b9e387 PW |
5364 | /* l3_main_2 -> sl2if */ |
5365 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = { | |
5366 | .master = &omap44xx_l3_main_2_hwmod, | |
5367 | .slave = &omap44xx_sl2if_hwmod, | |
5368 | .clk = "l3_div_ck", | |
5369 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5370 | }; | |
5371 | ||
1e3b5e59 BC |
5372 | static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = { |
5373 | { | |
5374 | .pa_start = 0x4012c000, | |
5375 | .pa_end = 0x4012c3ff, | |
5376 | .flags = ADDR_TYPE_RT | |
5377 | }, | |
5378 | { } | |
5379 | }; | |
5380 | ||
5381 | /* l4_abe -> slimbus1 */ | |
5382 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = { | |
5383 | .master = &omap44xx_l4_abe_hwmod, | |
5384 | .slave = &omap44xx_slimbus1_hwmod, | |
5385 | .clk = "ocp_abe_iclk", | |
5386 | .addr = omap44xx_slimbus1_addrs, | |
5387 | .user = OCP_USER_MPU, | |
5388 | }; | |
5389 | ||
5390 | static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = { | |
5391 | { | |
5392 | .pa_start = 0x4902c000, | |
5393 | .pa_end = 0x4902c3ff, | |
5394 | .flags = ADDR_TYPE_RT | |
5395 | }, | |
5396 | { } | |
5397 | }; | |
5398 | ||
5399 | /* l4_abe -> slimbus1 (dma) */ | |
5400 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = { | |
5401 | .master = &omap44xx_l4_abe_hwmod, | |
5402 | .slave = &omap44xx_slimbus1_hwmod, | |
5403 | .clk = "ocp_abe_iclk", | |
5404 | .addr = omap44xx_slimbus1_dma_addrs, | |
5405 | .user = OCP_USER_SDMA, | |
5406 | }; | |
5407 | ||
5408 | static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = { | |
5409 | { | |
5410 | .pa_start = 0x48076000, | |
5411 | .pa_end = 0x480763ff, | |
5412 | .flags = ADDR_TYPE_RT | |
5413 | }, | |
5414 | { } | |
5415 | }; | |
5416 | ||
5417 | /* l4_per -> slimbus2 */ | |
5418 | static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = { | |
5419 | .master = &omap44xx_l4_per_hwmod, | |
5420 | .slave = &omap44xx_slimbus2_hwmod, | |
5421 | .clk = "l4_div_ck", | |
5422 | .addr = omap44xx_slimbus2_addrs, | |
5423 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5424 | }; | |
5425 | ||
844a3b63 PW |
5426 | static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { |
5427 | { | |
5428 | .pa_start = 0x4a0dd000, | |
5429 | .pa_end = 0x4a0dd03f, | |
5430 | .flags = ADDR_TYPE_RT | |
5431 | }, | |
5432 | { } | |
5433 | }; | |
5434 | ||
5435 | /* l4_cfg -> smartreflex_core */ | |
5436 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { | |
5437 | .master = &omap44xx_l4_cfg_hwmod, | |
5438 | .slave = &omap44xx_smartreflex_core_hwmod, | |
5439 | .clk = "l4_div_ck", | |
5440 | .addr = omap44xx_smartreflex_core_addrs, | |
5441 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5442 | }; | |
5443 | ||
5444 | static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { | |
5445 | { | |
5446 | .pa_start = 0x4a0db000, | |
5447 | .pa_end = 0x4a0db03f, | |
5448 | .flags = ADDR_TYPE_RT | |
5449 | }, | |
5450 | { } | |
5451 | }; | |
5452 | ||
5453 | /* l4_cfg -> smartreflex_iva */ | |
5454 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { | |
5455 | .master = &omap44xx_l4_cfg_hwmod, | |
5456 | .slave = &omap44xx_smartreflex_iva_hwmod, | |
5457 | .clk = "l4_div_ck", | |
5458 | .addr = omap44xx_smartreflex_iva_addrs, | |
5459 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5460 | }; | |
5461 | ||
5462 | static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { | |
5463 | { | |
5464 | .pa_start = 0x4a0d9000, | |
5465 | .pa_end = 0x4a0d903f, | |
5466 | .flags = ADDR_TYPE_RT | |
5467 | }, | |
5468 | { } | |
5469 | }; | |
5470 | ||
5471 | /* l4_cfg -> smartreflex_mpu */ | |
5472 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { | |
5473 | .master = &omap44xx_l4_cfg_hwmod, | |
5474 | .slave = &omap44xx_smartreflex_mpu_hwmod, | |
5475 | .clk = "l4_div_ck", | |
5476 | .addr = omap44xx_smartreflex_mpu_addrs, | |
5477 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5478 | }; | |
5479 | ||
5480 | static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { | |
5481 | { | |
5482 | .pa_start = 0x4a0f6000, | |
5483 | .pa_end = 0x4a0f6fff, | |
5484 | .flags = ADDR_TYPE_RT | |
5485 | }, | |
5486 | { } | |
5487 | }; | |
5488 | ||
5489 | /* l4_cfg -> spinlock */ | |
5490 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { | |
5491 | .master = &omap44xx_l4_cfg_hwmod, | |
5492 | .slave = &omap44xx_spinlock_hwmod, | |
5493 | .clk = "l4_div_ck", | |
5494 | .addr = omap44xx_spinlock_addrs, | |
5495 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5496 | }; | |
5497 | ||
5498 | static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { | |
5499 | { | |
5500 | .pa_start = 0x4a318000, | |
5501 | .pa_end = 0x4a31807f, | |
5502 | .flags = ADDR_TYPE_RT | |
5503 | }, | |
5504 | { } | |
5505 | }; | |
5506 | ||
5507 | /* l4_wkup -> timer1 */ | |
5508 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { | |
5509 | .master = &omap44xx_l4_wkup_hwmod, | |
5510 | .slave = &omap44xx_timer1_hwmod, | |
5511 | .clk = "l4_wkup_clk_mux_ck", | |
5512 | .addr = omap44xx_timer1_addrs, | |
5513 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5514 | }; | |
5515 | ||
5516 | static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { | |
5517 | { | |
5518 | .pa_start = 0x48032000, | |
5519 | .pa_end = 0x4803207f, | |
5520 | .flags = ADDR_TYPE_RT | |
5521 | }, | |
5522 | { } | |
5523 | }; | |
5524 | ||
5525 | /* l4_per -> timer2 */ | |
5526 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { | |
5527 | .master = &omap44xx_l4_per_hwmod, | |
5528 | .slave = &omap44xx_timer2_hwmod, | |
5529 | .clk = "l4_div_ck", | |
5530 | .addr = omap44xx_timer2_addrs, | |
5531 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5532 | }; | |
5533 | ||
5534 | static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { | |
5535 | { | |
5536 | .pa_start = 0x48034000, | |
5537 | .pa_end = 0x4803407f, | |
5538 | .flags = ADDR_TYPE_RT | |
5539 | }, | |
5540 | { } | |
5541 | }; | |
5542 | ||
5543 | /* l4_per -> timer3 */ | |
5544 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { | |
5545 | .master = &omap44xx_l4_per_hwmod, | |
5546 | .slave = &omap44xx_timer3_hwmod, | |
5547 | .clk = "l4_div_ck", | |
5548 | .addr = omap44xx_timer3_addrs, | |
5549 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5550 | }; | |
5551 | ||
5552 | static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { | |
5553 | { | |
5554 | .pa_start = 0x48036000, | |
5555 | .pa_end = 0x4803607f, | |
5556 | .flags = ADDR_TYPE_RT | |
5557 | }, | |
5558 | { } | |
5559 | }; | |
5560 | ||
5561 | /* l4_per -> timer4 */ | |
5562 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { | |
5563 | .master = &omap44xx_l4_per_hwmod, | |
5564 | .slave = &omap44xx_timer4_hwmod, | |
5565 | .clk = "l4_div_ck", | |
5566 | .addr = omap44xx_timer4_addrs, | |
5567 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5568 | }; | |
5569 | ||
5570 | static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { | |
5571 | { | |
5572 | .pa_start = 0x40138000, | |
5573 | .pa_end = 0x4013807f, | |
5574 | .flags = ADDR_TYPE_RT | |
5575 | }, | |
5576 | { } | |
5577 | }; | |
5578 | ||
5579 | /* l4_abe -> timer5 */ | |
5580 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { | |
5581 | .master = &omap44xx_l4_abe_hwmod, | |
5582 | .slave = &omap44xx_timer5_hwmod, | |
5583 | .clk = "ocp_abe_iclk", | |
5584 | .addr = omap44xx_timer5_addrs, | |
5585 | .user = OCP_USER_MPU, | |
5586 | }; | |
5587 | ||
5588 | static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { | |
5589 | { | |
5590 | .pa_start = 0x49038000, | |
5591 | .pa_end = 0x4903807f, | |
5592 | .flags = ADDR_TYPE_RT | |
5593 | }, | |
5594 | { } | |
5595 | }; | |
5596 | ||
5597 | /* l4_abe -> timer5 (dma) */ | |
5598 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { | |
5599 | .master = &omap44xx_l4_abe_hwmod, | |
5600 | .slave = &omap44xx_timer5_hwmod, | |
5601 | .clk = "ocp_abe_iclk", | |
5602 | .addr = omap44xx_timer5_dma_addrs, | |
5603 | .user = OCP_USER_SDMA, | |
5604 | }; | |
5605 | ||
5606 | static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { | |
5607 | { | |
5608 | .pa_start = 0x4013a000, | |
5609 | .pa_end = 0x4013a07f, | |
5610 | .flags = ADDR_TYPE_RT | |
5611 | }, | |
5612 | { } | |
5613 | }; | |
5614 | ||
5615 | /* l4_abe -> timer6 */ | |
5616 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { | |
5617 | .master = &omap44xx_l4_abe_hwmod, | |
5618 | .slave = &omap44xx_timer6_hwmod, | |
5619 | .clk = "ocp_abe_iclk", | |
5620 | .addr = omap44xx_timer6_addrs, | |
5621 | .user = OCP_USER_MPU, | |
5622 | }; | |
5623 | ||
5624 | static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { | |
5625 | { | |
5626 | .pa_start = 0x4903a000, | |
5627 | .pa_end = 0x4903a07f, | |
5628 | .flags = ADDR_TYPE_RT | |
5629 | }, | |
5630 | { } | |
5631 | }; | |
5632 | ||
5633 | /* l4_abe -> timer6 (dma) */ | |
5634 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { | |
5635 | .master = &omap44xx_l4_abe_hwmod, | |
5636 | .slave = &omap44xx_timer6_hwmod, | |
5637 | .clk = "ocp_abe_iclk", | |
5638 | .addr = omap44xx_timer6_dma_addrs, | |
5639 | .user = OCP_USER_SDMA, | |
5640 | }; | |
5641 | ||
5642 | static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { | |
5643 | { | |
5644 | .pa_start = 0x4013c000, | |
5645 | .pa_end = 0x4013c07f, | |
5646 | .flags = ADDR_TYPE_RT | |
5647 | }, | |
5648 | { } | |
5649 | }; | |
5650 | ||
5651 | /* l4_abe -> timer7 */ | |
5652 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { | |
5653 | .master = &omap44xx_l4_abe_hwmod, | |
5654 | .slave = &omap44xx_timer7_hwmod, | |
5655 | .clk = "ocp_abe_iclk", | |
5656 | .addr = omap44xx_timer7_addrs, | |
5657 | .user = OCP_USER_MPU, | |
5658 | }; | |
5659 | ||
5660 | static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { | |
5661 | { | |
5662 | .pa_start = 0x4903c000, | |
5663 | .pa_end = 0x4903c07f, | |
5664 | .flags = ADDR_TYPE_RT | |
5665 | }, | |
5666 | { } | |
5667 | }; | |
5668 | ||
5669 | /* l4_abe -> timer7 (dma) */ | |
5670 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { | |
5671 | .master = &omap44xx_l4_abe_hwmod, | |
5672 | .slave = &omap44xx_timer7_hwmod, | |
5673 | .clk = "ocp_abe_iclk", | |
5674 | .addr = omap44xx_timer7_dma_addrs, | |
5675 | .user = OCP_USER_SDMA, | |
5676 | }; | |
5677 | ||
5678 | static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { | |
5679 | { | |
5680 | .pa_start = 0x4013e000, | |
5681 | .pa_end = 0x4013e07f, | |
5682 | .flags = ADDR_TYPE_RT | |
5683 | }, | |
5684 | { } | |
5685 | }; | |
5686 | ||
5687 | /* l4_abe -> timer8 */ | |
5688 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { | |
5689 | .master = &omap44xx_l4_abe_hwmod, | |
5690 | .slave = &omap44xx_timer8_hwmod, | |
5691 | .clk = "ocp_abe_iclk", | |
5692 | .addr = omap44xx_timer8_addrs, | |
5693 | .user = OCP_USER_MPU, | |
5694 | }; | |
5695 | ||
5696 | static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { | |
5697 | { | |
5698 | .pa_start = 0x4903e000, | |
5699 | .pa_end = 0x4903e07f, | |
5700 | .flags = ADDR_TYPE_RT | |
5701 | }, | |
5702 | { } | |
5703 | }; | |
5704 | ||
5705 | /* l4_abe -> timer8 (dma) */ | |
5706 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { | |
5707 | .master = &omap44xx_l4_abe_hwmod, | |
5708 | .slave = &omap44xx_timer8_hwmod, | |
5709 | .clk = "ocp_abe_iclk", | |
5710 | .addr = omap44xx_timer8_dma_addrs, | |
5711 | .user = OCP_USER_SDMA, | |
5712 | }; | |
5713 | ||
5714 | static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { | |
5715 | { | |
5716 | .pa_start = 0x4803e000, | |
5717 | .pa_end = 0x4803e07f, | |
5718 | .flags = ADDR_TYPE_RT | |
5719 | }, | |
5720 | { } | |
5721 | }; | |
5722 | ||
5723 | /* l4_per -> timer9 */ | |
5724 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { | |
5725 | .master = &omap44xx_l4_per_hwmod, | |
5726 | .slave = &omap44xx_timer9_hwmod, | |
5727 | .clk = "l4_div_ck", | |
5728 | .addr = omap44xx_timer9_addrs, | |
5729 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5730 | }; | |
5731 | ||
5732 | static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { | |
5733 | { | |
5734 | .pa_start = 0x48086000, | |
5735 | .pa_end = 0x4808607f, | |
5736 | .flags = ADDR_TYPE_RT | |
5737 | }, | |
5738 | { } | |
5739 | }; | |
5740 | ||
5741 | /* l4_per -> timer10 */ | |
5742 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { | |
5743 | .master = &omap44xx_l4_per_hwmod, | |
5744 | .slave = &omap44xx_timer10_hwmod, | |
5745 | .clk = "l4_div_ck", | |
5746 | .addr = omap44xx_timer10_addrs, | |
5747 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5748 | }; | |
5749 | ||
5750 | static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { | |
5751 | { | |
5752 | .pa_start = 0x48088000, | |
5753 | .pa_end = 0x4808807f, | |
5754 | .flags = ADDR_TYPE_RT | |
5755 | }, | |
5756 | { } | |
5757 | }; | |
5758 | ||
5759 | /* l4_per -> timer11 */ | |
5760 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { | |
5761 | .master = &omap44xx_l4_per_hwmod, | |
5762 | .slave = &omap44xx_timer11_hwmod, | |
5763 | .clk = "l4_div_ck", | |
5764 | .addr = omap44xx_timer11_addrs, | |
af88fa9a BC |
5765 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
5766 | }; | |
5767 | ||
844a3b63 PW |
5768 | static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { |
5769 | { | |
5770 | .pa_start = 0x4806a000, | |
5771 | .pa_end = 0x4806a0ff, | |
5772 | .flags = ADDR_TYPE_RT | |
af88fa9a | 5773 | }, |
844a3b63 PW |
5774 | { } |
5775 | }; | |
af88fa9a | 5776 | |
844a3b63 PW |
5777 | /* l4_per -> uart1 */ |
5778 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { | |
5779 | .master = &omap44xx_l4_per_hwmod, | |
5780 | .slave = &omap44xx_uart1_hwmod, | |
5781 | .clk = "l4_div_ck", | |
5782 | .addr = omap44xx_uart1_addrs, | |
5783 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5784 | }; | |
af88fa9a | 5785 | |
844a3b63 PW |
5786 | static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { |
5787 | { | |
5788 | .pa_start = 0x4806c000, | |
5789 | .pa_end = 0x4806c0ff, | |
5790 | .flags = ADDR_TYPE_RT | |
5791 | }, | |
5792 | { } | |
5793 | }; | |
af88fa9a | 5794 | |
844a3b63 PW |
5795 | /* l4_per -> uart2 */ |
5796 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { | |
5797 | .master = &omap44xx_l4_per_hwmod, | |
5798 | .slave = &omap44xx_uart2_hwmod, | |
5799 | .clk = "l4_div_ck", | |
5800 | .addr = omap44xx_uart2_addrs, | |
5801 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5802 | }; | |
af88fa9a | 5803 | |
844a3b63 PW |
5804 | static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { |
5805 | { | |
5806 | .pa_start = 0x48020000, | |
5807 | .pa_end = 0x480200ff, | |
5808 | .flags = ADDR_TYPE_RT | |
5809 | }, | |
5810 | { } | |
af88fa9a BC |
5811 | }; |
5812 | ||
844a3b63 PW |
5813 | /* l4_per -> uart3 */ |
5814 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { | |
5815 | .master = &omap44xx_l4_per_hwmod, | |
5816 | .slave = &omap44xx_uart3_hwmod, | |
5817 | .clk = "l4_div_ck", | |
5818 | .addr = omap44xx_uart3_addrs, | |
5819 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
af88fa9a BC |
5820 | }; |
5821 | ||
844a3b63 PW |
5822 | static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { |
5823 | { | |
5824 | .pa_start = 0x4806e000, | |
5825 | .pa_end = 0x4806e0ff, | |
5826 | .flags = ADDR_TYPE_RT | |
5827 | }, | |
5828 | { } | |
af88fa9a BC |
5829 | }; |
5830 | ||
844a3b63 PW |
5831 | /* l4_per -> uart4 */ |
5832 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { | |
5833 | .master = &omap44xx_l4_per_hwmod, | |
5834 | .slave = &omap44xx_uart4_hwmod, | |
5835 | .clk = "l4_div_ck", | |
5836 | .addr = omap44xx_uart4_addrs, | |
5837 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5838 | }; | |
5839 | ||
0c668875 BC |
5840 | static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = { |
5841 | { | |
5842 | .pa_start = 0x4a0a9000, | |
5843 | .pa_end = 0x4a0a93ff, | |
5844 | .flags = ADDR_TYPE_RT | |
5845 | }, | |
5846 | { } | |
5847 | }; | |
5848 | ||
5849 | /* l4_cfg -> usb_host_fs */ | |
b0a70cc8 | 5850 | static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = { |
0c668875 BC |
5851 | .master = &omap44xx_l4_cfg_hwmod, |
5852 | .slave = &omap44xx_usb_host_fs_hwmod, | |
5853 | .clk = "l4_div_ck", | |
5854 | .addr = omap44xx_usb_host_fs_addrs, | |
5855 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5856 | }; | |
5857 | ||
844a3b63 PW |
5858 | static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { |
5859 | { | |
5860 | .name = "uhh", | |
5861 | .pa_start = 0x4a064000, | |
5862 | .pa_end = 0x4a0647ff, | |
5863 | .flags = ADDR_TYPE_RT | |
5864 | }, | |
5865 | { | |
5866 | .name = "ohci", | |
5867 | .pa_start = 0x4a064800, | |
5868 | .pa_end = 0x4a064bff, | |
5869 | }, | |
5870 | { | |
5871 | .name = "ehci", | |
5872 | .pa_start = 0x4a064c00, | |
5873 | .pa_end = 0x4a064fff, | |
5874 | }, | |
5875 | {} | |
5876 | }; | |
5877 | ||
5878 | /* l4_cfg -> usb_host_hs */ | |
5879 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { | |
5880 | .master = &omap44xx_l4_cfg_hwmod, | |
5881 | .slave = &omap44xx_usb_host_hs_hwmod, | |
5882 | .clk = "l4_div_ck", | |
5883 | .addr = omap44xx_usb_host_hs_addrs, | |
5884 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5885 | }; | |
5886 | ||
5887 | static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { | |
5888 | { | |
5889 | .pa_start = 0x4a0ab000, | |
5890 | .pa_end = 0x4a0ab003, | |
5891 | .flags = ADDR_TYPE_RT | |
5892 | }, | |
5893 | { } | |
5894 | }; | |
5895 | ||
5896 | /* l4_cfg -> usb_otg_hs */ | |
5897 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { | |
5898 | .master = &omap44xx_l4_cfg_hwmod, | |
5899 | .slave = &omap44xx_usb_otg_hs_hwmod, | |
5900 | .clk = "l4_div_ck", | |
5901 | .addr = omap44xx_usb_otg_hs_addrs, | |
5902 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
af88fa9a BC |
5903 | }; |
5904 | ||
5905 | static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { | |
5906 | { | |
5907 | .name = "tll", | |
5908 | .pa_start = 0x4a062000, | |
5909 | .pa_end = 0x4a063fff, | |
5910 | .flags = ADDR_TYPE_RT | |
5911 | }, | |
5912 | {} | |
5913 | }; | |
5914 | ||
844a3b63 | 5915 | /* l4_cfg -> usb_tll_hs */ |
af88fa9a BC |
5916 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { |
5917 | .master = &omap44xx_l4_cfg_hwmod, | |
5918 | .slave = &omap44xx_usb_tll_hs_hwmod, | |
5919 | .clk = "l4_div_ck", | |
5920 | .addr = omap44xx_usb_tll_hs_addrs, | |
5921 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5922 | }; | |
5923 | ||
844a3b63 PW |
5924 | static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { |
5925 | { | |
5926 | .pa_start = 0x4a314000, | |
5927 | .pa_end = 0x4a31407f, | |
5928 | .flags = ADDR_TYPE_RT | |
af88fa9a | 5929 | }, |
844a3b63 PW |
5930 | { } |
5931 | }; | |
5932 | ||
5933 | /* l4_wkup -> wd_timer2 */ | |
5934 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { | |
5935 | .master = &omap44xx_l4_wkup_hwmod, | |
5936 | .slave = &omap44xx_wd_timer2_hwmod, | |
5937 | .clk = "l4_wkup_clk_mux_ck", | |
5938 | .addr = omap44xx_wd_timer2_addrs, | |
5939 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
5940 | }; | |
5941 | ||
5942 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { | |
5943 | { | |
5944 | .pa_start = 0x40130000, | |
5945 | .pa_end = 0x4013007f, | |
5946 | .flags = ADDR_TYPE_RT | |
5947 | }, | |
5948 | { } | |
5949 | }; | |
5950 | ||
5951 | /* l4_abe -> wd_timer3 */ | |
5952 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { | |
5953 | .master = &omap44xx_l4_abe_hwmod, | |
5954 | .slave = &omap44xx_wd_timer3_hwmod, | |
5955 | .clk = "ocp_abe_iclk", | |
5956 | .addr = omap44xx_wd_timer3_addrs, | |
5957 | .user = OCP_USER_MPU, | |
5958 | }; | |
5959 | ||
5960 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { | |
5961 | { | |
5962 | .pa_start = 0x49030000, | |
5963 | .pa_end = 0x4903007f, | |
5964 | .flags = ADDR_TYPE_RT | |
5965 | }, | |
5966 | { } | |
5967 | }; | |
5968 | ||
5969 | /* l4_abe -> wd_timer3 (dma) */ | |
5970 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { | |
5971 | .master = &omap44xx_l4_abe_hwmod, | |
5972 | .slave = &omap44xx_wd_timer3_hwmod, | |
5973 | .clk = "ocp_abe_iclk", | |
5974 | .addr = omap44xx_wd_timer3_dma_addrs, | |
5975 | .user = OCP_USER_SDMA, | |
af88fa9a BC |
5976 | }; |
5977 | ||
0a78c5c5 | 5978 | static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { |
42b9e387 PW |
5979 | &omap44xx_c2c__c2c_target_fw, |
5980 | &omap44xx_l4_cfg__c2c_target_fw, | |
0a78c5c5 PW |
5981 | &omap44xx_l3_main_1__dmm, |
5982 | &omap44xx_mpu__dmm, | |
42b9e387 | 5983 | &omap44xx_c2c__emif_fw, |
0a78c5c5 PW |
5984 | &omap44xx_dmm__emif_fw, |
5985 | &omap44xx_l4_cfg__emif_fw, | |
5986 | &omap44xx_iva__l3_instr, | |
5987 | &omap44xx_l3_main_3__l3_instr, | |
9a817bc8 | 5988 | &omap44xx_ocp_wp_noc__l3_instr, |
0a78c5c5 PW |
5989 | &omap44xx_dsp__l3_main_1, |
5990 | &omap44xx_dss__l3_main_1, | |
5991 | &omap44xx_l3_main_2__l3_main_1, | |
5992 | &omap44xx_l4_cfg__l3_main_1, | |
5993 | &omap44xx_mmc1__l3_main_1, | |
5994 | &omap44xx_mmc2__l3_main_1, | |
5995 | &omap44xx_mpu__l3_main_1, | |
42b9e387 | 5996 | &omap44xx_c2c_target_fw__l3_main_2, |
96566043 | 5997 | &omap44xx_debugss__l3_main_2, |
0a78c5c5 | 5998 | &omap44xx_dma_system__l3_main_2, |
b050f688 | 5999 | &omap44xx_fdif__l3_main_2, |
9def390e | 6000 | &omap44xx_gpu__l3_main_2, |
0a78c5c5 PW |
6001 | &omap44xx_hsi__l3_main_2, |
6002 | &omap44xx_ipu__l3_main_2, | |
6003 | &omap44xx_iss__l3_main_2, | |
6004 | &omap44xx_iva__l3_main_2, | |
6005 | &omap44xx_l3_main_1__l3_main_2, | |
6006 | &omap44xx_l4_cfg__l3_main_2, | |
b0a70cc8 | 6007 | /* &omap44xx_usb_host_fs__l3_main_2, */ |
0a78c5c5 PW |
6008 | &omap44xx_usb_host_hs__l3_main_2, |
6009 | &omap44xx_usb_otg_hs__l3_main_2, | |
6010 | &omap44xx_l3_main_1__l3_main_3, | |
6011 | &omap44xx_l3_main_2__l3_main_3, | |
6012 | &omap44xx_l4_cfg__l3_main_3, | |
b0a70cc8 | 6013 | /* &omap44xx_aess__l4_abe, */ |
0a78c5c5 PW |
6014 | &omap44xx_dsp__l4_abe, |
6015 | &omap44xx_l3_main_1__l4_abe, | |
6016 | &omap44xx_mpu__l4_abe, | |
6017 | &omap44xx_l3_main_1__l4_cfg, | |
6018 | &omap44xx_l3_main_2__l4_per, | |
6019 | &omap44xx_l4_cfg__l4_wkup, | |
6020 | &omap44xx_mpu__mpu_private, | |
9a817bc8 | 6021 | &omap44xx_l4_cfg__ocp_wp_noc, |
b0a70cc8 PW |
6022 | /* &omap44xx_l4_abe__aess, */ |
6023 | /* &omap44xx_l4_abe__aess_dma, */ | |
42b9e387 | 6024 | &omap44xx_l3_main_2__c2c, |
0a78c5c5 | 6025 | &omap44xx_l4_wkup__counter_32k, |
a0b5d813 PW |
6026 | &omap44xx_l4_cfg__ctrl_module_core, |
6027 | &omap44xx_l4_cfg__ctrl_module_pad_core, | |
6028 | &omap44xx_l4_wkup__ctrl_module_wkup, | |
6029 | &omap44xx_l4_wkup__ctrl_module_pad_wkup, | |
96566043 | 6030 | &omap44xx_l3_instr__debugss, |
0a78c5c5 PW |
6031 | &omap44xx_l4_cfg__dma_system, |
6032 | &omap44xx_l4_abe__dmic, | |
6033 | &omap44xx_l4_abe__dmic_dma, | |
6034 | &omap44xx_dsp__iva, | |
42b9e387 | 6035 | &omap44xx_dsp__sl2if, |
0a78c5c5 PW |
6036 | &omap44xx_l4_cfg__dsp, |
6037 | &omap44xx_l3_main_2__dss, | |
6038 | &omap44xx_l4_per__dss, | |
6039 | &omap44xx_l3_main_2__dss_dispc, | |
6040 | &omap44xx_l4_per__dss_dispc, | |
6041 | &omap44xx_l3_main_2__dss_dsi1, | |
6042 | &omap44xx_l4_per__dss_dsi1, | |
6043 | &omap44xx_l3_main_2__dss_dsi2, | |
6044 | &omap44xx_l4_per__dss_dsi2, | |
6045 | &omap44xx_l3_main_2__dss_hdmi, | |
6046 | &omap44xx_l4_per__dss_hdmi, | |
6047 | &omap44xx_l3_main_2__dss_rfbi, | |
6048 | &omap44xx_l4_per__dss_rfbi, | |
6049 | &omap44xx_l3_main_2__dss_venc, | |
6050 | &omap44xx_l4_per__dss_venc, | |
42b9e387 | 6051 | &omap44xx_l4_per__elm, |
bf30f950 PW |
6052 | &omap44xx_emif_fw__emif1, |
6053 | &omap44xx_emif_fw__emif2, | |
b050f688 | 6054 | &omap44xx_l4_cfg__fdif, |
0a78c5c5 PW |
6055 | &omap44xx_l4_wkup__gpio1, |
6056 | &omap44xx_l4_per__gpio2, | |
6057 | &omap44xx_l4_per__gpio3, | |
6058 | &omap44xx_l4_per__gpio4, | |
6059 | &omap44xx_l4_per__gpio5, | |
6060 | &omap44xx_l4_per__gpio6, | |
eb42b5d3 | 6061 | &omap44xx_l3_main_2__gpmc, |
9def390e | 6062 | &omap44xx_l3_main_2__gpu, |
a091c08e | 6063 | &omap44xx_l4_per__hdq1w, |
0a78c5c5 PW |
6064 | &omap44xx_l4_cfg__hsi, |
6065 | &omap44xx_l4_per__i2c1, | |
6066 | &omap44xx_l4_per__i2c2, | |
6067 | &omap44xx_l4_per__i2c3, | |
6068 | &omap44xx_l4_per__i2c4, | |
6069 | &omap44xx_l3_main_2__ipu, | |
6070 | &omap44xx_l3_main_2__iss, | |
42b9e387 | 6071 | &omap44xx_iva__sl2if, |
0a78c5c5 PW |
6072 | &omap44xx_l3_main_2__iva, |
6073 | &omap44xx_l4_wkup__kbd, | |
6074 | &omap44xx_l4_cfg__mailbox, | |
896d4e98 BC |
6075 | &omap44xx_l4_abe__mcasp, |
6076 | &omap44xx_l4_abe__mcasp_dma, | |
0a78c5c5 PW |
6077 | &omap44xx_l4_abe__mcbsp1, |
6078 | &omap44xx_l4_abe__mcbsp1_dma, | |
6079 | &omap44xx_l4_abe__mcbsp2, | |
6080 | &omap44xx_l4_abe__mcbsp2_dma, | |
6081 | &omap44xx_l4_abe__mcbsp3, | |
6082 | &omap44xx_l4_abe__mcbsp3_dma, | |
6083 | &omap44xx_l4_per__mcbsp4, | |
6084 | &omap44xx_l4_abe__mcpdm, | |
6085 | &omap44xx_l4_abe__mcpdm_dma, | |
6086 | &omap44xx_l4_per__mcspi1, | |
6087 | &omap44xx_l4_per__mcspi2, | |
6088 | &omap44xx_l4_per__mcspi3, | |
6089 | &omap44xx_l4_per__mcspi4, | |
6090 | &omap44xx_l4_per__mmc1, | |
6091 | &omap44xx_l4_per__mmc2, | |
6092 | &omap44xx_l4_per__mmc3, | |
6093 | &omap44xx_l4_per__mmc4, | |
6094 | &omap44xx_l4_per__mmc5, | |
e17f18c0 | 6095 | &omap44xx_l3_main_2__ocmc_ram, |
0c668875 | 6096 | &omap44xx_l4_cfg__ocp2scp_usb_phy, |
794b480a PW |
6097 | &omap44xx_mpu_private__prcm_mpu, |
6098 | &omap44xx_l4_wkup__cm_core_aon, | |
6099 | &omap44xx_l4_cfg__cm_core, | |
6100 | &omap44xx_l4_wkup__prm, | |
6101 | &omap44xx_l4_wkup__scrm, | |
42b9e387 | 6102 | &omap44xx_l3_main_2__sl2if, |
1e3b5e59 BC |
6103 | &omap44xx_l4_abe__slimbus1, |
6104 | &omap44xx_l4_abe__slimbus1_dma, | |
6105 | &omap44xx_l4_per__slimbus2, | |
0a78c5c5 PW |
6106 | &omap44xx_l4_cfg__smartreflex_core, |
6107 | &omap44xx_l4_cfg__smartreflex_iva, | |
6108 | &omap44xx_l4_cfg__smartreflex_mpu, | |
6109 | &omap44xx_l4_cfg__spinlock, | |
6110 | &omap44xx_l4_wkup__timer1, | |
6111 | &omap44xx_l4_per__timer2, | |
6112 | &omap44xx_l4_per__timer3, | |
6113 | &omap44xx_l4_per__timer4, | |
6114 | &omap44xx_l4_abe__timer5, | |
6115 | &omap44xx_l4_abe__timer5_dma, | |
6116 | &omap44xx_l4_abe__timer6, | |
6117 | &omap44xx_l4_abe__timer6_dma, | |
6118 | &omap44xx_l4_abe__timer7, | |
6119 | &omap44xx_l4_abe__timer7_dma, | |
6120 | &omap44xx_l4_abe__timer8, | |
6121 | &omap44xx_l4_abe__timer8_dma, | |
6122 | &omap44xx_l4_per__timer9, | |
6123 | &omap44xx_l4_per__timer10, | |
6124 | &omap44xx_l4_per__timer11, | |
6125 | &omap44xx_l4_per__uart1, | |
6126 | &omap44xx_l4_per__uart2, | |
6127 | &omap44xx_l4_per__uart3, | |
6128 | &omap44xx_l4_per__uart4, | |
b0a70cc8 | 6129 | /* &omap44xx_l4_cfg__usb_host_fs, */ |
0a78c5c5 PW |
6130 | &omap44xx_l4_cfg__usb_host_hs, |
6131 | &omap44xx_l4_cfg__usb_otg_hs, | |
6132 | &omap44xx_l4_cfg__usb_tll_hs, | |
6133 | &omap44xx_l4_wkup__wd_timer2, | |
6134 | &omap44xx_l4_abe__wd_timer3, | |
6135 | &omap44xx_l4_abe__wd_timer3_dma, | |
55d2cb08 BC |
6136 | NULL, |
6137 | }; | |
6138 | ||
6139 | int __init omap44xx_hwmod_init(void) | |
6140 | { | |
9ebfd285 | 6141 | omap_hwmod_init(); |
0a78c5c5 | 6142 | return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); |
55d2cb08 BC |
6143 | } |
6144 |