[deliverable/linux.git] / arch / arm / mach-omap2 / omap_phy_internal.c

/*
  * This file configures the internal USB PHY in OMAP4430. Used
  * with TWL6030 transceiver and MUSB on OMAP4430.
  *
  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
  *
  * Author: Hema HK <hemahk@ti.com>
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  *
  */

#include <linux/types.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/usb.h>

#include <plat/usb.h>
#include "control.h"

/* OMAP control module register for UTMI PHY */
#define CONTROL_DEV_CONF		0x300
#define PHY_PD				0x1

#define USBOTGHS_CONTROL		0x33c
#define	AVALID				BIT(0)
#define	BVALID				BIT(1)
#define	VBUSVALID			BIT(2)
#define	SESSEND				BIT(3)
#define	IDDIG				BIT(4)

static struct clk *phyclk, *clk48m, *clk32k;
static void __iomem *ctrl_base;
static int usbotghs_control;

int omap4430_phy_init(struct device *dev)
{
	ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
	if (!ctrl_base) {
		dev_err(dev, "control module ioremap failed\n");
		return -ENOMEM;
	}
	/* Power down the phy */
	__raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
	phyclk = clk_get(dev, "ocp2scp_usb_phy_ick");

	if (IS_ERR(phyclk)) {
		dev_err(dev, "cannot clk_get ocp2scp_usb_phy_ick\n");
		iounmap(ctrl_base);
		return PTR_ERR(phyclk);
	}

	clk48m = clk_get(dev, "ocp2scp_usb_phy_phy_48m");
	if (IS_ERR(clk48m)) {
		dev_err(dev, "cannot clk_get ocp2scp_usb_phy_phy_48m\n");
		clk_put(phyclk);
		iounmap(ctrl_base);
		return PTR_ERR(clk48m);
	}

	clk32k = clk_get(dev, "usb_phy_cm_clk32k");
	if (IS_ERR(clk32k)) {
		dev_err(dev, "cannot clk_get usb_phy_cm_clk32k\n");
		clk_put(phyclk);
		clk_put(clk48m);
		iounmap(ctrl_base);
		return PTR_ERR(clk32k);
	}
	return 0;
}

int omap4430_phy_set_clk(struct device *dev, int on)
{
	static int state;

	if (on && !state) {
		/* Enable the phy clocks */
		clk_enable(phyclk);
		clk_enable(clk48m);
		clk_enable(clk32k);
		state = 1;
	} else if (state) {
		/* Disable the phy clocks */
		clk_disable(phyclk);
		clk_disable(clk48m);
		clk_disable(clk32k);
		state = 0;
	}
	return 0;
}

int omap4430_phy_power(struct device *dev, int ID, int on)
{
	if (on) {
		if (ID)
			/* enable VBUS valid, IDDIG groung */
			__raw_writel(AVALID | VBUSVALID, ctrl_base +
							USBOTGHS_CONTROL);
		else
			/*
			 * Enable VBUS Valid, AValid and IDDIG
			 * high impedance
			 */
			__raw_writel(IDDIG | AVALID | VBUSVALID,
						ctrl_base + USBOTGHS_CONTROL);
	} else {
		/* Enable session END and IDIG to high impedance. */
		__raw_writel(SESSEND | IDDIG, ctrl_base +
					USBOTGHS_CONTROL);
	}
	return 0;
}

int omap4430_phy_suspend(struct device *dev, int suspend)
{
	if (suspend) {
		/* Disable the clocks */
		omap4430_phy_set_clk(dev, 0);
		/* Power down the phy */
		__raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);

		/* save the context */
		usbotghs_control = __raw_readl(ctrl_base + USBOTGHS_CONTROL);
	} else {
		/* Enable the internel phy clcoks */
		omap4430_phy_set_clk(dev, 1);
		/* power on the phy */
		if (__raw_readl(ctrl_base + CONTROL_DEV_CONF) & PHY_PD) {
			__raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF);
			mdelay(200);
		}

		/* restore the context */
		__raw_writel(usbotghs_control, ctrl_base + USBOTGHS_CONTROL);
	}

	return 0;
}

int omap4430_phy_exit(struct device *dev)
{
	if (ctrl_base)
		iounmap(ctrl_base);
	if (phyclk)
		clk_put(phyclk);
	if (clk48m)
		clk_put(clk48m);
	if (clk32k)
		clk_put(clk32k);

	return 0;
}

void am35x_musb_reset(void)
{
	u32	regval;

	/* Reset the musb interface */
	regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);

	regval |= AM35XX_USBOTGSS_SW_RST;
	omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);

	regval &= ~AM35XX_USBOTGSS_SW_RST;
	omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);

	regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
}

void am35x_musb_phy_power(u8 on)
{
	unsigned long timeout = jiffies + msecs_to_jiffies(100);
	u32 devconf2;

	if (on) {
		/*
		 * Start the on-chip PHY and its PLL.
		 */
		devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);

		devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
		devconf2 |= CONF2_PHY_PLLON;

		omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);

		pr_info(KERN_INFO "Waiting for PHY clock good...\n");
		while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
				& CONF2_PHYCLKGD)) {
			cpu_relax();

			if (time_after(jiffies, timeout)) {
				pr_err(KERN_ERR "musb PHY clock good timed out\n");
				break;
			}
		}
	} else {
		/*
		 * Power down the on-chip PHY.
		 */
		devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);

		devconf2 &= ~CONF2_PHY_PLLON;
		devconf2 |=  CONF2_PHYPWRDN | CONF2_OTGPWRDN;
		omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
	}
}

void am35x_musb_clear_irq(void)
{
	u32 regval;

	regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
	regval |= AM35XX_USBOTGSS_INT_CLR;
	omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
	regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
}

void am35x_musb_set_mode(u8 musb_mode)
{
	u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);

	devconf2 &= ~CONF2_OTGMODE;
	switch (musb_mode) {
#ifdef	CONFIG_USB_MUSB_HDRC_HCD
	case MUSB_HOST:		/* Force VBUS valid, ID = 0 */
		devconf2 |= CONF2_FORCE_HOST;
		break;
#endif
#ifdef	CONFIG_USB_GADGET_MUSB_HDRC
	case MUSB_PERIPHERAL:	/* Force VBUS valid, ID = 1 */
		devconf2 |= CONF2_FORCE_DEVICE;
		break;
#endif
#ifdef	CONFIG_USB_MUSB_OTG
	case MUSB_OTG:		/* Don't override the VBUS/ID comparators */
		devconf2 |= CONF2_NO_OVERRIDE;
		break;
#endif
	default:
		pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);
	}

	omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
}
Commit	Line	Data
c33fad0c HH	1	/*
	2	* This file configures the internal USB PHY in OMAP4430. Used
	3	* with TWL6030 transceiver and MUSB on OMAP4430.
	4	*
	5	* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* Author: Hema HK <hemahk@ti.com>
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*
	22	*/
	23
	24	#include <linux/types.h>
	25	#include <linux/delay.h>
	26	#include <linux/clk.h>
	27	#include <linux/io.h>
	28	#include <linux/err.h>
	29	#include <linux/usb.h>
	30
	31	#include <plat/usb.h>
fe5a4901	32	#include "control.h"
c33fad0c HH	33
	34	/* OMAP control module register for UTMI PHY */
	35	#define CONTROL_DEV_CONF 0x300
	36	#define PHY_PD 0x1
	37
	38	#define USBOTGHS_CONTROL 0x33c
	39	#define AVALID BIT(0)
	40	#define BVALID BIT(1)
	41	#define VBUSVALID BIT(2)
	42	#define SESSEND BIT(3)
	43	#define IDDIG BIT(4)
	44
	45	static struct clk phyclk, clk48m, *clk32k;
	46	static void __iomem *ctrl_base;
8c59ef38	47	static int usbotghs_control;
c33fad0c HH	48
	49	int omap4430_phy_init(struct device *dev)
	50	{
	51	ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
	52	if (!ctrl_base) {
	53	dev_err(dev, "control module ioremap failed\n");
	54	return -ENOMEM;
	55	}
	56	/* Power down the phy */
	57	__raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
	58	phyclk = clk_get(dev, "ocp2scp_usb_phy_ick");
	59
	60	if (IS_ERR(phyclk)) {
	61	dev_err(dev, "cannot clk_get ocp2scp_usb_phy_ick\n");
	62	iounmap(ctrl_base);
	63	return PTR_ERR(phyclk);
	64	}
	65
	66	clk48m = clk_get(dev, "ocp2scp_usb_phy_phy_48m");
	67	if (IS_ERR(clk48m)) {
	68	dev_err(dev, "cannot clk_get ocp2scp_usb_phy_phy_48m\n");
	69	clk_put(phyclk);
	70	iounmap(ctrl_base);
	71	return PTR_ERR(clk48m);
	72	}
	73
	74	clk32k = clk_get(dev, "usb_phy_cm_clk32k");
	75	if (IS_ERR(clk32k)) {
	76	dev_err(dev, "cannot clk_get usb_phy_cm_clk32k\n");
	77	clk_put(phyclk);
	78	clk_put(clk48m);
	79	iounmap(ctrl_base);
	80	return PTR_ERR(clk32k);
	81	}
	82	return 0;
	83	}
	84
	85	int omap4430_phy_set_clk(struct device *dev, int on)
	86	{
	87	static int state;
	88
	89	if (on && !state) {
	90	/* Enable the phy clocks */
	91	clk_enable(phyclk);
	92	clk_enable(clk48m);
	93	clk_enable(clk32k);
	94	state = 1;
	95	} else if (state) {
	96	/* Disable the phy clocks */
	97	clk_disable(phyclk);
	98	clk_disable(clk48m);
	99	clk_disable(clk32k);
	100	state = 0;
	101	}
	102	return 0;
	103	}
	104
	105	int omap4430_phy_power(struct device *dev, int ID, int on)
	106	{
	107	if (on) {
c33fad0c HH	108	if (ID)
	109	/* enable VBUS valid, IDDIG groung */
	110	__raw_writel(AVALID \| VBUSVALID, ctrl_base +
	111	USBOTGHS_CONTROL);
	112	else
	113	/*
	114	* Enable VBUS Valid, AValid and IDDIG
25985edc	115	* high impedance
c33fad0c HH	116	*/
	117	__raw_writel(IDDIG \| AVALID \| VBUSVALID,
	118	ctrl_base + USBOTGHS_CONTROL);
	119	} else {
25985edc	120	/* Enable session END and IDIG to high impedance. */
c33fad0c HH	121	__raw_writel(SESSEND \| IDDIG, ctrl_base +
c33fad0c HH	122	USBOTGHS_CONTROL);
ee896e34 HH	123	}
	124	return 0;
	125	}
	126
	127	int omap4430_phy_suspend(struct device *dev, int suspend)
	128	{
	129	if (suspend) {
c33fad0c HH	130	/* Disable the clocks */
	131	omap4430_phy_set_clk(dev, 0);
	132	/* Power down the phy */
	133	__raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
8c59ef38 HH	134
	135	/* save the context */
	136	usbotghs_control = __raw_readl(ctrl_base + USBOTGHS_CONTROL);
ee896e34 HH	137	} else {
	138	/* Enable the internel phy clcoks */
	139	omap4430_phy_set_clk(dev, 1);
	140	/* power on the phy */
	141	if (__raw_readl(ctrl_base + CONTROL_DEV_CONF) & PHY_PD) {
	142	__raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF);
	143	mdelay(200);
	144	}
8c59ef38 HH	145
	146	/* restore the context */
	147	__raw_writel(usbotghs_control, ctrl_base + USBOTGHS_CONTROL);
c33fad0c HH	148	}
	149
	150	return 0;
	151	}
	152
	153	int omap4430_phy_exit(struct device *dev)
	154	{
	155	if (ctrl_base)
	156	iounmap(ctrl_base);
	157	if (phyclk)
	158	clk_put(phyclk);
	159	if (clk48m)
	160	clk_put(clk48m);
	161	if (clk32k)
	162	clk_put(clk32k);
	163
	164	return 0;
	165	}
fe5a4901 HH	166
	167	void am35x_musb_reset(void)
	168	{
	169	u32 regval;
	170
	171	/* Reset the musb interface */
	172	regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
	173
	174	regval \|= AM35XX_USBOTGSS_SW_RST;
	175	omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
	176
	177	regval &= ~AM35XX_USBOTGSS_SW_RST;
	178	omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
	179
	180	regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
	181	}
	182
	183	void am35x_musb_phy_power(u8 on)
	184	{
	185	unsigned long timeout = jiffies + msecs_to_jiffies(100);
	186	u32 devconf2;
	187
	188	if (on) {
	189	/*
	190	* Start the on-chip PHY and its PLL.
	191	*/
	192	devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
	193
	194	devconf2 &= ~(CONF2_RESET \| CONF2_PHYPWRDN \| CONF2_OTGPWRDN);
	195	devconf2 \|= CONF2_PHY_PLLON;
	196
	197	omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
	198
	199	pr_info(KERN_INFO "Waiting for PHY clock good...\n");
	200	while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
	201	& CONF2_PHYCLKGD)) {
	202	cpu_relax();
	203
	204	if (time_after(jiffies, timeout)) {
	205	pr_err(KERN_ERR "musb PHY clock good timed out\n");
	206	break;
	207	}
	208	}
	209	} else {
	210	/*
	211	* Power down the on-chip PHY.
	212	*/
	213	devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
	214
	215	devconf2 &= ~CONF2_PHY_PLLON;
	216	devconf2 \|= CONF2_PHYPWRDN \| CONF2_OTGPWRDN;
	217	omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
	218	}
	219	}
	220
	221	void am35x_musb_clear_irq(void)
	222	{
	223	u32 regval;
	224
	225	regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
	226	regval \|= AM35XX_USBOTGSS_INT_CLR;
	227	omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
	228	regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
	229	}
230
231	void am35x_musb_set_mode(u8 musb_mode)
232	{
233	u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
234
235	devconf2 &= ~CONF2_OTGMODE;
236	switch (musb_mode) {
237	#ifdef CONFIG_USB_MUSB_HDRC_HCD
238	case MUSB_HOST: /* Force VBUS valid, ID = 0 */
239	devconf2 \|= CONF2_FORCE_HOST;
240	break;
241	#endif
242	#ifdef CONFIG_USB_GADGET_MUSB_HDRC
243	case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
244	devconf2 \|= CONF2_FORCE_DEVICE;
245	break;
246	#endif
247	#ifdef CONFIG_USB_MUSB_OTG
248	case MUSB_OTG: /* Don't override the VBUS/ID comparators */
249	devconf2 \|= CONF2_NO_OVERRIDE;
250	break;
251	#endif
252	default:
253	pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);
254	}
255
256	omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
257	}