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fbc319f6 TG |
1 | /** |
2 | * OMAP and TWL PMIC specific intializations. | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments Incorporated. | |
5 | * Thara Gopinath | |
6 | * Copyright (C) 2009 Texas Instruments Incorporated. | |
7 | * Nishanth Menon | |
8 | * Copyright (C) 2009 Nokia Corporation | |
9 | * Paul Walmsley | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/err.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/kernel.h> | |
7bc3ed9a | 19 | #include <linux/i2c/twl.h> |
fbc319f6 | 20 | |
e1d6f472 | 21 | #include "voltage.h" |
fbc319f6 | 22 | |
dda0aea7 NM |
23 | #include "pm.h" |
24 | ||
fbc319f6 TG |
25 | #define OMAP3_SRI2C_SLAVE_ADDR 0x12 |
26 | #define OMAP3_VDD_MPU_SR_CONTROL_REG 0x00 | |
27 | #define OMAP3_VDD_CORE_SR_CONTROL_REG 0x01 | |
28 | #define OMAP3_VP_CONFIG_ERROROFFSET 0x00 | |
29 | #define OMAP3_VP_VSTEPMIN_VSTEPMIN 0x1 | |
30 | #define OMAP3_VP_VSTEPMAX_VSTEPMAX 0x04 | |
31 | #define OMAP3_VP_VLIMITTO_TIMEOUT_US 200 | |
32 | ||
33 | #define OMAP3430_VP1_VLIMITTO_VDDMIN 0x14 | |
34 | #define OMAP3430_VP1_VLIMITTO_VDDMAX 0x42 | |
35 | #define OMAP3430_VP2_VLIMITTO_VDDMIN 0x18 | |
36 | #define OMAP3430_VP2_VLIMITTO_VDDMAX 0x2c | |
37 | ||
38 | #define OMAP3630_VP1_VLIMITTO_VDDMIN 0x18 | |
39 | #define OMAP3630_VP1_VLIMITTO_VDDMAX 0x3c | |
40 | #define OMAP3630_VP2_VLIMITTO_VDDMIN 0x18 | |
41 | #define OMAP3630_VP2_VLIMITTO_VDDMAX 0x30 | |
42 | ||
7bc3ed9a TG |
43 | #define OMAP4_SRI2C_SLAVE_ADDR 0x12 |
44 | #define OMAP4_VDD_MPU_SR_VOLT_REG 0x55 | |
45 | #define OMAP4_VDD_IVA_SR_VOLT_REG 0x5B | |
46 | #define OMAP4_VDD_CORE_SR_VOLT_REG 0x61 | |
47 | ||
48 | #define OMAP4_VP_CONFIG_ERROROFFSET 0x00 | |
49 | #define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01 | |
50 | #define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04 | |
51 | #define OMAP4_VP_VLIMITTO_TIMEOUT_US 200 | |
52 | ||
53 | #define OMAP4_VP_MPU_VLIMITTO_VDDMIN 0xA | |
54 | #define OMAP4_VP_MPU_VLIMITTO_VDDMAX 0x39 | |
55 | #define OMAP4_VP_IVA_VLIMITTO_VDDMIN 0xA | |
56 | #define OMAP4_VP_IVA_VLIMITTO_VDDMAX 0x2D | |
57 | #define OMAP4_VP_CORE_VLIMITTO_VDDMIN 0xA | |
58 | #define OMAP4_VP_CORE_VLIMITTO_VDDMAX 0x28 | |
59 | ||
60 | static bool is_offset_valid; | |
61 | static u8 smps_offset; | |
40713189 TG |
62 | /* |
63 | * Flag to ensure Smartreflex bit in TWL | |
64 | * being cleared in board file is not overwritten. | |
65 | */ | |
66 | static bool __initdata twl_sr_enable_autoinit; | |
7bc3ed9a | 67 | |
40713189 | 68 | #define TWL4030_DCDC_GLOBAL_CFG 0x06 |
7bc3ed9a | 69 | #define REG_SMPS_OFFSET 0xE0 |
40713189 | 70 | #define SMARTREFLEX_ENABLE BIT(3) |
7bc3ed9a | 71 | |
c84ff1cc | 72 | static unsigned long twl4030_vsel_to_uv(const u8 vsel) |
fbc319f6 TG |
73 | { |
74 | return (((vsel * 125) + 6000)) * 100; | |
75 | } | |
76 | ||
c84ff1cc | 77 | static u8 twl4030_uv_to_vsel(unsigned long uv) |
fbc319f6 TG |
78 | { |
79 | return DIV_ROUND_UP(uv - 600000, 12500); | |
80 | } | |
81 | ||
c84ff1cc | 82 | static unsigned long twl6030_vsel_to_uv(const u8 vsel) |
7bc3ed9a TG |
83 | { |
84 | /* | |
85 | * In TWL6030 depending on the value of SMPS_OFFSET | |
86 | * efuse register the voltage range supported in | |
87 | * standard mode can be either between 0.6V - 1.3V or | |
88 | * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse | |
89 | * is programmed to all 0's where as starting from | |
90 | * TWL6030 ES1.1 the efuse is programmed to 1 | |
91 | */ | |
92 | if (!is_offset_valid) { | |
93 | twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset, | |
94 | REG_SMPS_OFFSET); | |
95 | is_offset_valid = true; | |
96 | } | |
97 | ||
98 | /* | |
99 | * There is no specific formula for voltage to vsel | |
100 | * conversion above 1.3V. There are special hardcoded | |
101 | * values for voltages above 1.3V. Currently we are | |
102 | * hardcoding only for 1.35 V which is used for 1GH OPP for | |
103 | * OMAP4430. | |
104 | */ | |
105 | if (vsel == 0x3A) | |
106 | return 1350000; | |
107 | ||
108 | if (smps_offset & 0x8) | |
58e241f7 | 109 | return ((((vsel - 1) * 1266) + 70900)) * 10; |
7bc3ed9a | 110 | else |
58e241f7 | 111 | return ((((vsel - 1) * 1266) + 60770)) * 10; |
7bc3ed9a TG |
112 | } |
113 | ||
c84ff1cc | 114 | static u8 twl6030_uv_to_vsel(unsigned long uv) |
7bc3ed9a TG |
115 | { |
116 | /* | |
117 | * In TWL6030 depending on the value of SMPS_OFFSET | |
118 | * efuse register the voltage range supported in | |
119 | * standard mode can be either between 0.6V - 1.3V or | |
120 | * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse | |
121 | * is programmed to all 0's where as starting from | |
122 | * TWL6030 ES1.1 the efuse is programmed to 1 | |
123 | */ | |
124 | if (!is_offset_valid) { | |
125 | twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset, | |
126 | REG_SMPS_OFFSET); | |
127 | is_offset_valid = true; | |
128 | } | |
129 | ||
130 | /* | |
131 | * There is no specific formula for voltage to vsel | |
132 | * conversion above 1.3V. There are special hardcoded | |
133 | * values for voltages above 1.3V. Currently we are | |
134 | * hardcoding only for 1.35 V which is used for 1GH OPP for | |
135 | * OMAP4430. | |
136 | */ | |
137 | if (uv == 1350000) | |
138 | return 0x3A; | |
139 | ||
140 | if (smps_offset & 0x8) | |
58e241f7 | 141 | return DIV_ROUND_UP(uv - 709000, 12660) + 1; |
7bc3ed9a | 142 | else |
58e241f7 | 143 | return DIV_ROUND_UP(uv - 607700, 12660) + 1; |
7bc3ed9a TG |
144 | } |
145 | ||
ce8ebe0d | 146 | static struct omap_voltdm_pmic omap3_mpu_pmic = { |
fbc319f6 TG |
147 | .slew_rate = 4000, |
148 | .step_size = 12500, | |
149 | .on_volt = 1200000, | |
150 | .onlp_volt = 1000000, | |
151 | .ret_volt = 975000, | |
152 | .off_volt = 600000, | |
153 | .volt_setup_time = 0xfff, | |
154 | .vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET, | |
155 | .vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN, | |
156 | .vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX, | |
157 | .vp_vddmin = OMAP3430_VP1_VLIMITTO_VDDMIN, | |
158 | .vp_vddmax = OMAP3430_VP1_VLIMITTO_VDDMAX, | |
159 | .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US, | |
160 | .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR, | |
e74e4405 | 161 | .volt_reg_addr = OMAP3_VDD_MPU_SR_CONTROL_REG, |
f5395480 | 162 | .i2c_high_speed = true, |
fbc319f6 TG |
163 | .vsel_to_uv = twl4030_vsel_to_uv, |
164 | .uv_to_vsel = twl4030_uv_to_vsel, | |
165 | }; | |
166 | ||
ce8ebe0d | 167 | static struct omap_voltdm_pmic omap3_core_pmic = { |
fbc319f6 TG |
168 | .slew_rate = 4000, |
169 | .step_size = 12500, | |
170 | .on_volt = 1200000, | |
171 | .onlp_volt = 1000000, | |
172 | .ret_volt = 975000, | |
173 | .off_volt = 600000, | |
174 | .volt_setup_time = 0xfff, | |
175 | .vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET, | |
176 | .vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN, | |
177 | .vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX, | |
178 | .vp_vddmin = OMAP3430_VP2_VLIMITTO_VDDMIN, | |
179 | .vp_vddmax = OMAP3430_VP2_VLIMITTO_VDDMAX, | |
180 | .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US, | |
181 | .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR, | |
e74e4405 | 182 | .volt_reg_addr = OMAP3_VDD_CORE_SR_CONTROL_REG, |
f5395480 | 183 | .i2c_high_speed = true, |
fbc319f6 TG |
184 | .vsel_to_uv = twl4030_vsel_to_uv, |
185 | .uv_to_vsel = twl4030_uv_to_vsel, | |
186 | }; | |
187 | ||
ce8ebe0d | 188 | static struct omap_voltdm_pmic omap4_mpu_pmic = { |
7bc3ed9a | 189 | .slew_rate = 4000, |
58e241f7 | 190 | .step_size = 12660, |
7bc3ed9a TG |
191 | .on_volt = 1350000, |
192 | .onlp_volt = 1350000, | |
193 | .ret_volt = 837500, | |
194 | .off_volt = 600000, | |
195 | .volt_setup_time = 0, | |
196 | .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET, | |
197 | .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN, | |
198 | .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX, | |
199 | .vp_vddmin = OMAP4_VP_MPU_VLIMITTO_VDDMIN, | |
200 | .vp_vddmax = OMAP4_VP_MPU_VLIMITTO_VDDMAX, | |
201 | .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US, | |
202 | .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR, | |
e74e4405 | 203 | .volt_reg_addr = OMAP4_VDD_MPU_SR_VOLT_REG, |
f5395480 | 204 | .i2c_high_speed = true, |
7bc3ed9a TG |
205 | .vsel_to_uv = twl6030_vsel_to_uv, |
206 | .uv_to_vsel = twl6030_uv_to_vsel, | |
207 | }; | |
208 | ||
ce8ebe0d | 209 | static struct omap_voltdm_pmic omap4_iva_pmic = { |
7bc3ed9a | 210 | .slew_rate = 4000, |
58e241f7 | 211 | .step_size = 12660, |
7bc3ed9a TG |
212 | .on_volt = 1100000, |
213 | .onlp_volt = 1100000, | |
214 | .ret_volt = 837500, | |
215 | .off_volt = 600000, | |
216 | .volt_setup_time = 0, | |
217 | .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET, | |
218 | .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN, | |
219 | .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX, | |
220 | .vp_vddmin = OMAP4_VP_IVA_VLIMITTO_VDDMIN, | |
221 | .vp_vddmax = OMAP4_VP_IVA_VLIMITTO_VDDMAX, | |
222 | .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US, | |
223 | .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR, | |
e74e4405 | 224 | .volt_reg_addr = OMAP4_VDD_IVA_SR_VOLT_REG, |
f5395480 | 225 | .i2c_high_speed = true, |
7bc3ed9a TG |
226 | .vsel_to_uv = twl6030_vsel_to_uv, |
227 | .uv_to_vsel = twl6030_uv_to_vsel, | |
228 | }; | |
229 | ||
ce8ebe0d | 230 | static struct omap_voltdm_pmic omap4_core_pmic = { |
7bc3ed9a | 231 | .slew_rate = 4000, |
58e241f7 | 232 | .step_size = 12660, |
7bc3ed9a TG |
233 | .on_volt = 1100000, |
234 | .onlp_volt = 1100000, | |
235 | .ret_volt = 837500, | |
236 | .off_volt = 600000, | |
237 | .volt_setup_time = 0, | |
238 | .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET, | |
239 | .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN, | |
240 | .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX, | |
241 | .vp_vddmin = OMAP4_VP_CORE_VLIMITTO_VDDMIN, | |
242 | .vp_vddmax = OMAP4_VP_CORE_VLIMITTO_VDDMAX, | |
243 | .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US, | |
244 | .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR, | |
e74e4405 | 245 | .volt_reg_addr = OMAP4_VDD_CORE_SR_VOLT_REG, |
7bc3ed9a TG |
246 | .vsel_to_uv = twl6030_vsel_to_uv, |
247 | .uv_to_vsel = twl6030_uv_to_vsel, | |
248 | }; | |
249 | ||
250 | int __init omap4_twl_init(void) | |
251 | { | |
252 | struct voltagedomain *voltdm; | |
253 | ||
254 | if (!cpu_is_omap44xx()) | |
255 | return -ENODEV; | |
256 | ||
81a60482 | 257 | voltdm = voltdm_lookup("mpu"); |
ce8ebe0d | 258 | omap_voltage_register_pmic(voltdm, &omap4_mpu_pmic); |
7bc3ed9a | 259 | |
81a60482 | 260 | voltdm = voltdm_lookup("iva"); |
ce8ebe0d | 261 | omap_voltage_register_pmic(voltdm, &omap4_iva_pmic); |
7bc3ed9a | 262 | |
81a60482 | 263 | voltdm = voltdm_lookup("core"); |
ce8ebe0d | 264 | omap_voltage_register_pmic(voltdm, &omap4_core_pmic); |
7bc3ed9a TG |
265 | |
266 | return 0; | |
267 | } | |
268 | ||
fbc319f6 TG |
269 | int __init omap3_twl_init(void) |
270 | { | |
271 | struct voltagedomain *voltdm; | |
272 | ||
273 | if (!cpu_is_omap34xx()) | |
274 | return -ENODEV; | |
275 | ||
276 | if (cpu_is_omap3630()) { | |
ce8ebe0d KH |
277 | omap3_mpu_pmic.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN; |
278 | omap3_mpu_pmic.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX; | |
279 | omap3_core_pmic.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN; | |
280 | omap3_core_pmic.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX; | |
fbc319f6 TG |
281 | } |
282 | ||
40713189 TG |
283 | /* |
284 | * The smartreflex bit on twl4030 specifies if the setting of voltage | |
285 | * is done over the I2C_SR path. Since this setting is independent of | |
286 | * the actual usage of smartreflex AVS module, we enable TWL SR bit | |
287 | * by default irrespective of whether smartreflex AVS module is enabled | |
288 | * on the OMAP side or not. This is because without this bit enabled, | |
289 | * the voltage scaling through vp forceupdate/bypass mechanism of | |
290 | * voltage scaling will not function on TWL over I2C_SR. | |
291 | */ | |
292 | if (!twl_sr_enable_autoinit) | |
293 | omap3_twl_set_sr_bit(true); | |
294 | ||
280a7275 | 295 | voltdm = voltdm_lookup("mpu_iva"); |
ce8ebe0d | 296 | omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic); |
fbc319f6 | 297 | |
81a60482 | 298 | voltdm = voltdm_lookup("core"); |
ce8ebe0d | 299 | omap_voltage_register_pmic(voltdm, &omap3_core_pmic); |
fbc319f6 TG |
300 | |
301 | return 0; | |
302 | } | |
40713189 TG |
303 | |
304 | /** | |
305 | * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL | |
306 | * @enable: enable SR mode in twl or not | |
307 | * | |
308 | * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure | |
309 | * voltage scaling through OMAP SR works. Else, the smartreflex bit | |
310 | * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but | |
311 | * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct | |
312 | * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages, | |
313 | * in those scenarios this bit is to be cleared (enable = false). | |
314 | * | |
25985edc | 315 | * Returns 0 on success, error is returned if I2C read/write fails. |
40713189 TG |
316 | */ |
317 | int __init omap3_twl_set_sr_bit(bool enable) | |
318 | { | |
319 | u8 temp; | |
320 | int ret; | |
321 | if (twl_sr_enable_autoinit) | |
322 | pr_warning("%s: unexpected multiple calls\n", __func__); | |
323 | ||
324 | ret = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &temp, | |
325 | TWL4030_DCDC_GLOBAL_CFG); | |
326 | if (ret) | |
327 | goto err; | |
328 | ||
329 | if (enable) | |
330 | temp |= SMARTREFLEX_ENABLE; | |
331 | else | |
332 | temp &= ~SMARTREFLEX_ENABLE; | |
333 | ||
334 | ret = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp, | |
335 | TWL4030_DCDC_GLOBAL_CFG); | |
336 | if (!ret) { | |
337 | twl_sr_enable_autoinit = true; | |
338 | return 0; | |
339 | } | |
340 | err: | |
341 | pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret); | |
342 | return ret; | |
343 | } |