Commit | Line | Data |
---|---|---|
6f88e9bc KH |
1 | /* |
2 | * pm.c - Common OMAP2+ power management-related code | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments, Inc. | |
5 | * Copyright (C) 2010 Nokia Corporation | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/err.h> | |
1482d8be | 16 | #include <linux/opp.h> |
dc28094b | 17 | #include <linux/export.h> |
1416408d | 18 | #include <linux/suspend.h> |
24d7b40a | 19 | #include <linux/cpu.h> |
6f88e9bc | 20 | |
335aece5 G |
21 | #include <asm/system_misc.h> |
22 | ||
6f88e9bc KH |
23 | #include <plat/omap-pm.h> |
24 | #include <plat/omap_device.h> | |
4e65331c | 25 | #include "common.h" |
6f88e9bc | 26 | |
1416408d | 27 | #include "prcm-common.h" |
e1d6f472 | 28 | #include "voltage.h" |
72e06d08 | 29 | #include "powerdomain.h" |
1540f214 | 30 | #include "clockdomain.h" |
0c0a5d61 | 31 | #include "pm.h" |
46232a36 | 32 | #include "twl-common.h" |
eb6a2c75 | 33 | |
6f88e9bc KH |
34 | static struct omap_device_pm_latency *pm_lats; |
35 | ||
1416408d PW |
36 | /* |
37 | * omap_pm_suspend: points to a function that does the SoC-specific | |
38 | * suspend work | |
39 | */ | |
40 | int (*omap_pm_suspend)(void); | |
41 | ||
9cf793f9 | 42 | static int __init _init_omap_device(char *name) |
6f88e9bc KH |
43 | { |
44 | struct omap_hwmod *oh; | |
3528c58e | 45 | struct platform_device *pdev; |
6f88e9bc KH |
46 | |
47 | oh = omap_hwmod_lookup(name); | |
48 | if (WARN(!oh, "%s: could not find omap_hwmod for %s\n", | |
49 | __func__, name)) | |
50 | return -ENODEV; | |
51 | ||
3528c58e KH |
52 | pdev = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false); |
53 | if (WARN(IS_ERR(pdev), "%s: could not build omap_device for %s\n", | |
6f88e9bc KH |
54 | __func__, name)) |
55 | return -ENODEV; | |
56 | ||
6f88e9bc KH |
57 | return 0; |
58 | } | |
59 | ||
60 | /* | |
61 | * Build omap_devices for processors and bus. | |
62 | */ | |
1f3b372b | 63 | static void __init omap2_init_processor_devices(void) |
6f88e9bc | 64 | { |
766e7afc | 65 | _init_omap_device("mpu"); |
2de0baef | 66 | if (omap3_has_iva()) |
766e7afc | 67 | _init_omap_device("iva"); |
2de0baef | 68 | |
cbf27660 | 69 | if (cpu_is_omap44xx()) { |
766e7afc BC |
70 | _init_omap_device("l3_main_1"); |
71 | _init_omap_device("dsp"); | |
72 | _init_omap_device("iva"); | |
cbf27660 | 73 | } else { |
766e7afc | 74 | _init_omap_device("l3_main"); |
cbf27660 | 75 | } |
6f88e9bc KH |
76 | } |
77 | ||
71a488db RN |
78 | /* Types of sleep_switch used in omap_set_pwrdm_state */ |
79 | #define FORCEWAKEUP_SWITCH 0 | |
80 | #define LOWPOWERSTATE_SWITCH 1 | |
81 | ||
92206fd2 PW |
82 | int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused) |
83 | { | |
b71c7217 PW |
84 | if ((clkdm->flags & CLKDM_CAN_ENABLE_AUTO) && |
85 | !(clkdm->flags & CLKDM_MISSING_IDLE_REPORTING)) | |
92206fd2 PW |
86 | clkdm_allow_idle(clkdm); |
87 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && | |
88 | atomic_read(&clkdm->usecount) == 0) | |
89 | clkdm_sleep(clkdm); | |
90 | return 0; | |
91 | } | |
92 | ||
eb6a2c75 SS |
93 | /* |
94 | * This sets pwrdm state (other than mpu & core. Currently only ON & | |
33de32b3 | 95 | * RET are supported. |
eb6a2c75 | 96 | */ |
e68e8093 | 97 | int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 pwrst) |
eb6a2c75 | 98 | { |
e68e8093 PW |
99 | u8 curr_pwrst, next_pwrst; |
100 | int sleep_switch = -1, ret = 0, hwsup = 0; | |
eb6a2c75 | 101 | |
e68e8093 | 102 | if (!pwrdm || IS_ERR(pwrdm)) |
eb6a2c75 SS |
103 | return -EINVAL; |
104 | ||
e68e8093 PW |
105 | while (!(pwrdm->pwrsts & (1 << pwrst))) { |
106 | if (pwrst == PWRDM_POWER_OFF) | |
eb6a2c75 | 107 | return ret; |
e68e8093 | 108 | pwrst--; |
eb6a2c75 SS |
109 | } |
110 | ||
e68e8093 PW |
111 | next_pwrst = pwrdm_read_next_pwrst(pwrdm); |
112 | if (next_pwrst == pwrst) | |
eb6a2c75 SS |
113 | return ret; |
114 | ||
e68e8093 PW |
115 | curr_pwrst = pwrdm_read_pwrst(pwrdm); |
116 | if (curr_pwrst < PWRDM_POWER_ON) { | |
117 | if ((curr_pwrst > pwrst) && | |
71a488db RN |
118 | (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) { |
119 | sleep_switch = LOWPOWERSTATE_SWITCH; | |
120 | } else { | |
b86cfb52 | 121 | hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]); |
68b921ad | 122 | clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); |
71a488db RN |
123 | sleep_switch = FORCEWAKEUP_SWITCH; |
124 | } | |
eb6a2c75 SS |
125 | } |
126 | ||
e68e8093 PW |
127 | ret = pwrdm_set_next_pwrst(pwrdm, pwrst); |
128 | if (ret) | |
129 | pr_err("%s: unable to set power state of powerdomain: %s\n", | |
e9a5190a | 130 | __func__, pwrdm->name); |
eb6a2c75 | 131 | |
71a488db RN |
132 | switch (sleep_switch) { |
133 | case FORCEWAKEUP_SWITCH: | |
b86cfb52 | 134 | if (hwsup) |
5cd1937b | 135 | clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); |
33de32b3 | 136 | else |
68b921ad | 137 | clkdm_sleep(pwrdm->pwrdm_clkdms[0]); |
71a488db RN |
138 | break; |
139 | case LOWPOWERSTATE_SWITCH: | |
140 | pwrdm_set_lowpwrstchange(pwrdm); | |
e68e8093 PW |
141 | pwrdm_wait_transition(pwrdm); |
142 | pwrdm_state_switch(pwrdm); | |
71a488db | 143 | break; |
eb6a2c75 SS |
144 | } |
145 | ||
eb6a2c75 SS |
146 | return ret; |
147 | } | |
148 | ||
1416408d PW |
149 | |
150 | ||
1482d8be | 151 | /* |
1e2d2df3 | 152 | * This API is to be called during init to set the various voltage |
1482d8be TG |
153 | * domains to the voltage as per the opp table. Typically we boot up |
154 | * at the nominal voltage. So this function finds out the rate of | |
155 | * the clock associated with the voltage domain, finds out the correct | |
1e2d2df3 | 156 | * opp entry and sets the voltage domain to the voltage specified |
1482d8be TG |
157 | * in the opp entry |
158 | */ | |
159 | static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, | |
0f7aa005 | 160 | const char *oh_name) |
1482d8be TG |
161 | { |
162 | struct voltagedomain *voltdm; | |
163 | struct clk *clk; | |
164 | struct opp *opp; | |
165 | unsigned long freq, bootup_volt; | |
0f7aa005 | 166 | struct device *dev; |
1482d8be | 167 | |
0f7aa005 | 168 | if (!vdd_name || !clk_name || !oh_name) { |
e9a5190a | 169 | pr_err("%s: invalid parameters\n", __func__); |
1482d8be TG |
170 | goto exit; |
171 | } | |
172 | ||
24d7b40a KH |
173 | if (!strncmp(oh_name, "mpu", 3)) |
174 | /* | |
175 | * All current OMAPs share voltage rail and clock | |
176 | * source, so CPU0 is used to represent the MPU-SS. | |
177 | */ | |
178 | dev = get_cpu_device(0); | |
179 | else | |
180 | dev = omap_device_get_by_hwmod_name(oh_name); | |
181 | ||
0f7aa005 BC |
182 | if (IS_ERR(dev)) { |
183 | pr_err("%s: Unable to get dev pointer for hwmod %s\n", | |
184 | __func__, oh_name); | |
185 | goto exit; | |
186 | } | |
187 | ||
81a60482 | 188 | voltdm = voltdm_lookup(vdd_name); |
93b44bea | 189 | if (!voltdm) { |
e9a5190a | 190 | pr_err("%s: unable to get vdd pointer for vdd_%s\n", |
1482d8be TG |
191 | __func__, vdd_name); |
192 | goto exit; | |
193 | } | |
194 | ||
195 | clk = clk_get(NULL, clk_name); | |
196 | if (IS_ERR(clk)) { | |
e9a5190a | 197 | pr_err("%s: unable to get clk %s\n", __func__, clk_name); |
1482d8be TG |
198 | goto exit; |
199 | } | |
200 | ||
5dcc3b97 | 201 | freq = clk_get_rate(clk); |
1482d8be TG |
202 | clk_put(clk); |
203 | ||
6369fd41 | 204 | rcu_read_lock(); |
1482d8be TG |
205 | opp = opp_find_freq_ceil(dev, &freq); |
206 | if (IS_ERR(opp)) { | |
6369fd41 | 207 | rcu_read_unlock(); |
e9a5190a | 208 | pr_err("%s: unable to find boot up OPP for vdd_%s\n", |
1482d8be TG |
209 | __func__, vdd_name); |
210 | goto exit; | |
211 | } | |
212 | ||
213 | bootup_volt = opp_get_voltage(opp); | |
6369fd41 | 214 | rcu_read_unlock(); |
1482d8be | 215 | if (!bootup_volt) { |
7852ec05 PW |
216 | pr_err("%s: unable to find voltage corresponding to the bootup OPP for vdd_%s\n", |
217 | __func__, vdd_name); | |
1482d8be TG |
218 | goto exit; |
219 | } | |
220 | ||
5e5651be | 221 | voltdm_scale(voltdm, bootup_volt); |
1482d8be TG |
222 | return 0; |
223 | ||
224 | exit: | |
e9a5190a | 225 | pr_err("%s: unable to set vdd_%s\n", __func__, vdd_name); |
1482d8be TG |
226 | return -EINVAL; |
227 | } | |
228 | ||
1416408d PW |
229 | #ifdef CONFIG_SUSPEND |
230 | static int omap_pm_enter(suspend_state_t suspend_state) | |
231 | { | |
232 | int ret = 0; | |
233 | ||
234 | if (!omap_pm_suspend) | |
235 | return -ENOENT; /* XXX doublecheck */ | |
236 | ||
237 | switch (suspend_state) { | |
238 | case PM_SUSPEND_STANDBY: | |
239 | case PM_SUSPEND_MEM: | |
240 | ret = omap_pm_suspend(); | |
241 | break; | |
242 | default: | |
243 | ret = -EINVAL; | |
244 | } | |
245 | ||
246 | return ret; | |
247 | } | |
248 | ||
249 | static int omap_pm_begin(suspend_state_t state) | |
250 | { | |
251 | disable_hlt(); | |
252 | if (cpu_is_omap34xx()) | |
253 | omap_prcm_irq_prepare(); | |
254 | return 0; | |
255 | } | |
256 | ||
257 | static void omap_pm_end(void) | |
258 | { | |
259 | enable_hlt(); | |
260 | return; | |
261 | } | |
262 | ||
263 | static void omap_pm_finish(void) | |
264 | { | |
265 | if (cpu_is_omap34xx()) | |
266 | omap_prcm_irq_complete(); | |
267 | } | |
268 | ||
269 | static const struct platform_suspend_ops omap_pm_ops = { | |
270 | .begin = omap_pm_begin, | |
271 | .end = omap_pm_end, | |
272 | .enter = omap_pm_enter, | |
273 | .finish = omap_pm_finish, | |
274 | .valid = suspend_valid_only_mem, | |
275 | }; | |
276 | ||
277 | #endif /* CONFIG_SUSPEND */ | |
278 | ||
1482d8be TG |
279 | static void __init omap3_init_voltages(void) |
280 | { | |
281 | if (!cpu_is_omap34xx()) | |
282 | return; | |
283 | ||
0f7aa005 BC |
284 | omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu"); |
285 | omap2_set_init_voltage("core", "l3_ick", "l3_main"); | |
1482d8be TG |
286 | } |
287 | ||
1376ee1d TG |
288 | static void __init omap4_init_voltages(void) |
289 | { | |
290 | if (!cpu_is_omap44xx()) | |
291 | return; | |
292 | ||
0f7aa005 BC |
293 | omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu"); |
294 | omap2_set_init_voltage("core", "l3_div_ck", "l3_main_1"); | |
295 | omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva"); | |
1376ee1d TG |
296 | } |
297 | ||
6f88e9bc KH |
298 | static int __init omap2_common_pm_init(void) |
299 | { | |
476b679a BC |
300 | if (!of_have_populated_dt()) |
301 | omap2_init_processor_devices(); | |
6f88e9bc KH |
302 | omap_pm_if_init(); |
303 | ||
304 | return 0; | |
305 | } | |
1cbbe37a | 306 | postcore_initcall(omap2_common_pm_init); |
6f88e9bc | 307 | |
bbd707ac | 308 | int __init omap2_common_pm_late_init(void) |
2f34ce81 | 309 | { |
506d81ef BC |
310 | /* |
311 | * In the case of DT, the PMIC and SR initialization will be done using | |
312 | * a completely different mechanism. | |
313 | * Disable this part if a DT blob is available. | |
314 | */ | |
315 | if (of_have_populated_dt()) | |
316 | return 0; | |
317 | ||
fbc319f6 | 318 | /* Init the voltage layer */ |
46232a36 | 319 | omap_pmic_late_init(); |
2f34ce81 | 320 | omap_voltage_late_init(); |
1482d8be TG |
321 | |
322 | /* Initialize the voltages */ | |
323 | omap3_init_voltages(); | |
1376ee1d | 324 | omap4_init_voltages(); |
1482d8be | 325 | |
fbc319f6 | 326 | /* Smartreflex device init */ |
0c0a5d61 | 327 | omap_devinit_smartreflex(); |
2f34ce81 | 328 | |
1416408d PW |
329 | #ifdef CONFIG_SUSPEND |
330 | suspend_set_ops(&omap_pm_ops); | |
331 | #endif | |
332 | ||
2f34ce81 TG |
333 | return 0; |
334 | } |