Commit | Line | Data |
---|---|---|
8bd22949 KH |
1 | /* |
2 | * OMAP3 Power Management Routines | |
3 | * | |
4 | * Copyright (C) 2006-2008 Nokia Corporation | |
5 | * Tony Lindgren <tony@atomide.com> | |
6 | * Jouni Hogander | |
7 | * | |
2f5939c3 RN |
8 | * Copyright (C) 2007 Texas Instruments, Inc. |
9 | * Rajendra Nayak <rnayak@ti.com> | |
10 | * | |
8bd22949 KH |
11 | * Copyright (C) 2005 Texas Instruments, Inc. |
12 | * Richard Woodruff <r-woodruff2@ti.com> | |
13 | * | |
14 | * Based on pm.c for omap1 | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/pm.h> | |
22 | #include <linux/suspend.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/gpio.h> | |
c40552bc | 28 | #include <linux/clk.h> |
dccaad89 | 29 | #include <linux/delay.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
0d8e2d0d | 31 | #include <linux/console.h> |
5e7c58dc | 32 | #include <trace/events/power.h> |
8bd22949 | 33 | |
ce491cf8 | 34 | #include <plat/sram.h> |
1540f214 | 35 | #include "clockdomain.h" |
72e06d08 | 36 | #include "powerdomain.h" |
ce491cf8 | 37 | #include <plat/serial.h> |
61255ab9 | 38 | #include <plat/sdrc.h> |
2f5939c3 RN |
39 | #include <plat/prcm.h> |
40 | #include <plat/gpmc.h> | |
f2d11858 | 41 | #include <plat/dma.h> |
8bd22949 | 42 | |
59fb659b | 43 | #include "cm2xxx_3xxx.h" |
8bd22949 KH |
44 | #include "cm-regbits-34xx.h" |
45 | #include "prm-regbits-34xx.h" | |
46 | ||
59fb659b | 47 | #include "prm2xxx_3xxx.h" |
8bd22949 | 48 | #include "pm.h" |
13a6fe0f | 49 | #include "sdrc.h" |
4814ced5 | 50 | #include "control.h" |
13a6fe0f | 51 | |
e83df17f KH |
52 | #ifdef CONFIG_SUSPEND |
53 | static suspend_state_t suspend_state = PM_SUSPEND_ON; | |
54 | static inline bool is_suspending(void) | |
55 | { | |
56 | return (suspend_state != PM_SUSPEND_ON); | |
57 | } | |
58 | #else | |
59 | static inline bool is_suspending(void) | |
60 | { | |
61 | return false; | |
62 | } | |
63 | #endif | |
64 | ||
8cdfd834 NM |
65 | /* pm34xx errata defined in pm.h */ |
66 | u16 pm34xx_errata; | |
67 | ||
8bd22949 KH |
68 | struct power_state { |
69 | struct powerdomain *pwrdm; | |
70 | u32 next_state; | |
10f90ed2 | 71 | #ifdef CONFIG_SUSPEND |
8bd22949 | 72 | u32 saved_state; |
10f90ed2 | 73 | #endif |
8bd22949 KH |
74 | struct list_head node; |
75 | }; | |
76 | ||
77 | static LIST_HEAD(pwrst_list); | |
78 | ||
79 | static void (*_omap_sram_idle)(u32 *addr, int save_state); | |
80 | ||
27d59a4a TK |
81 | static int (*_omap_save_secure_sram)(u32 *addr); |
82 | ||
fa3c2a4f RN |
83 | static struct powerdomain *mpu_pwrdm, *neon_pwrdm; |
84 | static struct powerdomain *core_pwrdm, *per_pwrdm; | |
c16c3f67 | 85 | static struct powerdomain *cam_pwrdm; |
fa3c2a4f | 86 | |
2f5939c3 RN |
87 | static inline void omap3_per_save_context(void) |
88 | { | |
89 | omap_gpio_save_context(); | |
90 | } | |
91 | ||
92 | static inline void omap3_per_restore_context(void) | |
93 | { | |
94 | omap_gpio_restore_context(); | |
95 | } | |
96 | ||
3a7ec26b KJ |
97 | static void omap3_enable_io_chain(void) |
98 | { | |
99 | int timeout = 0; | |
100 | ||
101 | if (omap_rev() >= OMAP3430_REV_ES3_1) { | |
c4d7e58f | 102 | omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, |
2bc4ef71 | 103 | PM_WKEN); |
3a7ec26b | 104 | /* Do a readback to assure write has been done */ |
c4d7e58f | 105 | omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); |
3a7ec26b | 106 | |
c4d7e58f | 107 | while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) & |
2bc4ef71 | 108 | OMAP3430_ST_IO_CHAIN_MASK)) { |
3a7ec26b KJ |
109 | timeout++; |
110 | if (timeout > 1000) { | |
111 | printk(KERN_ERR "Wake up daisy chain " | |
112 | "activation failed.\n"); | |
113 | return; | |
114 | } | |
c4d7e58f | 115 | omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, |
0b96a3a3 | 116 | WKUP_MOD, PM_WKEN); |
3a7ec26b KJ |
117 | } |
118 | } | |
119 | } | |
120 | ||
121 | static void omap3_disable_io_chain(void) | |
122 | { | |
123 | if (omap_rev() >= OMAP3430_REV_ES3_1) | |
c4d7e58f | 124 | omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, |
2bc4ef71 | 125 | PM_WKEN); |
3a7ec26b KJ |
126 | } |
127 | ||
2f5939c3 RN |
128 | static void omap3_core_save_context(void) |
129 | { | |
596efe47 | 130 | omap3_ctrl_save_padconf(); |
dccaad89 TK |
131 | |
132 | /* | |
133 | * Force write last pad into memory, as this can fail in some | |
83521291 | 134 | * cases according to errata 1.157, 1.185 |
dccaad89 TK |
135 | */ |
136 | omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), | |
137 | OMAP343X_CONTROL_MEM_WKUP + 0x2a0); | |
138 | ||
2f5939c3 RN |
139 | /* Save the Interrupt controller context */ |
140 | omap_intc_save_context(); | |
141 | /* Save the GPMC context */ | |
142 | omap3_gpmc_save_context(); | |
143 | /* Save the system control module context, padconf already save above*/ | |
144 | omap3_control_save_context(); | |
f2d11858 | 145 | omap_dma_global_context_save(); |
2f5939c3 RN |
146 | } |
147 | ||
148 | static void omap3_core_restore_context(void) | |
149 | { | |
150 | /* Restore the control module context, padconf restored by h/w */ | |
151 | omap3_control_restore_context(); | |
152 | /* Restore the GPMC context */ | |
153 | omap3_gpmc_restore_context(); | |
154 | /* Restore the interrupt controller context */ | |
155 | omap_intc_restore_context(); | |
f2d11858 | 156 | omap_dma_global_context_restore(); |
2f5939c3 RN |
157 | } |
158 | ||
9d97140b TK |
159 | /* |
160 | * FIXME: This function should be called before entering off-mode after | |
161 | * OMAP3 secure services have been accessed. Currently it is only called | |
162 | * once during boot sequence, but this works as we are not using secure | |
163 | * services. | |
164 | */ | |
617fcc98 | 165 | static void omap3_save_secure_ram_context(void) |
27d59a4a TK |
166 | { |
167 | u32 ret; | |
617fcc98 | 168 | int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
27d59a4a TK |
169 | |
170 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { | |
27d59a4a TK |
171 | /* |
172 | * MPU next state must be set to POWER_ON temporarily, | |
173 | * otherwise the WFI executed inside the ROM code | |
174 | * will hang the system. | |
175 | */ | |
176 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); | |
177 | ret = _omap_save_secure_sram((u32 *) | |
178 | __pa(omap3_secure_ram_storage)); | |
617fcc98 | 179 | pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); |
27d59a4a TK |
180 | /* Following is for error tracking, it should not happen */ |
181 | if (ret) { | |
182 | printk(KERN_ERR "save_secure_sram() returns %08x\n", | |
183 | ret); | |
184 | while (1) | |
185 | ; | |
186 | } | |
187 | } | |
188 | } | |
189 | ||
77da2d91 JH |
190 | /* |
191 | * PRCM Interrupt Handler Helper Function | |
192 | * | |
193 | * The purpose of this function is to clear any wake-up events latched | |
194 | * in the PRCM PM_WKST_x registers. It is possible that a wake-up event | |
195 | * may occur whilst attempting to clear a PM_WKST_x register and thus | |
196 | * set another bit in this register. A while loop is used to ensure | |
197 | * that any peripheral wake-up events occurring while attempting to | |
198 | * clear the PM_WKST_x are detected and cleared. | |
199 | */ | |
8cb0ac99 | 200 | static int prcm_clear_mod_irqs(s16 module, u8 regs) |
8bd22949 | 201 | { |
71a80775 | 202 | u32 wkst, fclk, iclk, clken; |
77da2d91 JH |
203 | u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; |
204 | u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; | |
205 | u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; | |
5d805978 PW |
206 | u16 grpsel_off = (regs == 3) ? |
207 | OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; | |
8cb0ac99 | 208 | int c = 0; |
8bd22949 | 209 | |
c4d7e58f PW |
210 | wkst = omap2_prm_read_mod_reg(module, wkst_off); |
211 | wkst &= omap2_prm_read_mod_reg(module, grpsel_off); | |
8bd22949 | 212 | if (wkst) { |
c4d7e58f PW |
213 | iclk = omap2_cm_read_mod_reg(module, iclk_off); |
214 | fclk = omap2_cm_read_mod_reg(module, fclk_off); | |
77da2d91 | 215 | while (wkst) { |
71a80775 | 216 | clken = wkst; |
c4d7e58f | 217 | omap2_cm_set_mod_reg_bits(clken, module, iclk_off); |
71a80775 VP |
218 | /* |
219 | * For USBHOST, we don't know whether HOST1 or | |
220 | * HOST2 woke us up, so enable both f-clocks | |
221 | */ | |
222 | if (module == OMAP3430ES2_USBHOST_MOD) | |
223 | clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; | |
c4d7e58f PW |
224 | omap2_cm_set_mod_reg_bits(clken, module, fclk_off); |
225 | omap2_prm_write_mod_reg(wkst, module, wkst_off); | |
226 | wkst = omap2_prm_read_mod_reg(module, wkst_off); | |
8cb0ac99 | 227 | c++; |
77da2d91 | 228 | } |
c4d7e58f PW |
229 | omap2_cm_write_mod_reg(iclk, module, iclk_off); |
230 | omap2_cm_write_mod_reg(fclk, module, fclk_off); | |
8bd22949 | 231 | } |
8cb0ac99 PW |
232 | |
233 | return c; | |
234 | } | |
235 | ||
236 | static int _prcm_int_handle_wakeup(void) | |
237 | { | |
238 | int c; | |
239 | ||
240 | c = prcm_clear_mod_irqs(WKUP_MOD, 1); | |
241 | c += prcm_clear_mod_irqs(CORE_MOD, 1); | |
242 | c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); | |
243 | if (omap_rev() > OMAP3430_REV_ES1_0) { | |
244 | c += prcm_clear_mod_irqs(CORE_MOD, 3); | |
245 | c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); | |
246 | } | |
247 | ||
248 | return c; | |
77da2d91 | 249 | } |
8bd22949 | 250 | |
77da2d91 JH |
251 | /* |
252 | * PRCM Interrupt Handler | |
253 | * | |
254 | * The PRM_IRQSTATUS_MPU register indicates if there are any pending | |
255 | * interrupts from the PRCM for the MPU. These bits must be cleared in | |
256 | * order to clear the PRCM interrupt. The PRCM interrupt handler is | |
257 | * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear | |
258 | * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU | |
259 | * register indicates that a wake-up event is pending for the MPU and | |
260 | * this bit can only be cleared if the all the wake-up events latched | |
261 | * in the various PM_WKST_x registers have been cleared. The interrupt | |
262 | * handler is implemented using a do-while loop so that if a wake-up | |
263 | * event occurred during the processing of the prcm interrupt handler | |
264 | * (setting a bit in the corresponding PM_WKST_x register and thus | |
265 | * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) | |
266 | * this would be handled. | |
267 | */ | |
268 | static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) | |
269 | { | |
d6290a3e | 270 | u32 irqenable_mpu, irqstatus_mpu; |
8cb0ac99 | 271 | int c = 0; |
77da2d91 | 272 | |
c4d7e58f | 273 | irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD, |
d6290a3e | 274 | OMAP3_PRM_IRQENABLE_MPU_OFFSET); |
c4d7e58f | 275 | irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, |
d6290a3e KH |
276 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
277 | irqstatus_mpu &= irqenable_mpu; | |
8cb0ac99 | 278 | |
d6290a3e | 279 | do { |
2bc4ef71 PW |
280 | if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK | |
281 | OMAP3430_IO_ST_MASK)) { | |
8cb0ac99 PW |
282 | c = _prcm_int_handle_wakeup(); |
283 | ||
284 | /* | |
285 | * Is the MPU PRCM interrupt handler racing with the | |
286 | * IVA2 PRCM interrupt handler ? | |
287 | */ | |
288 | WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " | |
289 | "but no wakeup sources are marked\n"); | |
290 | } else { | |
291 | /* XXX we need to expand our PRCM interrupt handler */ | |
292 | WARN(1, "prcm: WARNING: PRCM interrupt received, but " | |
293 | "no code to handle it (%08x)\n", irqstatus_mpu); | |
294 | } | |
295 | ||
c4d7e58f | 296 | omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD, |
77da2d91 | 297 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
8bd22949 | 298 | |
c4d7e58f | 299 | irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, |
d6290a3e KH |
300 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
301 | irqstatus_mpu &= irqenable_mpu; | |
302 | ||
303 | } while (irqstatus_mpu); | |
8bd22949 KH |
304 | |
305 | return IRQ_HANDLED; | |
306 | } | |
307 | ||
076f2cc4 | 308 | static void omap34xx_do_sram_idle(unsigned long save_state) |
57f277b0 | 309 | { |
076f2cc4 | 310 | _omap_sram_idle(omap3_arm_context, save_state); |
57f277b0 RN |
311 | } |
312 | ||
99e6a4d2 | 313 | void omap_sram_idle(void) |
8bd22949 KH |
314 | { |
315 | /* Variable to tell what needs to be saved and restored | |
316 | * in omap_sram_idle*/ | |
317 | /* save_state = 0 => Nothing to save and restored */ | |
318 | /* save_state = 1 => Only L1 and logic lost */ | |
319 | /* save_state = 2 => Only L2 lost */ | |
320 | /* save_state = 3 => L1, L2 and logic lost */ | |
fa3c2a4f RN |
321 | int save_state = 0; |
322 | int mpu_next_state = PWRDM_POWER_ON; | |
323 | int per_next_state = PWRDM_POWER_ON; | |
324 | int core_next_state = PWRDM_POWER_ON; | |
72e06d08 | 325 | int per_going_off; |
2f5939c3 | 326 | int core_prev_state, per_prev_state; |
13a6fe0f | 327 | u32 sdrc_pwr = 0; |
8bd22949 KH |
328 | |
329 | if (!_omap_sram_idle) | |
330 | return; | |
331 | ||
fa3c2a4f RN |
332 | pwrdm_clear_all_prev_pwrst(mpu_pwrdm); |
333 | pwrdm_clear_all_prev_pwrst(neon_pwrdm); | |
334 | pwrdm_clear_all_prev_pwrst(core_pwrdm); | |
335 | pwrdm_clear_all_prev_pwrst(per_pwrdm); | |
336 | ||
8bd22949 KH |
337 | mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
338 | switch (mpu_next_state) { | |
fa3c2a4f | 339 | case PWRDM_POWER_ON: |
8bd22949 KH |
340 | case PWRDM_POWER_RET: |
341 | /* No need to save context */ | |
342 | save_state = 0; | |
343 | break; | |
61255ab9 RN |
344 | case PWRDM_POWER_OFF: |
345 | save_state = 3; | |
346 | break; | |
8bd22949 KH |
347 | default: |
348 | /* Invalid state */ | |
349 | printk(KERN_ERR "Invalid mpu state in sram_idle\n"); | |
350 | return; | |
351 | } | |
fe617af7 PDS |
352 | pwrdm_pre_transition(); |
353 | ||
fa3c2a4f RN |
354 | /* NEON control */ |
355 | if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) | |
7139178e | 356 | pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); |
fa3c2a4f | 357 | |
40742fa8 | 358 | /* Enable IO-PAD and IO-CHAIN wakeups */ |
658ce97e | 359 | per_next_state = pwrdm_read_next_pwrst(per_pwrdm); |
ecf157d0 | 360 | core_next_state = pwrdm_read_next_pwrst(core_pwrdm); |
d5c47d7e KH |
361 | if (omap3_has_io_wakeup() && |
362 | (per_next_state < PWRDM_POWER_ON || | |
363 | core_next_state < PWRDM_POWER_ON)) { | |
c4d7e58f | 364 | omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); |
40742fa8 MC |
365 | omap3_enable_io_chain(); |
366 | } | |
367 | ||
0d8e2d0d | 368 | /* Block console output in case it is on one of the OMAP UARTs */ |
e83df17f KH |
369 | if (!is_suspending()) |
370 | if (per_next_state < PWRDM_POWER_ON || | |
371 | core_next_state < PWRDM_POWER_ON) | |
ac751efa | 372 | if (!console_trylock()) |
e83df17f | 373 | goto console_still_active; |
0d8e2d0d | 374 | |
40742fa8 | 375 | /* PER */ |
658ce97e | 376 | if (per_next_state < PWRDM_POWER_ON) { |
72e06d08 | 377 | per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; |
658ce97e | 378 | omap_uart_prepare_idle(2); |
cd4f1fae | 379 | omap_uart_prepare_idle(3); |
72e06d08 | 380 | omap2_gpio_prepare_for_idle(per_going_off); |
e7410cf7 | 381 | if (per_next_state == PWRDM_POWER_OFF) |
ecf157d0 | 382 | omap3_per_save_context(); |
658ce97e KH |
383 | } |
384 | ||
385 | /* CORE */ | |
fa3c2a4f | 386 | if (core_next_state < PWRDM_POWER_ON) { |
fa3c2a4f RN |
387 | omap_uart_prepare_idle(0); |
388 | omap_uart_prepare_idle(1); | |
2f5939c3 RN |
389 | if (core_next_state == PWRDM_POWER_OFF) { |
390 | omap3_core_save_context(); | |
f0611a5c | 391 | omap3_cm_save_context(); |
2f5939c3 | 392 | } |
fa3c2a4f | 393 | } |
40742fa8 | 394 | |
f18cc2ff | 395 | omap3_intc_prepare_idle(); |
8bd22949 | 396 | |
13a6fe0f | 397 | /* |
f265dc4c RN |
398 | * On EMU/HS devices ROM code restores a SRDC value |
399 | * from scratchpad which has automatic self refresh on timeout | |
83521291 | 400 | * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. |
f265dc4c RN |
401 | * Hence store/restore the SDRC_POWER register here. |
402 | */ | |
13a6fe0f TK |
403 | if (omap_rev() >= OMAP3430_REV_ES3_0 && |
404 | omap_type() != OMAP2_DEVICE_TYPE_GP && | |
f265dc4c | 405 | core_next_state == PWRDM_POWER_OFF) |
13a6fe0f | 406 | sdrc_pwr = sdrc_read_reg(SDRC_POWER); |
13a6fe0f | 407 | |
61255ab9 | 408 | /* |
076f2cc4 RK |
409 | * omap3_arm_context is the location where some ARM context |
410 | * get saved. The rest is placed on the stack, and restored | |
411 | * from there before resuming. | |
61255ab9 | 412 | */ |
076f2cc4 RK |
413 | if (save_state == 1 || save_state == 3) |
414 | cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, save_state, | |
415 | omap34xx_do_sram_idle); | |
416 | else | |
417 | omap34xx_do_sram_idle(save_state); | |
8bd22949 | 418 | |
f265dc4c | 419 | /* Restore normal SDRC POWER settings */ |
13a6fe0f TK |
420 | if (omap_rev() >= OMAP3430_REV_ES3_0 && |
421 | omap_type() != OMAP2_DEVICE_TYPE_GP && | |
422 | core_next_state == PWRDM_POWER_OFF) | |
423 | sdrc_write_reg(sdrc_pwr, SDRC_POWER); | |
424 | ||
658ce97e | 425 | /* CORE */ |
fa3c2a4f | 426 | if (core_next_state < PWRDM_POWER_ON) { |
2f5939c3 RN |
427 | core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); |
428 | if (core_prev_state == PWRDM_POWER_OFF) { | |
429 | omap3_core_restore_context(); | |
f0611a5c | 430 | omap3_cm_restore_context(); |
2f5939c3 | 431 | omap3_sram_restore_context(); |
8a917d2f | 432 | omap2_sms_restore_context(); |
2f5939c3 | 433 | } |
658ce97e KH |
434 | omap_uart_resume_idle(0); |
435 | omap_uart_resume_idle(1); | |
436 | if (core_next_state == PWRDM_POWER_OFF) | |
c4d7e58f | 437 | omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, |
658ce97e KH |
438 | OMAP3430_GR_MOD, |
439 | OMAP3_PRM_VOLTCTRL_OFFSET); | |
440 | } | |
f18cc2ff | 441 | omap3_intc_resume_idle(); |
658ce97e KH |
442 | |
443 | /* PER */ | |
444 | if (per_next_state < PWRDM_POWER_ON) { | |
445 | per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); | |
43ffcd9a KH |
446 | omap2_gpio_resume_after_idle(); |
447 | if (per_prev_state == PWRDM_POWER_OFF) | |
658ce97e | 448 | omap3_per_restore_context(); |
ecf157d0 | 449 | omap_uart_resume_idle(2); |
cd4f1fae | 450 | omap_uart_resume_idle(3); |
fa3c2a4f | 451 | } |
fe617af7 | 452 | |
e83df17f | 453 | if (!is_suspending()) |
ac751efa | 454 | console_unlock(); |
0d8e2d0d PW |
455 | |
456 | console_still_active: | |
3a7ec26b | 457 | /* Disable IO-PAD and IO-CHAIN wakeup */ |
58a5559e KH |
458 | if (omap3_has_io_wakeup() && |
459 | (per_next_state < PWRDM_POWER_ON || | |
460 | core_next_state < PWRDM_POWER_ON)) { | |
c4d7e58f PW |
461 | omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, |
462 | PM_WKEN); | |
3a7ec26b KJ |
463 | omap3_disable_io_chain(); |
464 | } | |
658ce97e | 465 | |
fe617af7 PDS |
466 | pwrdm_post_transition(); |
467 | ||
5cd1937b | 468 | clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); |
8bd22949 KH |
469 | } |
470 | ||
20b01669 | 471 | int omap3_can_sleep(void) |
8bd22949 | 472 | { |
c40552bc KH |
473 | if (!sleep_while_idle) |
474 | return 0; | |
4af4016c KH |
475 | if (!omap_uart_can_sleep()) |
476 | return 0; | |
8bd22949 KH |
477 | return 1; |
478 | } | |
479 | ||
8bd22949 KH |
480 | static void omap3_pm_idle(void) |
481 | { | |
482 | local_irq_disable(); | |
483 | local_fiq_disable(); | |
484 | ||
485 | if (!omap3_can_sleep()) | |
486 | goto out; | |
487 | ||
cf22854c | 488 | if (omap_irq_pending() || need_resched()) |
8bd22949 KH |
489 | goto out; |
490 | ||
5e7c58dc JP |
491 | trace_power_start(POWER_CSTATE, 1, smp_processor_id()); |
492 | trace_cpu_idle(1, smp_processor_id()); | |
493 | ||
8bd22949 KH |
494 | omap_sram_idle(); |
495 | ||
5e7c58dc JP |
496 | trace_power_end(smp_processor_id()); |
497 | trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); | |
498 | ||
8bd22949 KH |
499 | out: |
500 | local_fiq_enable(); | |
501 | local_irq_enable(); | |
502 | } | |
503 | ||
10f90ed2 | 504 | #ifdef CONFIG_SUSPEND |
8bd22949 KH |
505 | static int omap3_pm_suspend(void) |
506 | { | |
507 | struct power_state *pwrst; | |
508 | int state, ret = 0; | |
509 | ||
8e2efde9 AK |
510 | if (wakeup_timer_seconds || wakeup_timer_milliseconds) |
511 | omap2_pm_wakeup_on_timer(wakeup_timer_seconds, | |
512 | wakeup_timer_milliseconds); | |
d7814e4d | 513 | |
8bd22949 KH |
514 | /* Read current next_pwrsts */ |
515 | list_for_each_entry(pwrst, &pwrst_list, node) | |
516 | pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); | |
517 | /* Set ones wanted by suspend */ | |
518 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
eb6a2c75 | 519 | if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) |
8bd22949 KH |
520 | goto restore; |
521 | if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) | |
522 | goto restore; | |
523 | } | |
524 | ||
4af4016c | 525 | omap_uart_prepare_suspend(); |
2bbe3af3 TK |
526 | omap3_intc_suspend(); |
527 | ||
8bd22949 KH |
528 | omap_sram_idle(); |
529 | ||
530 | restore: | |
531 | /* Restore next_pwrsts */ | |
532 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
8bd22949 KH |
533 | state = pwrdm_read_prev_pwrst(pwrst->pwrdm); |
534 | if (state > pwrst->next_state) { | |
535 | printk(KERN_INFO "Powerdomain (%s) didn't enter " | |
536 | "target state %d\n", | |
537 | pwrst->pwrdm->name, pwrst->next_state); | |
538 | ret = -1; | |
539 | } | |
eb6a2c75 | 540 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); |
8bd22949 KH |
541 | } |
542 | if (ret) | |
543 | printk(KERN_ERR "Could not enter target state in pm_suspend\n"); | |
544 | else | |
545 | printk(KERN_INFO "Successfully put all powerdomains " | |
546 | "to target state\n"); | |
547 | ||
548 | return ret; | |
549 | } | |
550 | ||
2466211e | 551 | static int omap3_pm_enter(suspend_state_t unused) |
8bd22949 KH |
552 | { |
553 | int ret = 0; | |
554 | ||
2466211e | 555 | switch (suspend_state) { |
8bd22949 KH |
556 | case PM_SUSPEND_STANDBY: |
557 | case PM_SUSPEND_MEM: | |
558 | ret = omap3_pm_suspend(); | |
559 | break; | |
560 | default: | |
561 | ret = -EINVAL; | |
562 | } | |
563 | ||
564 | return ret; | |
565 | } | |
566 | ||
2466211e TK |
567 | /* Hooks to enable / disable UART interrupts during suspend */ |
568 | static int omap3_pm_begin(suspend_state_t state) | |
569 | { | |
c166381d | 570 | disable_hlt(); |
2466211e TK |
571 | suspend_state = state; |
572 | omap_uart_enable_irqs(0); | |
573 | return 0; | |
574 | } | |
575 | ||
576 | static void omap3_pm_end(void) | |
577 | { | |
578 | suspend_state = PM_SUSPEND_ON; | |
579 | omap_uart_enable_irqs(1); | |
c166381d | 580 | enable_hlt(); |
2466211e TK |
581 | return; |
582 | } | |
583 | ||
2f55ac07 | 584 | static const struct platform_suspend_ops omap_pm_ops = { |
2466211e TK |
585 | .begin = omap3_pm_begin, |
586 | .end = omap3_pm_end, | |
8bd22949 | 587 | .enter = omap3_pm_enter, |
8bd22949 KH |
588 | .valid = suspend_valid_only_mem, |
589 | }; | |
10f90ed2 | 590 | #endif /* CONFIG_SUSPEND */ |
8bd22949 | 591 | |
1155e426 KH |
592 | |
593 | /** | |
594 | * omap3_iva_idle(): ensure IVA is in idle so it can be put into | |
595 | * retention | |
596 | * | |
597 | * In cases where IVA2 is activated by bootcode, it may prevent | |
598 | * full-chip retention or off-mode because it is not idle. This | |
599 | * function forces the IVA2 into idle state so it can go | |
600 | * into retention/off and thus allow full-chip retention/off. | |
601 | * | |
602 | **/ | |
603 | static void __init omap3_iva_idle(void) | |
604 | { | |
605 | /* ensure IVA2 clock is disabled */ | |
c4d7e58f | 606 | omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); |
1155e426 KH |
607 | |
608 | /* if no clock activity, nothing else to do */ | |
c4d7e58f | 609 | if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & |
1155e426 KH |
610 | OMAP3430_CLKACTIVITY_IVA2_MASK)) |
611 | return; | |
612 | ||
613 | /* Reset IVA2 */ | |
c4d7e58f | 614 | omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | |
2bc4ef71 PW |
615 | OMAP3430_RST2_IVA2_MASK | |
616 | OMAP3430_RST3_IVA2_MASK, | |
37903009 | 617 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
1155e426 KH |
618 | |
619 | /* Enable IVA2 clock */ | |
c4d7e58f | 620 | omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, |
1155e426 KH |
621 | OMAP3430_IVA2_MOD, CM_FCLKEN); |
622 | ||
623 | /* Set IVA2 boot mode to 'idle' */ | |
624 | omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, | |
625 | OMAP343X_CONTROL_IVA2_BOOTMOD); | |
626 | ||
627 | /* Un-reset IVA2 */ | |
c4d7e58f | 628 | omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
1155e426 KH |
629 | |
630 | /* Disable IVA2 clock */ | |
c4d7e58f | 631 | omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); |
1155e426 KH |
632 | |
633 | /* Reset IVA2 */ | |
c4d7e58f | 634 | omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | |
2bc4ef71 PW |
635 | OMAP3430_RST2_IVA2_MASK | |
636 | OMAP3430_RST3_IVA2_MASK, | |
37903009 | 637 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
1155e426 KH |
638 | } |
639 | ||
8111b221 | 640 | static void __init omap3_d2d_idle(void) |
8bd22949 | 641 | { |
8111b221 KH |
642 | u16 mask, padconf; |
643 | ||
644 | /* In a stand alone OMAP3430 where there is not a stacked | |
645 | * modem for the D2D Idle Ack and D2D MStandby must be pulled | |
646 | * high. S CONTROL_PADCONF_SAD2D_IDLEACK and | |
647 | * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ | |
648 | mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ | |
649 | padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); | |
650 | padconf |= mask; | |
651 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); | |
652 | ||
653 | padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); | |
654 | padconf |= mask; | |
655 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); | |
656 | ||
8bd22949 | 657 | /* reset modem */ |
c4d7e58f | 658 | omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | |
2bc4ef71 | 659 | OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, |
37903009 | 660 | CORE_MOD, OMAP2_RM_RSTCTRL); |
c4d7e58f | 661 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); |
8111b221 | 662 | } |
8bd22949 | 663 | |
8111b221 KH |
664 | static void __init prcm_setup_regs(void) |
665 | { | |
e5863689 G |
666 | u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? |
667 | OMAP3630_EN_UART4_MASK : 0; | |
668 | u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? | |
669 | OMAP3630_GRPSEL_UART4_MASK : 0; | |
670 | ||
4ef70c06 | 671 | /* XXX This should be handled by hwmod code or SCM init code */ |
2fd0f75c | 672 | omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); |
b296c811 | 673 | |
8bd22949 KH |
674 | /* |
675 | * Enable control of expternal oscillator through | |
676 | * sys_clkreq. In the long run clock framework should | |
677 | * take care of this. | |
678 | */ | |
c4d7e58f | 679 | omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, |
8bd22949 KH |
680 | 1 << OMAP_AUTOEXTCLKMODE_SHIFT, |
681 | OMAP3430_GR_MOD, | |
682 | OMAP3_PRM_CLKSRC_CTRL_OFFSET); | |
683 | ||
684 | /* setup wakup source */ | |
c4d7e58f | 685 | omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | |
2fd0f75c | 686 | OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, |
8bd22949 KH |
687 | WKUP_MOD, PM_WKEN); |
688 | /* No need to write EN_IO, that is always enabled */ | |
c4d7e58f | 689 | omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | |
275f675c PW |
690 | OMAP3430_GRPSEL_GPT1_MASK | |
691 | OMAP3430_GRPSEL_GPT12_MASK, | |
8bd22949 KH |
692 | WKUP_MOD, OMAP3430_PM_MPUGRPSEL); |
693 | /* For some reason IO doesn't generate wakeup event even if | |
694 | * it is selected to mpu wakeup goup */ | |
c4d7e58f | 695 | omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, |
8bd22949 | 696 | OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); |
1155e426 | 697 | |
b92c5721 | 698 | /* Enable PM_WKEN to support DSS LPR */ |
c4d7e58f | 699 | omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, |
b92c5721 SV |
700 | OMAP3430_DSS_MOD, PM_WKEN); |
701 | ||
b427f92f | 702 | /* Enable wakeups in PER */ |
c4d7e58f | 703 | omap2_prm_write_mod_reg(omap3630_en_uart4_mask | |
e5863689 | 704 | OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | |
2fd0f75c PW |
705 | OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | |
706 | OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | | |
707 | OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | | |
708 | OMAP3430_EN_MCBSP4_MASK, | |
b427f92f | 709 | OMAP3430_PER_MOD, PM_WKEN); |
eb350f74 | 710 | /* and allow them to wake up MPU */ |
c4d7e58f | 711 | omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask | |
e5863689 | 712 | OMAP3430_GRPSEL_GPIO2_MASK | |
275f675c PW |
713 | OMAP3430_GRPSEL_GPIO3_MASK | |
714 | OMAP3430_GRPSEL_GPIO4_MASK | | |
715 | OMAP3430_GRPSEL_GPIO5_MASK | | |
716 | OMAP3430_GRPSEL_GPIO6_MASK | | |
717 | OMAP3430_GRPSEL_UART3_MASK | | |
718 | OMAP3430_GRPSEL_MCBSP2_MASK | | |
719 | OMAP3430_GRPSEL_MCBSP3_MASK | | |
720 | OMAP3430_GRPSEL_MCBSP4_MASK, | |
eb350f74 KH |
721 | OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); |
722 | ||
d3fd3290 | 723 | /* Don't attach IVA interrupts */ |
c4d7e58f PW |
724 | omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); |
725 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); | |
726 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); | |
727 | omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); | |
d3fd3290 | 728 | |
b1340d17 | 729 | /* Clear any pending 'reset' flags */ |
c4d7e58f PW |
730 | omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); |
731 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); | |
732 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); | |
733 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); | |
734 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); | |
735 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); | |
736 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); | |
b1340d17 | 737 | |
014c46db | 738 | /* Clear any pending PRCM interrupts */ |
c4d7e58f | 739 | omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
014c46db | 740 | |
1155e426 | 741 | omap3_iva_idle(); |
8111b221 | 742 | omap3_d2d_idle(); |
8bd22949 KH |
743 | } |
744 | ||
c40552bc KH |
745 | void omap3_pm_off_mode_enable(int enable) |
746 | { | |
747 | struct power_state *pwrst; | |
748 | u32 state; | |
749 | ||
750 | if (enable) | |
751 | state = PWRDM_POWER_OFF; | |
752 | else | |
753 | state = PWRDM_POWER_RET; | |
754 | ||
755 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
cc1b6028 EV |
756 | if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && |
757 | pwrst->pwrdm == core_pwrdm && | |
758 | state == PWRDM_POWER_OFF) { | |
759 | pwrst->next_state = PWRDM_POWER_RET; | |
e16b41bf | 760 | pr_warn("%s: Core OFF disabled due to errata i583\n", |
cc1b6028 EV |
761 | __func__); |
762 | } else { | |
763 | pwrst->next_state = state; | |
764 | } | |
765 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); | |
c40552bc KH |
766 | } |
767 | } | |
768 | ||
68d4778c TK |
769 | int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) |
770 | { | |
771 | struct power_state *pwrst; | |
772 | ||
773 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
774 | if (pwrst->pwrdm == pwrdm) | |
775 | return pwrst->next_state; | |
776 | } | |
777 | return -EINVAL; | |
778 | } | |
779 | ||
780 | int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) | |
781 | { | |
782 | struct power_state *pwrst; | |
783 | ||
784 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
785 | if (pwrst->pwrdm == pwrdm) { | |
786 | pwrst->next_state = state; | |
787 | return 0; | |
788 | } | |
789 | } | |
790 | return -EINVAL; | |
791 | } | |
792 | ||
a23456e9 | 793 | static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) |
8bd22949 KH |
794 | { |
795 | struct power_state *pwrst; | |
796 | ||
797 | if (!pwrdm->pwrsts) | |
798 | return 0; | |
799 | ||
d3d381c6 | 800 | pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); |
8bd22949 KH |
801 | if (!pwrst) |
802 | return -ENOMEM; | |
803 | pwrst->pwrdm = pwrdm; | |
804 | pwrst->next_state = PWRDM_POWER_RET; | |
805 | list_add(&pwrst->node, &pwrst_list); | |
806 | ||
807 | if (pwrdm_has_hdwr_sar(pwrdm)) | |
808 | pwrdm_enable_hdwr_sar(pwrdm); | |
809 | ||
eb6a2c75 | 810 | return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); |
8bd22949 KH |
811 | } |
812 | ||
813 | /* | |
814 | * Enable hw supervised mode for all clockdomains if it's | |
815 | * supported. Initiate sleep transition for other clockdomains, if | |
816 | * they are not used | |
817 | */ | |
a23456e9 | 818 | static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) |
8bd22949 KH |
819 | { |
820 | if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) | |
5cd1937b | 821 | clkdm_allow_idle(clkdm); |
8bd22949 KH |
822 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && |
823 | atomic_read(&clkdm->usecount) == 0) | |
68b921ad | 824 | clkdm_sleep(clkdm); |
8bd22949 KH |
825 | return 0; |
826 | } | |
827 | ||
3231fc88 RN |
828 | void omap_push_sram_idle(void) |
829 | { | |
830 | _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, | |
831 | omap34xx_cpu_suspend_sz); | |
27d59a4a TK |
832 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) |
833 | _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, | |
834 | save_secure_ram_context_sz); | |
3231fc88 RN |
835 | } |
836 | ||
8cdfd834 NM |
837 | static void __init pm_errata_configure(void) |
838 | { | |
c4236d2e | 839 | if (cpu_is_omap3630()) { |
458e999e | 840 | pm34xx_errata |= PM_RTA_ERRATUM_i608; |
c4236d2e PDS |
841 | /* Enable the l2 cache toggling in sleep logic */ |
842 | enable_omap3630_toggle_l2_on_restore(); | |
cc1b6028 EV |
843 | if (omap_rev() < OMAP3630_REV_ES1_2) |
844 | pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583; | |
c4236d2e | 845 | } |
8cdfd834 NM |
846 | } |
847 | ||
7cc515f7 | 848 | static int __init omap3_pm_init(void) |
8bd22949 KH |
849 | { |
850 | struct power_state *pwrst, *tmp; | |
55ed9694 | 851 | struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; |
8bd22949 KH |
852 | int ret; |
853 | ||
854 | if (!cpu_is_omap34xx()) | |
855 | return -ENODEV; | |
856 | ||
8cdfd834 NM |
857 | pm_errata_configure(); |
858 | ||
8bd22949 KH |
859 | /* XXX prcm_setup_regs needs to be before enabling hw |
860 | * supervised mode for powerdomains */ | |
861 | prcm_setup_regs(); | |
862 | ||
863 | ret = request_irq(INT_34XX_PRCM_MPU_IRQ, | |
864 | (irq_handler_t)prcm_interrupt_handler, | |
865 | IRQF_DISABLED, "prcm", NULL); | |
866 | if (ret) { | |
867 | printk(KERN_ERR "request_irq failed to register for 0x%x\n", | |
868 | INT_34XX_PRCM_MPU_IRQ); | |
869 | goto err1; | |
870 | } | |
871 | ||
a23456e9 | 872 | ret = pwrdm_for_each(pwrdms_setup, NULL); |
8bd22949 KH |
873 | if (ret) { |
874 | printk(KERN_ERR "Failed to setup powerdomains\n"); | |
875 | goto err2; | |
876 | } | |
877 | ||
a23456e9 | 878 | (void) clkdm_for_each(clkdms_setup, NULL); |
8bd22949 KH |
879 | |
880 | mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); | |
881 | if (mpu_pwrdm == NULL) { | |
882 | printk(KERN_ERR "Failed to get mpu_pwrdm\n"); | |
883 | goto err2; | |
884 | } | |
885 | ||
fa3c2a4f RN |
886 | neon_pwrdm = pwrdm_lookup("neon_pwrdm"); |
887 | per_pwrdm = pwrdm_lookup("per_pwrdm"); | |
888 | core_pwrdm = pwrdm_lookup("core_pwrdm"); | |
c16c3f67 | 889 | cam_pwrdm = pwrdm_lookup("cam_pwrdm"); |
fa3c2a4f | 890 | |
55ed9694 PW |
891 | neon_clkdm = clkdm_lookup("neon_clkdm"); |
892 | mpu_clkdm = clkdm_lookup("mpu_clkdm"); | |
893 | per_clkdm = clkdm_lookup("per_clkdm"); | |
894 | core_clkdm = clkdm_lookup("core_clkdm"); | |
895 | ||
3231fc88 | 896 | omap_push_sram_idle(); |
10f90ed2 | 897 | #ifdef CONFIG_SUSPEND |
8bd22949 | 898 | suspend_set_ops(&omap_pm_ops); |
10f90ed2 | 899 | #endif /* CONFIG_SUSPEND */ |
8bd22949 KH |
900 | |
901 | pm_idle = omap3_pm_idle; | |
0343371e | 902 | omap3_idle_init(); |
8bd22949 | 903 | |
458e999e NM |
904 | /* |
905 | * RTA is disabled during initialization as per erratum i608 | |
906 | * it is safer to disable RTA by the bootloader, but we would like | |
907 | * to be doubly sure here and prevent any mishaps. | |
908 | */ | |
909 | if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) | |
910 | omap3630_ctrl_disable_rta(); | |
911 | ||
55ed9694 | 912 | clkdm_add_wkdep(neon_clkdm, mpu_clkdm); |
27d59a4a TK |
913 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { |
914 | omap3_secure_ram_storage = | |
915 | kmalloc(0x803F, GFP_KERNEL); | |
916 | if (!omap3_secure_ram_storage) | |
917 | printk(KERN_ERR "Memory allocation failed when" | |
918 | "allocating for secure sram context\n"); | |
9d97140b TK |
919 | |
920 | local_irq_disable(); | |
921 | local_fiq_disable(); | |
922 | ||
923 | omap_dma_global_context_save(); | |
617fcc98 | 924 | omap3_save_secure_ram_context(); |
9d97140b TK |
925 | omap_dma_global_context_restore(); |
926 | ||
927 | local_irq_enable(); | |
928 | local_fiq_enable(); | |
27d59a4a | 929 | } |
27d59a4a | 930 | |
9d97140b | 931 | omap3_save_scratchpad_contents(); |
8bd22949 KH |
932 | err1: |
933 | return ret; | |
934 | err2: | |
935 | free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); | |
936 | list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { | |
937 | list_del(&pwrst->node); | |
938 | kfree(pwrst); | |
939 | } | |
940 | return ret; | |
941 | } | |
942 | ||
943 | late_initcall(omap3_pm_init); |