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ad67ef68 PW |
1 | /* |
2 | * OMAP powerdomain control | |
3 | * | |
4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | |
55ed9694 | 5 | * Copyright (C) 2007-2009 Nokia Corporation |
ad67ef68 PW |
6 | * |
7 | * Written by Paul Walmsley | |
8 | * | |
3a759f09 AP |
9 | * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com> |
10 | * | |
ad67ef68 PW |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
33903eb5 | 15 | #undef DEBUG |
ad67ef68 PW |
16 | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/types.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/list.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/err.h> | |
25 | #include <linux/io.h> | |
26 | ||
27 | #include <asm/atomic.h> | |
28 | ||
29 | #include "cm.h" | |
30 | #include "cm-regbits-34xx.h" | |
3a759f09 | 31 | #include "cm-regbits-44xx.h" |
ad67ef68 PW |
32 | #include "prm.h" |
33 | #include "prm-regbits-34xx.h" | |
3a759f09 | 34 | #include "prm-regbits-44xx.h" |
ad67ef68 | 35 | |
ce491cf8 TL |
36 | #include <plat/cpu.h> |
37 | #include <plat/powerdomain.h> | |
38 | #include <plat/clockdomain.h> | |
55ed9694 | 39 | #include <plat/prcm.h> |
ad67ef68 | 40 | |
6199ab26 PDS |
41 | #include "pm.h" |
42 | ||
ba20bb12 PDS |
43 | enum { |
44 | PWRDM_STATE_NOW = 0, | |
45 | PWRDM_STATE_PREV, | |
46 | }; | |
47 | ||
3a759f09 AP |
48 | /* Variable holding value of the CPU dependent PWRSTCTRL Register Offset */ |
49 | static u16 pwrstctrl_reg_offs; | |
50 | ||
51 | /* Variable holding value of the CPU dependent PWRSTST Register Offset */ | |
52 | static u16 pwrstst_reg_offs; | |
53 | ||
54 | /* OMAP3 and OMAP4 specific register bit initialisations | |
55 | * Notice that the names here are not according to each power | |
56 | * domain but the bit mapping used applies to all of them | |
57 | */ | |
58 | ||
59 | /* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */ | |
60 | #define OMAP_MEM0_ONSTATE_MASK OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK | |
61 | #define OMAP_MEM1_ONSTATE_MASK OMAP3430_L1FLATMEMONSTATE_MASK | |
62 | #define OMAP_MEM2_ONSTATE_MASK OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK | |
63 | #define OMAP_MEM3_ONSTATE_MASK OMAP3430_L2FLATMEMONSTATE_MASK | |
64 | #define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK | |
65 | ||
66 | /* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */ | |
67 | #define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE | |
68 | #define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE | |
69 | #define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE | |
70 | #define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE | |
71 | #define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK | |
72 | ||
73 | /* OMAP3 and OMAP4 Memory Status bits */ | |
74 | #define OMAP_MEM0_STATEST_MASK OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK | |
75 | #define OMAP_MEM1_STATEST_MASK OMAP3430_L1FLATMEMSTATEST_MASK | |
76 | #define OMAP_MEM2_STATEST_MASK OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK | |
77 | #define OMAP_MEM3_STATEST_MASK OMAP3430_L2FLATMEMSTATEST_MASK | |
78 | #define OMAP_MEM4_STATEST_MASK OMAP4430_OCP_NRET_BANK_STATEST_MASK | |
79 | ||
ad67ef68 PW |
80 | /* pwrdm_list contains all registered struct powerdomains */ |
81 | static LIST_HEAD(pwrdm_list); | |
82 | ||
ad67ef68 PW |
83 | /* Private functions */ |
84 | ||
ad67ef68 PW |
85 | static struct powerdomain *_pwrdm_lookup(const char *name) |
86 | { | |
87 | struct powerdomain *pwrdm, *temp_pwrdm; | |
88 | ||
89 | pwrdm = NULL; | |
90 | ||
91 | list_for_each_entry(temp_pwrdm, &pwrdm_list, node) { | |
92 | if (!strcmp(name, temp_pwrdm->name)) { | |
93 | pwrdm = temp_pwrdm; | |
94 | break; | |
95 | } | |
96 | } | |
97 | ||
98 | return pwrdm; | |
99 | } | |
100 | ||
e909d62a PW |
101 | /** |
102 | * _pwrdm_register - register a powerdomain | |
103 | * @pwrdm: struct powerdomain * to register | |
104 | * | |
105 | * Adds a powerdomain to the internal powerdomain list. Returns | |
106 | * -EINVAL if given a null pointer, -EEXIST if a powerdomain is | |
107 | * already registered by the provided name, or 0 upon success. | |
108 | */ | |
109 | static int _pwrdm_register(struct powerdomain *pwrdm) | |
110 | { | |
111 | int i; | |
112 | ||
113 | if (!pwrdm) | |
114 | return -EINVAL; | |
115 | ||
116 | if (!omap_chip_is(pwrdm->omap_chip)) | |
117 | return -EINVAL; | |
118 | ||
119 | if (_pwrdm_lookup(pwrdm->name)) | |
120 | return -EEXIST; | |
121 | ||
122 | list_add(&pwrdm->node, &pwrdm_list); | |
123 | ||
124 | /* Initialize the powerdomain's state counter */ | |
cf57aa7c | 125 | for (i = 0; i < PWRDM_MAX_PWRSTS; i++) |
e909d62a PW |
126 | pwrdm->state_counter[i] = 0; |
127 | ||
cde08f81 TG |
128 | pwrdm->ret_logic_off_counter = 0; |
129 | for (i = 0; i < pwrdm->banks; i++) | |
130 | pwrdm->ret_mem_off_counter[i] = 0; | |
131 | ||
e909d62a PW |
132 | pwrdm_wait_transition(pwrdm); |
133 | pwrdm->state = pwrdm_read_pwrst(pwrdm); | |
134 | pwrdm->state_counter[pwrdm->state] = 1; | |
135 | ||
136 | pr_debug("powerdomain: registered %s\n", pwrdm->name); | |
137 | ||
138 | return 0; | |
139 | } | |
140 | ||
cde08f81 TG |
141 | static void _update_logic_membank_counters(struct powerdomain *pwrdm) |
142 | { | |
143 | int i; | |
144 | u8 prev_logic_pwrst, prev_mem_pwrst; | |
145 | ||
146 | prev_logic_pwrst = pwrdm_read_prev_logic_pwrst(pwrdm); | |
147 | if ((pwrdm->pwrsts_logic_ret == PWRSTS_OFF_RET) && | |
148 | (prev_logic_pwrst == PWRDM_POWER_OFF)) | |
149 | pwrdm->ret_logic_off_counter++; | |
150 | ||
151 | for (i = 0; i < pwrdm->banks; i++) { | |
152 | prev_mem_pwrst = pwrdm_read_prev_mem_pwrst(pwrdm, i); | |
153 | ||
154 | if ((pwrdm->pwrsts_mem_ret[i] == PWRSTS_OFF_RET) && | |
155 | (prev_mem_pwrst == PWRDM_POWER_OFF)) | |
156 | pwrdm->ret_mem_off_counter[i]++; | |
157 | } | |
158 | } | |
159 | ||
ba20bb12 PDS |
160 | static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag) |
161 | { | |
162 | ||
163 | int prev; | |
164 | int state; | |
165 | ||
166 | if (pwrdm == NULL) | |
167 | return -EINVAL; | |
168 | ||
169 | state = pwrdm_read_pwrst(pwrdm); | |
170 | ||
171 | switch (flag) { | |
172 | case PWRDM_STATE_NOW: | |
173 | prev = pwrdm->state; | |
174 | break; | |
175 | case PWRDM_STATE_PREV: | |
176 | prev = pwrdm_read_prev_pwrst(pwrdm); | |
177 | if (pwrdm->state != prev) | |
178 | pwrdm->state_counter[prev]++; | |
cde08f81 TG |
179 | if (prev == PWRDM_POWER_RET) |
180 | _update_logic_membank_counters(pwrdm); | |
ba20bb12 PDS |
181 | break; |
182 | default: | |
183 | return -EINVAL; | |
184 | } | |
185 | ||
186 | if (state != prev) | |
187 | pwrdm->state_counter[state]++; | |
188 | ||
6199ab26 PDS |
189 | pm_dbg_update_time(pwrdm, prev); |
190 | ||
ba20bb12 PDS |
191 | pwrdm->state = state; |
192 | ||
193 | return 0; | |
194 | } | |
195 | ||
6199ab26 | 196 | static int _pwrdm_pre_transition_cb(struct powerdomain *pwrdm, void *unused) |
ba20bb12 PDS |
197 | { |
198 | pwrdm_clear_all_prev_pwrst(pwrdm); | |
199 | _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW); | |
200 | return 0; | |
201 | } | |
202 | ||
6199ab26 | 203 | static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused) |
ba20bb12 PDS |
204 | { |
205 | _pwrdm_state_switch(pwrdm, PWRDM_STATE_PREV); | |
206 | return 0; | |
207 | } | |
208 | ||
ad67ef68 PW |
209 | /* Public functions */ |
210 | ||
211 | /** | |
212 | * pwrdm_init - set up the powerdomain layer | |
f0271d65 | 213 | * @pwrdm_list: array of struct powerdomain pointers to register |
ad67ef68 | 214 | * |
f0271d65 PW |
215 | * Loop through the array of powerdomains @pwrdm_list, registering all |
216 | * that are available on the current CPU. If pwrdm_list is supplied | |
217 | * and not null, all of the referenced powerdomains will be | |
218 | * registered. No return value. XXX pwrdm_list is not really a | |
219 | * "list"; it is an array. Rename appropriately. | |
ad67ef68 PW |
220 | */ |
221 | void pwrdm_init(struct powerdomain **pwrdm_list) | |
222 | { | |
223 | struct powerdomain **p = NULL; | |
224 | ||
3a759f09 AP |
225 | if (cpu_is_omap24xx() | cpu_is_omap34xx()) { |
226 | pwrstctrl_reg_offs = OMAP2_PM_PWSTCTRL; | |
227 | pwrstst_reg_offs = OMAP2_PM_PWSTST; | |
228 | } else if (cpu_is_omap44xx()) { | |
229 | pwrstctrl_reg_offs = OMAP4_PM_PWSTCTRL; | |
230 | pwrstst_reg_offs = OMAP4_PM_PWSTST; | |
231 | } else { | |
232 | printk(KERN_ERR "Power Domain struct not supported for " \ | |
233 | "this CPU\n"); | |
234 | return; | |
235 | } | |
236 | ||
ba20bb12 | 237 | if (pwrdm_list) { |
e909d62a PW |
238 | for (p = pwrdm_list; *p; p++) |
239 | _pwrdm_register(*p); | |
ad67ef68 | 240 | } |
ad67ef68 PW |
241 | } |
242 | ||
243 | /** | |
244 | * pwrdm_lookup - look up a powerdomain by name, return a pointer | |
245 | * @name: name of powerdomain | |
246 | * | |
f0271d65 PW |
247 | * Find a registered powerdomain by its name @name. Returns a pointer |
248 | * to the struct powerdomain if found, or NULL otherwise. | |
ad67ef68 PW |
249 | */ |
250 | struct powerdomain *pwrdm_lookup(const char *name) | |
251 | { | |
252 | struct powerdomain *pwrdm; | |
ad67ef68 PW |
253 | |
254 | if (!name) | |
255 | return NULL; | |
256 | ||
ad67ef68 | 257 | pwrdm = _pwrdm_lookup(name); |
ad67ef68 PW |
258 | |
259 | return pwrdm; | |
260 | } | |
261 | ||
262 | /** | |
e909d62a | 263 | * pwrdm_for_each - call function on each registered clockdomain |
ad67ef68 PW |
264 | * @fn: callback function * |
265 | * | |
f0271d65 PW |
266 | * Call the supplied function @fn for each registered powerdomain. |
267 | * The callback function @fn can return anything but 0 to bail out | |
268 | * early from the iterator. Returns the last return value of the | |
269 | * callback function, which should be 0 for success or anything else | |
270 | * to indicate failure; or -EINVAL if the function pointer is null. | |
ad67ef68 | 271 | */ |
e909d62a PW |
272 | int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), |
273 | void *user) | |
ad67ef68 PW |
274 | { |
275 | struct powerdomain *temp_pwrdm; | |
ad67ef68 PW |
276 | int ret = 0; |
277 | ||
278 | if (!fn) | |
279 | return -EINVAL; | |
280 | ||
ad67ef68 | 281 | list_for_each_entry(temp_pwrdm, &pwrdm_list, node) { |
6199ab26 | 282 | ret = (*fn)(temp_pwrdm, user); |
ad67ef68 PW |
283 | if (ret) |
284 | break; | |
285 | } | |
ee894b18 AB |
286 | |
287 | return ret; | |
288 | } | |
289 | ||
8420bb13 PW |
290 | /** |
291 | * pwrdm_add_clkdm - add a clockdomain to a powerdomain | |
292 | * @pwrdm: struct powerdomain * to add the clockdomain to | |
293 | * @clkdm: struct clockdomain * to associate with a powerdomain | |
294 | * | |
f0271d65 | 295 | * Associate the clockdomain @clkdm with a powerdomain @pwrdm. This |
8420bb13 PW |
296 | * enables the use of pwrdm_for_each_clkdm(). Returns -EINVAL if |
297 | * presented with invalid pointers; -ENOMEM if memory could not be allocated; | |
298 | * or 0 upon success. | |
299 | */ | |
300 | int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm) | |
301 | { | |
8420bb13 PW |
302 | int i; |
303 | int ret = -EINVAL; | |
304 | ||
305 | if (!pwrdm || !clkdm) | |
306 | return -EINVAL; | |
307 | ||
308 | pr_debug("powerdomain: associating clockdomain %s with powerdomain " | |
309 | "%s\n", clkdm->name, pwrdm->name); | |
310 | ||
8420bb13 PW |
311 | for (i = 0; i < PWRDM_MAX_CLKDMS; i++) { |
312 | if (!pwrdm->pwrdm_clkdms[i]) | |
313 | break; | |
314 | #ifdef DEBUG | |
315 | if (pwrdm->pwrdm_clkdms[i] == clkdm) { | |
316 | ret = -EINVAL; | |
317 | goto pac_exit; | |
318 | } | |
319 | #endif | |
320 | } | |
321 | ||
322 | if (i == PWRDM_MAX_CLKDMS) { | |
323 | pr_debug("powerdomain: increase PWRDM_MAX_CLKDMS for " | |
324 | "pwrdm %s clkdm %s\n", pwrdm->name, clkdm->name); | |
325 | WARN_ON(1); | |
326 | ret = -ENOMEM; | |
327 | goto pac_exit; | |
328 | } | |
329 | ||
330 | pwrdm->pwrdm_clkdms[i] = clkdm; | |
331 | ||
332 | ret = 0; | |
333 | ||
334 | pac_exit: | |
8420bb13 PW |
335 | return ret; |
336 | } | |
337 | ||
338 | /** | |
339 | * pwrdm_del_clkdm - remove a clockdomain from a powerdomain | |
340 | * @pwrdm: struct powerdomain * to add the clockdomain to | |
341 | * @clkdm: struct clockdomain * to associate with a powerdomain | |
342 | * | |
f0271d65 PW |
343 | * Dissociate the clockdomain @clkdm from the powerdomain |
344 | * @pwrdm. Returns -EINVAL if presented with invalid pointers; -ENOENT | |
345 | * if @clkdm was not associated with the powerdomain, or 0 upon | |
346 | * success. | |
8420bb13 PW |
347 | */ |
348 | int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm) | |
349 | { | |
8420bb13 PW |
350 | int ret = -EINVAL; |
351 | int i; | |
352 | ||
353 | if (!pwrdm || !clkdm) | |
354 | return -EINVAL; | |
355 | ||
356 | pr_debug("powerdomain: dissociating clockdomain %s from powerdomain " | |
357 | "%s\n", clkdm->name, pwrdm->name); | |
358 | ||
8420bb13 PW |
359 | for (i = 0; i < PWRDM_MAX_CLKDMS; i++) |
360 | if (pwrdm->pwrdm_clkdms[i] == clkdm) | |
361 | break; | |
362 | ||
363 | if (i == PWRDM_MAX_CLKDMS) { | |
364 | pr_debug("powerdomain: clkdm %s not associated with pwrdm " | |
365 | "%s ?!\n", clkdm->name, pwrdm->name); | |
366 | ret = -ENOENT; | |
367 | goto pdc_exit; | |
368 | } | |
369 | ||
370 | pwrdm->pwrdm_clkdms[i] = NULL; | |
371 | ||
372 | ret = 0; | |
373 | ||
374 | pdc_exit: | |
8420bb13 PW |
375 | return ret; |
376 | } | |
377 | ||
378 | /** | |
379 | * pwrdm_for_each_clkdm - call function on each clkdm in a pwrdm | |
380 | * @pwrdm: struct powerdomain * to iterate over | |
381 | * @fn: callback function * | |
382 | * | |
f0271d65 PW |
383 | * Call the supplied function @fn for each clockdomain in the powerdomain |
384 | * @pwrdm. The callback function can return anything but 0 to bail | |
e909d62a PW |
385 | * out early from the iterator. Returns -EINVAL if presented with |
386 | * invalid pointers; or passes along the last return value of the | |
387 | * callback function, which should be 0 for success or anything else | |
388 | * to indicate failure. | |
8420bb13 PW |
389 | */ |
390 | int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, | |
391 | int (*fn)(struct powerdomain *pwrdm, | |
392 | struct clockdomain *clkdm)) | |
393 | { | |
8420bb13 PW |
394 | int ret = 0; |
395 | int i; | |
396 | ||
397 | if (!fn) | |
398 | return -EINVAL; | |
399 | ||
8420bb13 PW |
400 | for (i = 0; i < PWRDM_MAX_CLKDMS && !ret; i++) |
401 | ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]); | |
402 | ||
8420bb13 PW |
403 | return ret; |
404 | } | |
405 | ||
ad67ef68 PW |
406 | /** |
407 | * pwrdm_get_mem_bank_count - get number of memory banks in this powerdomain | |
408 | * @pwrdm: struct powerdomain * | |
409 | * | |
f0271d65 | 410 | * Return the number of controllable memory banks in powerdomain @pwrdm, |
ad67ef68 PW |
411 | * starting with 1. Returns -EINVAL if the powerdomain pointer is null. |
412 | */ | |
413 | int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm) | |
414 | { | |
415 | if (!pwrdm) | |
416 | return -EINVAL; | |
417 | ||
418 | return pwrdm->banks; | |
419 | } | |
420 | ||
421 | /** | |
422 | * pwrdm_set_next_pwrst - set next powerdomain power state | |
423 | * @pwrdm: struct powerdomain * to set | |
424 | * @pwrst: one of the PWRDM_POWER_* macros | |
425 | * | |
f0271d65 | 426 | * Set the powerdomain @pwrdm's next power state to @pwrst. The powerdomain |
ad67ef68 PW |
427 | * may not enter this state immediately if the preconditions for this state |
428 | * have not been satisfied. Returns -EINVAL if the powerdomain pointer is | |
429 | * null or if the power state is invalid for the powerdomin, or returns 0 | |
430 | * upon success. | |
431 | */ | |
432 | int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) | |
433 | { | |
434 | if (!pwrdm) | |
435 | return -EINVAL; | |
436 | ||
437 | if (!(pwrdm->pwrsts & (1 << pwrst))) | |
438 | return -EINVAL; | |
439 | ||
440 | pr_debug("powerdomain: setting next powerstate for %s to %0x\n", | |
441 | pwrdm->name, pwrst); | |
442 | ||
443 | prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, | |
444 | (pwrst << OMAP_POWERSTATE_SHIFT), | |
3a759f09 | 445 | pwrdm->prcm_offs, pwrstctrl_reg_offs); |
ad67ef68 PW |
446 | |
447 | return 0; | |
448 | } | |
449 | ||
450 | /** | |
451 | * pwrdm_read_next_pwrst - get next powerdomain power state | |
452 | * @pwrdm: struct powerdomain * to get power state | |
453 | * | |
f0271d65 | 454 | * Return the powerdomain @pwrdm's next power state. Returns -EINVAL |
ad67ef68 PW |
455 | * if the powerdomain pointer is null or returns the next power state |
456 | * upon success. | |
457 | */ | |
458 | int pwrdm_read_next_pwrst(struct powerdomain *pwrdm) | |
459 | { | |
460 | if (!pwrdm) | |
461 | return -EINVAL; | |
462 | ||
3a759f09 AP |
463 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, |
464 | pwrstctrl_reg_offs, OMAP_POWERSTATE_MASK); | |
ad67ef68 PW |
465 | } |
466 | ||
467 | /** | |
468 | * pwrdm_read_pwrst - get current powerdomain power state | |
469 | * @pwrdm: struct powerdomain * to get power state | |
470 | * | |
f0271d65 | 471 | * Return the powerdomain @pwrdm's current power state. Returns -EINVAL |
ad67ef68 PW |
472 | * if the powerdomain pointer is null or returns the current power state |
473 | * upon success. | |
474 | */ | |
475 | int pwrdm_read_pwrst(struct powerdomain *pwrdm) | |
476 | { | |
477 | if (!pwrdm) | |
478 | return -EINVAL; | |
479 | ||
3a759f09 AP |
480 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, |
481 | pwrstst_reg_offs, OMAP_POWERSTATEST_MASK); | |
ad67ef68 PW |
482 | } |
483 | ||
484 | /** | |
485 | * pwrdm_read_prev_pwrst - get previous powerdomain power state | |
486 | * @pwrdm: struct powerdomain * to get previous power state | |
487 | * | |
f0271d65 | 488 | * Return the powerdomain @pwrdm's previous power state. Returns -EINVAL |
ad67ef68 PW |
489 | * if the powerdomain pointer is null or returns the previous power state |
490 | * upon success. | |
491 | */ | |
492 | int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) | |
493 | { | |
494 | if (!pwrdm) | |
495 | return -EINVAL; | |
496 | ||
497 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST, | |
498 | OMAP3430_LASTPOWERSTATEENTERED_MASK); | |
499 | } | |
500 | ||
501 | /** | |
502 | * pwrdm_set_logic_retst - set powerdomain logic power state upon retention | |
503 | * @pwrdm: struct powerdomain * to set | |
504 | * @pwrst: one of the PWRDM_POWER_* macros | |
505 | * | |
f0271d65 PW |
506 | * Set the next power state @pwrst that the logic portion of the |
507 | * powerdomain @pwrdm will enter when the powerdomain enters retention. | |
508 | * This will be either RETENTION or OFF, if supported. Returns | |
509 | * -EINVAL if the powerdomain pointer is null or the target power | |
510 | * state is not not supported, or returns 0 upon success. | |
ad67ef68 PW |
511 | */ |
512 | int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) | |
513 | { | |
514 | if (!pwrdm) | |
515 | return -EINVAL; | |
516 | ||
517 | if (!(pwrdm->pwrsts_logic_ret & (1 << pwrst))) | |
518 | return -EINVAL; | |
519 | ||
520 | pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n", | |
521 | pwrdm->name, pwrst); | |
522 | ||
523 | /* | |
524 | * The register bit names below may not correspond to the | |
525 | * actual names of the bits in each powerdomain's register, | |
526 | * but the type of value returned is the same for each | |
527 | * powerdomain. | |
528 | */ | |
529 | prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE, | |
530 | (pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE)), | |
3a759f09 | 531 | pwrdm->prcm_offs, pwrstctrl_reg_offs); |
ad67ef68 PW |
532 | |
533 | return 0; | |
534 | } | |
535 | ||
536 | /** | |
537 | * pwrdm_set_mem_onst - set memory power state while powerdomain ON | |
538 | * @pwrdm: struct powerdomain * to set | |
539 | * @bank: memory bank number to set (0-3) | |
540 | * @pwrst: one of the PWRDM_POWER_* macros | |
541 | * | |
f0271d65 PW |
542 | * Set the next power state @pwrst that memory bank @bank of the |
543 | * powerdomain @pwrdm will enter when the powerdomain enters the ON | |
544 | * state. @bank will be a number from 0 to 3, and represents different | |
545 | * types of memory, depending on the powerdomain. Returns -EINVAL if | |
546 | * the powerdomain pointer is null or the target power state is not | |
547 | * not supported for this memory bank, -EEXIST if the target memory | |
548 | * bank does not exist or is not controllable, or returns 0 upon | |
549 | * success. | |
ad67ef68 PW |
550 | */ |
551 | int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) | |
552 | { | |
553 | u32 m; | |
554 | ||
555 | if (!pwrdm) | |
556 | return -EINVAL; | |
557 | ||
558 | if (pwrdm->banks < (bank + 1)) | |
559 | return -EEXIST; | |
560 | ||
561 | if (!(pwrdm->pwrsts_mem_on[bank] & (1 << pwrst))) | |
562 | return -EINVAL; | |
563 | ||
564 | pr_debug("powerdomain: setting next memory powerstate for domain %s " | |
565 | "bank %0x while pwrdm-ON to %0x\n", pwrdm->name, bank, pwrst); | |
566 | ||
567 | /* | |
568 | * The register bit names below may not correspond to the | |
569 | * actual names of the bits in each powerdomain's register, | |
570 | * but the type of value returned is the same for each | |
571 | * powerdomain. | |
572 | */ | |
573 | switch (bank) { | |
574 | case 0: | |
3a759f09 | 575 | m = OMAP_MEM0_ONSTATE_MASK; |
ad67ef68 PW |
576 | break; |
577 | case 1: | |
3a759f09 | 578 | m = OMAP_MEM1_ONSTATE_MASK; |
ad67ef68 PW |
579 | break; |
580 | case 2: | |
3a759f09 | 581 | m = OMAP_MEM2_ONSTATE_MASK; |
ad67ef68 PW |
582 | break; |
583 | case 3: | |
3a759f09 AP |
584 | m = OMAP_MEM3_ONSTATE_MASK; |
585 | break; | |
586 | case 4: | |
587 | m = OMAP_MEM4_ONSTATE_MASK; | |
ad67ef68 PW |
588 | break; |
589 | default: | |
590 | WARN_ON(1); /* should never happen */ | |
591 | return -EEXIST; | |
592 | } | |
593 | ||
594 | prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), | |
3a759f09 | 595 | pwrdm->prcm_offs, pwrstctrl_reg_offs); |
ad67ef68 PW |
596 | |
597 | return 0; | |
598 | } | |
599 | ||
600 | /** | |
601 | * pwrdm_set_mem_retst - set memory power state while powerdomain in RET | |
602 | * @pwrdm: struct powerdomain * to set | |
603 | * @bank: memory bank number to set (0-3) | |
604 | * @pwrst: one of the PWRDM_POWER_* macros | |
605 | * | |
f0271d65 PW |
606 | * Set the next power state @pwrst that memory bank @bank of the |
607 | * powerdomain @pwrdm will enter when the powerdomain enters the | |
608 | * RETENTION state. Bank will be a number from 0 to 3, and represents | |
609 | * different types of memory, depending on the powerdomain. @pwrst | |
610 | * will be either RETENTION or OFF, if supported. Returns -EINVAL if | |
611 | * the powerdomain pointer is null or the target power state is not | |
612 | * not supported for this memory bank, -EEXIST if the target memory | |
613 | * bank does not exist or is not controllable, or returns 0 upon | |
614 | * success. | |
ad67ef68 PW |
615 | */ |
616 | int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) | |
617 | { | |
618 | u32 m; | |
619 | ||
620 | if (!pwrdm) | |
621 | return -EINVAL; | |
622 | ||
623 | if (pwrdm->banks < (bank + 1)) | |
624 | return -EEXIST; | |
625 | ||
626 | if (!(pwrdm->pwrsts_mem_ret[bank] & (1 << pwrst))) | |
627 | return -EINVAL; | |
628 | ||
629 | pr_debug("powerdomain: setting next memory powerstate for domain %s " | |
630 | "bank %0x while pwrdm-RET to %0x\n", pwrdm->name, bank, pwrst); | |
631 | ||
632 | /* | |
633 | * The register bit names below may not correspond to the | |
634 | * actual names of the bits in each powerdomain's register, | |
635 | * but the type of value returned is the same for each | |
636 | * powerdomain. | |
637 | */ | |
638 | switch (bank) { | |
639 | case 0: | |
3a759f09 | 640 | m = OMAP_MEM0_RETSTATE_MASK; |
ad67ef68 PW |
641 | break; |
642 | case 1: | |
3a759f09 | 643 | m = OMAP_MEM1_RETSTATE_MASK; |
ad67ef68 PW |
644 | break; |
645 | case 2: | |
3a759f09 | 646 | m = OMAP_MEM2_RETSTATE_MASK; |
ad67ef68 PW |
647 | break; |
648 | case 3: | |
3a759f09 AP |
649 | m = OMAP_MEM3_RETSTATE_MASK; |
650 | break; | |
651 | case 4: | |
652 | m = OMAP_MEM4_RETSTATE_MASK; | |
ad67ef68 PW |
653 | break; |
654 | default: | |
655 | WARN_ON(1); /* should never happen */ | |
656 | return -EEXIST; | |
657 | } | |
658 | ||
659 | prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, | |
3a759f09 | 660 | pwrstctrl_reg_offs); |
ad67ef68 PW |
661 | |
662 | return 0; | |
663 | } | |
664 | ||
665 | /** | |
666 | * pwrdm_read_logic_pwrst - get current powerdomain logic retention power state | |
667 | * @pwrdm: struct powerdomain * to get current logic retention power state | |
668 | * | |
f0271d65 PW |
669 | * Return the power state that the logic portion of powerdomain @pwrdm |
670 | * will enter when the powerdomain enters retention. Returns -EINVAL | |
671 | * if the powerdomain pointer is null or returns the logic retention | |
672 | * power state upon success. | |
ad67ef68 PW |
673 | */ |
674 | int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) | |
675 | { | |
676 | if (!pwrdm) | |
677 | return -EINVAL; | |
678 | ||
3a759f09 AP |
679 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, |
680 | pwrstst_reg_offs, OMAP3430_LOGICSTATEST); | |
ad67ef68 PW |
681 | } |
682 | ||
683 | /** | |
684 | * pwrdm_read_prev_logic_pwrst - get previous powerdomain logic power state | |
685 | * @pwrdm: struct powerdomain * to get previous logic power state | |
686 | * | |
f0271d65 PW |
687 | * Return the powerdomain @pwrdm's previous logic power state. Returns |
688 | * -EINVAL if the powerdomain pointer is null or returns the previous | |
689 | * logic power state upon success. | |
ad67ef68 PW |
690 | */ |
691 | int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) | |
692 | { | |
693 | if (!pwrdm) | |
694 | return -EINVAL; | |
695 | ||
696 | /* | |
697 | * The register bit names below may not correspond to the | |
698 | * actual names of the bits in each powerdomain's register, | |
699 | * but the type of value returned is the same for each | |
700 | * powerdomain. | |
701 | */ | |
702 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST, | |
703 | OMAP3430_LASTLOGICSTATEENTERED); | |
704 | } | |
705 | ||
1e3d0d2b TG |
706 | /** |
707 | * pwrdm_read_logic_retst - get next powerdomain logic power state | |
708 | * @pwrdm: struct powerdomain * to get next logic power state | |
709 | * | |
710 | * Return the powerdomain pwrdm's logic power state. Returns -EINVAL | |
711 | * if the powerdomain pointer is null or returns the next logic | |
712 | * power state upon success. | |
713 | */ | |
714 | int pwrdm_read_logic_retst(struct powerdomain *pwrdm) | |
715 | { | |
716 | if (!pwrdm) | |
717 | return -EINVAL; | |
718 | ||
719 | /* | |
720 | * The register bit names below may not correspond to the | |
721 | * actual names of the bits in each powerdomain's register, | |
722 | * but the type of value returned is the same for each | |
723 | * powerdomain. | |
724 | */ | |
725 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, pwrstctrl_reg_offs, | |
726 | OMAP3430_LOGICSTATEST); | |
727 | } | |
728 | ||
ad67ef68 PW |
729 | /** |
730 | * pwrdm_read_mem_pwrst - get current memory bank power state | |
731 | * @pwrdm: struct powerdomain * to get current memory bank power state | |
732 | * @bank: memory bank number (0-3) | |
733 | * | |
f0271d65 PW |
734 | * Return the powerdomain @pwrdm's current memory power state for bank |
735 | * @bank. Returns -EINVAL if the powerdomain pointer is null, -EEXIST if | |
ad67ef68 PW |
736 | * the target memory bank does not exist or is not controllable, or |
737 | * returns the current memory power state upon success. | |
738 | */ | |
739 | int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | |
740 | { | |
741 | u32 m; | |
742 | ||
743 | if (!pwrdm) | |
744 | return -EINVAL; | |
745 | ||
746 | if (pwrdm->banks < (bank + 1)) | |
747 | return -EEXIST; | |
748 | ||
3863c74b TG |
749 | if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK) |
750 | bank = 1; | |
751 | ||
ad67ef68 PW |
752 | /* |
753 | * The register bit names below may not correspond to the | |
754 | * actual names of the bits in each powerdomain's register, | |
755 | * but the type of value returned is the same for each | |
756 | * powerdomain. | |
757 | */ | |
758 | switch (bank) { | |
759 | case 0: | |
3a759f09 | 760 | m = OMAP_MEM0_STATEST_MASK; |
ad67ef68 PW |
761 | break; |
762 | case 1: | |
3a759f09 | 763 | m = OMAP_MEM1_STATEST_MASK; |
ad67ef68 PW |
764 | break; |
765 | case 2: | |
3a759f09 | 766 | m = OMAP_MEM2_STATEST_MASK; |
ad67ef68 PW |
767 | break; |
768 | case 3: | |
3a759f09 AP |
769 | m = OMAP_MEM3_STATEST_MASK; |
770 | break; | |
771 | case 4: | |
772 | m = OMAP_MEM4_STATEST_MASK; | |
ad67ef68 PW |
773 | break; |
774 | default: | |
775 | WARN_ON(1); /* should never happen */ | |
776 | return -EEXIST; | |
777 | } | |
778 | ||
3a759f09 AP |
779 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, |
780 | pwrstst_reg_offs, m); | |
ad67ef68 PW |
781 | } |
782 | ||
783 | /** | |
784 | * pwrdm_read_prev_mem_pwrst - get previous memory bank power state | |
785 | * @pwrdm: struct powerdomain * to get previous memory bank power state | |
786 | * @bank: memory bank number (0-3) | |
787 | * | |
f0271d65 PW |
788 | * Return the powerdomain @pwrdm's previous memory power state for |
789 | * bank @bank. Returns -EINVAL if the powerdomain pointer is null, | |
790 | * -EEXIST if the target memory bank does not exist or is not | |
791 | * controllable, or returns the previous memory power state upon | |
792 | * success. | |
ad67ef68 PW |
793 | */ |
794 | int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | |
795 | { | |
796 | u32 m; | |
797 | ||
798 | if (!pwrdm) | |
799 | return -EINVAL; | |
800 | ||
801 | if (pwrdm->banks < (bank + 1)) | |
802 | return -EEXIST; | |
803 | ||
3863c74b TG |
804 | if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK) |
805 | bank = 1; | |
806 | ||
ad67ef68 PW |
807 | /* |
808 | * The register bit names below may not correspond to the | |
809 | * actual names of the bits in each powerdomain's register, | |
810 | * but the type of value returned is the same for each | |
811 | * powerdomain. | |
812 | */ | |
813 | switch (bank) { | |
814 | case 0: | |
815 | m = OMAP3430_LASTMEM1STATEENTERED_MASK; | |
816 | break; | |
817 | case 1: | |
818 | m = OMAP3430_LASTMEM2STATEENTERED_MASK; | |
819 | break; | |
820 | case 2: | |
821 | m = OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK; | |
822 | break; | |
823 | case 3: | |
824 | m = OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK; | |
825 | break; | |
826 | default: | |
827 | WARN_ON(1); /* should never happen */ | |
828 | return -EEXIST; | |
829 | } | |
830 | ||
831 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, | |
832 | OMAP3430_PM_PREPWSTST, m); | |
833 | } | |
834 | ||
1e3d0d2b TG |
835 | /** |
836 | * pwrdm_read_mem_retst - get next memory bank power state | |
837 | * @pwrdm: struct powerdomain * to get mext memory bank power state | |
838 | * @bank: memory bank number (0-3) | |
839 | * | |
840 | * Return the powerdomain pwrdm's next memory power state for bank | |
841 | * x. Returns -EINVAL if the powerdomain pointer is null, -EEXIST if | |
842 | * the target memory bank does not exist or is not controllable, or | |
843 | * returns the next memory power state upon success. | |
844 | */ | |
845 | int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) | |
846 | { | |
847 | u32 m; | |
848 | ||
849 | if (!pwrdm) | |
850 | return -EINVAL; | |
851 | ||
852 | if (pwrdm->banks < (bank + 1)) | |
853 | return -EEXIST; | |
854 | ||
855 | /* | |
856 | * The register bit names below may not correspond to the | |
857 | * actual names of the bits in each powerdomain's register, | |
858 | * but the type of value returned is the same for each | |
859 | * powerdomain. | |
860 | */ | |
861 | switch (bank) { | |
862 | case 0: | |
863 | m = OMAP_MEM0_RETSTATE_MASK; | |
864 | break; | |
865 | case 1: | |
866 | m = OMAP_MEM1_RETSTATE_MASK; | |
867 | break; | |
868 | case 2: | |
869 | m = OMAP_MEM2_RETSTATE_MASK; | |
870 | break; | |
871 | case 3: | |
872 | m = OMAP_MEM3_RETSTATE_MASK; | |
873 | break; | |
874 | case 4: | |
875 | m = OMAP_MEM4_RETSTATE_MASK; | |
876 | default: | |
877 | WARN_ON(1); /* should never happen */ | |
878 | return -EEXIST; | |
879 | } | |
880 | ||
881 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, | |
882 | pwrstctrl_reg_offs, m); | |
883 | } | |
884 | ||
ad67ef68 PW |
885 | /** |
886 | * pwrdm_clear_all_prev_pwrst - clear previous powerstate register for a pwrdm | |
887 | * @pwrdm: struct powerdomain * to clear | |
888 | * | |
f0271d65 PW |
889 | * Clear the powerdomain's previous power state register @pwrdm. |
890 | * Clears the entire register, including logic and memory bank | |
891 | * previous power states. Returns -EINVAL if the powerdomain pointer | |
892 | * is null, or returns 0 upon success. | |
ad67ef68 PW |
893 | */ |
894 | int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) | |
895 | { | |
896 | if (!pwrdm) | |
897 | return -EINVAL; | |
898 | ||
899 | /* | |
900 | * XXX should get the powerdomain's current state here; | |
901 | * warn & fail if it is not ON. | |
902 | */ | |
903 | ||
904 | pr_debug("powerdomain: clearing previous power state reg for %s\n", | |
905 | pwrdm->name); | |
906 | ||
907 | prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST); | |
908 | ||
909 | return 0; | |
910 | } | |
911 | ||
0b7cbfb5 PW |
912 | /** |
913 | * pwrdm_enable_hdwr_sar - enable automatic hardware SAR for a pwrdm | |
914 | * @pwrdm: struct powerdomain * | |
915 | * | |
916 | * Enable automatic context save-and-restore upon power state change | |
f0271d65 PW |
917 | * for some devices in the powerdomain @pwrdm. Warning: this only |
918 | * affects a subset of devices in a powerdomain; check the TRM | |
919 | * closely. Returns -EINVAL if the powerdomain pointer is null or if | |
920 | * the powerdomain does not support automatic save-and-restore, or | |
921 | * returns 0 upon success. | |
0b7cbfb5 PW |
922 | */ |
923 | int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) | |
924 | { | |
925 | if (!pwrdm) | |
926 | return -EINVAL; | |
927 | ||
928 | if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR)) | |
929 | return -EINVAL; | |
930 | ||
931 | pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n", | |
932 | pwrdm->name); | |
933 | ||
934 | prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, | |
3a759f09 | 935 | pwrdm->prcm_offs, pwrstctrl_reg_offs); |
0b7cbfb5 PW |
936 | |
937 | return 0; | |
938 | } | |
939 | ||
940 | /** | |
941 | * pwrdm_disable_hdwr_sar - disable automatic hardware SAR for a pwrdm | |
942 | * @pwrdm: struct powerdomain * | |
943 | * | |
944 | * Disable automatic context save-and-restore upon power state change | |
f0271d65 PW |
945 | * for some devices in the powerdomain @pwrdm. Warning: this only |
946 | * affects a subset of devices in a powerdomain; check the TRM | |
947 | * closely. Returns -EINVAL if the powerdomain pointer is null or if | |
948 | * the powerdomain does not support automatic save-and-restore, or | |
949 | * returns 0 upon success. | |
0b7cbfb5 PW |
950 | */ |
951 | int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) | |
952 | { | |
953 | if (!pwrdm) | |
954 | return -EINVAL; | |
955 | ||
956 | if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR)) | |
957 | return -EINVAL; | |
958 | ||
959 | pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n", | |
960 | pwrdm->name); | |
961 | ||
962 | prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0, | |
3a759f09 | 963 | pwrdm->prcm_offs, pwrstctrl_reg_offs); |
0b7cbfb5 PW |
964 | |
965 | return 0; | |
966 | } | |
967 | ||
968 | /** | |
969 | * pwrdm_has_hdwr_sar - test whether powerdomain supports hardware SAR | |
970 | * @pwrdm: struct powerdomain * | |
971 | * | |
f0271d65 | 972 | * Returns 1 if powerdomain @pwrdm supports hardware save-and-restore |
0b7cbfb5 PW |
973 | * for some devices, or 0 if it does not. |
974 | */ | |
975 | bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm) | |
976 | { | |
977 | return (pwrdm && pwrdm->flags & PWRDM_HAS_HDWR_SAR) ? 1 : 0; | |
978 | } | |
979 | ||
ad67ef68 PW |
980 | /** |
981 | * pwrdm_wait_transition - wait for powerdomain power transition to finish | |
982 | * @pwrdm: struct powerdomain * to wait for | |
983 | * | |
f0271d65 | 984 | * If the powerdomain @pwrdm is in the process of a state transition, |
ad67ef68 PW |
985 | * spin until it completes the power transition, or until an iteration |
986 | * bailout value is reached. Returns -EINVAL if the powerdomain | |
987 | * pointer is null, -EAGAIN if the bailout value was reached, or | |
988 | * returns 0 upon success. | |
989 | */ | |
990 | int pwrdm_wait_transition(struct powerdomain *pwrdm) | |
991 | { | |
992 | u32 c = 0; | |
993 | ||
994 | if (!pwrdm) | |
995 | return -EINVAL; | |
996 | ||
997 | /* | |
998 | * REVISIT: pwrdm_wait_transition() may be better implemented | |
999 | * via a callback and a periodic timer check -- how long do we expect | |
1000 | * powerdomain transitions to take? | |
1001 | */ | |
1002 | ||
1003 | /* XXX Is this udelay() value meaningful? */ | |
3a759f09 | 1004 | while ((prm_read_mod_reg(pwrdm->prcm_offs, pwrstst_reg_offs) & |
ad67ef68 PW |
1005 | OMAP_INTRANSITION) && |
1006 | (c++ < PWRDM_TRANSITION_BAILOUT)) | |
3a759f09 | 1007 | udelay(1); |
ad67ef68 | 1008 | |
2687069f | 1009 | if (c > PWRDM_TRANSITION_BAILOUT) { |
ad67ef68 PW |
1010 | printk(KERN_ERR "powerdomain: waited too long for " |
1011 | "powerdomain %s to complete transition\n", pwrdm->name); | |
1012 | return -EAGAIN; | |
1013 | } | |
1014 | ||
1015 | pr_debug("powerdomain: completed transition in %d loops\n", c); | |
1016 | ||
1017 | return 0; | |
1018 | } | |
1019 | ||
ba20bb12 PDS |
1020 | int pwrdm_state_switch(struct powerdomain *pwrdm) |
1021 | { | |
1022 | return _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW); | |
1023 | } | |
1024 | ||
1025 | int pwrdm_clkdm_state_switch(struct clockdomain *clkdm) | |
1026 | { | |
1027 | if (clkdm != NULL && clkdm->pwrdm.ptr != NULL) { | |
1028 | pwrdm_wait_transition(clkdm->pwrdm.ptr); | |
1029 | return pwrdm_state_switch(clkdm->pwrdm.ptr); | |
1030 | } | |
1031 | ||
1032 | return -EINVAL; | |
1033 | } | |
ba20bb12 PDS |
1034 | |
1035 | int pwrdm_pre_transition(void) | |
1036 | { | |
6199ab26 | 1037 | pwrdm_for_each(_pwrdm_pre_transition_cb, NULL); |
ba20bb12 PDS |
1038 | return 0; |
1039 | } | |
1040 | ||
1041 | int pwrdm_post_transition(void) | |
1042 | { | |
6199ab26 | 1043 | pwrdm_for_each(_pwrdm_post_transition_cb, NULL); |
ba20bb12 PDS |
1044 | return 0; |
1045 | } | |
ad67ef68 | 1046 |