[deliverable/linux.git] / arch / arm / mach-omap2 / prcm-common.h

#ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
#define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H

/*
 * OMAP2/3 PRCM base and module definitions
 *
 * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
 * Copyright (C) 2007-2009 Nokia Corporation
 *
 * Written by Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/* Module offsets from both CM_BASE & PRM_BASE */

/*
 * Offsets that are the same on 24xx and 34xx
 *
 * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
 * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
 */
#define OCP_MOD						0x000
#define MPU_MOD						0x100
#define CORE_MOD					0x200
#define GFX_MOD						0x300
#define WKUP_MOD					0x400
#define PLL_MOD						0x500


/* Chip-specific module offsets */
#define OMAP24XX_GR_MOD					OCP_MOD
#define OMAP24XX_DSP_MOD				0x800

#define OMAP2430_MDM_MOD				0xc00

/* IVA2 module is < base on 3430 */
#define OMAP3430_IVA2_MOD				-0x800
#define OMAP3430ES2_SGX_MOD				GFX_MOD
#define OMAP3430_CCR_MOD				PLL_MOD
#define OMAP3430_DSS_MOD				0x600
#define OMAP3430_CAM_MOD				0x700
#define OMAP3430_PER_MOD				0x800
#define OMAP3430_EMU_MOD				0x900
#define OMAP3430_GR_MOD					0xa00
#define OMAP3430_NEON_MOD				0xb00
#define OMAP3430ES2_USBHOST_MOD				0xc00

/* 24XX register bits shared between CM & PRM registers */

/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
#define OMAP2420_EN_MMC_SHIFT				26
#define OMAP2420_EN_MMC_MASK				(1 << 26)
#define OMAP24XX_EN_UART2_SHIFT				22
#define OMAP24XX_EN_UART2_MASK				(1 << 22)
#define OMAP24XX_EN_UART1_SHIFT				21
#define OMAP24XX_EN_UART1_MASK				(1 << 21)
#define OMAP24XX_EN_MCSPI2_SHIFT			18
#define OMAP24XX_EN_MCSPI2_MASK				(1 << 18)
#define OMAP24XX_EN_MCSPI1_SHIFT			17
#define OMAP24XX_EN_MCSPI1_MASK				(1 << 17)
#define OMAP24XX_EN_MCBSP2_SHIFT			16
#define OMAP24XX_EN_MCBSP2_MASK				(1 << 16)
#define OMAP24XX_EN_MCBSP1_SHIFT			15
#define OMAP24XX_EN_MCBSP1_MASK				(1 << 15)
#define OMAP24XX_EN_GPT12_SHIFT				14
#define OMAP24XX_EN_GPT12_MASK				(1 << 14)
#define OMAP24XX_EN_GPT11_SHIFT				13
#define OMAP24XX_EN_GPT11_MASK				(1 << 13)
#define OMAP24XX_EN_GPT10_SHIFT				12
#define OMAP24XX_EN_GPT10_MASK				(1 << 12)
#define OMAP24XX_EN_GPT9_SHIFT				11
#define OMAP24XX_EN_GPT9_MASK				(1 << 11)
#define OMAP24XX_EN_GPT8_SHIFT				10
#define OMAP24XX_EN_GPT8_MASK				(1 << 10)
#define OMAP24XX_EN_GPT7_SHIFT				9
#define OMAP24XX_EN_GPT7_MASK				(1 << 9)
#define OMAP24XX_EN_GPT6_SHIFT				8
#define OMAP24XX_EN_GPT6_MASK				(1 << 8)
#define OMAP24XX_EN_GPT5_SHIFT				7
#define OMAP24XX_EN_GPT5_MASK				(1 << 7)
#define OMAP24XX_EN_GPT4_SHIFT				6
#define OMAP24XX_EN_GPT4_MASK				(1 << 6)
#define OMAP24XX_EN_GPT3_SHIFT				5
#define OMAP24XX_EN_GPT3_MASK				(1 << 5)
#define OMAP24XX_EN_GPT2_SHIFT				4
#define OMAP24XX_EN_GPT2_MASK				(1 << 4)
#define OMAP2420_EN_VLYNQ_SHIFT				3
#define OMAP2420_EN_VLYNQ_MASK				(1 << 3)

/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
#define OMAP2430_EN_GPIO5_SHIFT				10
#define OMAP2430_EN_GPIO5_MASK				(1 << 10)
#define OMAP2430_EN_MCSPI3_SHIFT			9
#define OMAP2430_EN_MCSPI3_MASK				(1 << 9)
#define OMAP2430_EN_MMCHS2_SHIFT			8
#define OMAP2430_EN_MMCHS2_MASK				(1 << 8)
#define OMAP2430_EN_MMCHS1_SHIFT			7
#define OMAP2430_EN_MMCHS1_MASK				(1 << 7)
#define OMAP24XX_EN_UART3_SHIFT				2
#define OMAP24XX_EN_UART3_MASK				(1 << 2)
#define OMAP24XX_EN_USB_SHIFT				0
#define OMAP24XX_EN_USB_MASK				(1 << 0)

/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
#define OMAP2430_EN_MDM_INTC_SHIFT			11
#define OMAP2430_EN_MDM_INTC_MASK			(1 << 11)
#define OMAP2430_EN_USBHS_SHIFT				6
#define OMAP2430_EN_USBHS_MASK				(1 << 6)

/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
#define OMAP2420_ST_MMC_SHIFT				26
#define OMAP2420_ST_MMC_MASK				(1 << 26)
#define OMAP24XX_ST_UART2_SHIFT				22
#define OMAP24XX_ST_UART2_MASK				(1 << 22)
#define OMAP24XX_ST_UART1_SHIFT				21
#define OMAP24XX_ST_UART1_MASK				(1 << 21)
#define OMAP24XX_ST_MCSPI2_SHIFT			18
#define OMAP24XX_ST_MCSPI2_MASK				(1 << 18)
#define OMAP24XX_ST_MCSPI1_SHIFT			17
#define OMAP24XX_ST_MCSPI1_MASK				(1 << 17)
#define OMAP24XX_ST_MCBSP2_SHIFT			16
#define OMAP24XX_ST_MCBSP2_MASK				(1 << 16)
#define OMAP24XX_ST_MCBSP1_SHIFT			15
#define OMAP24XX_ST_MCBSP1_MASK				(1 << 15)
#define OMAP24XX_ST_GPT12_SHIFT				14
#define OMAP24XX_ST_GPT12_MASK				(1 << 14)
#define OMAP24XX_ST_GPT11_SHIFT				13
#define OMAP24XX_ST_GPT11_MASK				(1 << 13)
#define OMAP24XX_ST_GPT10_SHIFT				12
#define OMAP24XX_ST_GPT10_MASK				(1 << 12)
#define OMAP24XX_ST_GPT9_SHIFT				11
#define OMAP24XX_ST_GPT9_MASK				(1 << 11)
#define OMAP24XX_ST_GPT8_SHIFT				10
#define OMAP24XX_ST_GPT8_MASK				(1 << 10)
#define OMAP24XX_ST_GPT7_SHIFT				9
#define OMAP24XX_ST_GPT7_MASK				(1 << 9)
#define OMAP24XX_ST_GPT6_SHIFT				8
#define OMAP24XX_ST_GPT6_MASK				(1 << 8)
#define OMAP24XX_ST_GPT5_SHIFT				7
#define OMAP24XX_ST_GPT5_MASK				(1 << 7)
#define OMAP24XX_ST_GPT4_SHIFT				6
#define OMAP24XX_ST_GPT4_MASK				(1 << 6)
#define OMAP24XX_ST_GPT3_SHIFT				5
#define OMAP24XX_ST_GPT3_MASK				(1 << 5)
#define OMAP24XX_ST_GPT2_SHIFT				4
#define OMAP24XX_ST_GPT2_MASK				(1 << 4)
#define OMAP2420_ST_VLYNQ_SHIFT				3
#define OMAP2420_ST_VLYNQ_MASK				(1 << 3)

/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
#define OMAP2430_ST_MDM_INTC_SHIFT			11
#define OMAP2430_ST_MDM_INTC_MASK			(1 << 11)
#define OMAP2430_ST_GPIO5_SHIFT				10
#define OMAP2430_ST_GPIO5_MASK				(1 << 10)
#define OMAP2430_ST_MCSPI3_SHIFT			9
#define OMAP2430_ST_MCSPI3_MASK				(1 << 9)
#define OMAP2430_ST_MMCHS2_SHIFT			8
#define OMAP2430_ST_MMCHS2_MASK				(1 << 8)
#define OMAP2430_ST_MMCHS1_SHIFT			7
#define OMAP2430_ST_MMCHS1_MASK				(1 << 7)
#define OMAP2430_ST_USBHS_SHIFT				6
#define OMAP2430_ST_USBHS_MASK				(1 << 6)
#define OMAP24XX_ST_UART3_SHIFT				2
#define OMAP24XX_ST_UART3_MASK				(1 << 2)
#define OMAP24XX_ST_USB_SHIFT				0
#define OMAP24XX_ST_USB_MASK				(1 << 0)

/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
#define OMAP24XX_EN_GPIOS_SHIFT				2
#define OMAP24XX_EN_GPIOS_MASK				(1 << 2)
#define OMAP24XX_EN_GPT1_SHIFT				0
#define OMAP24XX_EN_GPT1_MASK				(1 << 0)

/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
#define OMAP24XX_ST_GPIOS_SHIFT				2
#define OMAP24XX_ST_GPIOS_MASK				(1 << 2)
#define OMAP24XX_ST_GPT1_SHIFT				0
#define OMAP24XX_ST_GPT1_MASK				(1 << 0)

/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
#define OMAP2430_ST_MDM_SHIFT				0
#define OMAP2430_ST_MDM_MASK				(1 << 0)


/* 3430 register bits shared between CM & PRM registers */

/* CM_REVISION, PRM_REVISION shared bits */
#define OMAP3430_REV_SHIFT				0
#define OMAP3430_REV_MASK				(0xff << 0)

/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
#define OMAP3430_AUTOIDLE_MASK				(1 << 0)

/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
#define OMAP3430_EN_MMC3_MASK				(1 << 30)
#define OMAP3430_EN_MMC3_SHIFT				30
#define OMAP3430_EN_MMC2_MASK				(1 << 25)
#define OMAP3430_EN_MMC2_SHIFT				25
#define OMAP3430_EN_MMC1_MASK				(1 << 24)
#define OMAP3430_EN_MMC1_SHIFT				24
#define OMAP3430_EN_MCSPI4_MASK				(1 << 21)
#define OMAP3430_EN_MCSPI4_SHIFT			21
#define OMAP3430_EN_MCSPI3_MASK				(1 << 20)
#define OMAP3430_EN_MCSPI3_SHIFT			20
#define OMAP3430_EN_MCSPI2_MASK				(1 << 19)
#define OMAP3430_EN_MCSPI2_SHIFT			19
#define OMAP3430_EN_MCSPI1_MASK				(1 << 18)
#define OMAP3430_EN_MCSPI1_SHIFT			18
#define OMAP3430_EN_I2C3_MASK				(1 << 17)
#define OMAP3430_EN_I2C3_SHIFT				17
#define OMAP3430_EN_I2C2_MASK				(1 << 16)
#define OMAP3430_EN_I2C2_SHIFT				16
#define OMAP3430_EN_I2C1_MASK				(1 << 15)
#define OMAP3430_EN_I2C1_SHIFT				15
#define OMAP3430_EN_UART2_MASK				(1 << 14)
#define OMAP3430_EN_UART2_SHIFT				14
#define OMAP3430_EN_UART1_MASK				(1 << 13)
#define OMAP3430_EN_UART1_SHIFT				13
#define OMAP3430_EN_GPT11_MASK				(1 << 12)
#define OMAP3430_EN_GPT11_SHIFT				12
#define OMAP3430_EN_GPT10_MASK				(1 << 11)
#define OMAP3430_EN_GPT10_SHIFT				11
#define OMAP3430_EN_MCBSP5_MASK				(1 << 10)
#define OMAP3430_EN_MCBSP5_SHIFT			10
#define OMAP3430_EN_MCBSP1_MASK				(1 << 9)
#define OMAP3430_EN_MCBSP1_SHIFT			9
#define OMAP3430_EN_FSHOSTUSB_MASK			(1 << 5)
#define OMAP3430_EN_FSHOSTUSB_SHIFT			5
#define OMAP3430_EN_D2D_MASK				(1 << 3)
#define OMAP3430_EN_D2D_SHIFT				3

/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
#define OMAP3430_EN_HSOTGUSB_MASK			(1 << 4)
#define OMAP3430_EN_HSOTGUSB_SHIFT			4

/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
#define OMAP3430_ST_MMC3_SHIFT				30
#define OMAP3430_ST_MMC3_MASK				(1 << 30)
#define OMAP3430_ST_MMC2_SHIFT				25
#define OMAP3430_ST_MMC2_MASK				(1 << 25)
#define OMAP3430_ST_MMC1_SHIFT				24
#define OMAP3430_ST_MMC1_MASK				(1 << 24)
#define OMAP3430_ST_MCSPI4_SHIFT			21
#define OMAP3430_ST_MCSPI4_MASK				(1 << 21)
#define OMAP3430_ST_MCSPI3_SHIFT			20
#define OMAP3430_ST_MCSPI3_MASK				(1 << 20)
#define OMAP3430_ST_MCSPI2_SHIFT			19
#define OMAP3430_ST_MCSPI2_MASK				(1 << 19)
#define OMAP3430_ST_MCSPI1_SHIFT			18
#define OMAP3430_ST_MCSPI1_MASK				(1 << 18)
#define OMAP3430_ST_I2C3_SHIFT				17
#define OMAP3430_ST_I2C3_MASK				(1 << 17)
#define OMAP3430_ST_I2C2_SHIFT				16
#define OMAP3430_ST_I2C2_MASK				(1 << 16)
#define OMAP3430_ST_I2C1_SHIFT				15
#define OMAP3430_ST_I2C1_MASK				(1 << 15)
#define OMAP3430_ST_UART2_SHIFT				14
#define OMAP3430_ST_UART2_MASK				(1 << 14)
#define OMAP3430_ST_UART1_SHIFT				13
#define OMAP3430_ST_UART1_MASK				(1 << 13)
#define OMAP3430_ST_GPT11_SHIFT				12
#define OMAP3430_ST_GPT11_MASK				(1 << 12)
#define OMAP3430_ST_GPT10_SHIFT				11
#define OMAP3430_ST_GPT10_MASK				(1 << 11)
#define OMAP3430_ST_MCBSP5_SHIFT			10
#define OMAP3430_ST_MCBSP5_MASK				(1 << 10)
#define OMAP3430_ST_MCBSP1_SHIFT			9
#define OMAP3430_ST_MCBSP1_MASK				(1 << 9)
#define OMAP3430ES1_ST_FSHOSTUSB_SHIFT			5
#define OMAP3430ES1_ST_FSHOSTUSB_MASK			(1 << 5)
#define OMAP3430ES1_ST_HSOTGUSB_SHIFT			4
#define OMAP3430ES1_ST_HSOTGUSB_MASK			(1 << 4)
#define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT		5
#define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK		(1 << 5)
#define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT		4
#define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK		(1 << 4)
#define OMAP3430_ST_D2D_SHIFT				3
#define OMAP3430_ST_D2D_MASK				(1 << 3)

/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
#define OMAP3430_EN_GPIO1_MASK				(1 << 3)
#define OMAP3430_EN_GPIO1_SHIFT				3
#define OMAP3430_EN_GPT12_MASK				(1 << 1)
#define OMAP3430_EN_GPT12_SHIFT				1
#define OMAP3430_EN_GPT1_MASK				(1 << 0)
#define OMAP3430_EN_GPT1_SHIFT				0

/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
#define OMAP3430_EN_SR2_MASK				(1 << 7)
#define OMAP3430_EN_SR2_SHIFT				7
#define OMAP3430_EN_SR1_MASK				(1 << 6)
#define OMAP3430_EN_SR1_SHIFT				6

/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
#define OMAP3430_EN_GPT12_MASK				(1 << 1)
#define OMAP3430_EN_GPT12_SHIFT				1

/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
#define OMAP3430_ST_SR2_SHIFT				7
#define OMAP3430_ST_SR2_MASK				(1 << 7)
#define OMAP3430_ST_SR1_SHIFT				6
#define OMAP3430_ST_SR1_MASK				(1 << 6)
#define OMAP3430_ST_GPIO1_SHIFT				3
#define OMAP3430_ST_GPIO1_MASK				(1 << 3)
#define OMAP3430_ST_GPT12_SHIFT				1
#define OMAP3430_ST_GPT12_MASK				(1 << 1)
#define OMAP3430_ST_GPT1_SHIFT				0
#define OMAP3430_ST_GPT1_MASK				(1 << 0)

/*
 * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
 * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
 * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
 */
#define OMAP3430_EN_MPU_MASK				(1 << 1)
#define OMAP3430_EN_MPU_SHIFT				1

/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */

#define OMAP3630_EN_UART4_MASK				(1 << 18)
#define OMAP3630_EN_UART4_SHIFT				18
#define OMAP3430_EN_GPIO6_MASK				(1 << 17)
#define OMAP3430_EN_GPIO6_SHIFT				17
#define OMAP3430_EN_GPIO5_MASK				(1 << 16)
#define OMAP3430_EN_GPIO5_SHIFT				16
#define OMAP3430_EN_GPIO4_MASK				(1 << 15)
#define OMAP3430_EN_GPIO4_SHIFT				15
#define OMAP3430_EN_GPIO3_MASK				(1 << 14)
#define OMAP3430_EN_GPIO3_SHIFT				14
#define OMAP3430_EN_GPIO2_MASK				(1 << 13)
#define OMAP3430_EN_GPIO2_SHIFT				13
#define OMAP3430_EN_UART3_MASK				(1 << 11)
#define OMAP3430_EN_UART3_SHIFT				11
#define OMAP3430_EN_GPT9_MASK				(1 << 10)
#define OMAP3430_EN_GPT9_SHIFT				10
#define OMAP3430_EN_GPT8_MASK				(1 << 9)
#define OMAP3430_EN_GPT8_SHIFT				9
#define OMAP3430_EN_GPT7_MASK				(1 << 8)
#define OMAP3430_EN_GPT7_SHIFT				8
#define OMAP3430_EN_GPT6_MASK				(1 << 7)
#define OMAP3430_EN_GPT6_SHIFT				7
#define OMAP3430_EN_GPT5_MASK				(1 << 6)
#define OMAP3430_EN_GPT5_SHIFT				6
#define OMAP3430_EN_GPT4_MASK				(1 << 5)
#define OMAP3430_EN_GPT4_SHIFT				5
#define OMAP3430_EN_GPT3_MASK				(1 << 4)
#define OMAP3430_EN_GPT3_SHIFT				4
#define OMAP3430_EN_GPT2_MASK				(1 << 3)
#define OMAP3430_EN_GPT2_SHIFT				3

/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
/* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
 * be ST_* bits instead? */
#define OMAP3430_EN_MCBSP4_MASK				(1 << 2)
#define OMAP3430_EN_MCBSP4_SHIFT			2
#define OMAP3430_EN_MCBSP3_MASK				(1 << 1)
#define OMAP3430_EN_MCBSP3_SHIFT			1
#define OMAP3430_EN_MCBSP2_MASK				(1 << 0)
#define OMAP3430_EN_MCBSP2_SHIFT			0

/* CM_IDLEST_PER, PM_WKST_PER shared bits */
#define OMAP3630_ST_UART4_SHIFT				18
#define OMAP3630_ST_UART4_MASK				(1 << 18)
#define OMAP3430_ST_GPIO6_SHIFT				17
#define OMAP3430_ST_GPIO6_MASK				(1 << 17)
#define OMAP3430_ST_GPIO5_SHIFT				16
#define OMAP3430_ST_GPIO5_MASK				(1 << 16)
#define OMAP3430_ST_GPIO4_SHIFT				15
#define OMAP3430_ST_GPIO4_MASK				(1 << 15)
#define OMAP3430_ST_GPIO3_SHIFT				14
#define OMAP3430_ST_GPIO3_MASK				(1 << 14)
#define OMAP3430_ST_GPIO2_SHIFT				13
#define OMAP3430_ST_GPIO2_MASK				(1 << 13)
#define OMAP3430_ST_UART3_SHIFT				11
#define OMAP3430_ST_UART3_MASK				(1 << 11)
#define OMAP3430_ST_GPT9_SHIFT				10
#define OMAP3430_ST_GPT9_MASK				(1 << 10)
#define OMAP3430_ST_GPT8_SHIFT				9
#define OMAP3430_ST_GPT8_MASK				(1 << 9)
#define OMAP3430_ST_GPT7_SHIFT				8
#define OMAP3430_ST_GPT7_MASK				(1 << 8)
#define OMAP3430_ST_GPT6_SHIFT				7
#define OMAP3430_ST_GPT6_MASK				(1 << 7)
#define OMAP3430_ST_GPT5_SHIFT				6
#define OMAP3430_ST_GPT5_MASK				(1 << 6)
#define OMAP3430_ST_GPT4_SHIFT				5
#define OMAP3430_ST_GPT4_MASK				(1 << 5)
#define OMAP3430_ST_GPT3_SHIFT				4
#define OMAP3430_ST_GPT3_MASK				(1 << 4)
#define OMAP3430_ST_GPT2_SHIFT				3
#define OMAP3430_ST_GPT2_MASK				(1 << 3)

/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
#define OMAP3430_EN_CORE_SHIFT				0
#define OMAP3430_EN_CORE_MASK				(1 << 0)


/*
 * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
 * submodule to exit hardreset
 */
#define MAX_MODULE_HARDRESET_WAIT		10000

# ifndef __ASSEMBLER__
extern void __iomem *prm_base;
extern void __iomem *cm_base;
extern void __iomem *cm2_base;

/**
 * struct omap_prcm_irq - describes a PRCM interrupt bit
 * @name: a short name describing the interrupt type, e.g. "wkup" or "io"
 * @offset: the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs
 * @priority: should this interrupt be handled before @priority=false IRQs?
 *
 * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers.
 * On systems with multiple PRM MPU IRQ registers, the bitfields read from
 * the registers are concatenated, so @offset could be > 31 on these systems -
 * see omap_prm_irq_handler() for more details.  I/O ring interrupts should
 * have @priority set to true.
 */
struct omap_prcm_irq {
	const char *name;
	unsigned int offset;
	bool priority;
};

/**
 * struct omap_prcm_irq_setup - PRCM interrupt controller details
 * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register
 * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register
 * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers
 * @nr_irqs: number of entries in the @irqs array
 * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs)
 * @irq: MPU IRQ asserted when a PRCM interrupt arrives
 * @read_pending_irqs: fn ptr to determine if any PRCM IRQs are pending
 * @ocp_barrier: fn ptr to force buffered PRM writes to complete
 * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs
 * @restore_irqen: fn ptr to save and clear IRQENABLE regs
 * @saved_mask: IRQENABLE regs are saved here during suspend
 * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true
 * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init
 * @suspended: set to true after Linux suspend code has called our ->prepare()
 * @suspend_save_flag: set to true after IRQ masks have been saved and disabled
 *
 * @saved_mask, @priority_mask, @base_irq, @suspended, and
 * @suspend_save_flag are populated dynamically, and are not to be
 * specified in static initializers.
 */
struct omap_prcm_irq_setup {
	u16 ack;
	u16 mask;
	u8 nr_regs;
	u8 nr_irqs;
	const struct omap_prcm_irq *irqs;
	int irq;
	void (*read_pending_irqs)(unsigned long *events);
	void (*ocp_barrier)(void);
	void (*save_and_clear_irqen)(u32 *saved_mask);
	void (*restore_irqen)(u32 *saved_mask);
	u32 *saved_mask;
	u32 *priority_mask;
	int base_irq;
	bool suspended;
	bool suspend_save_flag;
};

/* OMAP_PRCM_IRQ: convenience macro for creating struct omap_prcm_irq records */
#define OMAP_PRCM_IRQ(_name, _offset, _priority) {	\
	.name = _name,					\
	.offset = _offset,				\
	.priority = _priority				\
	}

extern void omap_prcm_irq_cleanup(void);
extern int omap_prcm_register_chain_handler(
	struct omap_prcm_irq_setup *irq_setup);
extern int omap_prcm_event_to_irq(const char *event);
extern void omap_prcm_irq_prepare(void);
extern void omap_prcm_irq_complete(void);

# endif

#endif
Commit	Line	Data
69d88a00 PW	1	#ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
	2	#define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
	3
	4	/*
	5	* OMAP2/3 PRCM base and module definitions
	6	*
0a84a91c	7	* Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
77772d5f	8	* Copyright (C) 2007-2009 Nokia Corporation
69d88a00 PW	9	*
	10	* Written by Paul Walmsley
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*/
	16
69d88a00 PW	17	/* Module offsets from both CM_BASE & PRM_BASE */
	18
	19	/*
	20	* Offsets that are the same on 24xx and 34xx
	21	*
	22	* Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
	23	* CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
	24	*/
	25	#define OCP_MOD 0x000
	26	#define MPU_MOD 0x100
	27	#define CORE_MOD 0x200
	28	#define GFX_MOD 0x300
	29	#define WKUP_MOD 0x400
	30	#define PLL_MOD 0x500
	31
	32
	33	/* Chip-specific module offsets */
c2d43e39	34	#define OMAP24XX_GR_MOD OCP_MOD
69d88a00 PW	35	#define OMAP24XX_DSP_MOD 0x800
	36
	37	#define OMAP2430_MDM_MOD 0xc00
	38
	39	/* IVA2 module is < base on 3430 */
	40	#define OMAP3430_IVA2_MOD -0x800
	41	#define OMAP3430ES2_SGX_MOD GFX_MOD
	42	#define OMAP3430_CCR_MOD PLL_MOD
	43	#define OMAP3430_DSS_MOD 0x600
	44	#define OMAP3430_CAM_MOD 0x700
	45	#define OMAP3430_PER_MOD 0x800
	46	#define OMAP3430_EMU_MOD 0x900
	47	#define OMAP3430_GR_MOD 0xa00
	48	#define OMAP3430_NEON_MOD 0xb00
	49	#define OMAP3430ES2_USBHOST_MOD 0xc00
	50
69d88a00 PW	51	/* 24XX register bits shared between CM & PRM registers */
	52
	53	/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
	54	#define OMAP2420_EN_MMC_SHIFT 26
2fd0f75c	55	#define OMAP2420_EN_MMC_MASK (1 << 26)
69d88a00	56	#define OMAP24XX_EN_UART2_SHIFT 22
2fd0f75c	57	#define OMAP24XX_EN_UART2_MASK (1 << 22)
69d88a00	58	#define OMAP24XX_EN_UART1_SHIFT 21
2fd0f75c	59	#define OMAP24XX_EN_UART1_MASK (1 << 21)
69d88a00	60	#define OMAP24XX_EN_MCSPI2_SHIFT 18
2fd0f75c	61	#define OMAP24XX_EN_MCSPI2_MASK (1 << 18)
69d88a00	62	#define OMAP24XX_EN_MCSPI1_SHIFT 17
2fd0f75c	63	#define OMAP24XX_EN_MCSPI1_MASK (1 << 17)
69d88a00	64	#define OMAP24XX_EN_MCBSP2_SHIFT 16
2fd0f75c	65	#define OMAP24XX_EN_MCBSP2_MASK (1 << 16)
69d88a00	66	#define OMAP24XX_EN_MCBSP1_SHIFT 15
2fd0f75c	67	#define OMAP24XX_EN_MCBSP1_MASK (1 << 15)
69d88a00	68	#define OMAP24XX_EN_GPT12_SHIFT 14
2fd0f75c	69	#define OMAP24XX_EN_GPT12_MASK (1 << 14)
69d88a00	70	#define OMAP24XX_EN_GPT11_SHIFT 13
2fd0f75c	71	#define OMAP24XX_EN_GPT11_MASK (1 << 13)
69d88a00	72	#define OMAP24XX_EN_GPT10_SHIFT 12
2fd0f75c	73	#define OMAP24XX_EN_GPT10_MASK (1 << 12)
69d88a00	74	#define OMAP24XX_EN_GPT9_SHIFT 11
2fd0f75c	75	#define OMAP24XX_EN_GPT9_MASK (1 << 11)
69d88a00	76	#define OMAP24XX_EN_GPT8_SHIFT 10
2fd0f75c	77	#define OMAP24XX_EN_GPT8_MASK (1 << 10)
69d88a00	78	#define OMAP24XX_EN_GPT7_SHIFT 9
2fd0f75c	79	#define OMAP24XX_EN_GPT7_MASK (1 << 9)
69d88a00	80	#define OMAP24XX_EN_GPT6_SHIFT 8
2fd0f75c	81	#define OMAP24XX_EN_GPT6_MASK (1 << 8)
69d88a00	82	#define OMAP24XX_EN_GPT5_SHIFT 7
2fd0f75c	83	#define OMAP24XX_EN_GPT5_MASK (1 << 7)
69d88a00	84	#define OMAP24XX_EN_GPT4_SHIFT 6
2fd0f75c	85	#define OMAP24XX_EN_GPT4_MASK (1 << 6)
69d88a00	86	#define OMAP24XX_EN_GPT3_SHIFT 5
2fd0f75c	87	#define OMAP24XX_EN_GPT3_MASK (1 << 5)
69d88a00	88	#define OMAP24XX_EN_GPT2_SHIFT 4
2fd0f75c	89	#define OMAP24XX_EN_GPT2_MASK (1 << 4)
69d88a00	90	#define OMAP2420_EN_VLYNQ_SHIFT 3
2fd0f75c	91	#define OMAP2420_EN_VLYNQ_MASK (1 << 3)
69d88a00 PW	92
	93	/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
	94	#define OMAP2430_EN_GPIO5_SHIFT 10
2fd0f75c	95	#define OMAP2430_EN_GPIO5_MASK (1 << 10)
69d88a00	96	#define OMAP2430_EN_MCSPI3_SHIFT 9
2fd0f75c	97	#define OMAP2430_EN_MCSPI3_MASK (1 << 9)
69d88a00	98	#define OMAP2430_EN_MMCHS2_SHIFT 8
2fd0f75c	99	#define OMAP2430_EN_MMCHS2_MASK (1 << 8)
69d88a00	100	#define OMAP2430_EN_MMCHS1_SHIFT 7
2fd0f75c	101	#define OMAP2430_EN_MMCHS1_MASK (1 << 7)
69d88a00	102	#define OMAP24XX_EN_UART3_SHIFT 2
2fd0f75c	103	#define OMAP24XX_EN_UART3_MASK (1 << 2)
69d88a00	104	#define OMAP24XX_EN_USB_SHIFT 0
2fd0f75c	105	#define OMAP24XX_EN_USB_MASK (1 << 0)
69d88a00 PW	106
	107	/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
	108	#define OMAP2430_EN_MDM_INTC_SHIFT 11
2fd0f75c	109	#define OMAP2430_EN_MDM_INTC_MASK (1 << 11)
69d88a00	110	#define OMAP2430_EN_USBHS_SHIFT 6
2fd0f75c	111	#define OMAP2430_EN_USBHS_MASK (1 << 6)
69d88a00 PW	112
69d88a00 PW	113	/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
da0747d4 PW	114	#define OMAP2420_ST_MMC_SHIFT 26
	115	#define OMAP2420_ST_MMC_MASK (1 << 26)
	116	#define OMAP24XX_ST_UART2_SHIFT 22
	117	#define OMAP24XX_ST_UART2_MASK (1 << 22)
	118	#define OMAP24XX_ST_UART1_SHIFT 21
	119	#define OMAP24XX_ST_UART1_MASK (1 << 21)
	120	#define OMAP24XX_ST_MCSPI2_SHIFT 18
	121	#define OMAP24XX_ST_MCSPI2_MASK (1 << 18)
	122	#define OMAP24XX_ST_MCSPI1_SHIFT 17
	123	#define OMAP24XX_ST_MCSPI1_MASK (1 << 17)
3cb72fa4 C	124	#define OMAP24XX_ST_MCBSP2_SHIFT 16
	125	#define OMAP24XX_ST_MCBSP2_MASK (1 << 16)
	126	#define OMAP24XX_ST_MCBSP1_SHIFT 15
	127	#define OMAP24XX_ST_MCBSP1_MASK (1 << 15)
da0747d4 PW	128	#define OMAP24XX_ST_GPT12_SHIFT 14
	129	#define OMAP24XX_ST_GPT12_MASK (1 << 14)
	130	#define OMAP24XX_ST_GPT11_SHIFT 13
	131	#define OMAP24XX_ST_GPT11_MASK (1 << 13)
	132	#define OMAP24XX_ST_GPT10_SHIFT 12
	133	#define OMAP24XX_ST_GPT10_MASK (1 << 12)
	134	#define OMAP24XX_ST_GPT9_SHIFT 11
	135	#define OMAP24XX_ST_GPT9_MASK (1 << 11)
	136	#define OMAP24XX_ST_GPT8_SHIFT 10
	137	#define OMAP24XX_ST_GPT8_MASK (1 << 10)
	138	#define OMAP24XX_ST_GPT7_SHIFT 9
	139	#define OMAP24XX_ST_GPT7_MASK (1 << 9)
	140	#define OMAP24XX_ST_GPT6_SHIFT 8
	141	#define OMAP24XX_ST_GPT6_MASK (1 << 8)
	142	#define OMAP24XX_ST_GPT5_SHIFT 7
	143	#define OMAP24XX_ST_GPT5_MASK (1 << 7)
	144	#define OMAP24XX_ST_GPT4_SHIFT 6
	145	#define OMAP24XX_ST_GPT4_MASK (1 << 6)
	146	#define OMAP24XX_ST_GPT3_SHIFT 5
	147	#define OMAP24XX_ST_GPT3_MASK (1 << 5)
	148	#define OMAP24XX_ST_GPT2_SHIFT 4
	149	#define OMAP24XX_ST_GPT2_MASK (1 << 4)
	150	#define OMAP2420_ST_VLYNQ_SHIFT 3
	151	#define OMAP2420_ST_VLYNQ_MASK (1 << 3)
69d88a00 PW	152
69d88a00 PW	153	/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
da0747d4 PW	154	#define OMAP2430_ST_MDM_INTC_SHIFT 11
	155	#define OMAP2430_ST_MDM_INTC_MASK (1 << 11)
	156	#define OMAP2430_ST_GPIO5_SHIFT 10
	157	#define OMAP2430_ST_GPIO5_MASK (1 << 10)
	158	#define OMAP2430_ST_MCSPI3_SHIFT 9
	159	#define OMAP2430_ST_MCSPI3_MASK (1 << 9)
	160	#define OMAP2430_ST_MMCHS2_SHIFT 8
	161	#define OMAP2430_ST_MMCHS2_MASK (1 << 8)
	162	#define OMAP2430_ST_MMCHS1_SHIFT 7
	163	#define OMAP2430_ST_MMCHS1_MASK (1 << 7)
	164	#define OMAP2430_ST_USBHS_SHIFT 6
	165	#define OMAP2430_ST_USBHS_MASK (1 << 6)
	166	#define OMAP24XX_ST_UART3_SHIFT 2
	167	#define OMAP24XX_ST_UART3_MASK (1 << 2)
	168	#define OMAP24XX_ST_USB_SHIFT 0
	169	#define OMAP24XX_ST_USB_MASK (1 << 0)
69d88a00 PW	170
	171	/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
	172	#define OMAP24XX_EN_GPIOS_SHIFT 2
2fd0f75c	173	#define OMAP24XX_EN_GPIOS_MASK (1 << 2)
69d88a00	174	#define OMAP24XX_EN_GPT1_SHIFT 0
2fd0f75c	175	#define OMAP24XX_EN_GPT1_MASK (1 << 0)
69d88a00 PW	176
69d88a00 PW	177	/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
c2015dc8 PW	178	#define OMAP24XX_ST_GPIOS_SHIFT 2
	179	#define OMAP24XX_ST_GPIOS_MASK (1 << 2)
	180	#define OMAP24XX_ST_GPT1_SHIFT 0
	181	#define OMAP24XX_ST_GPT1_MASK (1 << 0)
69d88a00 PW	182
69d88a00 PW	183	/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
c2015dc8 PW	184	#define OMAP2430_ST_MDM_SHIFT 0
c2015dc8 PW	185	#define OMAP2430_ST_MDM_MASK (1 << 0)
69d88a00 PW	186
	187
	188	/* 3430 register bits shared between CM & PRM registers */
	189
	190	/* CM_REVISION, PRM_REVISION shared bits */
	191	#define OMAP3430_REV_SHIFT 0
	192	#define OMAP3430_REV_MASK (0xff << 0)
	193
	194	/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
2fd0f75c	195	#define OMAP3430_AUTOIDLE_MASK (1 << 0)
69d88a00 PW	196
69d88a00 PW	197	/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
b163605e PW	198	#define OMAP3430_EN_MMC3_MASK (1 << 30)
b163605e PW	199	#define OMAP3430_EN_MMC3_SHIFT 30
2fd0f75c	200	#define OMAP3430_EN_MMC2_MASK (1 << 25)
69d88a00	201	#define OMAP3430_EN_MMC2_SHIFT 25
2fd0f75c	202	#define OMAP3430_EN_MMC1_MASK (1 << 24)
69d88a00	203	#define OMAP3430_EN_MMC1_SHIFT 24
2fd0f75c	204	#define OMAP3430_EN_MCSPI4_MASK (1 << 21)
69d88a00	205	#define OMAP3430_EN_MCSPI4_SHIFT 21
2fd0f75c	206	#define OMAP3430_EN_MCSPI3_MASK (1 << 20)
69d88a00	207	#define OMAP3430_EN_MCSPI3_SHIFT 20
2fd0f75c	208	#define OMAP3430_EN_MCSPI2_MASK (1 << 19)
69d88a00	209	#define OMAP3430_EN_MCSPI2_SHIFT 19
2fd0f75c	210	#define OMAP3430_EN_MCSPI1_MASK (1 << 18)
69d88a00	211	#define OMAP3430_EN_MCSPI1_SHIFT 18
2fd0f75c	212	#define OMAP3430_EN_I2C3_MASK (1 << 17)
69d88a00	213	#define OMAP3430_EN_I2C3_SHIFT 17
2fd0f75c	214	#define OMAP3430_EN_I2C2_MASK (1 << 16)
69d88a00	215	#define OMAP3430_EN_I2C2_SHIFT 16
2fd0f75c	216	#define OMAP3430_EN_I2C1_MASK (1 << 15)
69d88a00	217	#define OMAP3430_EN_I2C1_SHIFT 15
2fd0f75c	218	#define OMAP3430_EN_UART2_MASK (1 << 14)
69d88a00	219	#define OMAP3430_EN_UART2_SHIFT 14
2fd0f75c	220	#define OMAP3430_EN_UART1_MASK (1 << 13)
69d88a00	221	#define OMAP3430_EN_UART1_SHIFT 13
2fd0f75c	222	#define OMAP3430_EN_GPT11_MASK (1 << 12)
69d88a00	223	#define OMAP3430_EN_GPT11_SHIFT 12
2fd0f75c	224	#define OMAP3430_EN_GPT10_MASK (1 << 11)
69d88a00	225	#define OMAP3430_EN_GPT10_SHIFT 11
2fd0f75c	226	#define OMAP3430_EN_MCBSP5_MASK (1 << 10)
69d88a00	227	#define OMAP3430_EN_MCBSP5_SHIFT 10
2fd0f75c	228	#define OMAP3430_EN_MCBSP1_MASK (1 << 9)
69d88a00	229	#define OMAP3430_EN_MCBSP1_SHIFT 9
2fd0f75c	230	#define OMAP3430_EN_FSHOSTUSB_MASK (1 << 5)
69d88a00	231	#define OMAP3430_EN_FSHOSTUSB_SHIFT 5
2fd0f75c	232	#define OMAP3430_EN_D2D_MASK (1 << 3)
69d88a00 PW	233	#define OMAP3430_EN_D2D_SHIFT 3
	234
	235	/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
2fd0f75c PW	236	#define OMAP3430_EN_HSOTGUSB_MASK (1 << 4)
2fd0f75c PW	237	#define OMAP3430_EN_HSOTGUSB_SHIFT 4
69d88a00 PW	238
69d88a00 PW	239	/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
b163605e PW	240	#define OMAP3430_ST_MMC3_SHIFT 30
b163605e PW	241	#define OMAP3430_ST_MMC3_MASK (1 << 30)
da0747d4 PW	242	#define OMAP3430_ST_MMC2_SHIFT 25
	243	#define OMAP3430_ST_MMC2_MASK (1 << 25)
	244	#define OMAP3430_ST_MMC1_SHIFT 24
	245	#define OMAP3430_ST_MMC1_MASK (1 << 24)
	246	#define OMAP3430_ST_MCSPI4_SHIFT 21
	247	#define OMAP3430_ST_MCSPI4_MASK (1 << 21)
	248	#define OMAP3430_ST_MCSPI3_SHIFT 20
	249	#define OMAP3430_ST_MCSPI3_MASK (1 << 20)
	250	#define OMAP3430_ST_MCSPI2_SHIFT 19
	251	#define OMAP3430_ST_MCSPI2_MASK (1 << 19)
	252	#define OMAP3430_ST_MCSPI1_SHIFT 18
	253	#define OMAP3430_ST_MCSPI1_MASK (1 << 18)
	254	#define OMAP3430_ST_I2C3_SHIFT 17
	255	#define OMAP3430_ST_I2C3_MASK (1 << 17)
	256	#define OMAP3430_ST_I2C2_SHIFT 16
	257	#define OMAP3430_ST_I2C2_MASK (1 << 16)
	258	#define OMAP3430_ST_I2C1_SHIFT 15
	259	#define OMAP3430_ST_I2C1_MASK (1 << 15)
	260	#define OMAP3430_ST_UART2_SHIFT 14
	261	#define OMAP3430_ST_UART2_MASK (1 << 14)
	262	#define OMAP3430_ST_UART1_SHIFT 13
	263	#define OMAP3430_ST_UART1_MASK (1 << 13)
	264	#define OMAP3430_ST_GPT11_SHIFT 12
	265	#define OMAP3430_ST_GPT11_MASK (1 << 12)
	266	#define OMAP3430_ST_GPT10_SHIFT 11
	267	#define OMAP3430_ST_GPT10_MASK (1 << 11)
	268	#define OMAP3430_ST_MCBSP5_SHIFT 10
	269	#define OMAP3430_ST_MCBSP5_MASK (1 << 10)
	270	#define OMAP3430_ST_MCBSP1_SHIFT 9
	271	#define OMAP3430_ST_MCBSP1_MASK (1 << 9)
	272	#define OMAP3430ES1_ST_FSHOSTUSB_SHIFT 5
	273	#define OMAP3430ES1_ST_FSHOSTUSB_MASK (1 << 5)
	274	#define OMAP3430ES1_ST_HSOTGUSB_SHIFT 4
	275	#define OMAP3430ES1_ST_HSOTGUSB_MASK (1 << 4)
	276	#define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5
	277	#define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK (1 << 5)
	278	#define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 4
	279	#define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK (1 << 4)
	280	#define OMAP3430_ST_D2D_SHIFT 3
	281	#define OMAP3430_ST_D2D_MASK (1 << 3)
69d88a00 PW	282
69d88a00 PW	283	/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
2fd0f75c	284	#define OMAP3430_EN_GPIO1_MASK (1 << 3)
69d88a00	285	#define OMAP3430_EN_GPIO1_SHIFT 3
2fd0f75c	286	#define OMAP3430_EN_GPT12_MASK (1 << 1)
8bd22949	287	#define OMAP3430_EN_GPT12_SHIFT 1
2fd0f75c	288	#define OMAP3430_EN_GPT1_MASK (1 << 0)
69d88a00 PW	289	#define OMAP3430_EN_GPT1_SHIFT 0
	290
	291	/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
2fd0f75c	292	#define OMAP3430_EN_SR2_MASK (1 << 7)
69d88a00	293	#define OMAP3430_EN_SR2_SHIFT 7
2fd0f75c	294	#define OMAP3430_EN_SR1_MASK (1 << 6)
69d88a00 PW	295	#define OMAP3430_EN_SR1_SHIFT 6
	296
	297	/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
2fd0f75c	298	#define OMAP3430_EN_GPT12_MASK (1 << 1)
69d88a00 PW	299	#define OMAP3430_EN_GPT12_SHIFT 1
	300
	301	/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
da0747d4 PW	302	#define OMAP3430_ST_SR2_SHIFT 7
	303	#define OMAP3430_ST_SR2_MASK (1 << 7)
	304	#define OMAP3430_ST_SR1_SHIFT 6
	305	#define OMAP3430_ST_SR1_MASK (1 << 6)
	306	#define OMAP3430_ST_GPIO1_SHIFT 3
	307	#define OMAP3430_ST_GPIO1_MASK (1 << 3)
	308	#define OMAP3430_ST_GPT12_SHIFT 1
	309	#define OMAP3430_ST_GPT12_MASK (1 << 1)
	310	#define OMAP3430_ST_GPT1_SHIFT 0
	311	#define OMAP3430_ST_GPT1_MASK (1 << 0)
69d88a00 PW	312
	313	/*
	314	* CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
	315	* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
	316	* PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
	317	*/
2fd0f75c	318	#define OMAP3430_EN_MPU_MASK (1 << 1)
69d88a00 PW	319	#define OMAP3430_EN_MPU_SHIFT 1
	320
	321	/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
046465b7 KH	322
	323	#define OMAP3630_EN_UART4_MASK (1 << 18)
	324	#define OMAP3630_EN_UART4_SHIFT 18
2fd0f75c	325	#define OMAP3430_EN_GPIO6_MASK (1 << 17)
69d88a00	326	#define OMAP3430_EN_GPIO6_SHIFT 17
2fd0f75c	327	#define OMAP3430_EN_GPIO5_MASK (1 << 16)
69d88a00	328	#define OMAP3430_EN_GPIO5_SHIFT 16
2fd0f75c	329	#define OMAP3430_EN_GPIO4_MASK (1 << 15)
69d88a00	330	#define OMAP3430_EN_GPIO4_SHIFT 15
2fd0f75c	331	#define OMAP3430_EN_GPIO3_MASK (1 << 14)
69d88a00	332	#define OMAP3430_EN_GPIO3_SHIFT 14
2fd0f75c	333	#define OMAP3430_EN_GPIO2_MASK (1 << 13)
69d88a00	334	#define OMAP3430_EN_GPIO2_SHIFT 13
2fd0f75c	335	#define OMAP3430_EN_UART3_MASK (1 << 11)
69d88a00	336	#define OMAP3430_EN_UART3_SHIFT 11
2fd0f75c	337	#define OMAP3430_EN_GPT9_MASK (1 << 10)
69d88a00	338	#define OMAP3430_EN_GPT9_SHIFT 10
2fd0f75c	339	#define OMAP3430_EN_GPT8_MASK (1 << 9)
69d88a00	340	#define OMAP3430_EN_GPT8_SHIFT 9
2fd0f75c	341	#define OMAP3430_EN_GPT7_MASK (1 << 8)
69d88a00	342	#define OMAP3430_EN_GPT7_SHIFT 8
2fd0f75c	343	#define OMAP3430_EN_GPT6_MASK (1 << 7)
69d88a00	344	#define OMAP3430_EN_GPT6_SHIFT 7
2fd0f75c	345	#define OMAP3430_EN_GPT5_MASK (1 << 6)
69d88a00	346	#define OMAP3430_EN_GPT5_SHIFT 6
2fd0f75c	347	#define OMAP3430_EN_GPT4_MASK (1 << 5)
69d88a00	348	#define OMAP3430_EN_GPT4_SHIFT 5
2fd0f75c	349	#define OMAP3430_EN_GPT3_MASK (1 << 4)
69d88a00	350	#define OMAP3430_EN_GPT3_SHIFT 4
2fd0f75c	351	#define OMAP3430_EN_GPT2_MASK (1 << 3)
69d88a00 PW	352	#define OMAP3430_EN_GPT2_SHIFT 3
	353
	354	/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
	355	/* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
	356	* be ST_* bits instead? */
2fd0f75c	357	#define OMAP3430_EN_MCBSP4_MASK (1 << 2)
69d88a00	358	#define OMAP3430_EN_MCBSP4_SHIFT 2
2fd0f75c	359	#define OMAP3430_EN_MCBSP3_MASK (1 << 1)
69d88a00	360	#define OMAP3430_EN_MCBSP3_SHIFT 1
2fd0f75c	361	#define OMAP3430_EN_MCBSP2_MASK (1 << 0)
69d88a00 PW	362	#define OMAP3430_EN_MCBSP2_SHIFT 0
	363
	364	/* CM_IDLEST_PER, PM_WKST_PER shared bits */
e5863689 G	365	#define OMAP3630_ST_UART4_SHIFT 18
e5863689 G	366	#define OMAP3630_ST_UART4_MASK (1 << 18)
da0747d4 PW	367	#define OMAP3430_ST_GPIO6_SHIFT 17
	368	#define OMAP3430_ST_GPIO6_MASK (1 << 17)
	369	#define OMAP3430_ST_GPIO5_SHIFT 16
	370	#define OMAP3430_ST_GPIO5_MASK (1 << 16)
	371	#define OMAP3430_ST_GPIO4_SHIFT 15
	372	#define OMAP3430_ST_GPIO4_MASK (1 << 15)
	373	#define OMAP3430_ST_GPIO3_SHIFT 14
	374	#define OMAP3430_ST_GPIO3_MASK (1 << 14)
	375	#define OMAP3430_ST_GPIO2_SHIFT 13
	376	#define OMAP3430_ST_GPIO2_MASK (1 << 13)
	377	#define OMAP3430_ST_UART3_SHIFT 11
	378	#define OMAP3430_ST_UART3_MASK (1 << 11)
	379	#define OMAP3430_ST_GPT9_SHIFT 10
	380	#define OMAP3430_ST_GPT9_MASK (1 << 10)
	381	#define OMAP3430_ST_GPT8_SHIFT 9
	382	#define OMAP3430_ST_GPT8_MASK (1 << 9)
	383	#define OMAP3430_ST_GPT7_SHIFT 8
	384	#define OMAP3430_ST_GPT7_MASK (1 << 8)
	385	#define OMAP3430_ST_GPT6_SHIFT 7
	386	#define OMAP3430_ST_GPT6_MASK (1 << 7)
	387	#define OMAP3430_ST_GPT5_SHIFT 6
	388	#define OMAP3430_ST_GPT5_MASK (1 << 6)
	389	#define OMAP3430_ST_GPT4_SHIFT 5
	390	#define OMAP3430_ST_GPT4_MASK (1 << 5)
	391	#define OMAP3430_ST_GPT3_SHIFT 4
	392	#define OMAP3430_ST_GPT3_MASK (1 << 4)
	393	#define OMAP3430_ST_GPT2_SHIFT 3
	394	#define OMAP3430_ST_GPT2_MASK (1 << 3)
69d88a00 PW	395
69d88a00 PW	396	/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
ecb24aa1 PW	397	#define OMAP3430_EN_CORE_SHIFT 0
ecb24aa1 PW	398	#define OMAP3430_EN_CORE_MASK (1 << 0)
69d88a00	399
d198b514 PW	400
	401	/*
	402	* MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
	403	* submodule to exit hardreset
	404	*/
	405	#define MAX_MODULE_HARDRESET_WAIT 10000
	406
59fb659b PW	407	# ifndef __ASSEMBLER__
	408	extern void __iomem *prm_base;
	409	extern void __iomem *cm_base;
	410	extern void __iomem *cm2_base;
0a84a91c TK	411
	412	/**
	413	* struct omap_prcm_irq - describes a PRCM interrupt bit
	414	* @name: a short name describing the interrupt type, e.g. "wkup" or "io"
	415	* @offset: the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs
	416	* @priority: should this interrupt be handled before @priority=false IRQs?
	417	*
	418	* Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers.
	419	* On systems with multiple PRM MPU IRQ registers, the bitfields read from
	420	* the registers are concatenated, so @offset could be > 31 on these systems -
	421	* see omap_prm_irq_handler() for more details. I/O ring interrupts should
	422	* have @priority set to true.
	423	*/
	424	struct omap_prcm_irq {
	425	const char *name;
	426	unsigned int offset;
	427	bool priority;
	428	};
	429
	430	/**
	431	* struct omap_prcm_irq_setup - PRCM interrupt controller details
	432	* @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register
	433	* @mask: PRM register offset for the first PRM_IRQENABLE_MPU register
	434	* @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers
	435	* @nr_irqs: number of entries in the @irqs array
	436	* @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs)
	437	* @irq: MPU IRQ asserted when a PRCM interrupt arrives
	438	* @read_pending_irqs: fn ptr to determine if any PRCM IRQs are pending
	439	* @ocp_barrier: fn ptr to force buffered PRM writes to complete
91285b6f TK	440	* @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs
	441	* @restore_irqen: fn ptr to save and clear IRQENABLE regs
	442	* @saved_mask: IRQENABLE regs are saved here during suspend
0a84a91c TK	443	* @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true
0a84a91c TK	444	* @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init
91285b6f TK	445	* @suspended: set to true after Linux suspend code has called our ->prepare()
91285b6f TK	446	* @suspend_save_flag: set to true after IRQ masks have been saved and disabled
0a84a91c	447	*
91285b6f TK	448	* @saved_mask, @priority_mask, @base_irq, @suspended, and
91285b6f TK	449	* @suspend_save_flag are populated dynamically, and are not to be
0a84a91c TK	450	* specified in static initializers.
	451	*/
	452	struct omap_prcm_irq_setup {
	453	u16 ack;
	454	u16 mask;
	455	u8 nr_regs;
	456	u8 nr_irqs;
	457	const struct omap_prcm_irq *irqs;
	458	int irq;
	459	void (read_pending_irqs)(unsigned long events);
	460	void (*ocp_barrier)(void);
91285b6f TK	461	void (save_and_clear_irqen)(u32 saved_mask);
	462	void (restore_irqen)(u32 saved_mask);
	463	u32 *saved_mask;
0a84a91c TK	464	u32 *priority_mask;
0a84a91c TK	465	int base_irq;
91285b6f TK	466	bool suspended;
91285b6f TK	467	bool suspend_save_flag;
0a84a91c TK	468	};
	469
	470	/* OMAP_PRCM_IRQ: convenience macro for creating struct omap_prcm_irq records */
	471	#define OMAP_PRCM_IRQ(_name, _offset, _priority) { \
	472	.name = _name, \
	473	.offset = _offset, \
	474	.priority = _priority \
	475	}
	476
	477	extern void omap_prcm_irq_cleanup(void);
	478	extern int omap_prcm_register_chain_handler(
	479	struct omap_prcm_irq_setup *irq_setup);
	480	extern int omap_prcm_event_to_irq(const char *event);
91285b6f TK	481	extern void omap_prcm_irq_prepare(void);
91285b6f TK	482	extern void omap_prcm_irq_complete(void);
0a84a91c	483
59fb659b PW	484	# endif
59fb659b PW	485
69d88a00 PW	486	#endif
69d88a00 PW	487