projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| c1294045 RN |
1 | /* |
| 2 | * OMAP44xx PRM instance offset macros | |
| 3 | * | |
| 79328706 BC |
4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2009-2010 Nokia Corporation | |
| c1294045 RN |
6 | * |
| 7 | * Paul Walmsley (paul@pwsan.com) | |
| 8 | * Rajendra Nayak (rnayak@ti.com) | |
| 9 | * Benoit Cousson (b-cousson@ti.com) | |
| 10 | * | |
| 11 | * This file is automatically generated from the OMAP hardware databases. | |
| 12 | * We respectfully ask that any modifications to this file be coordinated | |
| 13 | * with the public linux-omap@vger.kernel.org mailing list and the | |
| 14 | * authors above to ensure that the autogeneration scripts are kept | |
| 15 | * up-to-date with the file contents. | |
| 16 | * | |
| 17 | * This program is free software; you can redistribute it and/or modify | |
| 18 | * it under the terms of the GNU General Public License version 2 as | |
| 19 | * published by the Free Software Foundation. | |
| d198b514 PW |
20 | * |
| 21 | * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", | |
| 22 | * or "OMAP4430". | |
| c1294045 RN |
23 | */ |
| 24 | ||
| 25 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H | |
| 26 | #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H | |
| 27 | ||
| d198b514 PW |
28 | #include "prcm-common.h" |
| 29 | ||
| 30 | #define OMAP4430_PRM_BASE 0x4a306000 | |
| 31 | ||
| 32 | #define OMAP44XX_PRM_REGADDR(module, reg) \ | |
| 33 | OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg)) | |
| 34 | ||
| 35 | ||
| 36 | /* PRM instances */ | |
| 37 | #define OMAP4430_PRM_OCP_SOCKET_MOD 0x0000 | |
| 38 | #define OMAP4430_PRM_CKGEN_MOD 0x0100 | |
| 39 | #define OMAP4430_PRM_MPU_MOD 0x0300 | |
| 40 | #define OMAP4430_PRM_TESLA_MOD 0x0400 | |
| 41 | #define OMAP4430_PRM_ABE_MOD 0x0500 | |
| 42 | #define OMAP4430_PRM_ALWAYS_ON_MOD 0x0600 | |
| 43 | #define OMAP4430_PRM_CORE_MOD 0x0700 | |
| 44 | #define OMAP4430_PRM_IVAHD_MOD 0x0f00 | |
| 45 | #define OMAP4430_PRM_CAM_MOD 0x1000 | |
| 46 | #define OMAP4430_PRM_DSS_MOD 0x1100 | |
| 47 | #define OMAP4430_PRM_GFX_MOD 0x1200 | |
| 48 | #define OMAP4430_PRM_L3INIT_MOD 0x1300 | |
| 49 | #define OMAP4430_PRM_L4PER_MOD 0x1400 | |
| 50 | #define OMAP4430_PRM_CEFUSE_MOD 0x1600 | |
| 51 | #define OMAP4430_PRM_WKUP_MOD 0x1700 | |
| 52 | #define OMAP4430_PRM_WKUP_CM_MOD 0x1800 | |
| 53 | #define OMAP4430_PRM_EMU_MOD 0x1900 | |
| 54 | #define OMAP4430_PRM_EMU_CM_MOD 0x1a00 | |
| 55 | #define OMAP4430_PRM_DEVICE_MOD 0x1b00 | |
| 56 | #define OMAP4430_PRM_INSTR_MOD 0x1f00 | |
| 57 | ||
| 58 | ||
| 59 | /* OMAP4 specific register offsets */ | |
| 60 | #define OMAP4_RM_RSTCTRL 0x0000 | |
| 61 | #define OMAP4_RM_RSTTIME 0x0004 | |
| 62 | #define OMAP4_RM_RSTST 0x0008 | |
| 63 | #define OMAP4_PM_PWSTCTRL 0x0000 | |
| 64 | #define OMAP4_PM_PWSTST 0x0004 | |
| 65 | ||
| c1294045 RN |
66 | |
| 67 | /* PRM */ | |
| 68 | ||
| c1294045 | 69 | /* PRM.OCP_SOCKET_PRM register offsets */ |
| 2339ea99 | 70 | #define OMAP4_REVISION_PRM_OFFSET 0x0000 |
| c1294045 | 71 | #define OMAP4430_REVISION_PRM OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0000) |
| 2339ea99 | 72 | #define OMAP4_PRM_IRQSTATUS_MPU_OFFSET 0x0010 |
| c1294045 | 73 | #define OMAP4430_PRM_IRQSTATUS_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0010) |
| 2339ea99 | 74 | #define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 |
| c1294045 | 75 | #define OMAP4430_PRM_IRQSTATUS_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0014) |
| 2339ea99 | 76 | #define OMAP4_PRM_IRQENABLE_MPU_OFFSET 0x0018 |
| c1294045 | 77 | #define OMAP4430_PRM_IRQENABLE_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0018) |
| 2339ea99 | 78 | #define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET 0x001c |
| c1294045 | 79 | #define OMAP4430_PRM_IRQENABLE_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x001c) |
| 2339ea99 | 80 | #define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET 0x0020 |
| c1294045 | 81 | #define OMAP4430_PRM_IRQSTATUS_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0020) |
| 2339ea99 | 82 | #define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET 0x0028 |
| c1294045 | 83 | #define OMAP4430_PRM_IRQENABLE_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0028) |
| 2339ea99 | 84 | #define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET 0x0030 |
| c1294045 | 85 | #define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030) |
| 2339ea99 | 86 | #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038 |
| c1294045 | 87 | #define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038) |
| fdd4f409 RN |
88 | #define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 |
| 89 | #define OMAP4430_CM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040) | |
| c1294045 RN |
90 | |
| 91 | /* PRM.CKGEN_PRM register offsets */ | |
| 2339ea99 | 92 | #define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000 |
| c1294045 | 93 | #define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000) |
| 2339ea99 | 94 | #define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008 |
| c1294045 | 95 | #define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008) |
| 2339ea99 | 96 | #define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c |
| c1294045 | 97 | #define OMAP4430_CM_ABE_PLL_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x000c) |
| 2339ea99 | 98 | #define OMAP4_CM_SYS_CLKSEL_OFFSET 0x0010 |
| c1294045 RN |
99 | #define OMAP4430_CM_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0010) |
| 100 | ||
| 101 | /* PRM.MPU_PRM register offsets */ | |
| 2339ea99 | 102 | #define OMAP4_PM_MPU_PWRSTCTRL_OFFSET 0x0000 |
| c1294045 | 103 | #define OMAP4430_PM_MPU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0000) |
| 2339ea99 | 104 | #define OMAP4_PM_MPU_PWRSTST_OFFSET 0x0004 |
| c1294045 | 105 | #define OMAP4430_PM_MPU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0004) |
| 2339ea99 | 106 | #define OMAP4_RM_MPU_RSTST_OFFSET 0x0014 |
| c1294045 | 107 | #define OMAP4430_RM_MPU_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0014) |
| 2339ea99 | 108 | #define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 |
| c1294045 RN |
109 | #define OMAP4430_RM_MPU_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0024) |
| 110 | ||
| 111 | /* PRM.TESLA_PRM register offsets */ | |
| 2339ea99 | 112 | #define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET 0x0000 |
| c1294045 | 113 | #define OMAP4430_PM_TESLA_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0000) |
| 2339ea99 | 114 | #define OMAP4_PM_TESLA_PWRSTST_OFFSET 0x0004 |
| c1294045 | 115 | #define OMAP4430_PM_TESLA_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0004) |
| 2339ea99 | 116 | #define OMAP4_RM_TESLA_RSTCTRL_OFFSET 0x0010 |
| c1294045 | 117 | #define OMAP4430_RM_TESLA_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0010) |
| 2339ea99 | 118 | #define OMAP4_RM_TESLA_RSTST_OFFSET 0x0014 |
| c1294045 | 119 | #define OMAP4430_RM_TESLA_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0014) |
| 2339ea99 | 120 | #define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET 0x0024 |
| c1294045 RN |
121 | #define OMAP4430_RM_TESLA_TESLA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0024) |
| 122 | ||
| 123 | /* PRM.ABE_PRM register offsets */ | |
| 2339ea99 | 124 | #define OMAP4_PM_ABE_PWRSTCTRL_OFFSET 0x0000 |
| c1294045 | 125 | #define OMAP4430_PM_ABE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0000) |
| 2339ea99 | 126 | #define OMAP4_PM_ABE_PWRSTST_OFFSET 0x0004 |
| c1294045 | 127 | #define OMAP4430_PM_ABE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0004) |
| 2339ea99 | 128 | #define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET 0x002c |
| c1294045 | 129 | #define OMAP4430_RM_ABE_AESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x002c) |
| 2339ea99 | 130 | #define OMAP4_PM_ABE_PDM_WKDEP_OFFSET 0x0030 |
| c1294045 | 131 | #define OMAP4430_PM_ABE_PDM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0030) |
| 2339ea99 | 132 | #define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET 0x0034 |
| c1294045 | 133 | #define OMAP4430_RM_ABE_PDM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0034) |
| 2339ea99 | 134 | #define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET 0x0038 |
| c1294045 | 135 | #define OMAP4430_PM_ABE_DMIC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0038) |
| 2339ea99 | 136 | #define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c |
| c1294045 | 137 | #define OMAP4430_RM_ABE_DMIC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x003c) |
| 2339ea99 | 138 | #define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET 0x0040 |
| c1294045 | 139 | #define OMAP4430_PM_ABE_MCASP_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0040) |
| 2339ea99 | 140 | #define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044 |
| c1294045 | 141 | #define OMAP4430_RM_ABE_MCASP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0044) |
| 2339ea99 | 142 | #define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048 |
| c1294045 | 143 | #define OMAP4430_PM_ABE_MCBSP1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0048) |
| 2339ea99 | 144 | #define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c |
| c1294045 | 145 | #define OMAP4430_RM_ABE_MCBSP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x004c) |
| 2339ea99 | 146 | #define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050 |
| c1294045 | 147 | #define OMAP4430_PM_ABE_MCBSP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0050) |
| 2339ea99 | 148 | #define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054 |
| c1294045 | 149 | #define OMAP4430_RM_ABE_MCBSP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0054) |
| 2339ea99 | 150 | #define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058 |
| c1294045 | 151 | #define OMAP4430_PM_ABE_MCBSP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0058) |
| 2339ea99 | 152 | #define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c |
| c1294045 | 153 | #define OMAP4430_RM_ABE_MCBSP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x005c) |
| 2339ea99 | 154 | #define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET 0x0060 |
| c1294045 | 155 | #define OMAP4430_PM_ABE_SLIMBUS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0060) |
| 2339ea99 | 156 | #define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET 0x0064 |
| c1294045 | 157 | #define OMAP4430_RM_ABE_SLIMBUS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0064) |
| 2339ea99 | 158 | #define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068 |
| c1294045 | 159 | #define OMAP4430_PM_ABE_TIMER5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0068) |
| 2339ea99 | 160 | #define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c |
| c1294045 | 161 | #define OMAP4430_RM_ABE_TIMER5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x006c) |
| 2339ea99 | 162 | #define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070 |
| c1294045 | 163 | #define OMAP4430_PM_ABE_TIMER6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0070) |
| 2339ea99 | 164 | #define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074 |
| c1294045 | 165 | #define OMAP4430_RM_ABE_TIMER6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0074) |
| 2339ea99 | 166 | #define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078 |
| c1294045 | 167 | #define OMAP4430_PM_ABE_TIMER7_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0078) |
| 2339ea99 | 168 | #define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c |
| c1294045 | 169 | #define OMAP4430_RM_ABE_TIMER7_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x007c) |
| 2339ea99 | 170 | #define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080 |
| c1294045 | 171 | #define OMAP4430_PM_ABE_TIMER8_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0080) |
| 2339ea99 | 172 | #define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084 |
| c1294045 | 173 | #define OMAP4430_RM_ABE_TIMER8_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0084) |
| 2339ea99 | 174 | #define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET 0x0088 |
| c1294045 | 175 | #define OMAP4430_PM_ABE_WDT3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0088) |
| 2339ea99 | 176 | #define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET 0x008c |
| c1294045 RN |
177 | #define OMAP4430_RM_ABE_WDT3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x008c) |
| 178 | ||
| 179 | /* PRM.ALWAYS_ON_PRM register offsets */ | |
| 2339ea99 | 180 | #define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET 0x0024 |
| c1294045 | 181 | #define OMAP4430_RM_ALWON_MDMINTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0024) |
| 2339ea99 | 182 | #define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET 0x0028 |
| c1294045 | 183 | #define OMAP4430_PM_ALWON_SR_MPU_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0028) |
| 2339ea99 | 184 | #define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET 0x002c |
| c1294045 | 185 | #define OMAP4430_RM_ALWON_SR_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x002c) |
| 2339ea99 | 186 | #define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET 0x0030 |
| c1294045 | 187 | #define OMAP4430_PM_ALWON_SR_IVA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0030) |
| 2339ea99 | 188 | #define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET 0x0034 |
| c1294045 | 189 | #define OMAP4430_RM_ALWON_SR_IVA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0034) |
| 2339ea99 | 190 | #define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET 0x0038 |
| c1294045 | 191 | #define OMAP4430_PM_ALWON_SR_CORE_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0038) |
| 2339ea99 | 192 | #define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET 0x003c |
| c1294045 RN |
193 | #define OMAP4430_RM_ALWON_SR_CORE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x003c) |
| 194 | ||
| 195 | /* PRM.CORE_PRM register offsets */ | |
| 2339ea99 | 196 | #define OMAP4_PM_CORE_PWRSTCTRL_OFFSET 0x0000 |
| c1294045 | 197 | #define OMAP4430_PM_CORE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0000) |
| 2339ea99 | 198 | #define OMAP4_PM_CORE_PWRSTST_OFFSET 0x0004 |
| c1294045 | 199 | #define OMAP4430_PM_CORE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0004) |
| 2339ea99 | 200 | #define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET 0x0024 |
| c1294045 | 201 | #define OMAP4430_RM_L3_1_L3_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0024) |
| 2339ea99 | 202 | #define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET 0x0124 |
| c1294045 | 203 | #define OMAP4430_RM_L3_2_L3_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0124) |
| 2339ea99 | 204 | #define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET 0x012c |
| c1294045 | 205 | #define OMAP4430_RM_L3_2_GPMC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x012c) |
| 2339ea99 | 206 | #define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET 0x0134 |
| c1294045 | 207 | #define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0134) |
| 2339ea99 | 208 | #define OMAP4_RM_DUCATI_RSTCTRL_OFFSET 0x0210 |
| c1294045 | 209 | #define OMAP4430_RM_DUCATI_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0210) |
| 2339ea99 | 210 | #define OMAP4_RM_DUCATI_RSTST_OFFSET 0x0214 |
| c1294045 | 211 | #define OMAP4430_RM_DUCATI_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0214) |
| 2339ea99 | 212 | #define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET 0x0224 |
| c1294045 | 213 | #define OMAP4430_RM_DUCATI_DUCATI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0224) |
| 2339ea99 | 214 | #define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET 0x0324 |
| c1294045 | 215 | #define OMAP4430_RM_SDMA_SDMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0324) |
| 2339ea99 | 216 | #define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET 0x0424 |
| c1294045 | 217 | #define OMAP4430_RM_MEMIF_DMM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0424) |
| 2339ea99 | 218 | #define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET 0x042c |
| c1294045 | 219 | #define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x042c) |
| 2339ea99 | 220 | #define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET 0x0434 |
| c1294045 | 221 | #define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0434) |
| 2339ea99 | 222 | #define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET 0x043c |
| c1294045 | 223 | #define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x043c) |
| 2339ea99 | 224 | #define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET 0x0444 |
| c1294045 | 225 | #define OMAP4430_RM_MEMIF_DLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0444) |
| 2339ea99 | 226 | #define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET 0x0454 |
| c1294045 | 227 | #define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0454) |
| 2339ea99 | 228 | #define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET 0x045c |
| c1294045 | 229 | #define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x045c) |
| 2339ea99 | 230 | #define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET 0x0464 |
| c1294045 | 231 | #define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0464) |
| 2339ea99 | 232 | #define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524 |
| c1294045 | 233 | #define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0524) |
| 2339ea99 | 234 | #define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET 0x052c |
| c1294045 | 235 | #define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x052c) |
| 2339ea99 | 236 | #define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534 |
| c1294045 | 237 | #define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0534) |
| 2339ea99 | 238 | #define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 |
| c1294045 | 239 | #define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0624) |
| 2339ea99 | 240 | #define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET 0x062c |
| c1294045 | 241 | #define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x062c) |
| 2339ea99 | 242 | #define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634 |
| c1294045 | 243 | #define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0634) |
| 2339ea99 | 244 | #define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c |
| c1294045 | 245 | #define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x063c) |
| 2339ea99 | 246 | #define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET 0x0724 |
| c1294045 | 247 | #define OMAP4430_RM_L3INSTR_L3_3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0724) |
| 2339ea99 | 248 | #define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c |
| c1294045 | 249 | #define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x072c) |
| 2339ea99 | 250 | #define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET 0x0744 |
| c1294045 RN |
251 | #define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0744) |
| 252 | ||
| 253 | /* PRM.IVAHD_PRM register offsets */ | |
| 2339ea99 | 254 | #define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET 0x0000 |
| c1294045 | 255 | #define OMAP4430_PM_IVAHD_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0000) |
| 2339ea99 | 256 | #define OMAP4_PM_IVAHD_PWRSTST_OFFSET 0x0004 |
| c1294045 | 257 | #define OMAP4430_PM_IVAHD_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0004) |
| 2339ea99 | 258 | #define OMAP4_RM_IVAHD_RSTCTRL_OFFSET 0x0010 |
| c1294045 | 259 | #define OMAP4430_RM_IVAHD_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0010) |
| 2339ea99 | 260 | #define OMAP4_RM_IVAHD_RSTST_OFFSET 0x0014 |
| c1294045 | 261 | #define OMAP4430_RM_IVAHD_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0014) |
| 2339ea99 | 262 | #define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET 0x0024 |
| c1294045 | 263 | #define OMAP4430_RM_IVAHD_IVAHD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0024) |
| 2339ea99 | 264 | #define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET 0x002c |
| c1294045 RN |
265 | #define OMAP4430_RM_IVAHD_SL2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x002c) |
| 266 | ||
| 267 | /* PRM.CAM_PRM register offsets */ | |
| 2339ea99 | 268 | #define OMAP4_PM_CAM_PWRSTCTRL_OFFSET 0x0000 |
| c1294045 | 269 | #define OMAP4430_PM_CAM_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0000) |
| 2339ea99 | 270 | #define OMAP4_PM_CAM_PWRSTST_OFFSET 0x0004 |
| c1294045 | 271 | #define OMAP4430_PM_CAM_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0004) |
| 2339ea99 | 272 | #define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET 0x0024 |
| c1294045 | 273 | #define OMAP4430_RM_CAM_ISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0024) |
| 2339ea99 | 274 | #define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c |
| c1294045 RN |
275 | #define OMAP4430_RM_CAM_FDIF_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x002c) |
| 276 | ||
| 277 | /* PRM.DSS_PRM register offsets */ | |
| 2339ea99 | 278 | #define OMAP4_PM_DSS_PWRSTCTRL_OFFSET 0x0000 |
| c1294045 | 279 | #define OMAP4430_PM_DSS_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0000) |
| 2339ea99 | 280 | #define OMAP4_PM_DSS_PWRSTST_OFFSET 0x0004 |
| c1294045 | 281 | #define OMAP4430_PM_DSS_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0004) |
| 2339ea99 | 282 | #define OMAP4_PM_DSS_DSS_WKDEP_OFFSET 0x0020 |
| c1294045 | 283 | #define OMAP4430_PM_DSS_DSS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0020) |
| 2339ea99 | 284 | #define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 |
| c1294045 | 285 | #define OMAP4430_RM_DSS_DSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0024) |
| 2339ea99 | 286 | #define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET 0x002c |
| c1294045 RN |
287 | #define OMAP4430_RM_DSS_DEISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x002c) |
| 288 | ||
| 289 | /* PRM.GFX_PRM register offsets */ | |
| 2339ea99 | 290 | #define OMAP4_PM_GFX_PWRSTCTRL_OFFSET 0x0000 |
| c1294045 | 291 | #define OMAP4430_PM_GFX_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0000) |
| 2339ea99 | 292 | #define OMAP4_PM_GFX_PWRSTST_OFFSET 0x0004 |
| c1294045 | 293 | #define OMAP4430_PM_GFX_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0004) |
| 2339ea99 | 294 | #define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET 0x0024 |
| c1294045 RN |
295 | #define OMAP4430_RM_GFX_GFX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0024) |
| 296 | ||
| 297 | /* PRM.L3INIT_PRM register offsets */ | |
| 2339ea99 | 298 | #define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 |
| c1294045 | 299 | #define OMAP4430_PM_L3INIT_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0000) |
| 2339ea99 | 300 | #define OMAP4_PM_L3INIT_PWRSTST_OFFSET 0x0004 |
| c1294045 | 301 | #define OMAP4430_PM_L3INIT_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0004) |
| 2339ea99 | 302 | #define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 |
| c1294045 | 303 | #define OMAP4430_PM_L3INIT_MMC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0028) |
| 2339ea99 | 304 | #define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c |
| c1294045 | 305 | #define OMAP4430_RM_L3INIT_MMC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x002c) |
| 2339ea99 | 306 | #define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 |
| c1294045 | 307 | #define OMAP4430_PM_L3INIT_MMC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0030) |
| 2339ea99 | 308 | #define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 |
| c1294045 | 309 | #define OMAP4430_RM_L3INIT_MMC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0034) |
| 2339ea99 | 310 | #define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038 |
| c1294045 | 311 | #define OMAP4430_PM_L3INIT_HSI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0038) |
| 2339ea99 | 312 | #define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c |
| c1294045 | 313 | #define OMAP4430_RM_L3INIT_HSI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x003c) |
| 2339ea99 | 314 | #define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET 0x0040 |
| c1294045 | 315 | #define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0040) |
| 2339ea99 | 316 | #define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET 0x0044 |
| c1294045 | 317 | #define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0044) |
| 2339ea99 | 318 | #define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET 0x0058 |
| c1294045 | 319 | #define OMAP4430_PM_L3INIT_USB_HOST_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0058) |
| 2339ea99 | 320 | #define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET 0x005c |
| c1294045 | 321 | #define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x005c) |
| 2339ea99 | 322 | #define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET 0x0060 |
| c1294045 | 323 | #define OMAP4430_PM_L3INIT_USB_OTG_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0060) |
| 2339ea99 | 324 | #define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET 0x0064 |
| c1294045 | 325 | #define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0064) |
| 2339ea99 | 326 | #define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET 0x0068 |
| c1294045 | 327 | #define OMAP4430_PM_L3INIT_USB_TLL_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0068) |
| 2339ea99 | 328 | #define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET 0x006c |
| c1294045 | 329 | #define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x006c) |
| 2339ea99 | 330 | #define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET 0x007c |
| c1294045 | 331 | #define OMAP4430_RM_L3INIT_P1500_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x007c) |
| 2339ea99 | 332 | #define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET 0x0084 |
| c1294045 | 333 | #define OMAP4430_RM_L3INIT_EMAC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0084) |
| 2339ea99 | 334 | #define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 |
| c1294045 | 335 | #define OMAP4430_PM_L3INIT_SATA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0088) |
| 2339ea99 | 336 | #define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c |
| c1294045 | 337 | #define OMAP4430_RM_L3INIT_SATA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x008c) |
| 2339ea99 | 338 | #define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET 0x0094 |
| c1294045 | 339 | #define OMAP4430_RM_L3INIT_TPPSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0094) |
| 2339ea99 | 340 | #define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET 0x0098 |
| c1294045 | 341 | #define OMAP4430_PM_L3INIT_PCIESS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0098) |
| 2339ea99 | 342 | #define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET 0x009c |
| c1294045 | 343 | #define OMAP4430_RM_L3INIT_PCIESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x009c) |
| 2339ea99 | 344 | #define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET 0x00ac |
| c1294045 | 345 | #define OMAP4430_RM_L3INIT_CCPTX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00ac) |
| 2339ea99 | 346 | #define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET 0x00c0 |
| c1294045 | 347 | #define OMAP4430_PM_L3INIT_XHPI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c0) |
| 2339ea99 | 348 | #define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET 0x00c4 |
| c1294045 | 349 | #define OMAP4430_RM_L3INIT_XHPI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c4) |
| 2339ea99 | 350 | #define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET 0x00c8 |
| c1294045 | 351 | #define OMAP4430_PM_L3INIT_MMC6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c8) |
| 2339ea99 | 352 | #define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET 0x00cc |
| c1294045 | 353 | #define OMAP4430_RM_L3INIT_MMC6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00cc) |
| 2339ea99 | 354 | #define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET 0x00d0 |
| c1294045 | 355 | #define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d0) |
| 2339ea99 | 356 | #define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET 0x00d4 |
| c1294045 | 357 | #define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d4) |
| 2339ea99 | 358 | #define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET 0x00e4 |
| c1294045 RN |
359 | #define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00e4) |
| 360 | ||
| 361 | /* PRM.L4PER_PRM register offsets */ | |
| 2339ea99 | 362 | #define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET 0x0000 |
| c1294045 | 363 | #define OMAP4430_PM_L4PER_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0000) |
| 2339ea99 | 364 | #define OMAP4_PM_L4PER_PWRSTST_OFFSET 0x0004 |
| c1294045 | 365 | #define OMAP4430_PM_L4PER_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0004) |
| 2339ea99 | 366 | #define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET 0x0024 |
| c1294045 | 367 | #define OMAP4430_RM_L4PER_ADC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0024) |
| 2339ea99 | 368 | #define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET 0x0028 |
| c1294045 | 369 | #define OMAP4430_PM_L4PER_DMTIMER10_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0028) |
| 2339ea99 | 370 | #define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET 0x002c |
| c1294045 | 371 | #define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x002c) |
| 2339ea99 | 372 | #define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET 0x0030 |
| c1294045 | 373 | #define OMAP4430_PM_L4PER_DMTIMER11_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0030) |
| 2339ea99 | 374 | #define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET 0x0034 |
| c1294045 | 375 | #define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0034) |
| 2339ea99 | 376 | #define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET 0x0038 |
| c1294045 | 377 | #define OMAP4430_PM_L4PER_DMTIMER2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0038) |
| 2339ea99 | 378 | #define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET 0x003c |
| c1294045 | 379 | #define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x003c) |
| 2339ea99 | 380 | #define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET 0x0040 |
| c1294045 | 381 | #define OMAP4430_PM_L4PER_DMTIMER3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0040) |
| 2339ea99 | 382 | #define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET 0x0044 |
| c1294045 | 383 | #define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0044) |
| 2339ea99 | 384 | #define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET 0x0048 |
| c1294045 | 385 | #define OMAP4430_PM_L4PER_DMTIMER4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0048) |
| 2339ea99 | 386 | #define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET 0x004c |
| c1294045 | 387 | #define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x004c) |
| 2339ea99 | 388 | #define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET 0x0050 |
| c1294045 | 389 | #define OMAP4430_PM_L4PER_DMTIMER9_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0050) |
| 2339ea99 | 390 | #define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET 0x0054 |
| c1294045 | 391 | #define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0054) |
| 2339ea99 | 392 | #define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c |
| c1294045 | 393 | #define OMAP4430_RM_L4PER_ELM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x005c) |
| 2339ea99 | 394 | #define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060 |
| c1294045 | 395 | #define OMAP4430_PM_L4PER_GPIO2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0060) |
| 2339ea99 | 396 | #define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064 |
| c1294045 | 397 | #define OMAP4430_RM_L4PER_GPIO2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0064) |
| 2339ea99 | 398 | #define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068 |
| c1294045 | 399 | #define OMAP4430_PM_L4PER_GPIO3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0068) |
| 2339ea99 | 400 | #define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c |
| c1294045 | 401 | #define OMAP4430_RM_L4PER_GPIO3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x006c) |
| 2339ea99 | 402 | #define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070 |
| c1294045 | 403 | #define OMAP4430_PM_L4PER_GPIO4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0070) |
| 2339ea99 | 404 | #define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074 |
| c1294045 | 405 | #define OMAP4430_RM_L4PER_GPIO4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0074) |
| 2339ea99 | 406 | #define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078 |
| c1294045 | 407 | #define OMAP4430_PM_L4PER_GPIO5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0078) |
| 2339ea99 | 408 | #define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c |
| c1294045 | 409 | #define OMAP4430_RM_L4PER_GPIO5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x007c) |
| 2339ea99 | 410 | #define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080 |
| c1294045 | 411 | #define OMAP4430_PM_L4PER_GPIO6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0080) |
| 2339ea99 | 412 | #define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084 |
| c1294045 | 413 | #define OMAP4430_RM_L4PER_GPIO6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0084) |
| 2339ea99 | 414 | #define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c |
| c1294045 | 415 | #define OMAP4430_RM_L4PER_HDQ1W_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x008c) |
| 2339ea99 | 416 | #define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET 0x0090 |
| c1294045 | 417 | #define OMAP4430_PM_L4PER_HECC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0090) |
| 2339ea99 | 418 | #define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET 0x0094 |
| c1294045 | 419 | #define OMAP4430_RM_L4PER_HECC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0094) |
| 2339ea99 | 420 | #define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET 0x0098 |
| c1294045 | 421 | #define OMAP4430_PM_L4PER_HECC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0098) |
| 2339ea99 | 422 | #define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET 0x009c |
| c1294045 | 423 | #define OMAP4430_RM_L4PER_HECC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x009c) |
| 2339ea99 | 424 | #define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0 |
| c1294045 | 425 | #define OMAP4430_PM_L4PER_I2C1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a0) |
| 2339ea99 | 426 | #define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4 |
| c1294045 | 427 | #define OMAP4430_RM_L4PER_I2C1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a4) |
| 2339ea99 | 428 | #define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8 |
| c1294045 | 429 | #define OMAP4430_PM_L4PER_I2C2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a8) |
| 2339ea99 | 430 | #define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac |
| c1294045 | 431 | #define OMAP4430_RM_L4PER_I2C2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ac) |
| 2339ea99 | 432 | #define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0 |
| c1294045 | 433 | #define OMAP4430_PM_L4PER_I2C3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b0) |
| 2339ea99 | 434 | #define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4 |
| c1294045 | 435 | #define OMAP4430_RM_L4PER_I2C3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b4) |
| 2339ea99 | 436 | #define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8 |
| c1294045 | 437 | #define OMAP4430_PM_L4PER_I2C4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b8) |
| 2339ea99 | 438 | #define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc |
| c1294045 | 439 | #define OMAP4430_RM_L4PER_I2C4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00bc) |
| 2339ea99 | 440 | #define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x00c0 |
| c1294045 | 441 | #define OMAP4430_RM_L4PER_L4_PER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00c0) |
| 2339ea99 | 442 | #define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET 0x00d0 |
| c1294045 | 443 | #define OMAP4430_PM_L4PER_MCASP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d0) |
| 2339ea99 | 444 | #define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET 0x00d4 |
| c1294045 | 445 | #define OMAP4430_RM_L4PER_MCASP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d4) |
| 2339ea99 | 446 | #define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET 0x00d8 |
| c1294045 | 447 | #define OMAP4430_PM_L4PER_MCASP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d8) |
| 2339ea99 | 448 | #define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET 0x00dc |
| c1294045 | 449 | #define OMAP4430_RM_L4PER_MCASP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00dc) |
| 2339ea99 | 450 | #define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET 0x00e0 |
| c1294045 | 451 | #define OMAP4430_PM_L4PER_MCBSP4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e0) |
| 2339ea99 | 452 | #define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET 0x00e4 |
| c1294045 | 453 | #define OMAP4430_RM_L4PER_MCBSP4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e4) |
| 2339ea99 | 454 | #define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET 0x00ec |
| c1294045 | 455 | #define OMAP4430_RM_L4PER_MGATE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ec) |
| 2339ea99 | 456 | #define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0 |
| c1294045 | 457 | #define OMAP4430_PM_L4PER_MCSPI1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f0) |
| 2339ea99 | 458 | #define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4 |
| c1294045 | 459 | #define OMAP4430_RM_L4PER_MCSPI1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f4) |
| 2339ea99 | 460 | #define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8 |
| c1294045 | 461 | #define OMAP4430_PM_L4PER_MCSPI2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f8) |
| 2339ea99 | 462 | #define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc |
| c1294045 | 463 | #define OMAP4430_RM_L4PER_MCSPI2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00fc) |
| 2339ea99 | 464 | #define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100 |
| c1294045 | 465 | #define OMAP4430_PM_L4PER_MCSPI3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0100) |
| 2339ea99 | 466 | #define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104 |
| c1294045 | 467 | #define OMAP4430_RM_L4PER_MCSPI3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0104) |
| 2339ea99 | 468 | #define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108 |
| c1294045 | 469 | #define OMAP4430_PM_L4PER_MCSPI4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0108) |
| 2339ea99 | 470 | #define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c |
| c1294045 | 471 | #define OMAP4430_RM_L4PER_MCSPI4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x010c) |
| 2339ea99 | 472 | #define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET 0x0120 |
| c1294045 | 473 | #define OMAP4430_PM_L4PER_MMCSD3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0120) |
| 2339ea99 | 474 | #define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET 0x0124 |
| c1294045 | 475 | #define OMAP4430_RM_L4PER_MMCSD3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0124) |
| 2339ea99 | 476 | #define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET 0x0128 |
| c1294045 | 477 | #define OMAP4430_PM_L4PER_MMCSD4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0128) |
| 2339ea99 | 478 | #define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET 0x012c |
| c1294045 | 479 | #define OMAP4430_RM_L4PER_MMCSD4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x012c) |
| 2339ea99 | 480 | #define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET 0x0134 |
| c1294045 | 481 | #define OMAP4430_RM_L4PER_MSPROHG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0134) |
| 2339ea99 | 482 | #define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET 0x0138 |
| c1294045 | 483 | #define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0138) |
| 2339ea99 | 484 | #define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET 0x013c |
| c1294045 | 485 | #define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x013c) |
| 2339ea99 | 486 | #define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET 0x0140 |
| c1294045 | 487 | #define OMAP4430_PM_L4PER_UART1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0140) |
| 2339ea99 | 488 | #define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144 |
| c1294045 | 489 | #define OMAP4430_RM_L4PER_UART1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0144) |
| 2339ea99 | 490 | #define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET 0x0148 |
| c1294045 | 491 | #define OMAP4430_PM_L4PER_UART2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0148) |
| 2339ea99 | 492 | #define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c |
| c1294045 | 493 | #define OMAP4430_RM_L4PER_UART2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x014c) |
| 2339ea99 | 494 | #define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET 0x0150 |
| c1294045 | 495 | #define OMAP4430_PM_L4PER_UART3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0150) |
| 2339ea99 | 496 | #define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154 |
| c1294045 | 497 | #define OMAP4430_RM_L4PER_UART3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0154) |
| 2339ea99 | 498 | #define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET 0x0158 |
| c1294045 | 499 | #define OMAP4430_PM_L4PER_UART4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0158) |
| 2339ea99 | 500 | #define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c |
| c1294045 | 501 | #define OMAP4430_RM_L4PER_UART4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x015c) |
| 2339ea99 | 502 | #define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET 0x0160 |
| c1294045 | 503 | #define OMAP4430_PM_L4PER_MMCSD5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0160) |
| 2339ea99 | 504 | #define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET 0x0164 |
| c1294045 | 505 | #define OMAP4430_RM_L4PER_MMCSD5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0164) |
| 2339ea99 | 506 | #define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET 0x0168 |
| c1294045 | 507 | #define OMAP4430_PM_L4PER_I2C5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0168) |
| 2339ea99 | 508 | #define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET 0x016c |
| c1294045 | 509 | #define OMAP4430_RM_L4PER_I2C5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x016c) |
| 2339ea99 | 510 | #define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4 |
| c1294045 | 511 | #define OMAP4430_RM_L4SEC_AES1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01a4) |
| 2339ea99 | 512 | #define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac |
| c1294045 | 513 | #define OMAP4430_RM_L4SEC_AES2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01ac) |
| 2339ea99 | 514 | #define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4 |
| c1294045 | 515 | #define OMAP4430_RM_L4SEC_DES3DES_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01b4) |
| 2339ea99 | 516 | #define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET 0x01bc |
| c1294045 | 517 | #define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01bc) |
| 2339ea99 | 518 | #define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4 |
| c1294045 | 519 | #define OMAP4430_RM_L4SEC_RNG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01c4) |
| 2339ea99 | 520 | #define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc |
| c1294045 | 521 | #define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01cc) |
| 2339ea99 | 522 | #define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET 0x01dc |
| c1294045 RN |
523 | #define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01dc) |
| 524 | ||
| 525 | /* PRM.CEFUSE_PRM register offsets */ | |
| 2339ea99 | 526 | #define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000 |
| c1294045 | 527 | #define OMAP4430_PM_CEFUSE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0000) |
| 2339ea99 | 528 | #define OMAP4_PM_CEFUSE_PWRSTST_OFFSET 0x0004 |
| c1294045 | 529 | #define OMAP4430_PM_CEFUSE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0004) |
| 2339ea99 | 530 | #define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET 0x0024 |
| c1294045 RN |
531 | #define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0024) |
| 532 | ||
| 533 | /* PRM.WKUP_PRM register offsets */ | |
| 2339ea99 | 534 | #define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET 0x0024 |
| c1294045 | 535 | #define OMAP4430_RM_WKUP_L4WKUP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0024) |
| 2339ea99 | 536 | #define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET 0x002c |
| c1294045 | 537 | #define OMAP4430_RM_WKUP_WDT1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x002c) |
| 2339ea99 | 538 | #define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET 0x0030 |
| c1294045 | 539 | #define OMAP4430_PM_WKUP_WDT2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0030) |
| 2339ea99 | 540 | #define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET 0x0034 |
| c1294045 | 541 | #define OMAP4430_RM_WKUP_WDT2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0034) |
| 2339ea99 | 542 | #define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET 0x0038 |
| c1294045 | 543 | #define OMAP4430_PM_WKUP_GPIO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0038) |
| 2339ea99 | 544 | #define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET 0x003c |
| c1294045 | 545 | #define OMAP4430_RM_WKUP_GPIO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x003c) |
| 2339ea99 | 546 | #define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET 0x0040 |
| c1294045 | 547 | #define OMAP4430_PM_WKUP_TIMER1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0040) |
| 2339ea99 | 548 | #define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET 0x0044 |
| c1294045 | 549 | #define OMAP4430_RM_WKUP_TIMER1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0044) |
| 2339ea99 | 550 | #define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET 0x0048 |
| c1294045 | 551 | #define OMAP4430_PM_WKUP_TIMER12_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0048) |
| 2339ea99 | 552 | #define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET 0x004c |
| c1294045 | 553 | #define OMAP4430_RM_WKUP_TIMER12_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x004c) |
| 2339ea99 | 554 | #define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET 0x0054 |
| c1294045 | 555 | #define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0054) |
| 2339ea99 | 556 | #define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET 0x0058 |
| c1294045 | 557 | #define OMAP4430_PM_WKUP_USIM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0058) |
| 2339ea99 | 558 | #define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET 0x005c |
| c1294045 | 559 | #define OMAP4430_RM_WKUP_USIM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x005c) |
| 2339ea99 | 560 | #define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET 0x0064 |
| c1294045 | 561 | #define OMAP4430_RM_WKUP_SARRAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0064) |
| 2339ea99 | 562 | #define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET 0x0078 |
| c1294045 | 563 | #define OMAP4430_PM_WKUP_KEYBOARD_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0078) |
| 2339ea99 | 564 | #define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET 0x007c |
| c1294045 | 565 | #define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x007c) |
| 2339ea99 | 566 | #define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET 0x0080 |
| c1294045 | 567 | #define OMAP4430_PM_WKUP_RTC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0080) |
| 2339ea99 | 568 | #define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET 0x0084 |
| c1294045 RN |
569 | #define OMAP4430_RM_WKUP_RTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0084) |
| 570 | ||
| 571 | /* PRM.WKUP_CM register offsets */ | |
| 2339ea99 | 572 | #define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET 0x0000 |
| c1294045 | 573 | #define OMAP4430_CM_WKUP_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0000) |
| 2339ea99 | 574 | #define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0020 |
| c1294045 | 575 | #define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0020) |
| 2339ea99 | 576 | #define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0028 |
| c1294045 | 577 | #define OMAP4430_CM_WKUP_WDT1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0028) |
| 2339ea99 | 578 | #define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET 0x0030 |
| c1294045 | 579 | #define OMAP4430_CM_WKUP_WDT2_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0030) |
| 2339ea99 | 580 | #define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET 0x0038 |
| c1294045 | 581 | #define OMAP4430_CM_WKUP_GPIO1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0038) |
| 2339ea99 | 582 | #define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0040 |
| c1294045 | 583 | #define OMAP4430_CM_WKUP_TIMER1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0040) |
| 2339ea99 | 584 | #define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET 0x0048 |
| c1294045 | 585 | #define OMAP4430_CM_WKUP_TIMER12_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0048) |
| 2339ea99 | 586 | #define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0050 |
| c1294045 | 587 | #define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0050) |
| 2339ea99 | 588 | #define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET 0x0058 |
| c1294045 | 589 | #define OMAP4430_CM_WKUP_USIM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0058) |
| 2339ea99 | 590 | #define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET 0x0060 |
| c1294045 | 591 | #define OMAP4430_CM_WKUP_SARRAM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0060) |
| 2339ea99 | 592 | #define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET 0x0078 |
| c1294045 | 593 | #define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0078) |
| 2339ea99 | 594 | #define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET 0x0080 |
| c1294045 | 595 | #define OMAP4430_CM_WKUP_RTC_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0080) |
| 2339ea99 | 596 | #define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET 0x0088 |
| c1294045 RN |
597 | #define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0088) |
| 598 | ||
| 599 | /* PRM.EMU_PRM register offsets */ | |
| 2339ea99 | 600 | #define OMAP4_PM_EMU_PWRSTCTRL_OFFSET 0x0000 |
| c1294045 | 601 | #define OMAP4430_PM_EMU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0000) |
| 2339ea99 | 602 | #define OMAP4_PM_EMU_PWRSTST_OFFSET 0x0004 |
| c1294045 | 603 | #define OMAP4430_PM_EMU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0004) |
| 2339ea99 | 604 | #define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 |
| c1294045 RN |
605 | #define OMAP4430_RM_EMU_DEBUGSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0024) |
| 606 | ||
| 607 | /* PRM.EMU_CM register offsets */ | |
| 2339ea99 | 608 | #define OMAP4_CM_EMU_CLKSTCTRL_OFFSET 0x0000 |
| c1294045 | 609 | #define OMAP4430_CM_EMU_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0000) |
| 2339ea99 | 610 | #define OMAP4_CM_EMU_DYNAMICDEP_OFFSET 0x0008 |
| c1294045 | 611 | #define OMAP4430_CM_EMU_DYNAMICDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0008) |
| 2339ea99 | 612 | #define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020 |
| c1294045 RN |
613 | #define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0020) |
| 614 | ||
| 615 | /* PRM.DEVICE_PRM register offsets */ | |
| 2339ea99 | 616 | #define OMAP4_PRM_RSTCTRL_OFFSET 0x0000 |
| c1294045 | 617 | #define OMAP4430_PRM_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0000) |
| 2339ea99 | 618 | #define OMAP4_PRM_RSTST_OFFSET 0x0004 |
| c1294045 | 619 | #define OMAP4430_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0004) |
| 2339ea99 | 620 | #define OMAP4_PRM_RSTTIME_OFFSET 0x0008 |
| c1294045 | 621 | #define OMAP4430_PRM_RSTTIME OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0008) |
| 2339ea99 | 622 | #define OMAP4_PRM_CLKREQCTRL_OFFSET 0x000c |
| c1294045 | 623 | #define OMAP4430_PRM_CLKREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x000c) |
| 2339ea99 | 624 | #define OMAP4_PRM_VOLTCTRL_OFFSET 0x0010 |
| c1294045 | 625 | #define OMAP4430_PRM_VOLTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0010) |
| 2339ea99 | 626 | #define OMAP4_PRM_PWRREQCTRL_OFFSET 0x0014 |
| c1294045 | 627 | #define OMAP4430_PRM_PWRREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0014) |
| 2339ea99 | 628 | #define OMAP4_PRM_PSCON_COUNT_OFFSET 0x0018 |
| c1294045 | 629 | #define OMAP4430_PRM_PSCON_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0018) |
| 2339ea99 | 630 | #define OMAP4_PRM_IO_COUNT_OFFSET 0x001c |
| c1294045 | 631 | #define OMAP4430_PRM_IO_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x001c) |
| 2339ea99 | 632 | #define OMAP4_PRM_IO_PMCTRL_OFFSET 0x0020 |
| c1294045 | 633 | #define OMAP4430_PRM_IO_PMCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0020) |
| 2339ea99 | 634 | #define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 |
| c1294045 | 635 | #define OMAP4430_PRM_VOLTSETUP_WARMRESET OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0024) |
| 2339ea99 | 636 | #define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 |
| c1294045 | 637 | #define OMAP4430_PRM_VOLTSETUP_CORE_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0028) |
| 2339ea99 | 638 | #define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c |
| c1294045 | 639 | #define OMAP4430_PRM_VOLTSETUP_MPU_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x002c) |
| 2339ea99 | 640 | #define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET 0x0030 |
| c1294045 | 641 | #define OMAP4430_PRM_VOLTSETUP_IVA_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0030) |
| 2339ea99 | 642 | #define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 |
| c1294045 | 643 | #define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0034) |
| 2339ea99 | 644 | #define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 |
| c1294045 | 645 | #define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0038) |
| 2339ea99 | 646 | #define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET 0x003c |
| c1294045 | 647 | #define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x003c) |
| 2339ea99 | 648 | #define OMAP4_PRM_VP_CORE_CONFIG_OFFSET 0x0040 |
| c1294045 | 649 | #define OMAP4430_PRM_VP_CORE_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0040) |
| 2339ea99 | 650 | #define OMAP4_PRM_VP_CORE_STATUS_OFFSET 0x0044 |
| c1294045 | 651 | #define OMAP4430_PRM_VP_CORE_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0044) |
| 2339ea99 | 652 | #define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048 |
| c1294045 | 653 | #define OMAP4430_PRM_VP_CORE_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0048) |
| 2339ea99 | 654 | #define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c |
| c1294045 | 655 | #define OMAP4430_PRM_VP_CORE_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x004c) |
| 2339ea99 | 656 | #define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050 |
| c1294045 | 657 | #define OMAP4430_PRM_VP_CORE_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0050) |
| 2339ea99 | 658 | #define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054 |
| c1294045 | 659 | #define OMAP4430_PRM_VP_CORE_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0054) |
| 2339ea99 | 660 | #define OMAP4_PRM_VP_MPU_CONFIG_OFFSET 0x0058 |
| c1294045 | 661 | #define OMAP4430_PRM_VP_MPU_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0058) |
| 2339ea99 | 662 | #define OMAP4_PRM_VP_MPU_STATUS_OFFSET 0x005c |
| c1294045 | 663 | #define OMAP4430_PRM_VP_MPU_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x005c) |
| 2339ea99 | 664 | #define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060 |
| c1294045 | 665 | #define OMAP4430_PRM_VP_MPU_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0060) |
| 2339ea99 | 666 | #define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064 |
| c1294045 | 667 | #define OMAP4430_PRM_VP_MPU_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0064) |
| 2339ea99 | 668 | #define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068 |
| c1294045 | 669 | #define OMAP4430_PRM_VP_MPU_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0068) |
| 2339ea99 | 670 | #define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c |
| c1294045 | 671 | #define OMAP4430_PRM_VP_MPU_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x006c) |
| 2339ea99 | 672 | #define OMAP4_PRM_VP_IVA_CONFIG_OFFSET 0x0070 |
| c1294045 | 673 | #define OMAP4430_PRM_VP_IVA_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0070) |
| 2339ea99 | 674 | #define OMAP4_PRM_VP_IVA_STATUS_OFFSET 0x0074 |
| c1294045 | 675 | #define OMAP4430_PRM_VP_IVA_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0074) |
| 2339ea99 | 676 | #define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET 0x0078 |
| c1294045 | 677 | #define OMAP4430_PRM_VP_IVA_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0078) |
| 2339ea99 | 678 | #define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET 0x007c |
| c1294045 | 679 | #define OMAP4430_PRM_VP_IVA_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x007c) |
| 2339ea99 | 680 | #define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET 0x0080 |
| c1294045 | 681 | #define OMAP4430_PRM_VP_IVA_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0080) |
| 2339ea99 | 682 | #define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET 0x0084 |
| c1294045 | 683 | #define OMAP4430_PRM_VP_IVA_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0084) |
| 2339ea99 | 684 | #define OMAP4_PRM_VC_SMPS_SA_OFFSET 0x0088 |
| c1294045 | 685 | #define OMAP4430_PRM_VC_SMPS_SA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0088) |
| 2339ea99 | 686 | #define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET 0x008c |
| c1294045 | 687 | #define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x008c) |
| 2339ea99 | 688 | #define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET 0x0090 |
| c1294045 | 689 | #define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0090) |
| 2339ea99 | 690 | #define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094 |
| c1294045 | 691 | #define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0094) |
| 2339ea99 | 692 | #define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x0098 |
| c1294045 | 693 | #define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0098) |
| 2339ea99 | 694 | #define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET 0x009c |
| c1294045 | 695 | #define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x009c) |
| 2339ea99 | 696 | #define OMAP4_PRM_VC_VAL_BYPASS_OFFSET 0x00a0 |
| c1294045 | 697 | #define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a0) |
| 2339ea99 | 698 | #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4 |
| c1294045 | 699 | #define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a4) |
| 2339ea99 | 700 | #define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8 |
| c1294045 | 701 | #define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a8) |
| 2339ea99 | 702 | #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac |
| c1294045 | 703 | #define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ac) |
| 2339ea99 | 704 | #define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0 |
| c1294045 | 705 | #define OMAP4430_PRM_SRAM_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b0) |
| 2339ea99 | 706 | #define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET 0x00b4 |
| c1294045 | 707 | #define OMAP4430_PRM_SRAM_WKUP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b4) |
| 2339ea99 | 708 | #define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x00b8 |
| c1294045 | 709 | #define OMAP4430_PRM_LDO_SRAM_CORE_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b8) |
| 2339ea99 | 710 | #define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x00bc |
| c1294045 | 711 | #define OMAP4430_PRM_LDO_SRAM_CORE_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00bc) |
| 2339ea99 | 712 | #define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x00c0 |
| c1294045 | 713 | #define OMAP4430_PRM_LDO_SRAM_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c0) |
| 2339ea99 | 714 | #define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x00c4 |
| c1294045 | 715 | #define OMAP4430_PRM_LDO_SRAM_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c4) |
| 2339ea99 | 716 | #define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET 0x00c8 |
| c1294045 | 717 | #define OMAP4430_PRM_LDO_SRAM_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c8) |
| 2339ea99 | 718 | #define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET 0x00cc |
| c1294045 | 719 | #define OMAP4430_PRM_LDO_SRAM_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00cc) |
| 2339ea99 | 720 | #define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET 0x00d0 |
| c1294045 | 721 | #define OMAP4430_PRM_LDO_ABB_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d0) |
| 2339ea99 | 722 | #define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET 0x00d4 |
| c1294045 | 723 | #define OMAP4430_PRM_LDO_ABB_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d4) |
| 2339ea99 | 724 | #define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET 0x00d8 |
| c1294045 | 725 | #define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8) |
| 2339ea99 | 726 | #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc |
| c1294045 | 727 | #define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc) |
| fdd4f409 RN |
728 | #define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET 0x00e0 |
| 729 | #define OMAP4430_PRM_LDO_BANDGAP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0) | |
| 2339ea99 | 730 | #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4 |
| c1294045 | 731 | #define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4) |
| 2339ea99 | 732 | #define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8 |
| c1294045 | 733 | #define OMAP4430_PRM_PHASE1_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e8) |
| 2339ea99 | 734 | #define OMAP4_PRM_PHASE2A_CNDP_OFFSET 0x00ec |
| c1294045 | 735 | #define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ec) |
| 2339ea99 | 736 | #define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0 |
| c1294045 | 737 | #define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0) |
| 2339ea99 | 738 | #define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4 |
| c1294045 | 739 | #define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4) |
| fdd4f409 RN |
740 | #define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 |
| 741 | #define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f8) | |
| c1294045 | 742 | |
| d198b514 PW |
743 | /* Function prototypes */ |
| 744 | # ifndef __ASSEMBLER__ | |
| 745 | ||
| 746 | extern u32 omap4_prm_read_mod_reg(s16 module, u16 idx); | |
| 747 | extern void omap4_prm_write_mod_reg(u32 val, s16 module, u16 idx); | |
| 748 | extern u32 omap4_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); | |
| 749 | extern u32 omap4_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); | |
| 750 | extern u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask); | |
| 751 | extern u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg); | |
| 752 | extern u32 omap4_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); | |
| 753 | extern u32 omap4_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); | |
| 754 | ||
| 755 | extern int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift); | |
| 756 | extern int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift); | |
| 757 | extern int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift); | |
| 758 | ||
| 759 | # endif | |
| c1294045 | 760 | |
| c1294045 | 761 | #endif |