[deliverable/linux.git] / arch / arm / mach-omap2 / prm_common.c

/*
 * OMAP2+ common Power & Reset Management (PRM) IP block functions
 *
 * Copyright (C) 2011 Texas Instruments, Inc.
 * Tero Kristo <t-kristo@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *
 * For historical purposes, the API used to configure the PRM
 * interrupt handler refers to it as the "PRCM interrupt."  The
 * underlying registers are located in the PRM on OMAP3/4.
 *
 * XXX This code should eventually be moved to a PRM driver.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/slab.h>

#include <plat/common.h>
#include <plat/prcm.h>

#include "prm2xxx_3xxx.h"
#include "prm44xx.h"

/*
 * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
 * XXX this is technically not needed, since
 * omap_prcm_register_chain_handler() could allocate this based on the
 * actual amount of memory needed for the SoC
 */
#define OMAP_PRCM_MAX_NR_PENDING_REG		2

/*
 * prcm_irq_chips: an array of all of the "generic IRQ chips" in use
 * by the PRCM interrupt handler code.  There will be one 'chip' per
 * PRM_{IRQSTATUS,IRQENABLE}_MPU register pair.  (So OMAP3 will have
 * one "chip" and OMAP4 will have two.)
 */
static struct irq_chip_generic **prcm_irq_chips;

/*
 * prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
 * is currently running on.  Defined and passed by initialization code
 * that calls omap_prcm_register_chain_handler().
 */
static struct omap_prcm_irq_setup *prcm_irq_setup;

/* Private functions */

/*
 * Move priority events from events to priority_events array
 */
static void omap_prcm_events_filter_priority(unsigned long *events,
	unsigned long *priority_events)
{
	int i;

	for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
		priority_events[i] =
			events[i] & prcm_irq_setup->priority_mask[i];
		events[i] ^= priority_events[i];
	}
}

/*
 * PRCM Interrupt Handler
 *
 * This is a common handler for the OMAP PRCM interrupts. Pending
 * interrupts are detected by a call to prcm_pending_events and
 * dispatched accordingly. Clearing of the wakeup events should be
 * done by the SoC specific individual handlers.
 */
static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
	unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned int virtirq;
	int nr_irq = prcm_irq_setup->nr_regs * 32;

	/*
	 * If we are suspended, mask all interrupts from PRCM level,
	 * this does not ack them, and they will be pending until we
	 * re-enable the interrupts, at which point the
	 * omap_prcm_irq_handler will be executed again.  The
	 * _save_and_clear_irqen() function must ensure that the PRM
	 * write to disable all IRQs has reached the PRM before
	 * returning, or spurious PRCM interrupts may occur during
	 * suspend.
	 */
	if (prcm_irq_setup->suspended) {
		prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
		prcm_irq_setup->suspend_save_flag = true;
	}

	/*
	 * Loop until all pending irqs are handled, since
	 * generic_handle_irq() can cause new irqs to come
	 */
	while (!prcm_irq_setup->suspended) {
		prcm_irq_setup->read_pending_irqs(pending);

		/* No bit set, then all IRQs are handled */
		if (find_first_bit(pending, nr_irq) >= nr_irq)
			break;

		omap_prcm_events_filter_priority(pending, priority_pending);

		/*
		 * Loop on all currently pending irqs so that new irqs
		 * cannot starve previously pending irqs
		 */

		/* Serve priority events first */
		for_each_set_bit(virtirq, priority_pending, nr_irq)
			generic_handle_irq(prcm_irq_setup->base_irq + virtirq);

		/* Serve normal events next */
		for_each_set_bit(virtirq, pending, nr_irq)
			generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
	}
	if (chip->irq_ack)
		chip->irq_ack(&desc->irq_data);
	if (chip->irq_eoi)
		chip->irq_eoi(&desc->irq_data);
	chip->irq_unmask(&desc->irq_data);

	prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
}

/* Public functions */

/**
 * omap_prcm_event_to_irq - given a PRCM event name, returns the
 * corresponding IRQ on which the handler should be registered
 * @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
 *
 * Returns the Linux internal IRQ ID corresponding to @name upon success,
 * or -ENOENT upon failure.
 */
int omap_prcm_event_to_irq(const char *name)
{
	int i;

	if (!prcm_irq_setup || !name)
		return -ENOENT;

	for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
		if (!strcmp(prcm_irq_setup->irqs[i].name, name))
			return prcm_irq_setup->base_irq +
				prcm_irq_setup->irqs[i].offset;

	return -ENOENT;
}

/**
 * omap_prcm_irq_cleanup - reverses memory allocated and other steps
 * done by omap_prcm_register_chain_handler()
 *
 * No return value.
 */
void omap_prcm_irq_cleanup(void)
{
	int i;

	if (!prcm_irq_setup) {
		pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
		return;
	}

	if (prcm_irq_chips) {
		for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
			if (prcm_irq_chips[i])
				irq_remove_generic_chip(prcm_irq_chips[i],
					0xffffffff, 0, 0);
			prcm_irq_chips[i] = NULL;
		}
		kfree(prcm_irq_chips);
		prcm_irq_chips = NULL;
	}

	kfree(prcm_irq_setup->saved_mask);
	prcm_irq_setup->saved_mask = NULL;

	kfree(prcm_irq_setup->priority_mask);
	prcm_irq_setup->priority_mask = NULL;

	irq_set_chained_handler(prcm_irq_setup->irq, NULL);

	if (prcm_irq_setup->base_irq > 0)
		irq_free_descs(prcm_irq_setup->base_irq,
			prcm_irq_setup->nr_regs * 32);
	prcm_irq_setup->base_irq = 0;
}

void omap_prcm_irq_prepare(void)
{
	prcm_irq_setup->suspended = true;
}

void omap_prcm_irq_complete(void)
{
	prcm_irq_setup->suspended = false;

	/* If we have not saved the masks, do not attempt to restore */
	if (!prcm_irq_setup->suspend_save_flag)
		return;

	prcm_irq_setup->suspend_save_flag = false;

	/*
	 * Re-enable all masked PRCM irq sources, this causes the PRCM
	 * interrupt to fire immediately if the events were masked
	 * previously in the chain handler
	 */
	prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
}

/**
 * omap_prcm_register_chain_handler - initializes the prcm chained interrupt
 * handler based on provided parameters
 * @irq_setup: hardware data about the underlying PRM/PRCM
 *
 * Set up the PRCM chained interrupt handler on the PRCM IRQ.  Sets up
 * one generic IRQ chip per PRM interrupt status/enable register pair.
 * Returns 0 upon success, -EINVAL if called twice or if invalid
 * arguments are passed, or -ENOMEM on any other error.
 */
int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
{
	int nr_regs;
	u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
	int offset, i;
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	if (!irq_setup)
		return -EINVAL;

	nr_regs = irq_setup->nr_regs;

	if (prcm_irq_setup) {
		pr_err("PRCM: already initialized; won't reinitialize\n");
		return -EINVAL;
	}

	if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
		pr_err("PRCM: nr_regs too large\n");
		return -EINVAL;
	}

	prcm_irq_setup = irq_setup;

	prcm_irq_chips = kzalloc(sizeof(void *) * nr_regs, GFP_KERNEL);
	prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL);
	prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
		GFP_KERNEL);

	if (!prcm_irq_chips || !prcm_irq_setup->saved_mask ||
	    !prcm_irq_setup->priority_mask) {
		pr_err("PRCM: kzalloc failed\n");
		goto err;
	}

	memset(mask, 0, sizeof(mask));

	for (i = 0; i < irq_setup->nr_irqs; i++) {
		offset = irq_setup->irqs[i].offset;
		mask[offset >> 5] |= 1 << (offset & 0x1f);
		if (irq_setup->irqs[i].priority)
			irq_setup->priority_mask[offset >> 5] |=
				1 << (offset & 0x1f);
	}

	irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);

	irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
		0);

	if (irq_setup->base_irq < 0) {
		pr_err("PRCM: failed to allocate irq descs: %d\n",
			irq_setup->base_irq);
		goto err;
	}

	for (i = 0; i < irq_setup->nr_regs; i++) {
		gc = irq_alloc_generic_chip("PRCM", 1,
			irq_setup->base_irq + i * 32, prm_base,
			handle_level_irq);

		if (!gc) {
			pr_err("PRCM: failed to allocate generic chip\n");
			goto err;
		}
		ct = gc->chip_types;
		ct->chip.irq_ack = irq_gc_ack_set_bit;
		ct->chip.irq_mask = irq_gc_mask_clr_bit;
		ct->chip.irq_unmask = irq_gc_mask_set_bit;

		ct->regs.ack = irq_setup->ack + i * 4;
		ct->regs.mask = irq_setup->mask + i * 4;

		irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
		prcm_irq_chips[i] = gc;
	}

	return 0;

err:
	omap_prcm_irq_cleanup();
	return -ENOMEM;
}
Commit	Line	Data
0a84a91c TK	1	/*
	2	* OMAP2+ common Power & Reset Management (PRM) IP block functions
	3	*
	4	* Copyright (C) 2011 Texas Instruments, Inc.
	5	* Tero Kristo <t-kristo@ti.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	*
	12	* For historical purposes, the API used to configure the PRM
	13	* interrupt handler refers to it as the "PRCM interrupt." The
	14	* underlying registers are located in the PRM on OMAP3/4.
	15	*
	16	* XXX This code should eventually be moved to a PRM driver.
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/init.h>
	22	#include <linux/io.h>
	23	#include <linux/irq.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/slab.h>
	26
0a84a91c TK	27	#include <plat/common.h>
0a84a91c TK	28	#include <plat/prcm.h>
0a84a91c TK	29
	30	#include "prm2xxx_3xxx.h"
	31	#include "prm44xx.h"
	32
	33	/*
	34	* OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
	35	* XXX this is technically not needed, since
	36	* omap_prcm_register_chain_handler() could allocate this based on the
	37	* actual amount of memory needed for the SoC
	38	*/
	39	#define OMAP_PRCM_MAX_NR_PENDING_REG 2
	40
	41	/*
	42	* prcm_irq_chips: an array of all of the "generic IRQ chips" in use
	43	* by the PRCM interrupt handler code. There will be one 'chip' per
	44	* PRM_{IRQSTATUS,IRQENABLE}_MPU register pair. (So OMAP3 will have
	45	* one "chip" and OMAP4 will have two.)
	46	*/
	47	static struct irq_chip_generic **prcm_irq_chips;
	48
	49	/*
	50	* prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
	51	* is currently running on. Defined and passed by initialization code
	52	* that calls omap_prcm_register_chain_handler().
	53	*/
	54	static struct omap_prcm_irq_setup *prcm_irq_setup;
	55
	56	/* Private functions */
	57
	58	/*
	59	* Move priority events from events to priority_events array
	60	*/
	61	static void omap_prcm_events_filter_priority(unsigned long *events,
	62	unsigned long *priority_events)
	63	{
	64	int i;
	65
	66	for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
	67	priority_events[i] =
	68	events[i] & prcm_irq_setup->priority_mask[i];
	69	events[i] ^= priority_events[i];
	70	}
	71	}
	72
	73	/*
	74	* PRCM Interrupt Handler
	75	*
	76	* This is a common handler for the OMAP PRCM interrupts. Pending
	77	* interrupts are detected by a call to prcm_pending_events and
	78	* dispatched accordingly. Clearing of the wakeup events should be
	79	* done by the SoC specific individual handlers.
	80	*/
	81	static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
	82	{
	83	unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
	84	unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
	85	struct irq_chip *chip = irq_desc_get_chip(desc);
	86	unsigned int virtirq;
b56f2cb7	87	int nr_irq = prcm_irq_setup->nr_regs * 32;
0a84a91c	88
91285b6f TK	89	/*
	90	* If we are suspended, mask all interrupts from PRCM level,
	91	* this does not ack them, and they will be pending until we
	92	* re-enable the interrupts, at which point the
	93	* omap_prcm_irq_handler will be executed again. The
	94	* _save_and_clear_irqen() function must ensure that the PRM
	95	* write to disable all IRQs has reached the PRM before
	96	* returning, or spurious PRCM interrupts may occur during
	97	* suspend.
	98	*/
	99	if (prcm_irq_setup->suspended) {
	100	prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
	101	prcm_irq_setup->suspend_save_flag = true;
	102	}
	103
0a84a91c TK	104	/*
	105	* Loop until all pending irqs are handled, since
	106	* generic_handle_irq() can cause new irqs to come
	107	*/
91285b6f	108	while (!prcm_irq_setup->suspended) {
0a84a91c TK	109	prcm_irq_setup->read_pending_irqs(pending);
	110
	111	/* No bit set, then all IRQs are handled */
b56f2cb7	112	if (find_first_bit(pending, nr_irq) >= nr_irq)
0a84a91c TK	113	break;
	114
	115	omap_prcm_events_filter_priority(pending, priority_pending);
	116
	117	/*
	118	* Loop on all currently pending irqs so that new irqs
	119	* cannot starve previously pending irqs
	120	*/
	121
	122	/* Serve priority events first */
b56f2cb7	123	for_each_set_bit(virtirq, priority_pending, nr_irq)
0a84a91c TK	124	generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
	125
	126	/* Serve normal events next */
b56f2cb7	127	for_each_set_bit(virtirq, pending, nr_irq)
0a84a91c TK	128	generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
	129	}
	130	if (chip->irq_ack)
	131	chip->irq_ack(&desc->irq_data);
	132	if (chip->irq_eoi)
	133	chip->irq_eoi(&desc->irq_data);
	134	chip->irq_unmask(&desc->irq_data);
	135
	136	prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
	137	}
	138
	139	/* Public functions */
	140
	141	/**
	142	* omap_prcm_event_to_irq - given a PRCM event name, returns the
	143	* corresponding IRQ on which the handler should be registered
	144	* @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
	145	*
	146	* Returns the Linux internal IRQ ID corresponding to @name upon success,
	147	* or -ENOENT upon failure.
	148	*/
	149	int omap_prcm_event_to_irq(const char *name)
	150	{
	151	int i;
	152
	153	if (!prcm_irq_setup \|\| !name)
	154	return -ENOENT;
	155
	156	for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
	157	if (!strcmp(prcm_irq_setup->irqs[i].name, name))
	158	return prcm_irq_setup->base_irq +
	159	prcm_irq_setup->irqs[i].offset;
	160
	161	return -ENOENT;
	162	}
	163
	164	/**
	165	* omap_prcm_irq_cleanup - reverses memory allocated and other steps
	166	* done by omap_prcm_register_chain_handler()
	167	*
	168	* No return value.
	169	*/
	170	void omap_prcm_irq_cleanup(void)
	171	{
	172	int i;
	173
	174	if (!prcm_irq_setup) {
	175	pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
	176	return;
	177	}
	178
	179	if (prcm_irq_chips) {
	180	for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
	181	if (prcm_irq_chips[i])
	182	irq_remove_generic_chip(prcm_irq_chips[i],
	183	0xffffffff, 0, 0);
	184	prcm_irq_chips[i] = NULL;
	185	}
	186	kfree(prcm_irq_chips);
	187	prcm_irq_chips = NULL;
	188	}
	189
91285b6f TK	190	kfree(prcm_irq_setup->saved_mask);
	191	prcm_irq_setup->saved_mask = NULL;
	192
0a84a91c TK	193	kfree(prcm_irq_setup->priority_mask);
	194	prcm_irq_setup->priority_mask = NULL;
	195
	196	irq_set_chained_handler(prcm_irq_setup->irq, NULL);
	197
	198	if (prcm_irq_setup->base_irq > 0)
	199	irq_free_descs(prcm_irq_setup->base_irq,
	200	prcm_irq_setup->nr_regs * 32);
	201	prcm_irq_setup->base_irq = 0;
	202	}
	203
91285b6f TK	204	void omap_prcm_irq_prepare(void)
	205	{
	206	prcm_irq_setup->suspended = true;
	207	}
	208
	209	void omap_prcm_irq_complete(void)
	210	{
	211	prcm_irq_setup->suspended = false;
	212
	213	/* If we have not saved the masks, do not attempt to restore */
	214	if (!prcm_irq_setup->suspend_save_flag)
	215	return;
	216
	217	prcm_irq_setup->suspend_save_flag = false;
	218
	219	/*
	220	* Re-enable all masked PRCM irq sources, this causes the PRCM
	221	* interrupt to fire immediately if the events were masked
	222	* previously in the chain handler
	223	*/
	224	prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
	225	}
	226
0a84a91c TK	227	/**
	228	* omap_prcm_register_chain_handler - initializes the prcm chained interrupt
	229	* handler based on provided parameters
	230	* @irq_setup: hardware data about the underlying PRM/PRCM
	231	*
	232	* Set up the PRCM chained interrupt handler on the PRCM IRQ. Sets up
	233	* one generic IRQ chip per PRM interrupt status/enable register pair.
	234	* Returns 0 upon success, -EINVAL if called twice or if invalid
	235	* arguments are passed, or -ENOMEM on any other error.
	236	*/
	237	int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
	238	{
eeb3711b	239	int nr_regs;
0a84a91c TK	240	u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
	241	int offset, i;
	242	struct irq_chip_generic *gc;
	243	struct irq_chip_type *ct;
	244
	245	if (!irq_setup)
	246	return -EINVAL;
	247
eeb3711b PW	248	nr_regs = irq_setup->nr_regs;
eeb3711b PW	249
0a84a91c TK	250	if (prcm_irq_setup) {
	251	pr_err("PRCM: already initialized; won't reinitialize\n");
	252	return -EINVAL;
	253	}
	254
	255	if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
	256	pr_err("PRCM: nr_regs too large\n");
	257	return -EINVAL;
	258	}
	259
	260	prcm_irq_setup = irq_setup;
	261
	262	prcm_irq_chips = kzalloc(sizeof(void ) nr_regs, GFP_KERNEL);
91285b6f	263	prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL);
0a84a91c TK	264	prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
	265	GFP_KERNEL);
	266
91285b6f TK	267	if (!prcm_irq_chips \|\| !prcm_irq_setup->saved_mask \|\|
91285b6f TK	268	!prcm_irq_setup->priority_mask) {
0a84a91c TK	269	pr_err("PRCM: kzalloc failed\n");
	270	goto err;
	271	}
	272
	273	memset(mask, 0, sizeof(mask));
	274
	275	for (i = 0; i < irq_setup->nr_irqs; i++) {
	276	offset = irq_setup->irqs[i].offset;
	277	mask[offset >> 5] \|= 1 << (offset & 0x1f);
	278	if (irq_setup->irqs[i].priority)
	279	irq_setup->priority_mask[offset >> 5] \|=
	280	1 << (offset & 0x1f);
	281	}
	282
	283	irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);
	284
	285	irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
	286	0);
	287
	288	if (irq_setup->base_irq < 0) {
	289	pr_err("PRCM: failed to allocate irq descs: %d\n",
	290	irq_setup->base_irq);
	291	goto err;
	292	}
	293
4ba7c3c3	294	for (i = 0; i < irq_setup->nr_regs; i++) {
0a84a91c TK	295	gc = irq_alloc_generic_chip("PRCM", 1,
	296	irq_setup->base_irq + i * 32, prm_base,
	297	handle_level_irq);
	298
	299	if (!gc) {
	300	pr_err("PRCM: failed to allocate generic chip\n");
	301	goto err;
	302	}
	303	ct = gc->chip_types;
	304	ct->chip.irq_ack = irq_gc_ack_set_bit;
	305	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	306	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	307
	308	ct->regs.ack = irq_setup->ack + i * 4;
	309	ct->regs.mask = irq_setup->mask + i * 4;
	310
	311	irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
	312	prcm_irq_chips[i] = gc;
	313	}
	314
	315	return 0;
	316
	317	err:
	318	omap_prcm_irq_cleanup();
	319	return -ENOMEM;
	320	}