Commit | Line | Data |
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0a84a91c TK |
1 | /* |
2 | * OMAP2+ common Power & Reset Management (PRM) IP block functions | |
3 | * | |
4 | * Copyright (C) 2011 Texas Instruments, Inc. | |
5 | * Tero Kristo <t-kristo@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * | |
12 | * For historical purposes, the API used to configure the PRM | |
13 | * interrupt handler refers to it as the "PRCM interrupt." The | |
14 | * underlying registers are located in the PRM on OMAP3/4. | |
15 | * | |
16 | * XXX This code should eventually be moved to a PRM driver. | |
17 | */ | |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/irq.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/slab.h> | |
26 | ||
0a84a91c | 27 | #include "prm2xxx_3xxx.h" |
2bb2a5d3 PW |
28 | #include "prm2xxx.h" |
29 | #include "prm3xxx.h" | |
0a84a91c | 30 | #include "prm44xx.h" |
d9a16f9a | 31 | #include "common.h" |
0a84a91c TK |
32 | |
33 | /* | |
34 | * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs | |
35 | * XXX this is technically not needed, since | |
36 | * omap_prcm_register_chain_handler() could allocate this based on the | |
37 | * actual amount of memory needed for the SoC | |
38 | */ | |
39 | #define OMAP_PRCM_MAX_NR_PENDING_REG 2 | |
40 | ||
41 | /* | |
42 | * prcm_irq_chips: an array of all of the "generic IRQ chips" in use | |
43 | * by the PRCM interrupt handler code. There will be one 'chip' per | |
44 | * PRM_{IRQSTATUS,IRQENABLE}_MPU register pair. (So OMAP3 will have | |
45 | * one "chip" and OMAP4 will have two.) | |
46 | */ | |
47 | static struct irq_chip_generic **prcm_irq_chips; | |
48 | ||
49 | /* | |
50 | * prcm_irq_setup: the PRCM IRQ parameters for the hardware the code | |
51 | * is currently running on. Defined and passed by initialization code | |
52 | * that calls omap_prcm_register_chain_handler(). | |
53 | */ | |
54 | static struct omap_prcm_irq_setup *prcm_irq_setup; | |
55 | ||
d9a16f9a PW |
56 | /* prm_base: base virtual address of the PRM IP block */ |
57 | void __iomem *prm_base; | |
58 | ||
e24c3573 PW |
59 | /* |
60 | * prm_ll_data: function pointers to SoC-specific implementations of | |
61 | * common PRM functions | |
62 | */ | |
63 | static struct prm_ll_data null_prm_ll_data; | |
64 | static struct prm_ll_data *prm_ll_data = &null_prm_ll_data; | |
65 | ||
0a84a91c TK |
66 | /* Private functions */ |
67 | ||
68 | /* | |
69 | * Move priority events from events to priority_events array | |
70 | */ | |
71 | static void omap_prcm_events_filter_priority(unsigned long *events, | |
72 | unsigned long *priority_events) | |
73 | { | |
74 | int i; | |
75 | ||
76 | for (i = 0; i < prcm_irq_setup->nr_regs; i++) { | |
77 | priority_events[i] = | |
78 | events[i] & prcm_irq_setup->priority_mask[i]; | |
79 | events[i] ^= priority_events[i]; | |
80 | } | |
81 | } | |
82 | ||
83 | /* | |
84 | * PRCM Interrupt Handler | |
85 | * | |
86 | * This is a common handler for the OMAP PRCM interrupts. Pending | |
87 | * interrupts are detected by a call to prcm_pending_events and | |
88 | * dispatched accordingly. Clearing of the wakeup events should be | |
89 | * done by the SoC specific individual handlers. | |
90 | */ | |
91 | static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc) | |
92 | { | |
93 | unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG]; | |
94 | unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG]; | |
95 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
96 | unsigned int virtirq; | |
b56f2cb7 | 97 | int nr_irq = prcm_irq_setup->nr_regs * 32; |
0a84a91c | 98 | |
91285b6f TK |
99 | /* |
100 | * If we are suspended, mask all interrupts from PRCM level, | |
101 | * this does not ack them, and they will be pending until we | |
102 | * re-enable the interrupts, at which point the | |
103 | * omap_prcm_irq_handler will be executed again. The | |
104 | * _save_and_clear_irqen() function must ensure that the PRM | |
105 | * write to disable all IRQs has reached the PRM before | |
106 | * returning, or spurious PRCM interrupts may occur during | |
107 | * suspend. | |
108 | */ | |
109 | if (prcm_irq_setup->suspended) { | |
110 | prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask); | |
111 | prcm_irq_setup->suspend_save_flag = true; | |
112 | } | |
113 | ||
0a84a91c TK |
114 | /* |
115 | * Loop until all pending irqs are handled, since | |
116 | * generic_handle_irq() can cause new irqs to come | |
117 | */ | |
91285b6f | 118 | while (!prcm_irq_setup->suspended) { |
0a84a91c TK |
119 | prcm_irq_setup->read_pending_irqs(pending); |
120 | ||
121 | /* No bit set, then all IRQs are handled */ | |
b56f2cb7 | 122 | if (find_first_bit(pending, nr_irq) >= nr_irq) |
0a84a91c TK |
123 | break; |
124 | ||
125 | omap_prcm_events_filter_priority(pending, priority_pending); | |
126 | ||
127 | /* | |
128 | * Loop on all currently pending irqs so that new irqs | |
129 | * cannot starve previously pending irqs | |
130 | */ | |
131 | ||
132 | /* Serve priority events first */ | |
b56f2cb7 | 133 | for_each_set_bit(virtirq, priority_pending, nr_irq) |
0a84a91c TK |
134 | generic_handle_irq(prcm_irq_setup->base_irq + virtirq); |
135 | ||
136 | /* Serve normal events next */ | |
b56f2cb7 | 137 | for_each_set_bit(virtirq, pending, nr_irq) |
0a84a91c TK |
138 | generic_handle_irq(prcm_irq_setup->base_irq + virtirq); |
139 | } | |
140 | if (chip->irq_ack) | |
141 | chip->irq_ack(&desc->irq_data); | |
142 | if (chip->irq_eoi) | |
143 | chip->irq_eoi(&desc->irq_data); | |
144 | chip->irq_unmask(&desc->irq_data); | |
145 | ||
146 | prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */ | |
147 | } | |
148 | ||
149 | /* Public functions */ | |
150 | ||
151 | /** | |
152 | * omap_prcm_event_to_irq - given a PRCM event name, returns the | |
153 | * corresponding IRQ on which the handler should be registered | |
154 | * @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq | |
155 | * | |
156 | * Returns the Linux internal IRQ ID corresponding to @name upon success, | |
157 | * or -ENOENT upon failure. | |
158 | */ | |
159 | int omap_prcm_event_to_irq(const char *name) | |
160 | { | |
161 | int i; | |
162 | ||
163 | if (!prcm_irq_setup || !name) | |
164 | return -ENOENT; | |
165 | ||
166 | for (i = 0; i < prcm_irq_setup->nr_irqs; i++) | |
167 | if (!strcmp(prcm_irq_setup->irqs[i].name, name)) | |
168 | return prcm_irq_setup->base_irq + | |
169 | prcm_irq_setup->irqs[i].offset; | |
170 | ||
171 | return -ENOENT; | |
172 | } | |
173 | ||
174 | /** | |
175 | * omap_prcm_irq_cleanup - reverses memory allocated and other steps | |
176 | * done by omap_prcm_register_chain_handler() | |
177 | * | |
178 | * No return value. | |
179 | */ | |
180 | void omap_prcm_irq_cleanup(void) | |
181 | { | |
182 | int i; | |
183 | ||
184 | if (!prcm_irq_setup) { | |
185 | pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n"); | |
186 | return; | |
187 | } | |
188 | ||
189 | if (prcm_irq_chips) { | |
190 | for (i = 0; i < prcm_irq_setup->nr_regs; i++) { | |
191 | if (prcm_irq_chips[i]) | |
192 | irq_remove_generic_chip(prcm_irq_chips[i], | |
193 | 0xffffffff, 0, 0); | |
194 | prcm_irq_chips[i] = NULL; | |
195 | } | |
196 | kfree(prcm_irq_chips); | |
197 | prcm_irq_chips = NULL; | |
198 | } | |
199 | ||
91285b6f TK |
200 | kfree(prcm_irq_setup->saved_mask); |
201 | prcm_irq_setup->saved_mask = NULL; | |
202 | ||
0a84a91c TK |
203 | kfree(prcm_irq_setup->priority_mask); |
204 | prcm_irq_setup->priority_mask = NULL; | |
205 | ||
206 | irq_set_chained_handler(prcm_irq_setup->irq, NULL); | |
207 | ||
208 | if (prcm_irq_setup->base_irq > 0) | |
209 | irq_free_descs(prcm_irq_setup->base_irq, | |
210 | prcm_irq_setup->nr_regs * 32); | |
211 | prcm_irq_setup->base_irq = 0; | |
212 | } | |
213 | ||
91285b6f TK |
214 | void omap_prcm_irq_prepare(void) |
215 | { | |
216 | prcm_irq_setup->suspended = true; | |
217 | } | |
218 | ||
219 | void omap_prcm_irq_complete(void) | |
220 | { | |
221 | prcm_irq_setup->suspended = false; | |
222 | ||
223 | /* If we have not saved the masks, do not attempt to restore */ | |
224 | if (!prcm_irq_setup->suspend_save_flag) | |
225 | return; | |
226 | ||
227 | prcm_irq_setup->suspend_save_flag = false; | |
228 | ||
229 | /* | |
230 | * Re-enable all masked PRCM irq sources, this causes the PRCM | |
231 | * interrupt to fire immediately if the events were masked | |
232 | * previously in the chain handler | |
233 | */ | |
234 | prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask); | |
235 | } | |
236 | ||
0a84a91c TK |
237 | /** |
238 | * omap_prcm_register_chain_handler - initializes the prcm chained interrupt | |
239 | * handler based on provided parameters | |
240 | * @irq_setup: hardware data about the underlying PRM/PRCM | |
241 | * | |
242 | * Set up the PRCM chained interrupt handler on the PRCM IRQ. Sets up | |
243 | * one generic IRQ chip per PRM interrupt status/enable register pair. | |
244 | * Returns 0 upon success, -EINVAL if called twice or if invalid | |
245 | * arguments are passed, or -ENOMEM on any other error. | |
246 | */ | |
247 | int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup) | |
248 | { | |
eeb3711b | 249 | int nr_regs; |
0a84a91c TK |
250 | u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG]; |
251 | int offset, i; | |
252 | struct irq_chip_generic *gc; | |
253 | struct irq_chip_type *ct; | |
254 | ||
255 | if (!irq_setup) | |
256 | return -EINVAL; | |
257 | ||
eeb3711b PW |
258 | nr_regs = irq_setup->nr_regs; |
259 | ||
0a84a91c TK |
260 | if (prcm_irq_setup) { |
261 | pr_err("PRCM: already initialized; won't reinitialize\n"); | |
262 | return -EINVAL; | |
263 | } | |
264 | ||
265 | if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) { | |
266 | pr_err("PRCM: nr_regs too large\n"); | |
267 | return -EINVAL; | |
268 | } | |
269 | ||
270 | prcm_irq_setup = irq_setup; | |
271 | ||
272 | prcm_irq_chips = kzalloc(sizeof(void *) * nr_regs, GFP_KERNEL); | |
91285b6f | 273 | prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL); |
0a84a91c TK |
274 | prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs, |
275 | GFP_KERNEL); | |
276 | ||
91285b6f TK |
277 | if (!prcm_irq_chips || !prcm_irq_setup->saved_mask || |
278 | !prcm_irq_setup->priority_mask) { | |
0a84a91c TK |
279 | pr_err("PRCM: kzalloc failed\n"); |
280 | goto err; | |
281 | } | |
282 | ||
283 | memset(mask, 0, sizeof(mask)); | |
284 | ||
285 | for (i = 0; i < irq_setup->nr_irqs; i++) { | |
286 | offset = irq_setup->irqs[i].offset; | |
287 | mask[offset >> 5] |= 1 << (offset & 0x1f); | |
288 | if (irq_setup->irqs[i].priority) | |
289 | irq_setup->priority_mask[offset >> 5] |= | |
290 | 1 << (offset & 0x1f); | |
291 | } | |
292 | ||
293 | irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler); | |
294 | ||
295 | irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32, | |
296 | 0); | |
297 | ||
298 | if (irq_setup->base_irq < 0) { | |
299 | pr_err("PRCM: failed to allocate irq descs: %d\n", | |
300 | irq_setup->base_irq); | |
301 | goto err; | |
302 | } | |
303 | ||
4ba7c3c3 | 304 | for (i = 0; i < irq_setup->nr_regs; i++) { |
0a84a91c TK |
305 | gc = irq_alloc_generic_chip("PRCM", 1, |
306 | irq_setup->base_irq + i * 32, prm_base, | |
307 | handle_level_irq); | |
308 | ||
309 | if (!gc) { | |
310 | pr_err("PRCM: failed to allocate generic chip\n"); | |
311 | goto err; | |
312 | } | |
313 | ct = gc->chip_types; | |
314 | ct->chip.irq_ack = irq_gc_ack_set_bit; | |
315 | ct->chip.irq_mask = irq_gc_mask_clr_bit; | |
316 | ct->chip.irq_unmask = irq_gc_mask_set_bit; | |
317 | ||
318 | ct->regs.ack = irq_setup->ack + i * 4; | |
319 | ct->regs.mask = irq_setup->mask + i * 4; | |
320 | ||
321 | irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0); | |
322 | prcm_irq_chips[i] = gc; | |
323 | } | |
324 | ||
325 | return 0; | |
326 | ||
327 | err: | |
328 | omap_prcm_irq_cleanup(); | |
329 | return -ENOMEM; | |
330 | } | |
3f4990f4 | 331 | |
d9a16f9a PW |
332 | /** |
333 | * omap2_set_globals_prm - set the PRM base address (for early use) | |
334 | * @prm: PRM base virtual address | |
335 | * | |
336 | * XXX Will be replaced when the PRM/CM drivers are completed. | |
3f4990f4 | 337 | */ |
d9a16f9a | 338 | void __init omap2_set_globals_prm(void __iomem *prm) |
3f4990f4 | 339 | { |
d9a16f9a | 340 | prm_base = prm; |
3f4990f4 S |
341 | } |
342 | ||
2bb2a5d3 PW |
343 | /** |
344 | * prm_read_reset_sources - return the sources of the SoC's last reset | |
345 | * | |
346 | * Return a u32 bitmask representing the reset sources that caused the | |
347 | * SoC to reset. The low-level per-SoC functions called by this | |
348 | * function remap the SoC-specific reset source bits into an | |
349 | * OMAP-common set of reset source bits, defined in | |
350 | * arch/arm/mach-omap2/prm.h. Returns the standardized reset source | |
351 | * u32 bitmask from the hardware upon success, or returns (1 << | |
352 | * OMAP_UNKNOWN_RST_SRC_ID_SHIFT) if no low-level read_reset_sources() | |
353 | * function was registered. | |
3f4990f4 | 354 | */ |
2bb2a5d3 | 355 | u32 prm_read_reset_sources(void) |
3f4990f4 | 356 | { |
2bb2a5d3 | 357 | u32 ret = 1 << OMAP_UNKNOWN_RST_SRC_ID_SHIFT; |
3f4990f4 | 358 | |
2bb2a5d3 PW |
359 | if (prm_ll_data->read_reset_sources) |
360 | ret = prm_ll_data->read_reset_sources(); | |
361 | else | |
362 | WARN_ONCE(1, "prm: %s: no mapping function defined for reset sources\n", __func__); | |
3f4990f4 | 363 | |
2bb2a5d3 | 364 | return ret; |
3f4990f4 S |
365 | } |
366 | ||
e6d3a8b0 RN |
367 | /** |
368 | * prm_was_any_context_lost_old - was device context lost? (old API) | |
369 | * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION) | |
370 | * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST) | |
371 | * @idx: CONTEXT register offset | |
372 | * | |
373 | * Return 1 if any bits were set in the *_CONTEXT_* register | |
374 | * identified by (@part, @inst, @idx), which means that some context | |
375 | * was lost for that module; otherwise, return 0. XXX Deprecated; | |
376 | * callers need to use a less-SoC-dependent way to identify hardware | |
377 | * IP blocks. | |
378 | */ | |
379 | bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx) | |
380 | { | |
381 | bool ret = true; | |
382 | ||
383 | if (prm_ll_data->was_any_context_lost_old) | |
384 | ret = prm_ll_data->was_any_context_lost_old(part, inst, idx); | |
385 | else | |
386 | WARN_ONCE(1, "prm: %s: no mapping function defined\n", | |
387 | __func__); | |
388 | ||
389 | return ret; | |
390 | } | |
391 | ||
392 | /** | |
393 | * prm_clear_context_lost_flags_old - clear context loss flags (old API) | |
394 | * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION) | |
395 | * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST) | |
396 | * @idx: CONTEXT register offset | |
397 | * | |
398 | * Clear hardware context loss bits for the module identified by | |
399 | * (@part, @inst, @idx). No return value. XXX Deprecated; callers | |
400 | * need to use a less-SoC-dependent way to identify hardware IP | |
401 | * blocks. | |
402 | */ | |
403 | void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx) | |
404 | { | |
405 | if (prm_ll_data->clear_context_loss_flags_old) | |
406 | prm_ll_data->clear_context_loss_flags_old(part, inst, idx); | |
407 | else | |
408 | WARN_ONCE(1, "prm: %s: no mapping function defined\n", | |
409 | __func__); | |
410 | } | |
411 | ||
e24c3573 PW |
412 | /** |
413 | * prm_register - register per-SoC low-level data with the PRM | |
414 | * @pld: low-level per-SoC OMAP PRM data & function pointers to register | |
415 | * | |
416 | * Register per-SoC low-level OMAP PRM data and function pointers with | |
417 | * the OMAP PRM common interface. The caller must keep the data | |
418 | * pointed to by @pld valid until it calls prm_unregister() and | |
419 | * it returns successfully. Returns 0 upon success, -EINVAL if @pld | |
420 | * is NULL, or -EEXIST if prm_register() has already been called | |
421 | * without an intervening prm_unregister(). | |
422 | */ | |
423 | int prm_register(struct prm_ll_data *pld) | |
3f4990f4 | 424 | { |
e24c3573 PW |
425 | if (!pld) |
426 | return -EINVAL; | |
3f4990f4 | 427 | |
e24c3573 PW |
428 | if (prm_ll_data != &null_prm_ll_data) |
429 | return -EEXIST; | |
3f4990f4 | 430 | |
e24c3573 | 431 | prm_ll_data = pld; |
3f4990f4 | 432 | |
3f4990f4 S |
433 | return 0; |
434 | } | |
435 | ||
e24c3573 PW |
436 | /** |
437 | * prm_unregister - unregister per-SoC low-level data & function pointers | |
438 | * @pld: low-level per-SoC OMAP PRM data & function pointers to unregister | |
439 | * | |
440 | * Unregister per-SoC low-level OMAP PRM data and function pointers | |
441 | * that were previously registered with prm_register(). The | |
442 | * caller may not destroy any of the data pointed to by @pld until | |
443 | * this function returns successfully. Returns 0 upon success, or | |
444 | * -EINVAL if @pld is NULL or if @pld does not match the struct | |
445 | * prm_ll_data * previously registered by prm_register(). | |
446 | */ | |
447 | int prm_unregister(struct prm_ll_data *pld) | |
3f4990f4 | 448 | { |
e24c3573 PW |
449 | if (!pld || prm_ll_data != pld) |
450 | return -EINVAL; | |
451 | ||
452 | prm_ll_data = &null_prm_ll_data; | |
3f4990f4 | 453 | |
3f4990f4 S |
454 | return 0; |
455 | } |