[deliverable/linux.git] / arch / arm / mach-omap2 / prm_common.c

/*
 * OMAP2+ common Power & Reset Management (PRM) IP block functions
 *
 * Copyright (C) 2011 Texas Instruments, Inc.
 * Tero Kristo <t-kristo@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *
 * For historical purposes, the API used to configure the PRM
 * interrupt handler refers to it as the "PRCM interrupt."  The
 * underlying registers are located in the PRM on OMAP3/4.
 *
 * XXX This code should eventually be moved to a PRM driver.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/slab.h>

#include "soc.h"
#include "prm2xxx_3xxx.h"
#include "prm2xxx.h"
#include "prm3xxx.h"
#include "prm44xx.h"
#include "common.h"

/*
 * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
 * XXX this is technically not needed, since
 * omap_prcm_register_chain_handler() could allocate this based on the
 * actual amount of memory needed for the SoC
 */
#define OMAP_PRCM_MAX_NR_PENDING_REG		2

/*
 * prcm_irq_chips: an array of all of the "generic IRQ chips" in use
 * by the PRCM interrupt handler code.  There will be one 'chip' per
 * PRM_{IRQSTATUS,IRQENABLE}_MPU register pair.  (So OMAP3 will have
 * one "chip" and OMAP4 will have two.)
 */
static struct irq_chip_generic **prcm_irq_chips;

/*
 * prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
 * is currently running on.  Defined and passed by initialization code
 * that calls omap_prcm_register_chain_handler().
 */
static struct omap_prcm_irq_setup *prcm_irq_setup;

/* prm_base: base virtual address of the PRM IP block */
void __iomem *prm_base;

/*
 * prm_ll_data: function pointers to SoC-specific implementations of
 * common PRM functions
 */
static struct prm_ll_data null_prm_ll_data;
static struct prm_ll_data *prm_ll_data = &null_prm_ll_data;

/* Private functions */

/*
 * Move priority events from events to priority_events array
 */
static void omap_prcm_events_filter_priority(unsigned long *events,
	unsigned long *priority_events)
{
	int i;

	for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
		priority_events[i] =
			events[i] & prcm_irq_setup->priority_mask[i];
		events[i] ^= priority_events[i];
	}
}

/*
 * PRCM Interrupt Handler
 *
 * This is a common handler for the OMAP PRCM interrupts. Pending
 * interrupts are detected by a call to prcm_pending_events and
 * dispatched accordingly. Clearing of the wakeup events should be
 * done by the SoC specific individual handlers.
 */
static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
	unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned int virtirq;
	int nr_irq = prcm_irq_setup->nr_regs * 32;

	/*
	 * If we are suspended, mask all interrupts from PRCM level,
	 * this does not ack them, and they will be pending until we
	 * re-enable the interrupts, at which point the
	 * omap_prcm_irq_handler will be executed again.  The
	 * _save_and_clear_irqen() function must ensure that the PRM
	 * write to disable all IRQs has reached the PRM before
	 * returning, or spurious PRCM interrupts may occur during
	 * suspend.
	 */
	if (prcm_irq_setup->suspended) {
		prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
		prcm_irq_setup->suspend_save_flag = true;
	}

	/*
	 * Loop until all pending irqs are handled, since
	 * generic_handle_irq() can cause new irqs to come
	 */
	while (!prcm_irq_setup->suspended) {
		prcm_irq_setup->read_pending_irqs(pending);

		/* No bit set, then all IRQs are handled */
		if (find_first_bit(pending, nr_irq) >= nr_irq)
			break;

		omap_prcm_events_filter_priority(pending, priority_pending);

		/*
		 * Loop on all currently pending irqs so that new irqs
		 * cannot starve previously pending irqs
		 */

		/* Serve priority events first */
		for_each_set_bit(virtirq, priority_pending, nr_irq)
			generic_handle_irq(prcm_irq_setup->base_irq + virtirq);

		/* Serve normal events next */
		for_each_set_bit(virtirq, pending, nr_irq)
			generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
	}
	if (chip->irq_ack)
		chip->irq_ack(&desc->irq_data);
	if (chip->irq_eoi)
		chip->irq_eoi(&desc->irq_data);
	chip->irq_unmask(&desc->irq_data);

	prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
}

/* Public functions */

/**
 * omap_prcm_event_to_irq - given a PRCM event name, returns the
 * corresponding IRQ on which the handler should be registered
 * @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
 *
 * Returns the Linux internal IRQ ID corresponding to @name upon success,
 * or -ENOENT upon failure.
 */
int omap_prcm_event_to_irq(const char *name)
{
	int i;

	if (!prcm_irq_setup || !name)
		return -ENOENT;

	for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
		if (!strcmp(prcm_irq_setup->irqs[i].name, name))
			return prcm_irq_setup->base_irq +
				prcm_irq_setup->irqs[i].offset;

	return -ENOENT;
}

/**
 * omap_prcm_irq_cleanup - reverses memory allocated and other steps
 * done by omap_prcm_register_chain_handler()
 *
 * No return value.
 */
void omap_prcm_irq_cleanup(void)
{
	int i;

	if (!prcm_irq_setup) {
		pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
		return;
	}

	if (prcm_irq_chips) {
		for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
			if (prcm_irq_chips[i])
				irq_remove_generic_chip(prcm_irq_chips[i],
					0xffffffff, 0, 0);
			prcm_irq_chips[i] = NULL;
		}
		kfree(prcm_irq_chips);
		prcm_irq_chips = NULL;
	}

	kfree(prcm_irq_setup->saved_mask);
	prcm_irq_setup->saved_mask = NULL;

	kfree(prcm_irq_setup->priority_mask);
	prcm_irq_setup->priority_mask = NULL;

	irq_set_chained_handler(prcm_irq_setup->irq, NULL);

	if (prcm_irq_setup->base_irq > 0)
		irq_free_descs(prcm_irq_setup->base_irq,
			prcm_irq_setup->nr_regs * 32);
	prcm_irq_setup->base_irq = 0;
}

void omap_prcm_irq_prepare(void)
{
	prcm_irq_setup->suspended = true;
}

void omap_prcm_irq_complete(void)
{
	prcm_irq_setup->suspended = false;

	/* If we have not saved the masks, do not attempt to restore */
	if (!prcm_irq_setup->suspend_save_flag)
		return;

	prcm_irq_setup->suspend_save_flag = false;

	/*
	 * Re-enable all masked PRCM irq sources, this causes the PRCM
	 * interrupt to fire immediately if the events were masked
	 * previously in the chain handler
	 */
	prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
}

/**
 * omap_prcm_register_chain_handler - initializes the prcm chained interrupt
 * handler based on provided parameters
 * @irq_setup: hardware data about the underlying PRM/PRCM
 *
 * Set up the PRCM chained interrupt handler on the PRCM IRQ.  Sets up
 * one generic IRQ chip per PRM interrupt status/enable register pair.
 * Returns 0 upon success, -EINVAL if called twice or if invalid
 * arguments are passed, or -ENOMEM on any other error.
 */
int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
{
	int nr_regs;
	u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
	int offset, i;
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	if (!irq_setup)
		return -EINVAL;

	nr_regs = irq_setup->nr_regs;

	if (prcm_irq_setup) {
		pr_err("PRCM: already initialized; won't reinitialize\n");
		return -EINVAL;
	}

	if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
		pr_err("PRCM: nr_regs too large\n");
		return -EINVAL;
	}

	prcm_irq_setup = irq_setup;

	prcm_irq_chips = kzalloc(sizeof(void *) * nr_regs, GFP_KERNEL);
	prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL);
	prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
		GFP_KERNEL);

	if (!prcm_irq_chips || !prcm_irq_setup->saved_mask ||
	    !prcm_irq_setup->priority_mask) {
		pr_err("PRCM: kzalloc failed\n");
		goto err;
	}

	memset(mask, 0, sizeof(mask));

	for (i = 0; i < irq_setup->nr_irqs; i++) {
		offset = irq_setup->irqs[i].offset;
		mask[offset >> 5] |= 1 << (offset & 0x1f);
		if (irq_setup->irqs[i].priority)
			irq_setup->priority_mask[offset >> 5] |=
				1 << (offset & 0x1f);
	}

	irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);

	irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
		0);

	if (irq_setup->base_irq < 0) {
		pr_err("PRCM: failed to allocate irq descs: %d\n",
			irq_setup->base_irq);
		goto err;
	}

	for (i = 0; i < irq_setup->nr_regs; i++) {
		gc = irq_alloc_generic_chip("PRCM", 1,
			irq_setup->base_irq + i * 32, prm_base,
			handle_level_irq);

		if (!gc) {
			pr_err("PRCM: failed to allocate generic chip\n");
			goto err;
		}
		ct = gc->chip_types;
		ct->chip.irq_ack = irq_gc_ack_set_bit;
		ct->chip.irq_mask = irq_gc_mask_clr_bit;
		ct->chip.irq_unmask = irq_gc_mask_set_bit;

		ct->regs.ack = irq_setup->ack + i * 4;
		ct->regs.mask = irq_setup->mask + i * 4;

		irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
		prcm_irq_chips[i] = gc;
	}

	if (of_have_populated_dt()) {
		int irq = omap_prcm_event_to_irq("io");
		if (cpu_is_omap34xx())
			omap_pcs_legacy_init(irq,
				omap3xxx_prm_reconfigure_io_chain);
		else
			omap_pcs_legacy_init(irq,
				omap44xx_prm_reconfigure_io_chain);
	}

	return 0;

err:
	omap_prcm_irq_cleanup();
	return -ENOMEM;
}

/**
 * omap2_set_globals_prm - set the PRM base address (for early use)
 * @prm: PRM base virtual address
 *
 * XXX Will be replaced when the PRM/CM drivers are completed.
 */
void __init omap2_set_globals_prm(void __iomem *prm)
{
	prm_base = prm;
}

/**
 * prm_read_reset_sources - return the sources of the SoC's last reset
 *
 * Return a u32 bitmask representing the reset sources that caused the
 * SoC to reset.  The low-level per-SoC functions called by this
 * function remap the SoC-specific reset source bits into an
 * OMAP-common set of reset source bits, defined in
 * arch/arm/mach-omap2/prm.h.  Returns the standardized reset source
 * u32 bitmask from the hardware upon success, or returns (1 <<
 * OMAP_UNKNOWN_RST_SRC_ID_SHIFT) if no low-level read_reset_sources()
 * function was registered.
 */
u32 prm_read_reset_sources(void)
{
	u32 ret = 1 << OMAP_UNKNOWN_RST_SRC_ID_SHIFT;

	if (prm_ll_data->read_reset_sources)
		ret = prm_ll_data->read_reset_sources();
	else
		WARN_ONCE(1, "prm: %s: no mapping function defined for reset sources\n", __func__);

	return ret;
}

/**
 * prm_was_any_context_lost_old - was device context lost? (old API)
 * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
 * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
 * @idx: CONTEXT register offset
 *
 * Return 1 if any bits were set in the *_CONTEXT_* register
 * identified by (@part, @inst, @idx), which means that some context
 * was lost for that module; otherwise, return 0.  XXX Deprecated;
 * callers need to use a less-SoC-dependent way to identify hardware
 * IP blocks.
 */
bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx)
{
	bool ret = true;

	if (prm_ll_data->was_any_context_lost_old)
		ret = prm_ll_data->was_any_context_lost_old(part, inst, idx);
	else
		WARN_ONCE(1, "prm: %s: no mapping function defined\n",
			  __func__);

	return ret;
}

/**
 * prm_clear_context_lost_flags_old - clear context loss flags (old API)
 * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
 * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
 * @idx: CONTEXT register offset
 *
 * Clear hardware context loss bits for the module identified by
 * (@part, @inst, @idx).  No return value.  XXX Deprecated; callers
 * need to use a less-SoC-dependent way to identify hardware IP
 * blocks.
 */
void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx)
{
	if (prm_ll_data->clear_context_loss_flags_old)
		prm_ll_data->clear_context_loss_flags_old(part, inst, idx);
	else
		WARN_ONCE(1, "prm: %s: no mapping function defined\n",
			  __func__);
}

/**
 * prm_register - register per-SoC low-level data with the PRM
 * @pld: low-level per-SoC OMAP PRM data & function pointers to register
 *
 * Register per-SoC low-level OMAP PRM data and function pointers with
 * the OMAP PRM common interface.  The caller must keep the data
 * pointed to by @pld valid until it calls prm_unregister() and
 * it returns successfully.  Returns 0 upon success, -EINVAL if @pld
 * is NULL, or -EEXIST if prm_register() has already been called
 * without an intervening prm_unregister().
 */
int prm_register(struct prm_ll_data *pld)
{
	if (!pld)
		return -EINVAL;

	if (prm_ll_data != &null_prm_ll_data)
		return -EEXIST;

	prm_ll_data = pld;

	return 0;
}

/**
 * prm_unregister - unregister per-SoC low-level data & function pointers
 * @pld: low-level per-SoC OMAP PRM data & function pointers to unregister
 *
 * Unregister per-SoC low-level OMAP PRM data and function pointers
 * that were previously registered with prm_register().  The
 * caller may not destroy any of the data pointed to by @pld until
 * this function returns successfully.  Returns 0 upon success, or
 * -EINVAL if @pld is NULL or if @pld does not match the struct
 * prm_ll_data * previously registered by prm_register().
 */
int prm_unregister(struct prm_ll_data *pld)
{
	if (!pld || prm_ll_data != pld)
		return -EINVAL;

	prm_ll_data = &null_prm_ll_data;

	return 0;
}
Commit	Line	Data
0a84a91c TK	1	/*
	2	* OMAP2+ common Power & Reset Management (PRM) IP block functions
	3	*
	4	* Copyright (C) 2011 Texas Instruments, Inc.
	5	* Tero Kristo <t-kristo@ti.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	*
	12	* For historical purposes, the API used to configure the PRM
	13	* interrupt handler refers to it as the "PRCM interrupt." The
	14	* underlying registers are located in the PRM on OMAP3/4.
	15	*
	16	* XXX This code should eventually be moved to a PRM driver.
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/init.h>
	22	#include <linux/io.h>
	23	#include <linux/irq.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/slab.h>
	26
30a69ef7	27	#include "soc.h"
0a84a91c	28	#include "prm2xxx_3xxx.h"
2bb2a5d3 PW	29	#include "prm2xxx.h"
2bb2a5d3 PW	30	#include "prm3xxx.h"
0a84a91c	31	#include "prm44xx.h"
d9a16f9a	32	#include "common.h"
0a84a91c TK	33
	34	/*
	35	* OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
	36	* XXX this is technically not needed, since
	37	* omap_prcm_register_chain_handler() could allocate this based on the
	38	* actual amount of memory needed for the SoC
	39	*/
	40	#define OMAP_PRCM_MAX_NR_PENDING_REG 2
	41
	42	/*
	43	* prcm_irq_chips: an array of all of the "generic IRQ chips" in use
	44	* by the PRCM interrupt handler code. There will be one 'chip' per
	45	* PRM_{IRQSTATUS,IRQENABLE}_MPU register pair. (So OMAP3 will have
	46	* one "chip" and OMAP4 will have two.)
	47	*/
	48	static struct irq_chip_generic **prcm_irq_chips;
	49
	50	/*
	51	* prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
	52	* is currently running on. Defined and passed by initialization code
	53	* that calls omap_prcm_register_chain_handler().
	54	*/
	55	static struct omap_prcm_irq_setup *prcm_irq_setup;
	56
d9a16f9a PW	57	/* prm_base: base virtual address of the PRM IP block */
	58	void __iomem *prm_base;
	59
e24c3573 PW	60	/*
	61	* prm_ll_data: function pointers to SoC-specific implementations of
	62	* common PRM functions
	63	*/
	64	static struct prm_ll_data null_prm_ll_data;
	65	static struct prm_ll_data *prm_ll_data = &null_prm_ll_data;
	66
0a84a91c TK	67	/* Private functions */
	68
	69	/*
	70	* Move priority events from events to priority_events array
	71	*/
	72	static void omap_prcm_events_filter_priority(unsigned long *events,
	73	unsigned long *priority_events)
	74	{
	75	int i;
	76
	77	for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
	78	priority_events[i] =
	79	events[i] & prcm_irq_setup->priority_mask[i];
	80	events[i] ^= priority_events[i];
	81	}
	82	}
	83
	84	/*
	85	* PRCM Interrupt Handler
	86	*
	87	* This is a common handler for the OMAP PRCM interrupts. Pending
	88	* interrupts are detected by a call to prcm_pending_events and
	89	* dispatched accordingly. Clearing of the wakeup events should be
	90	* done by the SoC specific individual handlers.
	91	*/
	92	static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
	93	{
	94	unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
	95	unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
	96	struct irq_chip *chip = irq_desc_get_chip(desc);
	97	unsigned int virtirq;
b56f2cb7	98	int nr_irq = prcm_irq_setup->nr_regs * 32;
0a84a91c	99
91285b6f TK	100	/*
	101	* If we are suspended, mask all interrupts from PRCM level,
	102	* this does not ack them, and they will be pending until we
	103	* re-enable the interrupts, at which point the
	104	* omap_prcm_irq_handler will be executed again. The
	105	* _save_and_clear_irqen() function must ensure that the PRM
	106	* write to disable all IRQs has reached the PRM before
	107	* returning, or spurious PRCM interrupts may occur during
	108	* suspend.
	109	*/
	110	if (prcm_irq_setup->suspended) {
	111	prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
	112	prcm_irq_setup->suspend_save_flag = true;
	113	}
	114
0a84a91c TK	115	/*
	116	* Loop until all pending irqs are handled, since
	117	* generic_handle_irq() can cause new irqs to come
	118	*/
91285b6f	119	while (!prcm_irq_setup->suspended) {
0a84a91c TK	120	prcm_irq_setup->read_pending_irqs(pending);
	121
	122	/* No bit set, then all IRQs are handled */
b56f2cb7	123	if (find_first_bit(pending, nr_irq) >= nr_irq)
0a84a91c TK	124	break;
	125
	126	omap_prcm_events_filter_priority(pending, priority_pending);
	127
	128	/*
	129	* Loop on all currently pending irqs so that new irqs
	130	* cannot starve previously pending irqs
	131	*/
	132
	133	/* Serve priority events first */
b56f2cb7	134	for_each_set_bit(virtirq, priority_pending, nr_irq)
0a84a91c TK	135	generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
	136
	137	/* Serve normal events next */
b56f2cb7	138	for_each_set_bit(virtirq, pending, nr_irq)
0a84a91c TK	139	generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
	140	}
	141	if (chip->irq_ack)
	142	chip->irq_ack(&desc->irq_data);
	143	if (chip->irq_eoi)
	144	chip->irq_eoi(&desc->irq_data);
	145	chip->irq_unmask(&desc->irq_data);
	146
	147	prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
	148	}
	149
	150	/* Public functions */
	151
	152	/**
	153	* omap_prcm_event_to_irq - given a PRCM event name, returns the
	154	* corresponding IRQ on which the handler should be registered
	155	* @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
	156	*
	157	* Returns the Linux internal IRQ ID corresponding to @name upon success,
	158	* or -ENOENT upon failure.
	159	*/
	160	int omap_prcm_event_to_irq(const char *name)
	161	{
	162	int i;
	163
	164	if (!prcm_irq_setup \|\| !name)
	165	return -ENOENT;
	166
	167	for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
	168	if (!strcmp(prcm_irq_setup->irqs[i].name, name))
	169	return prcm_irq_setup->base_irq +
	170	prcm_irq_setup->irqs[i].offset;
	171
	172	return -ENOENT;
	173	}
	174
	175	/**
	176	* omap_prcm_irq_cleanup - reverses memory allocated and other steps
	177	* done by omap_prcm_register_chain_handler()
	178	*
	179	* No return value.
	180	*/
	181	void omap_prcm_irq_cleanup(void)
	182	{
	183	int i;
	184
	185	if (!prcm_irq_setup) {
	186	pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
	187	return;
	188	}
	189
	190	if (prcm_irq_chips) {
	191	for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
	192	if (prcm_irq_chips[i])
	193	irq_remove_generic_chip(prcm_irq_chips[i],
	194	0xffffffff, 0, 0);
	195	prcm_irq_chips[i] = NULL;
	196	}
	197	kfree(prcm_irq_chips);
	198	prcm_irq_chips = NULL;
	199	}
	200
91285b6f TK	201	kfree(prcm_irq_setup->saved_mask);
	202	prcm_irq_setup->saved_mask = NULL;
	203
0a84a91c TK	204	kfree(prcm_irq_setup->priority_mask);
	205	prcm_irq_setup->priority_mask = NULL;
	206
	207	irq_set_chained_handler(prcm_irq_setup->irq, NULL);
	208
	209	if (prcm_irq_setup->base_irq > 0)
	210	irq_free_descs(prcm_irq_setup->base_irq,
	211	prcm_irq_setup->nr_regs * 32);
	212	prcm_irq_setup->base_irq = 0;
	213	}
	214
91285b6f TK	215	void omap_prcm_irq_prepare(void)
	216	{
	217	prcm_irq_setup->suspended = true;
	218	}
	219
	220	void omap_prcm_irq_complete(void)
	221	{
	222	prcm_irq_setup->suspended = false;
	223
	224	/* If we have not saved the masks, do not attempt to restore */
	225	if (!prcm_irq_setup->suspend_save_flag)
	226	return;
	227
	228	prcm_irq_setup->suspend_save_flag = false;
	229
	230	/*
	231	* Re-enable all masked PRCM irq sources, this causes the PRCM
	232	* interrupt to fire immediately if the events were masked
	233	* previously in the chain handler
	234	*/
	235	prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
	236	}
	237
0a84a91c TK	238	/**
	239	* omap_prcm_register_chain_handler - initializes the prcm chained interrupt
	240	* handler based on provided parameters
	241	* @irq_setup: hardware data about the underlying PRM/PRCM
	242	*
	243	* Set up the PRCM chained interrupt handler on the PRCM IRQ. Sets up
	244	* one generic IRQ chip per PRM interrupt status/enable register pair.
	245	* Returns 0 upon success, -EINVAL if called twice or if invalid
	246	* arguments are passed, or -ENOMEM on any other error.
	247	*/
	248	int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
	249	{
eeb3711b	250	int nr_regs;
0a84a91c TK	251	u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
	252	int offset, i;
	253	struct irq_chip_generic *gc;
	254	struct irq_chip_type *ct;
	255
	256	if (!irq_setup)
	257	return -EINVAL;
	258
eeb3711b PW	259	nr_regs = irq_setup->nr_regs;
eeb3711b PW	260
0a84a91c TK	261	if (prcm_irq_setup) {
	262	pr_err("PRCM: already initialized; won't reinitialize\n");
	263	return -EINVAL;
	264	}
	265
	266	if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
	267	pr_err("PRCM: nr_regs too large\n");
	268	return -EINVAL;
	269	}
	270
	271	prcm_irq_setup = irq_setup;
	272
	273	prcm_irq_chips = kzalloc(sizeof(void ) nr_regs, GFP_KERNEL);
91285b6f	274	prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL);
0a84a91c TK	275	prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
	276	GFP_KERNEL);
	277
91285b6f TK	278	if (!prcm_irq_chips \|\| !prcm_irq_setup->saved_mask \|\|
91285b6f TK	279	!prcm_irq_setup->priority_mask) {
0a84a91c TK	280	pr_err("PRCM: kzalloc failed\n");
	281	goto err;
	282	}
	283
	284	memset(mask, 0, sizeof(mask));
	285
	286	for (i = 0; i < irq_setup->nr_irqs; i++) {
	287	offset = irq_setup->irqs[i].offset;
	288	mask[offset >> 5] \|= 1 << (offset & 0x1f);
	289	if (irq_setup->irqs[i].priority)
	290	irq_setup->priority_mask[offset >> 5] \|=
	291	1 << (offset & 0x1f);
	292	}
	293
	294	irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);
	295
	296	irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
	297	0);
	298
	299	if (irq_setup->base_irq < 0) {
	300	pr_err("PRCM: failed to allocate irq descs: %d\n",
	301	irq_setup->base_irq);
	302	goto err;
	303	}
	304
4ba7c3c3	305	for (i = 0; i < irq_setup->nr_regs; i++) {
0a84a91c TK	306	gc = irq_alloc_generic_chip("PRCM", 1,
	307	irq_setup->base_irq + i * 32, prm_base,
	308	handle_level_irq);
	309
	310	if (!gc) {
	311	pr_err("PRCM: failed to allocate generic chip\n");
	312	goto err;
	313	}
	314	ct = gc->chip_types;
	315	ct->chip.irq_ack = irq_gc_ack_set_bit;
	316	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	317	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	318
	319	ct->regs.ack = irq_setup->ack + i * 4;
	320	ct->regs.mask = irq_setup->mask + i * 4;
	321
	322	irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
	323	prcm_irq_chips[i] = gc;
	324	}
	325
30a69ef7 TL	326	if (of_have_populated_dt()) {
	327	int irq = omap_prcm_event_to_irq("io");
	328	if (cpu_is_omap34xx())
	329	omap_pcs_legacy_init(irq,
	330	omap3xxx_prm_reconfigure_io_chain);
	331	else
	332	omap_pcs_legacy_init(irq,
	333	omap44xx_prm_reconfigure_io_chain);
	334	}
	335
0a84a91c TK	336	return 0;
	337
	338	err:
	339	omap_prcm_irq_cleanup();
	340	return -ENOMEM;
	341	}
3f4990f4	342
d9a16f9a PW	343	/**
	344	* omap2_set_globals_prm - set the PRM base address (for early use)
	345	* @prm: PRM base virtual address
	346	*
	347	* XXX Will be replaced when the PRM/CM drivers are completed.
3f4990f4	348	*/
d9a16f9a	349	void __init omap2_set_globals_prm(void __iomem *prm)
3f4990f4	350	{
d9a16f9a	351	prm_base = prm;
3f4990f4 S	352	}
3f4990f4 S	353
2bb2a5d3 PW	354	/**
	355	* prm_read_reset_sources - return the sources of the SoC's last reset
	356	*
	357	* Return a u32 bitmask representing the reset sources that caused the
	358	* SoC to reset. The low-level per-SoC functions called by this
	359	* function remap the SoC-specific reset source bits into an
	360	* OMAP-common set of reset source bits, defined in
	361	* arch/arm/mach-omap2/prm.h. Returns the standardized reset source
	362	* u32 bitmask from the hardware upon success, or returns (1 <<
	363	* OMAP_UNKNOWN_RST_SRC_ID_SHIFT) if no low-level read_reset_sources()
	364	* function was registered.
3f4990f4	365	*/
2bb2a5d3	366	u32 prm_read_reset_sources(void)
3f4990f4	367	{
2bb2a5d3	368	u32 ret = 1 << OMAP_UNKNOWN_RST_SRC_ID_SHIFT;
3f4990f4	369
2bb2a5d3 PW	370	if (prm_ll_data->read_reset_sources)
	371	ret = prm_ll_data->read_reset_sources();
	372	else
	373	WARN_ONCE(1, "prm: %s: no mapping function defined for reset sources\n", __func__);
3f4990f4	374
2bb2a5d3	375	return ret;
3f4990f4 S	376	}
3f4990f4 S	377
e6d3a8b0 RN	378	/**
	379	* prm_was_any_context_lost_old - was device context lost? (old API)
	380	* @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
	381	* @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
	382	* @idx: CONTEXT register offset
	383	*
	384	* Return 1 if any bits were set in the _CONTEXT_ register
	385	* identified by (@part, @inst, @idx), which means that some context
	386	* was lost for that module; otherwise, return 0. XXX Deprecated;
	387	* callers need to use a less-SoC-dependent way to identify hardware
	388	* IP blocks.
	389	*/
	390	bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx)
	391	{
	392	bool ret = true;
	393
	394	if (prm_ll_data->was_any_context_lost_old)
	395	ret = prm_ll_data->was_any_context_lost_old(part, inst, idx);
	396	else
	397	WARN_ONCE(1, "prm: %s: no mapping function defined\n",
	398	__func__);
	399
	400	return ret;
	401	}
	402
	403	/**
	404	* prm_clear_context_lost_flags_old - clear context loss flags (old API)
	405	* @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
	406	* @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
	407	* @idx: CONTEXT register offset
	408	*
	409	* Clear hardware context loss bits for the module identified by
	410	* (@part, @inst, @idx). No return value. XXX Deprecated; callers
	411	* need to use a less-SoC-dependent way to identify hardware IP
	412	* blocks.
	413	*/
	414	void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx)
	415	{
	416	if (prm_ll_data->clear_context_loss_flags_old)
	417	prm_ll_data->clear_context_loss_flags_old(part, inst, idx);
	418	else
	419	WARN_ONCE(1, "prm: %s: no mapping function defined\n",
	420	__func__);
	421	}
	422
e24c3573 PW	423	/**
	424	* prm_register - register per-SoC low-level data with the PRM
	425	* @pld: low-level per-SoC OMAP PRM data & function pointers to register
	426	*
	427	* Register per-SoC low-level OMAP PRM data and function pointers with
	428	* the OMAP PRM common interface. The caller must keep the data
	429	* pointed to by @pld valid until it calls prm_unregister() and
	430	* it returns successfully. Returns 0 upon success, -EINVAL if @pld
	431	* is NULL, or -EEXIST if prm_register() has already been called
	432	* without an intervening prm_unregister().
	433	*/
	434	int prm_register(struct prm_ll_data *pld)
3f4990f4	435	{
e24c3573 PW	436	if (!pld)
e24c3573 PW	437	return -EINVAL;
3f4990f4	438
e24c3573 PW	439	if (prm_ll_data != &null_prm_ll_data)
e24c3573 PW	440	return -EEXIST;
3f4990f4	441
e24c3573	442	prm_ll_data = pld;
3f4990f4	443
3f4990f4 S	444	return 0;
	445	}
	446
e24c3573 PW	447	/**
	448	* prm_unregister - unregister per-SoC low-level data & function pointers
	449	* @pld: low-level per-SoC OMAP PRM data & function pointers to unregister
	450	*
	451	* Unregister per-SoC low-level OMAP PRM data and function pointers
	452	* that were previously registered with prm_register(). The
	453	* caller may not destroy any of the data pointed to by @pld until
	454	* this function returns successfully. Returns 0 upon success, or
	455	* -EINVAL if @pld is NULL or if @pld does not match the struct
	456	* prm_ll_data * previously registered by prm_register().
	457	*/
	458	int prm_unregister(struct prm_ll_data *pld)
3f4990f4	459	{
e24c3573 PW	460	if (!pld \|\| prm_ll_data != pld)
	461	return -EINVAL;
	462
	463	prm_ll_data = &null_prm_ll_data;
3f4990f4	464
3f4990f4 S	465	return 0;
3f4990f4 S	466	}