[deliverable/linux.git] / arch / arm / mach-omap2 / serial.c

/*
 * arch/arm/mach-omap2/serial.c
 *
 * OMAP2 serial support.
 *
 * Copyright (C) 2005-2008 Nokia Corporation
 * Author: Paul Mundt <paul.mundt@nokia.com>
 *
 * Major rework for PM support by Kevin Hilman
 *
 * Based off of arch/arm/mach-omap/omap1/serial.c
 *
 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/console.h>

#include <plat/omap-serial.h>
#include "common.h"
#include <plat/board.h>
#include <plat/dma.h>
#include <plat/omap_hwmod.h>
#include <plat/omap_device.h>

#include "prm2xxx_3xxx.h"
#include "pm.h"
#include "cm2xxx_3xxx.h"
#include "prm-regbits-34xx.h"
#include "control.h"
#include "mux.h"

#define UART_ERRATA_i202_MDR1_ACCESS	(0x1 << 1)

/*
 * NOTE: By default the serial timeout is disabled as it causes lost characters
 * over the serial ports. This means that the UART clocks will stay on until
 * disabled via sysfs. This also causes that any deeper omap sleep states are
 * blocked. 
 */
#define DEFAULT_TIMEOUT 0

#define MAX_UART_HWMOD_NAME_LEN		16

struct omap_uart_state {
	int num;
	int can_sleep;

	void __iomem *wk_st;
	void __iomem *wk_en;
	u32 wk_mask;
	u32 dma_enabled;

	int clocked;

	struct list_head node;
	struct omap_hwmod *oh;
	struct platform_device *pdev;

	u32 errata;
};

static LIST_HEAD(uart_list);
static u8 num_uarts;

#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)

/*
 * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
 * The access to uart register after MDR1 Access
 * causes UART to corrupt data.
 *
 * Need a delay =
 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
 * give 10 times as much
 */
static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
		u8 fcr_val)
{
	u8 timeout = 255;

	serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
	udelay(2);
	serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
			UART_FCR_CLEAR_RCVR);
	/*
	 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
	 * TX_FIFO_E bit is 1.
	 */
	while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
				(UART_LSR_THRE | UART_LSR_DR))) {
		timeout--;
		if (!timeout) {
			/* Should *never* happen. we warn and carry on */
			dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
			serial_read_reg(uart, UART_LSR));
			break;
		}
		udelay(1);
	}
}

#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */

static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
{
	if (uart->clocked)
		return;

	omap_device_enable(uart->pdev);
	uart->clocked = 1;
	omap_uart_restore_context(uart);
}

#ifdef CONFIG_PM

static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
{
	if (!uart->clocked)
		return;

	omap_uart_save_context(uart);
	uart->clocked = 0;
	omap_device_idle(uart->pdev);
}

static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
{
	/* Set wake-enable bit */
	if (uart->wk_en && uart->wk_mask) {
		u32 v = __raw_readl(uart->wk_en);
		v |= uart->wk_mask;
		__raw_writel(v, uart->wk_en);
	}
}

static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
{
	/* Clear wake-enable bit */
	if (uart->wk_en && uart->wk_mask) {
		u32 v = __raw_readl(uart->wk_en);
		v &= ~uart->wk_mask;
		__raw_writel(v, uart->wk_en);
	}
}

static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
					       int enable)
{
	u8 idlemode;

	if (enable) {
		/**
		 * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
		 * in Smartidle Mode When Configured for DMA Operations.
		 */
		if (uart->dma_enabled)
			idlemode = HWMOD_IDLEMODE_FORCE;
		else
			idlemode = HWMOD_IDLEMODE_SMART;
	} else {
		idlemode = HWMOD_IDLEMODE_NO;
	}

	omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
}

static void omap_uart_block_sleep(struct omap_uart_state *uart)
{
	omap_uart_enable_clocks(uart);

	omap_uart_smart_idle_enable(uart, 0);
	uart->can_sleep = 0;
}

int omap_uart_can_sleep(void)
{
	struct omap_uart_state *uart;
	int can_sleep = 1;

	list_for_each_entry(uart, &uart_list, node) {
		if (!uart->clocked)
			continue;

		if (!uart->can_sleep) {
			can_sleep = 0;
			continue;
		}

		/* This UART can now safely sleep. */
		omap_uart_allow_sleep(uart);
	}

	return can_sleep;
}

static void omap_uart_idle_init(struct omap_uart_state *uart)
{
	int ret;

	uart->can_sleep = 0;
	omap_uart_smart_idle_enable(uart, 0);

	if (cpu_is_omap34xx() && !(cpu_is_ti81xx() || cpu_is_am33xx())) {
		u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
		u32 wk_mask = 0;

		/* XXX These PRM accesses do not belong here */
		uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
		uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
		switch (uart->num) {
		case 0:
			wk_mask = OMAP3430_ST_UART1_MASK;
			break;
		case 1:
			wk_mask = OMAP3430_ST_UART2_MASK;
			break;
		case 2:
			wk_mask = OMAP3430_ST_UART3_MASK;
			break;
		case 3:
			wk_mask = OMAP3630_ST_UART4_MASK;
			break;
		}
		uart->wk_mask = wk_mask;
	} else if (cpu_is_omap24xx()) {
		u32 wk_mask = 0;
		u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;

		switch (uart->num) {
		case 0:
			wk_mask = OMAP24XX_ST_UART1_MASK;
			break;
		case 1:
			wk_mask = OMAP24XX_ST_UART2_MASK;
			break;
		case 2:
			wk_en = OMAP24XX_PM_WKEN2;
			wk_st = OMAP24XX_PM_WKST2;
			wk_mask = OMAP24XX_ST_UART3_MASK;
			break;
		}
		uart->wk_mask = wk_mask;
		if (cpu_is_omap2430()) {
			uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
			uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
		} else if (cpu_is_omap2420()) {
			uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
			uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
		}
	} else {
		uart->wk_en = NULL;
		uart->wk_st = NULL;
		uart->wk_mask = 0;
	}
}

#else
static void omap_uart_block_sleep(struct omap_uart_state *uart)
{
	/* Needed to enable UART clocks when built without CONFIG_PM */
	omap_uart_enable_clocks(uart);
}
#endif /* CONFIG_PM */

#ifdef CONFIG_OMAP_MUX
static struct omap_device_pad default_uart1_pads[] __initdata = {
	{
		.name	= "uart1_cts.uart1_cts",
		.enable	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
	},
	{
		.name	= "uart1_rts.uart1_rts",
		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
	},
	{
		.name	= "uart1_tx.uart1_tx",
		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
	},
	{
		.name	= "uart1_rx.uart1_rx",
		.flags	= OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
		.enable	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
		.idle	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
	},
};

static struct omap_device_pad default_uart2_pads[] __initdata = {
	{
		.name	= "uart2_cts.uart2_cts",
		.enable	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
	},
	{
		.name	= "uart2_rts.uart2_rts",
		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
	},
	{
		.name	= "uart2_tx.uart2_tx",
		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
	},
	{
		.name	= "uart2_rx.uart2_rx",
		.flags	= OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
		.enable	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
		.idle	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
	},
};

static struct omap_device_pad default_uart3_pads[] __initdata = {
	{
		.name	= "uart3_cts_rctx.uart3_cts_rctx",
		.enable	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
	},
	{
		.name	= "uart3_rts_sd.uart3_rts_sd",
		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
	},
	{
		.name	= "uart3_tx_irtx.uart3_tx_irtx",
		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
	},
	{
		.name	= "uart3_rx_irrx.uart3_rx_irrx",
		.flags	= OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
		.enable	= OMAP_PIN_INPUT | OMAP_MUX_MODE0,
		.idle	= OMAP_PIN_INPUT | OMAP_MUX_MODE0,
	},
};

static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = {
	{
		.name   = "gpmc_wait2.uart4_tx",
		.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
	},
	{
		.name	= "gpmc_wait3.uart4_rx",
		.flags	= OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
		.enable	= OMAP_PIN_INPUT | OMAP_MUX_MODE2,
		.idle	= OMAP_PIN_INPUT | OMAP_MUX_MODE2,
	},
};

static struct omap_device_pad default_omap4_uart4_pads[] __initdata = {
	{
		.name	= "uart4_tx.uart4_tx",
		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
	},
	{
		.name	= "uart4_rx.uart4_rx",
		.flags	= OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
		.enable	= OMAP_PIN_INPUT | OMAP_MUX_MODE0,
		.idle	= OMAP_PIN_INPUT | OMAP_MUX_MODE0,
	},
};

static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
{
	switch (bdata->id) {
	case 0:
		bdata->pads = default_uart1_pads;
		bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads);
		break;
	case 1:
		bdata->pads = default_uart2_pads;
		bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads);
		break;
	case 2:
		bdata->pads = default_uart3_pads;
		bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads);
		break;
	case 3:
		if (cpu_is_omap44xx()) {
			bdata->pads = default_omap4_uart4_pads;
			bdata->pads_cnt =
				ARRAY_SIZE(default_omap4_uart4_pads);
		} else if (cpu_is_omap3630()) {
			bdata->pads = default_omap36xx_uart4_pads;
			bdata->pads_cnt =
				ARRAY_SIZE(default_omap36xx_uart4_pads);
		}
		break;
	default:
		break;
	}
}
#else
static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
#endif

static int __init omap_serial_early_init(void)
{
	int i = 0;

	do {
		char oh_name[MAX_UART_HWMOD_NAME_LEN];
		struct omap_hwmod *oh;
		struct omap_uart_state *uart;

		snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
			 "uart%d", i + 1);
		oh = omap_hwmod_lookup(oh_name);
		if (!oh)
			break;

		uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
		if (WARN_ON(!uart))
			return -ENODEV;

		uart->oh = oh;
		uart->num = i++;
		list_add_tail(&uart->node, &uart_list);
		num_uarts++;

		/*
		 * NOTE: omap_hwmod_setup*() has not yet been called,
		 *       so no hwmod functions will work yet.
		 */

		/*
		 * During UART early init, device need to be probed
		 * to determine SoC specific init before omap_device
		 * is ready.  Therefore, don't allow idle here
		 */
		uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
	} while (1);

	return 0;
}
core_initcall(omap_serial_early_init);

/**
 * omap_serial_init_port() - initialize single serial port
 * @bdata: port specific board data pointer
 *
 * This function initialies serial driver for given port only.
 * Platforms can call this function instead of omap_serial_init()
 * if they don't plan to use all available UARTs as serial ports.
 *
 * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
 * use only one of the two.
 */
void __init omap_serial_init_port(struct omap_board_data *bdata)
{
	struct omap_uart_state *uart;
	struct omap_hwmod *oh;
	struct platform_device *pdev;
	void *pdata = NULL;
	u32 pdata_size = 0;
	char *name;
	struct omap_uart_port_info omap_up;

	if (WARN_ON(!bdata))
		return;
	if (WARN_ON(bdata->id < 0))
		return;
	if (WARN_ON(bdata->id >= num_uarts))
		return;

	list_for_each_entry(uart, &uart_list, node)
		if (bdata->id == uart->num)
			break;

	oh = uart->oh;
	uart->dma_enabled = 0;
	name = DRIVER_NAME;

	omap_up.dma_enabled = uart->dma_enabled;
	omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
	omap_up.flags = UPF_BOOT_AUTOCONF;

	pdata = &omap_up;
	pdata_size = sizeof(struct omap_uart_port_info);

	if (WARN_ON(!oh))
		return;

	pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
				 NULL, 0, false);
	WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
	     name, oh->name);

	omap_device_disable_idle_on_suspend(pdev);
	oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);

	uart->pdev = pdev;

	oh->dev_attr = uart;

	console_lock(); /* in case the earlycon is on the UART */

	/*
	 * Because of early UART probing, UART did not get idled
	 * on init.  Now that omap_device is ready, ensure full idle
	 * before doing omap_device_enable().
	 */
	omap_hwmod_idle(uart->oh);

	omap_device_enable(uart->pdev);
	omap_uart_idle_init(uart);
	omap_hwmod_enable_wakeup(uart->oh);
	omap_device_idle(uart->pdev);

	omap_uart_block_sleep(uart);
	console_unlock();

	if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads) ||
		(pdata->wk_en && pdata->wk_mask))
		device_init_wakeup(&pdev->dev, true);

	/* Enable the MDR1 errata for OMAP3 */
	if (cpu_is_omap34xx() && !(cpu_is_ti81xx() || cpu_is_am33xx()))
		uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
}

/**
 * omap_serial_init() - initialize all supported serial ports
 *
 * Initializes all available UARTs as serial ports. Platforms
 * can call this function when they want to have default behaviour
 * for serial ports (e.g initialize them all as serial ports).
 */
void __init omap_serial_init(void)
{
	struct omap_uart_state *uart;
	struct omap_board_data bdata;

	list_for_each_entry(uart, &uart_list, node) {
		bdata.id = uart->num;
		bdata.flags = 0;
		bdata.pads = NULL;
		bdata.pads_cnt = 0;

		if (cpu_is_omap44xx() || cpu_is_omap34xx())
			omap_serial_fill_default_pads(&bdata);

		omap_serial_init_port(&bdata);

	}
}
Commit	Line	Data
1dbae815	1	/*
f30c2269	2	* arch/arm/mach-omap2/serial.c
1dbae815 TL	3	*
	4	* OMAP2 serial support.
	5	*
6e81176d	6	* Copyright (C) 2005-2008 Nokia Corporation
1dbae815 TL	7	* Author: Paul Mundt <paul.mundt@nokia.com>
1dbae815 TL	8	*
4af4016c KH	9	* Major rework for PM support by Kevin Hilman
4af4016c KH	10	*
1dbae815 TL	11	* Based off of arch/arm/mach-omap/omap1/serial.c
1dbae815 TL	12	*
44169075 SS	13	* Copyright (C) 2009 Texas Instruments
	14	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
	15	*
1dbae815 TL	16	* This file is subject to the terms and conditions of the GNU General Public
	17	* License. See the file "COPYING" in the main directory of this archive
	18	* for more details.
	19	*/
	20	#include <linux/kernel.h>
	21	#include <linux/init.h>
f8ce2547	22	#include <linux/clk.h>
fced80c7	23	#include <linux/io.h>
e03d37d8	24	#include <linux/delay.h>
6f251e9d KH	25	#include <linux/platform_device.h>
6f251e9d KH	26	#include <linux/slab.h>
3244fcd2	27	#include <linux/pm_runtime.h>
0d8e2d0d	28	#include <linux/console.h>
6f251e9d	29
6f251e9d	30	#include <plat/omap-serial.h>
4e65331c	31	#include "common.h"
ce491cf8	32	#include <plat/board.h>
6f251e9d KH	33	#include <plat/dma.h>
	34	#include <plat/omap_hwmod.h>
	35	#include <plat/omap_device.h>
4af4016c	36
59fb659b	37	#include "prm2xxx_3xxx.h"
4af4016c	38	#include "pm.h"
59fb659b	39	#include "cm2xxx_3xxx.h"
4af4016c	40	#include "prm-regbits-34xx.h"
4814ced5	41	#include "control.h"
40e44399	42	#include "mux.h"
4af4016c	43
00034509	44	#define UART_ERRATA_i202_MDR1_ACCESS (0x1 << 1)
5a927b36	45
301fe8ee TL	46	/*
	47	* NOTE: By default the serial timeout is disabled as it causes lost characters
	48	* over the serial ports. This means that the UART clocks will stay on until
	49	* disabled via sysfs. This also causes that any deeper omap sleep states are
	50	* blocked.
	51	*/
	52	#define DEFAULT_TIMEOUT 0
4af4016c	53
6f251e9d KH	54	#define MAX_UART_HWMOD_NAME_LEN 16
6f251e9d KH	55
4af4016c KH	56	struct omap_uart_state {
	57	int num;
	58	int can_sleep;
4af4016c KH	59
	60	void __iomem *wk_st;
	61	void __iomem *wk_en;
	62	u32 wk_mask;
6f251e9d	63	u32 dma_enabled;
4af4016c	64
4af4016c KH	65	int clocked;
4af4016c KH	66
4af4016c	67	struct list_head node;
6f251e9d KH	68	struct omap_hwmod *oh;
6f251e9d KH	69	struct platform_device *pdev;
1dbae815	70
5a927b36	71	u32 errata;
4af4016c KH	72	};
4af4016c KH	73
4af4016c	74	static LIST_HEAD(uart_list);
6f251e9d	75	static u8 num_uarts;
1dbae815	76
4af4016c KH	77	#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
4af4016c KH	78
00034509 D	79	/*
	80	* Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
	81	* The access to uart register after MDR1 Access
	82	* causes UART to corrupt data.
	83	*
	84	* Need a delay =
	85	* 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
	86	* give 10 times as much
	87	*/
	88	static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
	89	u8 fcr_val)
	90	{
00034509 D	91	u8 timeout = 255;
00034509 D	92
6f251e9d	93	serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
00034509	94	udelay(2);
6f251e9d	95	serial_write_reg(uart, UART_FCR, fcr_val \| UART_FCR_CLEAR_XMIT \|
00034509 D	96	UART_FCR_CLEAR_RCVR);
	97	/*
	98	* Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
	99	* TX_FIFO_E bit is 1.
	100	*/
6f251e9d	101	while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
00034509 D	102	(UART_LSR_THRE \| UART_LSR_DR))) {
	103	timeout--;
	104	if (!timeout) {
	105	/* Should never happen. we warn and carry on */
6f251e9d KH	106	dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
6f251e9d KH	107	serial_read_reg(uart, UART_LSR));
00034509 D	108	break;
	109	}
	110	udelay(1);
	111	}
	112	}
	113
4af4016c KH	114	#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
	115
	116	static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
	117	{
	118	if (uart->clocked)
	119	return;
	120
6f251e9d	121	omap_device_enable(uart->pdev);
4af4016c KH	122	uart->clocked = 1;
	123	omap_uart_restore_context(uart);
	124	}
	125
	126	#ifdef CONFIG_PM
	127
	128	static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
	129	{
	130	if (!uart->clocked)
	131	return;
	132
	133	omap_uart_save_context(uart);
	134	uart->clocked = 0;
6f251e9d	135	omap_device_idle(uart->pdev);
4af4016c KH	136	}
4af4016c KH	137
fd455ea8 KH	138	static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
	139	{
	140	/* Set wake-enable bit */
	141	if (uart->wk_en && uart->wk_mask) {
	142	u32 v = __raw_readl(uart->wk_en);
	143	v \|= uart->wk_mask;
	144	__raw_writel(v, uart->wk_en);
	145	}
fd455ea8 KH	146	}
	147
	148	static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
	149	{
	150	/* Clear wake-enable bit */
	151	if (uart->wk_en && uart->wk_mask) {
	152	u32 v = __raw_readl(uart->wk_en);
	153	v &= ~uart->wk_mask;
	154	__raw_writel(v, uart->wk_en);
	155	}
fd455ea8 KH	156	}
fd455ea8 KH	157
4af4016c	158	static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
6f251e9d	159	int enable)
4af4016c	160	{
6f251e9d	161	u8 idlemode;
4af4016c	162
6f251e9d KH	163	if (enable) {
	164	/**
	165	* Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
	166	* in Smartidle Mode When Configured for DMA Operations.
	167	*/
	168	if (uart->dma_enabled)
	169	idlemode = HWMOD_IDLEMODE_FORCE;
	170	else
	171	idlemode = HWMOD_IDLEMODE_SMART;
	172	} else {
	173	idlemode = HWMOD_IDLEMODE_NO;
	174	}
4af4016c	175
6f251e9d	176	omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
4af4016c KH	177	}
	178
	179	static void omap_uart_block_sleep(struct omap_uart_state *uart)
	180	{
	181	omap_uart_enable_clocks(uart);
	182
	183	omap_uart_smart_idle_enable(uart, 0);
	184	uart->can_sleep = 0;
4af4016c KH	185	}
4af4016c KH	186
4af4016c KH	187	int omap_uart_can_sleep(void)
	188	{
	189	struct omap_uart_state *uart;
	190	int can_sleep = 1;
	191
	192	list_for_each_entry(uart, &uart_list, node) {
	193	if (!uart->clocked)
	194	continue;
	195
	196	if (!uart->can_sleep) {
	197	can_sleep = 0;
	198	continue;
6e81176d	199	}
4af4016c KH	200
	201	/* This UART can now safely sleep. */
	202	omap_uart_allow_sleep(uart);
6e81176d	203	}
4af4016c KH	204
4af4016c KH	205	return can_sleep;
6e81176d JH	206	}
6e81176d JH	207
4af4016c KH	208	static void omap_uart_idle_init(struct omap_uart_state *uart)
4af4016c KH	209	{
4af4016c KH	210	int ret;
	211
	212	uart->can_sleep = 0;
4af4016c KH	213	omap_uart_smart_idle_enable(uart, 0);
4af4016c KH	214
a920360f	215	if (cpu_is_omap34xx() && !(cpu_is_ti81xx() \|\| cpu_is_am33xx())) {
52663aea	216	u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
4af4016c	217	u32 wk_mask = 0;
4af4016c	218
c4d7e58f	219	/* XXX These PRM accesses do not belong here */
4af4016c KH	220	uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
	221	uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
	222	switch (uart->num) {
	223	case 0:
	224	wk_mask = OMAP3430_ST_UART1_MASK;
4af4016c KH	225	break;
	226	case 1:
	227	wk_mask = OMAP3430_ST_UART2_MASK;
4af4016c KH	228	break;
	229	case 2:
	230	wk_mask = OMAP3430_ST_UART3_MASK;
4af4016c	231	break;
52663aea G	232	case 3:
52663aea G	233	wk_mask = OMAP3630_ST_UART4_MASK;
52663aea	234	break;
4af4016c KH	235	}
4af4016c KH	236	uart->wk_mask = wk_mask;
4af4016c KH	237	} else if (cpu_is_omap24xx()) {
4af4016c KH	238	u32 wk_mask = 0;
cb74f022	239	u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
4af4016c	240
4af4016c KH	241	switch (uart->num) {
	242	case 0:
	243	wk_mask = OMAP24XX_ST_UART1_MASK;
	244	break;
	245	case 1:
	246	wk_mask = OMAP24XX_ST_UART2_MASK;
	247	break;
	248	case 2:
cb74f022 KH	249	wk_en = OMAP24XX_PM_WKEN2;
cb74f022 KH	250	wk_st = OMAP24XX_PM_WKST2;
4af4016c KH	251	wk_mask = OMAP24XX_ST_UART3_MASK;
	252	break;
	253	}
	254	uart->wk_mask = wk_mask;
cb74f022 KH	255	if (cpu_is_omap2430()) {
	256	uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
	257	uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
	258	} else if (cpu_is_omap2420()) {
	259	uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
	260	uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
	261	}
4af4016c	262	} else {
c54bae1f NM	263	uart->wk_en = NULL;
c54bae1f NM	264	uart->wk_st = NULL;
4af4016c	265	uart->wk_mask = 0;
4af4016c	266	}
ba87a9be JH	267	}
ba87a9be JH	268
4af4016c	269	#else
a1b04cc1 SS	270	static void omap_uart_block_sleep(struct omap_uart_state *uart)
	271	{
	272	/* Needed to enable UART clocks when built without CONFIG_PM */
	273	omap_uart_enable_clocks(uart);
	274	}
4af4016c KH	275	#endif /* CONFIG_PM */
4af4016c KH	276
7496ba30 G	277	#ifdef CONFIG_OMAP_MUX
	278	static struct omap_device_pad default_uart1_pads[] __initdata = {
	279	{
	280	.name = "uart1_cts.uart1_cts",
	281	.enable = OMAP_PIN_INPUT_PULLUP \| OMAP_MUX_MODE0,
	282	},
	283	{
	284	.name = "uart1_rts.uart1_rts",
	285	.enable = OMAP_PIN_OUTPUT \| OMAP_MUX_MODE0,
	286	},
	287	{
	288	.name = "uart1_tx.uart1_tx",
	289	.enable = OMAP_PIN_OUTPUT \| OMAP_MUX_MODE0,
	290	},
	291	{
	292	.name = "uart1_rx.uart1_rx",
	293	.flags = OMAP_DEVICE_PAD_REMUX \| OMAP_DEVICE_PAD_WAKEUP,
	294	.enable = OMAP_PIN_INPUT_PULLUP \| OMAP_MUX_MODE0,
	295	.idle = OMAP_PIN_INPUT_PULLUP \| OMAP_MUX_MODE0,
	296	},
	297	};
	298
	299	static struct omap_device_pad default_uart2_pads[] __initdata = {
	300	{
	301	.name = "uart2_cts.uart2_cts",
	302	.enable = OMAP_PIN_INPUT_PULLUP \| OMAP_MUX_MODE0,
	303	},
	304	{
	305	.name = "uart2_rts.uart2_rts",
	306	.enable = OMAP_PIN_OUTPUT \| OMAP_MUX_MODE0,
	307	},
	308	{
	309	.name = "uart2_tx.uart2_tx",
	310	.enable = OMAP_PIN_OUTPUT \| OMAP_MUX_MODE0,
	311	},
	312	{
	313	.name = "uart2_rx.uart2_rx",
	314	.flags = OMAP_DEVICE_PAD_REMUX \| OMAP_DEVICE_PAD_WAKEUP,
	315	.enable = OMAP_PIN_INPUT_PULLUP \| OMAP_MUX_MODE0,
	316	.idle = OMAP_PIN_INPUT_PULLUP \| OMAP_MUX_MODE0,
	317	},
	318	};
	319
	320	static struct omap_device_pad default_uart3_pads[] __initdata = {
	321	{
	322	.name = "uart3_cts_rctx.uart3_cts_rctx",
	323	.enable = OMAP_PIN_INPUT_PULLUP \| OMAP_MUX_MODE0,
	324	},
	325	{
	326	.name = "uart3_rts_sd.uart3_rts_sd",
	327	.enable = OMAP_PIN_OUTPUT \| OMAP_MUX_MODE0,
	328	},
	329	{
	330	.name = "uart3_tx_irtx.uart3_tx_irtx",
	331	.enable = OMAP_PIN_OUTPUT \| OMAP_MUX_MODE0,
	332	},
	333	{
	334	.name = "uart3_rx_irrx.uart3_rx_irrx",
	335	.flags = OMAP_DEVICE_PAD_REMUX \| OMAP_DEVICE_PAD_WAKEUP,
	336	.enable = OMAP_PIN_INPUT \| OMAP_MUX_MODE0,
	337	.idle = OMAP_PIN_INPUT \| OMAP_MUX_MODE0,
	338	},
	339	};
	340
341	static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = {
342	{
343	.name = "gpmc_wait2.uart4_tx",
344	.enable = OMAP_PIN_OUTPUT \| OMAP_MUX_MODE0,
345	},
346	{
347	.name = "gpmc_wait3.uart4_rx",
348	.flags = OMAP_DEVICE_PAD_REMUX \| OMAP_DEVICE_PAD_WAKEUP,
349	.enable = OMAP_PIN_INPUT \| OMAP_MUX_MODE2,
350	.idle = OMAP_PIN_INPUT \| OMAP_MUX_MODE2,
351	},
352	};
353
354	static struct omap_device_pad default_omap4_uart4_pads[] __initdata = {
355	{
356	.name = "uart4_tx.uart4_tx",
357	.enable = OMAP_PIN_OUTPUT \| OMAP_MUX_MODE0,
358	},
359	{
360	.name = "uart4_rx.uart4_rx",
361	.flags = OMAP_DEVICE_PAD_REMUX \| OMAP_DEVICE_PAD_WAKEUP,
362	.enable = OMAP_PIN_INPUT \| OMAP_MUX_MODE0,
363	.idle = OMAP_PIN_INPUT \| OMAP_MUX_MODE0,
364	},
365	};
366
367	static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
368	{
369	switch (bdata->id) {
370	case 0:
371	bdata->pads = default_uart1_pads;
372	bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads);
373	break;
374	case 1:
375	bdata->pads = default_uart2_pads;
376	bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads);
377	break;
378	case 2:
379	bdata->pads = default_uart3_pads;
380	bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads);
381	break;
382	case 3:
383	if (cpu_is_omap44xx()) {
384	bdata->pads = default_omap4_uart4_pads;
385	bdata->pads_cnt =
386	ARRAY_SIZE(default_omap4_uart4_pads);
387	} else if (cpu_is_omap3630()) {
388	bdata->pads = default_omap36xx_uart4_pads;
389	bdata->pads_cnt =
390	ARRAY_SIZE(default_omap36xx_uart4_pads);
391	}
392	break;
393	default:
394	break;
395	}
396	}
397	#else
398	static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
399	#endif
400
3e16f925	401	static int __init omap_serial_early_init(void)
1dbae815	402	{
6f251e9d	403	int i = 0;
1dbae815	404
6f251e9d KH	405	do {
	406	char oh_name[MAX_UART_HWMOD_NAME_LEN];
	407	struct omap_hwmod *oh;
	408	struct omap_uart_state *uart;
21b90340	409
6f251e9d KH	410	snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
	411	"uart%d", i + 1);
	412	oh = omap_hwmod_lookup(oh_name);
	413	if (!oh)
	414	break;
	415
	416	uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
	417	if (WARN_ON(!uart))
3e16f925	418	return -ENODEV;
1dbae815	419
6f251e9d KH	420	uart->oh = oh;
	421	uart->num = i++;
	422	list_add_tail(&uart->node, &uart_list);
	423	num_uarts++;
1dbae815	424
84f90c9c	425	/*
550c8092	426	* NOTE: omap_hwmod_setup*() has not yet been called,
6f251e9d	427	* so no hwmod functions will work yet.
84f90c9c	428	*/
6e81176d	429
6f251e9d KH	430	/*
	431	* During UART early init, device need to be probed
	432	* to determine SoC specific init before omap_device
	433	* is ready. Therefore, don't allow idle here
	434	*/
	435	uart->oh->flags \|= HWMOD_INIT_NO_IDLE \| HWMOD_INIT_NO_RESET;
	436	} while (1);
3e16f925 TL	437
3e16f925 TL	438	return 0;
b3c6df3a	439	}
3e16f925	440	core_initcall(omap_serial_early_init);
b3c6df3a	441
f62349ee MW	442	/**
f62349ee MW	443	* omap_serial_init_port() - initialize single serial port
40e44399	444	* @bdata: port specific board data pointer
f62349ee	445	*
40e44399	446	* This function initialies serial driver for given port only.
f62349ee MW	447	* Platforms can call this function instead of omap_serial_init()
	448	* if they don't plan to use all available UARTs as serial ports.
	449	*
	450	* Don't mix calls to omap_serial_init_port() and omap_serial_init(),
	451	* use only one of the two.
	452	*/
40e44399	453	void __init omap_serial_init_port(struct omap_board_data *bdata)
b3c6df3a	454	{
f62349ee	455	struct omap_uart_state *uart;
6f251e9d	456	struct omap_hwmod *oh;
3528c58e	457	struct platform_device *pdev;
6f251e9d KH	458	void *pdata = NULL;
	459	u32 pdata_size = 0;
	460	char *name;
6f251e9d	461	struct omap_uart_port_info omap_up;
970a724d	462
40e44399	463	if (WARN_ON(!bdata))
6f251e9d	464	return;
40e44399 TL	465	if (WARN_ON(bdata->id < 0))
	466	return;
	467	if (WARN_ON(bdata->id >= num_uarts))
e88d556d	468	return;
f62349ee	469
6f251e9d	470	list_for_each_entry(uart, &uart_list, node)
40e44399	471	if (bdata->id == uart->num)
6f251e9d	472	break;
f2eeeae0	473
6f251e9d KH	474	oh = uart->oh;
6f251e9d KH	475	uart->dma_enabled = 0;
6f251e9d KH	476	name = DRIVER_NAME;
	477
	478	omap_up.dma_enabled = uart->dma_enabled;
	479	omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
273558b3	480	omap_up.flags = UPF_BOOT_AUTOCONF;
6f251e9d KH	481
	482	pdata = &omap_up;
	483	pdata_size = sizeof(struct omap_uart_port_info);
6f251e9d KH	484
	485	if (WARN_ON(!oh))
	486	return;
	487
3528c58e	488	pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
f718e2c0	489	NULL, 0, false);
3528c58e	490	WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
6f251e9d KH	491	name, oh->name);
6f251e9d KH	492
9f8b6949	493	omap_device_disable_idle_on_suspend(pdev);
40e44399 TL	494	oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
40e44399 TL	495
3528c58e	496	uart->pdev = pdev;
6f251e9d KH	497
	498	oh->dev_attr = uart;
	499
ac751efa	500	console_lock(); /* in case the earlycon is on the UART */
0d8e2d0d	501
6f251e9d KH	502	/*
	503	* Because of early UART probing, UART did not get idled
	504	* on init. Now that omap_device is ready, ensure full idle
	505	* before doing omap_device_enable().
	506	*/
	507	omap_hwmod_idle(uart->oh);
	508
	509	omap_device_enable(uart->pdev);
	510	omap_uart_idle_init(uart);
6f251e9d KH	511	omap_hwmod_enable_wakeup(uart->oh);
	512	omap_device_idle(uart->pdev);
	513
6f251e9d	514	omap_uart_block_sleep(uart);
ac751efa	515	console_unlock();
0d8e2d0d	516
7496ba30 G	517	if (((cpu_is_omap34xx() \|\| cpu_is_omap44xx()) && bdata->pads) \|\|
7496ba30 G	518	(pdata->wk_en && pdata->wk_mask))
3528c58e	519	device_init_wakeup(&pdev->dev, true);
00034509 D	520
00034509 D	521	/* Enable the MDR1 errata for OMAP3 */
a920360f	522	if (cpu_is_omap34xx() && !(cpu_is_ti81xx() \|\| cpu_is_am33xx()))
00034509	523	uart->errata \|= UART_ERRATA_i202_MDR1_ACCESS;
f62349ee MW	524	}
	525
	526	/**
b595076a	527	* omap_serial_init() - initialize all supported serial ports
f62349ee MW	528	*
	529	* Initializes all available UARTs as serial ports. Platforms
	530	* can call this function when they want to have default behaviour
	531	* for serial ports (e.g initialize them all as serial ports).
	532	*/
	533	void __init omap_serial_init(void)
	534	{
6f251e9d	535	struct omap_uart_state *uart;
40e44399	536	struct omap_board_data bdata;
f62349ee	537
40e44399 TL	538	list_for_each_entry(uart, &uart_list, node) {
	539	bdata.id = uart->num;
	540	bdata.flags = 0;
	541	bdata.pads = NULL;
	542	bdata.pads_cnt = 0;
7496ba30 G	543
	544	if (cpu_is_omap44xx() \|\| cpu_is_omap34xx())
	545	omap_serial_fill_default_pads(&bdata);
	546
40e44399 TL	547	omap_serial_init_port(&bdata);
	548
	549	}
1dbae815	550	}