[deliverable/linux.git] / arch / arm / mach-omap2 / serial.c

/*
 * arch/arm/mach-omap2/serial.c
 *
 * OMAP2 serial support.
 *
 * Copyright (C) 2005-2008 Nokia Corporation
 * Author: Paul Mundt <paul.mundt@nokia.com>
 *
 * Major rework for PM support by Kevin Hilman
 *
 * Based off of arch/arm/mach-omap/omap1/serial.c
 *
 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/console.h>

#include <plat/omap-serial.h>
#include "common.h"
#include <plat/board.h>
#include <plat/dma.h>
#include <plat/omap_hwmod.h>
#include <plat/omap_device.h>
#include <plat/omap-pm.h>

#include "prm2xxx_3xxx.h"
#include "pm.h"
#include "cm2xxx_3xxx.h"
#include "prm-regbits-34xx.h"
#include "control.h"
#include "mux.h"

/*
 * NOTE: By default the serial timeout is disabled as it causes lost characters
 * over the serial ports. This means that the UART clocks will stay on until
 * disabled via sysfs. This also causes that any deeper omap sleep states are
 * blocked. 
 */
#define DEFAULT_TIMEOUT 0

#define MAX_UART_HWMOD_NAME_LEN		16

struct omap_uart_state {
	int num;
	int can_sleep;

	void __iomem *wk_st;
	void __iomem *wk_en;
	u32 wk_mask;

	int clocked;

	struct list_head node;
	struct omap_hwmod *oh;
	struct platform_device *pdev;
};

static LIST_HEAD(uart_list);
static u8 num_uarts;

static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
{
	if (uart->clocked)
		return;

	omap_device_enable(uart->pdev);
	uart->clocked = 1;
	omap_uart_restore_context(uart);
}

#ifdef CONFIG_PM

static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
{
	if (!uart->clocked)
		return;

	omap_uart_save_context(uart);
	uart->clocked = 0;
	omap_device_idle(uart->pdev);
}

static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
{
	/* Set wake-enable bit */
	if (uart->wk_en && uart->wk_mask) {
		u32 v = __raw_readl(uart->wk_en);
		v |= uart->wk_mask;
		__raw_writel(v, uart->wk_en);
	}
}

static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
{
	/* Clear wake-enable bit */
	if (uart->wk_en && uart->wk_mask) {
		u32 v = __raw_readl(uart->wk_en);
		v &= ~uart->wk_mask;
		__raw_writel(v, uart->wk_en);
	}
}

static void omap_uart_block_sleep(struct omap_uart_state *uart)
{
	omap_uart_enable_clocks(uart);

	omap_uart_smart_idle_enable(uart, 0);
	uart->can_sleep = 0;
}

int omap_uart_can_sleep(void)
{
	struct omap_uart_state *uart;
	int can_sleep = 1;

	list_for_each_entry(uart, &uart_list, node) {
		if (!uart->clocked)
			continue;

		if (!uart->can_sleep) {
			can_sleep = 0;
			continue;
		}

		/* This UART can now safely sleep. */
		omap_uart_allow_sleep(uart);
	}

	return can_sleep;
}

static void omap_uart_idle_init(struct omap_uart_state *uart)
{
	int ret;

	uart->can_sleep = 0;
	omap_uart_smart_idle_enable(uart, 0);

	if (cpu_is_omap34xx() && !(cpu_is_ti81xx() || cpu_is_am33xx())) {
		u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
		u32 wk_mask = 0;

		/* XXX These PRM accesses do not belong here */
		uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
		uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
		switch (uart->num) {
		case 0:
			wk_mask = OMAP3430_ST_UART1_MASK;
			break;
		case 1:
			wk_mask = OMAP3430_ST_UART2_MASK;
			break;
		case 2:
			wk_mask = OMAP3430_ST_UART3_MASK;
			break;
		case 3:
			wk_mask = OMAP3630_ST_UART4_MASK;
			break;
		}
		uart->wk_mask = wk_mask;
	} else if (cpu_is_omap24xx()) {
		u32 wk_mask = 0;
		u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;

		switch (uart->num) {
		case 0:
			wk_mask = OMAP24XX_ST_UART1_MASK;
			break;
		case 1:
			wk_mask = OMAP24XX_ST_UART2_MASK;
			break;
		case 2:
			wk_en = OMAP24XX_PM_WKEN2;
			wk_st = OMAP24XX_PM_WKST2;
			wk_mask = OMAP24XX_ST_UART3_MASK;
			break;
		}
		uart->wk_mask = wk_mask;
		if (cpu_is_omap2430()) {
			uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
			uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
		} else if (cpu_is_omap2420()) {
			uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
			uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
		}
	} else {
		uart->wk_en = NULL;
		uart->wk_st = NULL;
		uart->wk_mask = 0;
	}
}

/*
 * Errata i291: [UART]:Cannot Acknowledge Idle Requests
 * in Smartidle Mode When Configured for DMA Operations.
 * WA: configure uart in force idle mode.
 */
static void omap_uart_set_noidle(struct platform_device *pdev)
{
	struct omap_device *od = to_omap_device(pdev);

	omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO);
}

static void omap_uart_set_forceidle(struct platform_device *pdev)
{
	struct omap_device *od = to_omap_device(pdev);

	omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_FORCE);
}

#else
static void omap_uart_set_noidle(struct platform_device *pdev) {}
static void omap_uart_set_forceidle(struct platform_device *pdev) {}
static void omap_uart_block_sleep(struct omap_uart_state *uart)
{
	/* Needed to enable UART clocks when built without CONFIG_PM */
	omap_uart_enable_clocks(uart);
}
#endif /* CONFIG_PM */

#ifdef CONFIG_OMAP_MUX
static struct omap_device_pad default_uart1_pads[] __initdata = {
	{
		.name	= "uart1_cts.uart1_cts",
		.enable	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
	},
	{
		.name	= "uart1_rts.uart1_rts",
		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
	},
	{
		.name	= "uart1_tx.uart1_tx",
		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
	},
	{
		.name	= "uart1_rx.uart1_rx",
		.flags	= OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
		.enable	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
		.idle	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
	},
};

static struct omap_device_pad default_uart2_pads[] __initdata = {
	{
		.name	= "uart2_cts.uart2_cts",
		.enable	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
	},
	{
		.name	= "uart2_rts.uart2_rts",
		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
	},
	{
		.name	= "uart2_tx.uart2_tx",
		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
	},
	{
		.name	= "uart2_rx.uart2_rx",
		.flags	= OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
		.enable	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
		.idle	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
	},
};

static struct omap_device_pad default_uart3_pads[] __initdata = {
	{
		.name	= "uart3_cts_rctx.uart3_cts_rctx",
		.enable	= OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
	},
	{
		.name	= "uart3_rts_sd.uart3_rts_sd",
		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
	},
	{
		.name	= "uart3_tx_irtx.uart3_tx_irtx",
		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
	},
	{
		.name	= "uart3_rx_irrx.uart3_rx_irrx",
		.flags	= OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
		.enable	= OMAP_PIN_INPUT | OMAP_MUX_MODE0,
		.idle	= OMAP_PIN_INPUT | OMAP_MUX_MODE0,
	},
};

static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = {
	{
		.name   = "gpmc_wait2.uart4_tx",
		.enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
	},
	{
		.name	= "gpmc_wait3.uart4_rx",
		.flags	= OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
		.enable	= OMAP_PIN_INPUT | OMAP_MUX_MODE2,
		.idle	= OMAP_PIN_INPUT | OMAP_MUX_MODE2,
	},
};

static struct omap_device_pad default_omap4_uart4_pads[] __initdata = {
	{
		.name	= "uart4_tx.uart4_tx",
		.enable	= OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
	},
	{
		.name	= "uart4_rx.uart4_rx",
		.flags	= OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
		.enable	= OMAP_PIN_INPUT | OMAP_MUX_MODE0,
		.idle	= OMAP_PIN_INPUT | OMAP_MUX_MODE0,
	},
};

static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
{
	switch (bdata->id) {
	case 0:
		bdata->pads = default_uart1_pads;
		bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads);
		break;
	case 1:
		bdata->pads = default_uart2_pads;
		bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads);
		break;
	case 2:
		bdata->pads = default_uart3_pads;
		bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads);
		break;
	case 3:
		if (cpu_is_omap44xx()) {
			bdata->pads = default_omap4_uart4_pads;
			bdata->pads_cnt =
				ARRAY_SIZE(default_omap4_uart4_pads);
		} else if (cpu_is_omap3630()) {
			bdata->pads = default_omap36xx_uart4_pads;
			bdata->pads_cnt =
				ARRAY_SIZE(default_omap36xx_uart4_pads);
		}
		break;
	default:
		break;
	}
}
#else
static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
#endif

static int __init omap_serial_early_init(void)
{
	int i = 0;

	do {
		char oh_name[MAX_UART_HWMOD_NAME_LEN];
		struct omap_hwmod *oh;
		struct omap_uart_state *uart;

		snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
			 "uart%d", i + 1);
		oh = omap_hwmod_lookup(oh_name);
		if (!oh)
			break;

		uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
		if (WARN_ON(!uart))
			return -ENODEV;

		uart->oh = oh;
		uart->num = i++;
		list_add_tail(&uart->node, &uart_list);
		num_uarts++;

		/*
		 * NOTE: omap_hwmod_setup*() has not yet been called,
		 *       so no hwmod functions will work yet.
		 */

		/*
		 * During UART early init, device need to be probed
		 * to determine SoC specific init before omap_device
		 * is ready.  Therefore, don't allow idle here
		 */
		uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
	} while (1);

	return 0;
}
core_initcall(omap_serial_early_init);

/**
 * omap_serial_init_port() - initialize single serial port
 * @bdata: port specific board data pointer
 *
 * This function initialies serial driver for given port only.
 * Platforms can call this function instead of omap_serial_init()
 * if they don't plan to use all available UARTs as serial ports.
 *
 * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
 * use only one of the two.
 */
void __init omap_serial_init_port(struct omap_board_data *bdata)
{
	struct omap_uart_state *uart;
	struct omap_hwmod *oh;
	struct platform_device *pdev;
	void *pdata = NULL;
	u32 pdata_size = 0;
	char *name;
	struct omap_uart_port_info omap_up;

	if (WARN_ON(!bdata))
		return;
	if (WARN_ON(bdata->id < 0))
		return;
	if (WARN_ON(bdata->id >= num_uarts))
		return;

	list_for_each_entry(uart, &uart_list, node)
		if (bdata->id == uart->num)
			break;

	oh = uart->oh;
	name = DRIVER_NAME;

	omap_up.dma_enabled = uart->dma_enabled;
	omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
	omap_up.flags = UPF_BOOT_AUTOCONF;
	omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count;
	omap_up.set_forceidle = omap_uart_set_forceidle;
	omap_up.set_noidle = omap_uart_set_noidle;

	/* Enable the MDR1 Errata i202 for OMAP2430/3xxx/44xx */
	if (!cpu_is_omap2420() && !cpu_is_ti816x())
		omap_up.errata |= UART_ERRATA_i202_MDR1_ACCESS;

	/* Enable DMA Mode Force Idle Errata i291 for omap34xx/3630 */
	if (cpu_is_omap34xx() || cpu_is_omap3630())
		omap_up.errata |= UART_ERRATA_i291_DMA_FORCEIDLE;

	pdata = &omap_up;
	pdata_size = sizeof(struct omap_uart_port_info);

	if (WARN_ON(!oh))
		return;

	pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
				 NULL, 0, false);
	WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
	     name, oh->name);

	omap_device_disable_idle_on_suspend(pdev);
	oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);

	uart->pdev = pdev;

	oh->dev_attr = uart;

	console_lock(); /* in case the earlycon is on the UART */

	/*
	 * Because of early UART probing, UART did not get idled
	 * on init.  Now that omap_device is ready, ensure full idle
	 * before doing omap_device_enable().
	 */
	omap_hwmod_idle(uart->oh);

	omap_device_enable(uart->pdev);
	omap_uart_idle_init(uart);
	omap_hwmod_enable_wakeup(uart->oh);
	omap_device_idle(uart->pdev);

	omap_uart_block_sleep(uart);
	console_unlock();

	if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads) ||
		(pdata->wk_en && pdata->wk_mask))
		device_init_wakeup(&pdev->dev, true);
}

/**
 * omap_serial_init() - initialize all supported serial ports
 *
 * Initializes all available UARTs as serial ports. Platforms
 * can call this function when they want to have default behaviour
 * for serial ports (e.g initialize them all as serial ports).
 */
void __init omap_serial_init(void)
{
	struct omap_uart_state *uart;
	struct omap_board_data bdata;

	list_for_each_entry(uart, &uart_list, node) {
		bdata.id = uart->num;
		bdata.flags = 0;
		bdata.pads = NULL;
		bdata.pads_cnt = 0;

		if (cpu_is_omap44xx() || cpu_is_omap34xx())
			omap_serial_fill_default_pads(&bdata);

		omap_serial_init_port(&bdata);

	}
}
Commit	Line	Data
1dbae815	1	/*
f30c2269	2	* arch/arm/mach-omap2/serial.c
1dbae815 TL	3	*
	4	* OMAP2 serial support.
	5	*
6e81176d	6	* Copyright (C) 2005-2008 Nokia Corporation
1dbae815 TL	7	* Author: Paul Mundt <paul.mundt@nokia.com>
1dbae815 TL	8	*
4af4016c KH	9	* Major rework for PM support by Kevin Hilman
4af4016c KH	10	*
1dbae815 TL	11	* Based off of arch/arm/mach-omap/omap1/serial.c
1dbae815 TL	12	*
44169075 SS	13	* Copyright (C) 2009 Texas Instruments
	14	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
	15	*
1dbae815 TL	16	* This file is subject to the terms and conditions of the GNU General Public
	17	* License. See the file "COPYING" in the main directory of this archive
	18	* for more details.
	19	*/
	20	#include <linux/kernel.h>
	21	#include <linux/init.h>
f8ce2547	22	#include <linux/clk.h>
fced80c7	23	#include <linux/io.h>
e03d37d8	24	#include <linux/delay.h>
6f251e9d KH	25	#include <linux/platform_device.h>
6f251e9d KH	26	#include <linux/slab.h>
3244fcd2	27	#include <linux/pm_runtime.h>
0d8e2d0d	28	#include <linux/console.h>
6f251e9d	29
6f251e9d	30	#include <plat/omap-serial.h>
4e65331c	31	#include "common.h"
ce491cf8	32	#include <plat/board.h>
6f251e9d KH	33	#include <plat/dma.h>
	34	#include <plat/omap_hwmod.h>
	35	#include <plat/omap_device.h>
ec3bebc6	36	#include <plat/omap-pm.h>
4af4016c	37
59fb659b	38	#include "prm2xxx_3xxx.h"
4af4016c	39	#include "pm.h"
59fb659b	40	#include "cm2xxx_3xxx.h"
4af4016c	41	#include "prm-regbits-34xx.h"
4814ced5	42	#include "control.h"
40e44399	43	#include "mux.h"
4af4016c	44
301fe8ee TL	45	/*
	46	* NOTE: By default the serial timeout is disabled as it causes lost characters
	47	* over the serial ports. This means that the UART clocks will stay on until
	48	* disabled via sysfs. This also causes that any deeper omap sleep states are
	49	* blocked.
	50	*/
	51	#define DEFAULT_TIMEOUT 0
4af4016c	52
6f251e9d KH	53	#define MAX_UART_HWMOD_NAME_LEN 16
6f251e9d KH	54
4af4016c KH	55	struct omap_uart_state {
	56	int num;
	57	int can_sleep;
4af4016c KH	58
	59	void __iomem *wk_st;
	60	void __iomem *wk_en;
	61	u32 wk_mask;
4af4016c	62
4af4016c KH	63	int clocked;
4af4016c KH	64
4af4016c	65	struct list_head node;
6f251e9d KH	66	struct omap_hwmod *oh;
6f251e9d KH	67	struct platform_device *pdev;
4af4016c KH	68	};
4af4016c KH	69
4af4016c	70	static LIST_HEAD(uart_list);
6f251e9d	71	static u8 num_uarts;
1dbae815	72
4af4016c KH	73	static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
	74	{
	75	if (uart->clocked)
	76	return;
	77
6f251e9d	78	omap_device_enable(uart->pdev);
4af4016c KH	79	uart->clocked = 1;
	80	omap_uart_restore_context(uart);
	81	}
	82
	83	#ifdef CONFIG_PM
	84
	85	static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
	86	{
	87	if (!uart->clocked)
	88	return;
	89
	90	omap_uart_save_context(uart);
	91	uart->clocked = 0;
6f251e9d	92	omap_device_idle(uart->pdev);
4af4016c KH	93	}
4af4016c KH	94
fd455ea8 KH	95	static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
	96	{
	97	/* Set wake-enable bit */
	98	if (uart->wk_en && uart->wk_mask) {
	99	u32 v = __raw_readl(uart->wk_en);
	100	v \|= uart->wk_mask;
	101	__raw_writel(v, uart->wk_en);
	102	}
fd455ea8 KH	103	}
	104
	105	static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
	106	{
	107	/* Clear wake-enable bit */
	108	if (uart->wk_en && uart->wk_mask) {
	109	u32 v = __raw_readl(uart->wk_en);
	110	v &= ~uart->wk_mask;
	111	__raw_writel(v, uart->wk_en);
	112	}
fd455ea8 KH	113	}
fd455ea8 KH	114
4af4016c KH	115	static void omap_uart_block_sleep(struct omap_uart_state *uart)
	116	{
	117	omap_uart_enable_clocks(uart);
	118
	119	omap_uart_smart_idle_enable(uart, 0);
	120	uart->can_sleep = 0;
4af4016c KH	121	}
4af4016c KH	122
4af4016c KH	123	int omap_uart_can_sleep(void)
	124	{
	125	struct omap_uart_state *uart;
	126	int can_sleep = 1;
	127
	128	list_for_each_entry(uart, &uart_list, node) {
	129	if (!uart->clocked)
	130	continue;
	131
	132	if (!uart->can_sleep) {
	133	can_sleep = 0;
	134	continue;
6e81176d	135	}
4af4016c KH	136
	137	/* This UART can now safely sleep. */
	138	omap_uart_allow_sleep(uart);
6e81176d	139	}
4af4016c KH	140
4af4016c KH	141	return can_sleep;
6e81176d JH	142	}
6e81176d JH	143
4af4016c KH	144	static void omap_uart_idle_init(struct omap_uart_state *uart)
4af4016c KH	145	{
4af4016c KH	146	int ret;
	147
	148	uart->can_sleep = 0;
4af4016c KH	149	omap_uart_smart_idle_enable(uart, 0);
4af4016c KH	150
a920360f	151	if (cpu_is_omap34xx() && !(cpu_is_ti81xx() \|\| cpu_is_am33xx())) {
52663aea	152	u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
4af4016c	153	u32 wk_mask = 0;
4af4016c	154
c4d7e58f	155	/* XXX These PRM accesses do not belong here */
4af4016c KH	156	uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
	157	uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
	158	switch (uart->num) {
	159	case 0:
	160	wk_mask = OMAP3430_ST_UART1_MASK;
4af4016c KH	161	break;
	162	case 1:
	163	wk_mask = OMAP3430_ST_UART2_MASK;
4af4016c KH	164	break;
	165	case 2:
	166	wk_mask = OMAP3430_ST_UART3_MASK;
4af4016c	167	break;
52663aea G	168	case 3:
52663aea G	169	wk_mask = OMAP3630_ST_UART4_MASK;
52663aea	170	break;
4af4016c KH	171	}
4af4016c KH	172	uart->wk_mask = wk_mask;
4af4016c KH	173	} else if (cpu_is_omap24xx()) {
4af4016c KH	174	u32 wk_mask = 0;
cb74f022	175	u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
4af4016c	176
4af4016c KH	177	switch (uart->num) {
	178	case 0:
	179	wk_mask = OMAP24XX_ST_UART1_MASK;
	180	break;
	181	case 1:
	182	wk_mask = OMAP24XX_ST_UART2_MASK;
	183	break;
	184	case 2:
cb74f022 KH	185	wk_en = OMAP24XX_PM_WKEN2;
cb74f022 KH	186	wk_st = OMAP24XX_PM_WKST2;
4af4016c KH	187	wk_mask = OMAP24XX_ST_UART3_MASK;
	188	break;
	189	}
	190	uart->wk_mask = wk_mask;
cb74f022 KH	191	if (cpu_is_omap2430()) {
	192	uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
	193	uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
	194	} else if (cpu_is_omap2420()) {
	195	uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
	196	uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
	197	}
4af4016c	198	} else {
c54bae1f NM	199	uart->wk_en = NULL;
c54bae1f NM	200	uart->wk_st = NULL;
4af4016c	201	uart->wk_mask = 0;
4af4016c	202	}
ba87a9be JH	203	}
ba87a9be JH	204
94734749 G	205	/*
	206	* Errata i291: [UART]:Cannot Acknowledge Idle Requests
	207	* in Smartidle Mode When Configured for DMA Operations.
	208	* WA: configure uart in force idle mode.
	209	*/
	210	static void omap_uart_set_noidle(struct platform_device *pdev)
	211	{
	212	struct omap_device *od = to_omap_device(pdev);
	213
	214	omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO);
	215	}
	216
	217	static void omap_uart_set_forceidle(struct platform_device *pdev)
	218	{
	219	struct omap_device *od = to_omap_device(pdev);
	220
	221	omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_FORCE);
	222	}
	223
4af4016c	224	#else
94734749 G	225	static void omap_uart_set_noidle(struct platform_device *pdev) {}
94734749 G	226	static void omap_uart_set_forceidle(struct platform_device *pdev) {}
a1b04cc1 SS	227	static void omap_uart_block_sleep(struct omap_uart_state *uart)
	228	{
	229	/* Needed to enable UART clocks when built without CONFIG_PM */
	230	omap_uart_enable_clocks(uart);
	231	}
4af4016c KH	232	#endif /* CONFIG_PM */
4af4016c KH	233
7496ba30 G	234	#ifdef CONFIG_OMAP_MUX
	235	static struct omap_device_pad default_uart1_pads[] __initdata = {
	236	{
	237	.name = "uart1_cts.uart1_cts",
	238	.enable = OMAP_PIN_INPUT_PULLUP \| OMAP_MUX_MODE0,
	239	},
	240	{
	241	.name = "uart1_rts.uart1_rts",
	242	.enable = OMAP_PIN_OUTPUT \| OMAP_MUX_MODE0,
	243	},
	244	{
	245	.name = "uart1_tx.uart1_tx",
	246	.enable = OMAP_PIN_OUTPUT \| OMAP_MUX_MODE0,
	247	},
	248	{
	249	.name = "uart1_rx.uart1_rx",
	250	.flags = OMAP_DEVICE_PAD_REMUX \| OMAP_DEVICE_PAD_WAKEUP,
	251	.enable = OMAP_PIN_INPUT_PULLUP \| OMAP_MUX_MODE0,
	252	.idle = OMAP_PIN_INPUT_PULLUP \| OMAP_MUX_MODE0,
	253	},
	254	};
	255
	256	static struct omap_device_pad default_uart2_pads[] __initdata = {
	257	{
	258	.name = "uart2_cts.uart2_cts",
	259	.enable = OMAP_PIN_INPUT_PULLUP \| OMAP_MUX_MODE0,
	260	},
	261	{
	262	.name = "uart2_rts.uart2_rts",
	263	.enable = OMAP_PIN_OUTPUT \| OMAP_MUX_MODE0,
	264	},
	265	{
	266	.name = "uart2_tx.uart2_tx",
	267	.enable = OMAP_PIN_OUTPUT \| OMAP_MUX_MODE0,
	268	},
	269	{
	270	.name = "uart2_rx.uart2_rx",
	271	.flags = OMAP_DEVICE_PAD_REMUX \| OMAP_DEVICE_PAD_WAKEUP,
	272	.enable = OMAP_PIN_INPUT_PULLUP \| OMAP_MUX_MODE0,
	273	.idle = OMAP_PIN_INPUT_PULLUP \| OMAP_MUX_MODE0,
	274	},
	275	};
	276
	277	static struct omap_device_pad default_uart3_pads[] __initdata = {
	278	{
	279	.name = "uart3_cts_rctx.uart3_cts_rctx",
	280	.enable = OMAP_PIN_INPUT_PULLUP \| OMAP_MUX_MODE0,
	281	},
	282	{
	283	.name = "uart3_rts_sd.uart3_rts_sd",
	284	.enable = OMAP_PIN_OUTPUT \| OMAP_MUX_MODE0,
	285	},
	286	{
	287	.name = "uart3_tx_irtx.uart3_tx_irtx",
	288	.enable = OMAP_PIN_OUTPUT \| OMAP_MUX_MODE0,
	289	},
	290	{
	291	.name = "uart3_rx_irrx.uart3_rx_irrx",
	292	.flags = OMAP_DEVICE_PAD_REMUX \| OMAP_DEVICE_PAD_WAKEUP,
	293	.enable = OMAP_PIN_INPUT \| OMAP_MUX_MODE0,
	294	.idle = OMAP_PIN_INPUT \| OMAP_MUX_MODE0,
	295	},
	296	};
	297
298	static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = {
299	{
300	.name = "gpmc_wait2.uart4_tx",
301	.enable = OMAP_PIN_OUTPUT \| OMAP_MUX_MODE0,
302	},
303	{
304	.name = "gpmc_wait3.uart4_rx",
305	.flags = OMAP_DEVICE_PAD_REMUX \| OMAP_DEVICE_PAD_WAKEUP,
306	.enable = OMAP_PIN_INPUT \| OMAP_MUX_MODE2,
307	.idle = OMAP_PIN_INPUT \| OMAP_MUX_MODE2,
308	},
309	};
310
311	static struct omap_device_pad default_omap4_uart4_pads[] __initdata = {
312	{
313	.name = "uart4_tx.uart4_tx",
314	.enable = OMAP_PIN_OUTPUT \| OMAP_MUX_MODE0,
315	},
316	{
317	.name = "uart4_rx.uart4_rx",
318	.flags = OMAP_DEVICE_PAD_REMUX \| OMAP_DEVICE_PAD_WAKEUP,
319	.enable = OMAP_PIN_INPUT \| OMAP_MUX_MODE0,
320	.idle = OMAP_PIN_INPUT \| OMAP_MUX_MODE0,
321	},
322	};
323
324	static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
325	{
326	switch (bdata->id) {
327	case 0:
328	bdata->pads = default_uart1_pads;
329	bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads);
330	break;
331	case 1:
332	bdata->pads = default_uart2_pads;
333	bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads);
334	break;
335	case 2:
336	bdata->pads = default_uart3_pads;
337	bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads);
338	break;
339	case 3:
340	if (cpu_is_omap44xx()) {
341	bdata->pads = default_omap4_uart4_pads;
342	bdata->pads_cnt =
343	ARRAY_SIZE(default_omap4_uart4_pads);
344	} else if (cpu_is_omap3630()) {
345	bdata->pads = default_omap36xx_uart4_pads;
346	bdata->pads_cnt =
347	ARRAY_SIZE(default_omap36xx_uart4_pads);
348	}
349	break;
350	default:
351	break;
352	}
353	}
354	#else
355	static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
356	#endif
357
3e16f925	358	static int __init omap_serial_early_init(void)
1dbae815	359	{
6f251e9d	360	int i = 0;
1dbae815	361
6f251e9d KH	362	do {
	363	char oh_name[MAX_UART_HWMOD_NAME_LEN];
	364	struct omap_hwmod *oh;
	365	struct omap_uart_state *uart;
21b90340	366
6f251e9d KH	367	snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
	368	"uart%d", i + 1);
	369	oh = omap_hwmod_lookup(oh_name);
	370	if (!oh)
	371	break;
	372
	373	uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
	374	if (WARN_ON(!uart))
3e16f925	375	return -ENODEV;
1dbae815	376
6f251e9d KH	377	uart->oh = oh;
	378	uart->num = i++;
	379	list_add_tail(&uart->node, &uart_list);
	380	num_uarts++;
1dbae815	381
84f90c9c	382	/*
550c8092	383	* NOTE: omap_hwmod_setup*() has not yet been called,
6f251e9d	384	* so no hwmod functions will work yet.
84f90c9c	385	*/
6e81176d	386
6f251e9d KH	387	/*
	388	* During UART early init, device need to be probed
	389	* to determine SoC specific init before omap_device
	390	* is ready. Therefore, don't allow idle here
	391	*/
	392	uart->oh->flags \|= HWMOD_INIT_NO_IDLE \| HWMOD_INIT_NO_RESET;
	393	} while (1);
3e16f925 TL	394
3e16f925 TL	395	return 0;
b3c6df3a	396	}
3e16f925	397	core_initcall(omap_serial_early_init);
b3c6df3a	398
f62349ee MW	399	/**
f62349ee MW	400	* omap_serial_init_port() - initialize single serial port
40e44399	401	* @bdata: port specific board data pointer
f62349ee	402	*
40e44399	403	* This function initialies serial driver for given port only.
f62349ee MW	404	* Platforms can call this function instead of omap_serial_init()
	405	* if they don't plan to use all available UARTs as serial ports.
	406	*
	407	* Don't mix calls to omap_serial_init_port() and omap_serial_init(),
	408	* use only one of the two.
	409	*/
40e44399	410	void __init omap_serial_init_port(struct omap_board_data *bdata)
b3c6df3a	411	{
f62349ee	412	struct omap_uart_state *uart;
6f251e9d	413	struct omap_hwmod *oh;
3528c58e	414	struct platform_device *pdev;
6f251e9d KH	415	void *pdata = NULL;
	416	u32 pdata_size = 0;
	417	char *name;
6f251e9d	418	struct omap_uart_port_info omap_up;
970a724d	419
40e44399	420	if (WARN_ON(!bdata))
6f251e9d	421	return;
40e44399 TL	422	if (WARN_ON(bdata->id < 0))
	423	return;
	424	if (WARN_ON(bdata->id >= num_uarts))
e88d556d	425	return;
f62349ee	426
6f251e9d	427	list_for_each_entry(uart, &uart_list, node)
40e44399	428	if (bdata->id == uart->num)
6f251e9d	429	break;
f2eeeae0	430
6f251e9d	431	oh = uart->oh;
6f251e9d KH	432	name = DRIVER_NAME;
	433
	434	omap_up.dma_enabled = uart->dma_enabled;
	435	omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
273558b3	436	omap_up.flags = UPF_BOOT_AUTOCONF;
ec3bebc6	437	omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count;
94734749 G	438	omap_up.set_forceidle = omap_uart_set_forceidle;
	439	omap_up.set_noidle = omap_uart_set_noidle;
	440
	441	/* Enable the MDR1 Errata i202 for OMAP2430/3xxx/44xx */
	442	if (!cpu_is_omap2420() && !cpu_is_ti816x())
	443	omap_up.errata \|= UART_ERRATA_i202_MDR1_ACCESS;
	444
	445	/* Enable DMA Mode Force Idle Errata i291 for omap34xx/3630 */
	446	if (cpu_is_omap34xx() \|\| cpu_is_omap3630())
	447	omap_up.errata \|= UART_ERRATA_i291_DMA_FORCEIDLE;
6f251e9d KH	448
	449	pdata = &omap_up;
	450	pdata_size = sizeof(struct omap_uart_port_info);
6f251e9d KH	451
	452	if (WARN_ON(!oh))
	453	return;
	454
3528c58e	455	pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
f718e2c0	456	NULL, 0, false);
3528c58e	457	WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
6f251e9d KH	458	name, oh->name);
6f251e9d KH	459
9f8b6949	460	omap_device_disable_idle_on_suspend(pdev);
40e44399 TL	461	oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
40e44399 TL	462
3528c58e	463	uart->pdev = pdev;
6f251e9d KH	464
	465	oh->dev_attr = uart;
	466
ac751efa	467	console_lock(); /* in case the earlycon is on the UART */
0d8e2d0d	468
6f251e9d KH	469	/*
	470	* Because of early UART probing, UART did not get idled
	471	* on init. Now that omap_device is ready, ensure full idle
	472	* before doing omap_device_enable().
	473	*/
	474	omap_hwmod_idle(uart->oh);
	475
	476	omap_device_enable(uart->pdev);
	477	omap_uart_idle_init(uart);
6f251e9d KH	478	omap_hwmod_enable_wakeup(uart->oh);
	479	omap_device_idle(uart->pdev);
	480
6f251e9d	481	omap_uart_block_sleep(uart);
ac751efa	482	console_unlock();
0d8e2d0d	483
7496ba30 G	484	if (((cpu_is_omap34xx() \|\| cpu_is_omap44xx()) && bdata->pads) \|\|
7496ba30 G	485	(pdata->wk_en && pdata->wk_mask))
3528c58e	486	device_init_wakeup(&pdev->dev, true);
f62349ee MW	487	}
	488
	489	/**
b595076a	490	* omap_serial_init() - initialize all supported serial ports
f62349ee MW	491	*
	492	* Initializes all available UARTs as serial ports. Platforms
	493	* can call this function when they want to have default behaviour
	494	* for serial ports (e.g initialize them all as serial ports).
	495	*/
	496	void __init omap_serial_init(void)
	497	{
6f251e9d	498	struct omap_uart_state *uart;
40e44399	499	struct omap_board_data bdata;
f62349ee	500
40e44399 TL	501	list_for_each_entry(uart, &uart_list, node) {
	502	bdata.id = uart->num;
	503	bdata.flags = 0;
	504	bdata.pads = NULL;
	505	bdata.pads_cnt = 0;
7496ba30 G	506
	507	if (cpu_is_omap44xx() \|\| cpu_is_omap34xx())
	508	omap_serial_fill_default_pads(&bdata);
	509
40e44399 TL	510	omap_serial_init_port(&bdata);
	511
	512	}
1dbae815	513	}