Commit | Line | Data |
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1dbae815 | 1 | /* |
f30c2269 | 2 | * arch/arm/mach-omap2/serial.c |
1dbae815 TL |
3 | * |
4 | * OMAP2 serial support. | |
5 | * | |
6e81176d | 6 | * Copyright (C) 2005-2008 Nokia Corporation |
1dbae815 TL |
7 | * Author: Paul Mundt <paul.mundt@nokia.com> |
8 | * | |
4af4016c KH |
9 | * Major rework for PM support by Kevin Hilman |
10 | * | |
1dbae815 TL |
11 | * Based off of arch/arm/mach-omap/omap1/serial.c |
12 | * | |
44169075 SS |
13 | * Copyright (C) 2009 Texas Instruments |
14 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com | |
15 | * | |
1dbae815 TL |
16 | * This file is subject to the terms and conditions of the GNU General Public |
17 | * License. See the file "COPYING" in the main directory of this archive | |
18 | * for more details. | |
19 | */ | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/serial_8250.h> | |
23 | #include <linux/serial_reg.h> | |
f8ce2547 | 24 | #include <linux/clk.h> |
fced80c7 | 25 | #include <linux/io.h> |
e03d37d8 | 26 | #include <linux/delay.h> |
1dbae815 | 27 | |
ce491cf8 TL |
28 | #include <plat/common.h> |
29 | #include <plat/board.h> | |
30 | #include <plat/clock.h> | |
31 | #include <plat/control.h> | |
4af4016c KH |
32 | |
33 | #include "prm.h" | |
34 | #include "pm.h" | |
35 | #include "prm-regbits-34xx.h" | |
36 | ||
ce13d471 | 37 | #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 |
4af4016c KH |
38 | #define UART_OMAP_WER 0x17 /* Wake-up enable register */ |
39 | ||
301fe8ee TL |
40 | /* |
41 | * NOTE: By default the serial timeout is disabled as it causes lost characters | |
42 | * over the serial ports. This means that the UART clocks will stay on until | |
43 | * disabled via sysfs. This also causes that any deeper omap sleep states are | |
44 | * blocked. | |
45 | */ | |
46 | #define DEFAULT_TIMEOUT 0 | |
4af4016c KH |
47 | |
48 | struct omap_uart_state { | |
49 | int num; | |
50 | int can_sleep; | |
51 | struct timer_list timer; | |
52 | u32 timeout; | |
53 | ||
54 | void __iomem *wk_st; | |
55 | void __iomem *wk_en; | |
56 | u32 wk_mask; | |
57 | u32 padconf; | |
58 | ||
59 | struct clk *ick; | |
60 | struct clk *fck; | |
61 | int clocked; | |
62 | ||
63 | struct plat_serial8250_port *p; | |
64 | struct list_head node; | |
fd455ea8 | 65 | struct platform_device pdev; |
1dbae815 | 66 | |
4af4016c KH |
67 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) |
68 | int context_valid; | |
69 | ||
70 | /* Registers to be saved/restored for OFF-mode */ | |
71 | u16 dll; | |
72 | u16 dlh; | |
73 | u16 ier; | |
74 | u16 sysc; | |
75 | u16 scr; | |
76 | u16 wer; | |
77 | #endif | |
78 | }; | |
79 | ||
4af4016c | 80 | static LIST_HEAD(uart_list); |
1dbae815 | 81 | |
fd455ea8 | 82 | static struct plat_serial8250_port serial_platform_data0[] = { |
1dbae815 | 83 | { |
1dbae815 TL |
84 | .irq = 72, |
85 | .flags = UPF_BOOT_AUTOCONF, | |
86 | .iotype = UPIO_MEM, | |
87 | .regshift = 2, | |
6e81176d | 88 | .uartclk = OMAP24XX_BASE_BAUD * 16, |
1dbae815 | 89 | }, { |
fd455ea8 KH |
90 | .flags = 0 |
91 | } | |
92 | }; | |
93 | ||
94 | static struct plat_serial8250_port serial_platform_data1[] = { | |
95 | { | |
1dbae815 TL |
96 | .irq = 73, |
97 | .flags = UPF_BOOT_AUTOCONF, | |
98 | .iotype = UPIO_MEM, | |
99 | .regshift = 2, | |
6e81176d | 100 | .uartclk = OMAP24XX_BASE_BAUD * 16, |
1dbae815 | 101 | }, { |
fd455ea8 KH |
102 | .flags = 0 |
103 | } | |
104 | }; | |
105 | ||
106 | static struct plat_serial8250_port serial_platform_data2[] = { | |
107 | { | |
1dbae815 TL |
108 | .irq = 74, |
109 | .flags = UPF_BOOT_AUTOCONF, | |
110 | .iotype = UPIO_MEM, | |
111 | .regshift = 2, | |
6e81176d | 112 | .uartclk = OMAP24XX_BASE_BAUD * 16, |
1dbae815 TL |
113 | }, { |
114 | .flags = 0 | |
115 | } | |
116 | }; | |
117 | ||
a3a9b36e | 118 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
0e3eaadf SS |
119 | static struct plat_serial8250_port serial_platform_data3[] = { |
120 | { | |
0e3eaadf SS |
121 | .irq = 70, |
122 | .flags = UPF_BOOT_AUTOCONF, | |
123 | .iotype = UPIO_MEM, | |
124 | .regshift = 2, | |
125 | .uartclk = OMAP24XX_BASE_BAUD * 16, | |
126 | }, { | |
127 | .flags = 0 | |
128 | } | |
129 | }; | |
a3a9b36e TL |
130 | |
131 | static inline void omap2_set_globals_uart4(struct omap_globals *omap2_globals) | |
132 | { | |
133 | serial_platform_data3[0].mapbase = omap2_globals->uart4_phys; | |
134 | } | |
135 | #else | |
136 | static inline void omap2_set_globals_uart4(struct omap_globals *omap2_globals) | |
137 | { | |
138 | } | |
0e3eaadf | 139 | #endif |
4f2c49fe TL |
140 | |
141 | void __init omap2_set_globals_uart(struct omap_globals *omap2_globals) | |
142 | { | |
143 | serial_platform_data0[0].mapbase = omap2_globals->uart1_phys; | |
144 | serial_platform_data1[0].mapbase = omap2_globals->uart2_phys; | |
145 | serial_platform_data2[0].mapbase = omap2_globals->uart3_phys; | |
a3a9b36e TL |
146 | if (cpu_is_omap3630() || cpu_is_omap44xx()) |
147 | omap2_set_globals_uart4(omap2_globals); | |
4f2c49fe TL |
148 | } |
149 | ||
9230372a AS |
150 | static inline unsigned int __serial_read_reg(struct uart_port *up, |
151 | int offset) | |
152 | { | |
153 | offset <<= up->regshift; | |
154 | return (unsigned int)__raw_readb(up->membase + offset); | |
155 | } | |
156 | ||
1dbae815 TL |
157 | static inline unsigned int serial_read_reg(struct plat_serial8250_port *up, |
158 | int offset) | |
159 | { | |
160 | offset <<= up->regshift; | |
161 | return (unsigned int)__raw_readb(up->membase + offset); | |
162 | } | |
163 | ||
e03d37d8 SS |
164 | static inline void __serial_write_reg(struct uart_port *up, int offset, |
165 | int value) | |
166 | { | |
167 | offset <<= up->regshift; | |
168 | __raw_writeb(value, up->membase + offset); | |
169 | } | |
170 | ||
1dbae815 TL |
171 | static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, |
172 | int value) | |
173 | { | |
174 | offset <<= p->regshift; | |
e8a91c95 | 175 | __raw_writeb(value, p->membase + offset); |
1dbae815 TL |
176 | } |
177 | ||
178 | /* | |
179 | * Internal UARTs need to be initialized for the 8250 autoconfig to work | |
180 | * properly. Note that the TX watermark initialization may not be needed | |
181 | * once the 8250.c watermark handling code is merged. | |
182 | */ | |
4af4016c | 183 | static inline void __init omap_uart_reset(struct omap_uart_state *uart) |
1dbae815 | 184 | { |
4af4016c KH |
185 | struct plat_serial8250_port *p = uart->p; |
186 | ||
1dbae815 TL |
187 | serial_write_reg(p, UART_OMAP_MDR1, 0x07); |
188 | serial_write_reg(p, UART_OMAP_SCR, 0x08); | |
189 | serial_write_reg(p, UART_OMAP_MDR1, 0x00); | |
671c7235 | 190 | serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0)); |
1dbae815 TL |
191 | } |
192 | ||
4af4016c KH |
193 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) |
194 | ||
4af4016c | 195 | static void omap_uart_save_context(struct omap_uart_state *uart) |
6e81176d | 196 | { |
4af4016c KH |
197 | u16 lcr = 0; |
198 | struct plat_serial8250_port *p = uart->p; | |
199 | ||
200 | if (!enable_off_mode) | |
201 | return; | |
202 | ||
203 | lcr = serial_read_reg(p, UART_LCR); | |
204 | serial_write_reg(p, UART_LCR, 0xBF); | |
205 | uart->dll = serial_read_reg(p, UART_DLL); | |
206 | uart->dlh = serial_read_reg(p, UART_DLM); | |
207 | serial_write_reg(p, UART_LCR, lcr); | |
208 | uart->ier = serial_read_reg(p, UART_IER); | |
209 | uart->sysc = serial_read_reg(p, UART_OMAP_SYSC); | |
210 | uart->scr = serial_read_reg(p, UART_OMAP_SCR); | |
211 | uart->wer = serial_read_reg(p, UART_OMAP_WER); | |
212 | ||
213 | uart->context_valid = 1; | |
214 | } | |
215 | ||
216 | static void omap_uart_restore_context(struct omap_uart_state *uart) | |
217 | { | |
218 | u16 efr = 0; | |
219 | struct plat_serial8250_port *p = uart->p; | |
220 | ||
221 | if (!enable_off_mode) | |
222 | return; | |
223 | ||
224 | if (!uart->context_valid) | |
225 | return; | |
226 | ||
227 | uart->context_valid = 0; | |
228 | ||
229 | serial_write_reg(p, UART_OMAP_MDR1, 0x7); | |
230 | serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ | |
231 | efr = serial_read_reg(p, UART_EFR); | |
232 | serial_write_reg(p, UART_EFR, UART_EFR_ECB); | |
233 | serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ | |
234 | serial_write_reg(p, UART_IER, 0x0); | |
235 | serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ | |
236 | serial_write_reg(p, UART_DLL, uart->dll); | |
237 | serial_write_reg(p, UART_DLM, uart->dlh); | |
238 | serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ | |
239 | serial_write_reg(p, UART_IER, uart->ier); | |
240 | serial_write_reg(p, UART_FCR, 0xA1); | |
241 | serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ | |
242 | serial_write_reg(p, UART_EFR, efr); | |
243 | serial_write_reg(p, UART_LCR, UART_LCR_WLEN8); | |
244 | serial_write_reg(p, UART_OMAP_SCR, uart->scr); | |
245 | serial_write_reg(p, UART_OMAP_WER, uart->wer); | |
246 | serial_write_reg(p, UART_OMAP_SYSC, uart->sysc); | |
247 | serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */ | |
248 | } | |
249 | #else | |
250 | static inline void omap_uart_save_context(struct omap_uart_state *uart) {} | |
251 | static inline void omap_uart_restore_context(struct omap_uart_state *uart) {} | |
252 | #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */ | |
253 | ||
254 | static inline void omap_uart_enable_clocks(struct omap_uart_state *uart) | |
255 | { | |
256 | if (uart->clocked) | |
257 | return; | |
258 | ||
259 | clk_enable(uart->ick); | |
260 | clk_enable(uart->fck); | |
261 | uart->clocked = 1; | |
262 | omap_uart_restore_context(uart); | |
263 | } | |
264 | ||
265 | #ifdef CONFIG_PM | |
266 | ||
267 | static inline void omap_uart_disable_clocks(struct omap_uart_state *uart) | |
268 | { | |
269 | if (!uart->clocked) | |
270 | return; | |
271 | ||
272 | omap_uart_save_context(uart); | |
273 | uart->clocked = 0; | |
274 | clk_disable(uart->ick); | |
275 | clk_disable(uart->fck); | |
276 | } | |
277 | ||
fd455ea8 KH |
278 | static void omap_uart_enable_wakeup(struct omap_uart_state *uart) |
279 | { | |
280 | /* Set wake-enable bit */ | |
281 | if (uart->wk_en && uart->wk_mask) { | |
282 | u32 v = __raw_readl(uart->wk_en); | |
283 | v |= uart->wk_mask; | |
284 | __raw_writel(v, uart->wk_en); | |
285 | } | |
286 | ||
287 | /* Ensure IOPAD wake-enables are set */ | |
288 | if (cpu_is_omap34xx() && uart->padconf) { | |
289 | u16 v = omap_ctrl_readw(uart->padconf); | |
290 | v |= OMAP3_PADCONF_WAKEUPENABLE0; | |
291 | omap_ctrl_writew(v, uart->padconf); | |
292 | } | |
293 | } | |
294 | ||
295 | static void omap_uart_disable_wakeup(struct omap_uart_state *uart) | |
296 | { | |
297 | /* Clear wake-enable bit */ | |
298 | if (uart->wk_en && uart->wk_mask) { | |
299 | u32 v = __raw_readl(uart->wk_en); | |
300 | v &= ~uart->wk_mask; | |
301 | __raw_writel(v, uart->wk_en); | |
302 | } | |
303 | ||
304 | /* Ensure IOPAD wake-enables are cleared */ | |
305 | if (cpu_is_omap34xx() && uart->padconf) { | |
306 | u16 v = omap_ctrl_readw(uart->padconf); | |
307 | v &= ~OMAP3_PADCONF_WAKEUPENABLE0; | |
308 | omap_ctrl_writew(v, uart->padconf); | |
309 | } | |
310 | } | |
311 | ||
4af4016c KH |
312 | static void omap_uart_smart_idle_enable(struct omap_uart_state *uart, |
313 | int enable) | |
314 | { | |
315 | struct plat_serial8250_port *p = uart->p; | |
316 | u16 sysc; | |
317 | ||
318 | sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7; | |
319 | if (enable) | |
320 | sysc |= 0x2 << 3; | |
321 | else | |
322 | sysc |= 0x1 << 3; | |
323 | ||
324 | serial_write_reg(p, UART_OMAP_SYSC, sysc); | |
325 | } | |
326 | ||
327 | static void omap_uart_block_sleep(struct omap_uart_state *uart) | |
328 | { | |
329 | omap_uart_enable_clocks(uart); | |
330 | ||
331 | omap_uart_smart_idle_enable(uart, 0); | |
332 | uart->can_sleep = 0; | |
ba87a9be JH |
333 | if (uart->timeout) |
334 | mod_timer(&uart->timer, jiffies + uart->timeout); | |
335 | else | |
336 | del_timer(&uart->timer); | |
4af4016c KH |
337 | } |
338 | ||
339 | static void omap_uart_allow_sleep(struct omap_uart_state *uart) | |
340 | { | |
fd455ea8 KH |
341 | if (device_may_wakeup(&uart->pdev.dev)) |
342 | omap_uart_enable_wakeup(uart); | |
343 | else | |
344 | omap_uart_disable_wakeup(uart); | |
345 | ||
4af4016c KH |
346 | if (!uart->clocked) |
347 | return; | |
348 | ||
349 | omap_uart_smart_idle_enable(uart, 1); | |
350 | uart->can_sleep = 1; | |
351 | del_timer(&uart->timer); | |
352 | } | |
353 | ||
354 | static void omap_uart_idle_timer(unsigned long data) | |
355 | { | |
356 | struct omap_uart_state *uart = (struct omap_uart_state *)data; | |
357 | ||
358 | omap_uart_allow_sleep(uart); | |
359 | } | |
360 | ||
361 | void omap_uart_prepare_idle(int num) | |
362 | { | |
363 | struct omap_uart_state *uart; | |
364 | ||
365 | list_for_each_entry(uart, &uart_list, node) { | |
366 | if (num == uart->num && uart->can_sleep) { | |
367 | omap_uart_disable_clocks(uart); | |
368 | return; | |
369 | } | |
370 | } | |
371 | } | |
372 | ||
373 | void omap_uart_resume_idle(int num) | |
374 | { | |
375 | struct omap_uart_state *uart; | |
376 | ||
377 | list_for_each_entry(uart, &uart_list, node) { | |
378 | if (num == uart->num) { | |
379 | omap_uart_enable_clocks(uart); | |
380 | ||
381 | /* Check for IO pad wakeup */ | |
382 | if (cpu_is_omap34xx() && uart->padconf) { | |
383 | u16 p = omap_ctrl_readw(uart->padconf); | |
384 | ||
385 | if (p & OMAP3_PADCONF_WAKEUPEVENT0) | |
386 | omap_uart_block_sleep(uart); | |
6e81176d | 387 | } |
4af4016c KH |
388 | |
389 | /* Check for normal UART wakeup */ | |
390 | if (__raw_readl(uart->wk_st) & uart->wk_mask) | |
391 | omap_uart_block_sleep(uart); | |
4af4016c KH |
392 | return; |
393 | } | |
394 | } | |
395 | } | |
396 | ||
397 | void omap_uart_prepare_suspend(void) | |
398 | { | |
399 | struct omap_uart_state *uart; | |
400 | ||
401 | list_for_each_entry(uart, &uart_list, node) { | |
402 | omap_uart_allow_sleep(uart); | |
403 | } | |
404 | } | |
405 | ||
406 | int omap_uart_can_sleep(void) | |
407 | { | |
408 | struct omap_uart_state *uart; | |
409 | int can_sleep = 1; | |
410 | ||
411 | list_for_each_entry(uart, &uart_list, node) { | |
412 | if (!uart->clocked) | |
413 | continue; | |
414 | ||
415 | if (!uart->can_sleep) { | |
416 | can_sleep = 0; | |
417 | continue; | |
6e81176d | 418 | } |
4af4016c KH |
419 | |
420 | /* This UART can now safely sleep. */ | |
421 | omap_uart_allow_sleep(uart); | |
6e81176d | 422 | } |
4af4016c KH |
423 | |
424 | return can_sleep; | |
6e81176d JH |
425 | } |
426 | ||
4af4016c KH |
427 | /** |
428 | * omap_uart_interrupt() | |
429 | * | |
430 | * This handler is used only to detect that *any* UART interrupt has | |
431 | * occurred. It does _nothing_ to handle the interrupt. Rather, | |
432 | * any UART interrupt will trigger the inactivity timer so the | |
433 | * UART will not idle or sleep for its timeout period. | |
434 | * | |
435 | **/ | |
436 | static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) | |
437 | { | |
438 | struct omap_uart_state *uart = dev_id; | |
439 | ||
440 | omap_uart_block_sleep(uart); | |
441 | ||
442 | return IRQ_NONE; | |
443 | } | |
444 | ||
445 | static void omap_uart_idle_init(struct omap_uart_state *uart) | |
446 | { | |
4af4016c KH |
447 | struct plat_serial8250_port *p = uart->p; |
448 | int ret; | |
449 | ||
450 | uart->can_sleep = 0; | |
fd455ea8 | 451 | uart->timeout = DEFAULT_TIMEOUT; |
4af4016c KH |
452 | setup_timer(&uart->timer, omap_uart_idle_timer, |
453 | (unsigned long) uart); | |
301fe8ee TL |
454 | if (uart->timeout) |
455 | mod_timer(&uart->timer, jiffies + uart->timeout); | |
4af4016c KH |
456 | omap_uart_smart_idle_enable(uart, 0); |
457 | ||
458 | if (cpu_is_omap34xx()) { | |
459 | u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD; | |
460 | u32 wk_mask = 0; | |
461 | u32 padconf = 0; | |
462 | ||
463 | uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1); | |
464 | uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1); | |
465 | switch (uart->num) { | |
466 | case 0: | |
467 | wk_mask = OMAP3430_ST_UART1_MASK; | |
468 | padconf = 0x182; | |
469 | break; | |
470 | case 1: | |
471 | wk_mask = OMAP3430_ST_UART2_MASK; | |
472 | padconf = 0x17a; | |
473 | break; | |
474 | case 2: | |
475 | wk_mask = OMAP3430_ST_UART3_MASK; | |
476 | padconf = 0x19e; | |
477 | break; | |
478 | } | |
479 | uart->wk_mask = wk_mask; | |
480 | uart->padconf = padconf; | |
481 | } else if (cpu_is_omap24xx()) { | |
482 | u32 wk_mask = 0; | |
483 | ||
484 | if (cpu_is_omap2430()) { | |
485 | uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1); | |
486 | uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1); | |
487 | } else if (cpu_is_omap2420()) { | |
488 | uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1); | |
489 | uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1); | |
490 | } | |
491 | switch (uart->num) { | |
492 | case 0: | |
493 | wk_mask = OMAP24XX_ST_UART1_MASK; | |
494 | break; | |
495 | case 1: | |
496 | wk_mask = OMAP24XX_ST_UART2_MASK; | |
497 | break; | |
498 | case 2: | |
499 | wk_mask = OMAP24XX_ST_UART3_MASK; | |
500 | break; | |
501 | } | |
502 | uart->wk_mask = wk_mask; | |
503 | } else { | |
504 | uart->wk_en = 0; | |
505 | uart->wk_st = 0; | |
506 | uart->wk_mask = 0; | |
507 | uart->padconf = 0; | |
508 | } | |
509 | ||
c426df87 | 510 | p->irqflags |= IRQF_SHARED; |
4af4016c KH |
511 | ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED, |
512 | "serial idle", (void *)uart); | |
513 | WARN_ON(ret); | |
514 | } | |
515 | ||
2466211e TK |
516 | void omap_uart_enable_irqs(int enable) |
517 | { | |
518 | int ret; | |
519 | struct omap_uart_state *uart; | |
520 | ||
521 | list_for_each_entry(uart, &uart_list, node) { | |
522 | if (enable) | |
523 | ret = request_irq(uart->p->irq, omap_uart_interrupt, | |
524 | IRQF_SHARED, "serial idle", (void *)uart); | |
525 | else | |
526 | free_irq(uart->p->irq, (void *)uart); | |
527 | } | |
528 | } | |
529 | ||
fd455ea8 KH |
530 | static ssize_t sleep_timeout_show(struct device *dev, |
531 | struct device_attribute *attr, | |
ba87a9be JH |
532 | char *buf) |
533 | { | |
fd455ea8 KH |
534 | struct platform_device *pdev = container_of(dev, |
535 | struct platform_device, dev); | |
536 | struct omap_uart_state *uart = container_of(pdev, | |
537 | struct omap_uart_state, pdev); | |
538 | ||
539 | return sprintf(buf, "%u\n", uart->timeout / HZ); | |
ba87a9be JH |
540 | } |
541 | ||
fd455ea8 KH |
542 | static ssize_t sleep_timeout_store(struct device *dev, |
543 | struct device_attribute *attr, | |
ba87a9be JH |
544 | const char *buf, size_t n) |
545 | { | |
fd455ea8 KH |
546 | struct platform_device *pdev = container_of(dev, |
547 | struct platform_device, dev); | |
548 | struct omap_uart_state *uart = container_of(pdev, | |
549 | struct omap_uart_state, pdev); | |
ba87a9be JH |
550 | unsigned int value; |
551 | ||
552 | if (sscanf(buf, "%u", &value) != 1) { | |
553 | printk(KERN_ERR "sleep_timeout_store: Invalid value\n"); | |
554 | return -EINVAL; | |
555 | } | |
fd455ea8 KH |
556 | |
557 | uart->timeout = value * HZ; | |
558 | if (uart->timeout) | |
559 | mod_timer(&uart->timer, jiffies + uart->timeout); | |
560 | else | |
561 | /* A zero value means disable timeout feature */ | |
562 | omap_uart_block_sleep(uart); | |
563 | ||
ba87a9be JH |
564 | return n; |
565 | } | |
566 | ||
fd455ea8 KH |
567 | DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store); |
568 | #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr)) | |
4af4016c KH |
569 | #else |
570 | static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} | |
fd455ea8 | 571 | #define DEV_CREATE_FILE(dev, attr) |
4af4016c KH |
572 | #endif /* CONFIG_PM */ |
573 | ||
9d30b99f | 574 | static struct omap_uart_state omap_uart[] = { |
fd455ea8 KH |
575 | { |
576 | .pdev = { | |
577 | .name = "serial8250", | |
578 | .id = PLAT8250_DEV_PLATFORM, | |
579 | .dev = { | |
580 | .platform_data = serial_platform_data0, | |
581 | }, | |
582 | }, | |
583 | }, { | |
584 | .pdev = { | |
585 | .name = "serial8250", | |
586 | .id = PLAT8250_DEV_PLATFORM1, | |
587 | .dev = { | |
588 | .platform_data = serial_platform_data1, | |
589 | }, | |
590 | }, | |
591 | }, { | |
592 | .pdev = { | |
593 | .name = "serial8250", | |
594 | .id = PLAT8250_DEV_PLATFORM2, | |
595 | .dev = { | |
596 | .platform_data = serial_platform_data2, | |
597 | }, | |
598 | }, | |
2aa57be2 | 599 | }, |
a3a9b36e | 600 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
0e3eaadf SS |
601 | { |
602 | .pdev = { | |
603 | .name = "serial8250", | |
61f04ee8 | 604 | .id = 3, |
0e3eaadf SS |
605 | .dev = { |
606 | .platform_data = serial_platform_data3, | |
607 | }, | |
608 | }, | |
609 | }, | |
610 | #endif | |
2aa57be2 VP |
611 | }; |
612 | ||
ce13d471 | 613 | /* |
614 | * Override the default 8250 read handler: mem_serial_in() | |
615 | * Empty RX fifo read causes an abort on omap3630 and omap4 | |
616 | * This function makes sure that an empty rx fifo is not read on these silicons | |
617 | * (OMAP1/2/3430 are not affected) | |
618 | */ | |
619 | static unsigned int serial_in_override(struct uart_port *up, int offset) | |
620 | { | |
621 | if (UART_RX == offset) { | |
622 | unsigned int lsr; | |
9230372a | 623 | lsr = __serial_read_reg(up, UART_LSR); |
ce13d471 | 624 | if (!(lsr & UART_LSR_DR)) |
625 | return -EPERM; | |
626 | } | |
9230372a AS |
627 | |
628 | return __serial_read_reg(up, offset); | |
ce13d471 | 629 | } |
630 | ||
e03d37d8 SS |
631 | static void serial_out_override(struct uart_port *up, int offset, int value) |
632 | { | |
633 | unsigned int status, tmout = 10000; | |
634 | ||
635 | status = __serial_read_reg(up, UART_LSR); | |
636 | while (!(status & UART_LSR_THRE)) { | |
637 | /* Wait up to 10ms for the character(s) to be sent. */ | |
638 | if (--tmout == 0) | |
639 | break; | |
640 | udelay(1); | |
641 | status = __serial_read_reg(up, UART_LSR); | |
642 | } | |
643 | __serial_write_reg(up, offset, value); | |
644 | } | |
b3c6df3a | 645 | void __init omap_serial_early_init(void) |
1dbae815 | 646 | { |
21b90340 | 647 | int i, nr_ports; |
6e81176d | 648 | char name[16]; |
1dbae815 | 649 | |
21b90340 TW |
650 | if (!(cpu_is_omap3630() || cpu_is_omap4430())) |
651 | nr_ports = 3; | |
652 | else | |
653 | nr_ports = ARRAY_SIZE(omap_uart); | |
654 | ||
1dbae815 TL |
655 | /* |
656 | * Make sure the serial ports are muxed on at this point. | |
657 | * You have to mux them off in device drivers later on | |
658 | * if not needed. | |
659 | */ | |
660 | ||
21b90340 | 661 | for (i = 0; i < nr_ports; i++) { |
4af4016c | 662 | struct omap_uart_state *uart = &omap_uart[i]; |
fd455ea8 KH |
663 | struct platform_device *pdev = &uart->pdev; |
664 | struct device *dev = &pdev->dev; | |
665 | struct plat_serial8250_port *p = dev->platform_data; | |
1dbae815 | 666 | |
e88d556d SA |
667 | /* Don't map zero-based physical address */ |
668 | if (p->mapbase == 0) { | |
669 | printk(KERN_WARNING "omap serial: No physical address" | |
670 | " for uart#%d, so skipping early_init...\n", i); | |
671 | continue; | |
672 | } | |
84f90c9c TL |
673 | /* |
674 | * Module 4KB + L4 interconnect 4KB | |
675 | * Static mapping, never released | |
676 | */ | |
677 | p->membase = ioremap(p->mapbase, SZ_8K); | |
678 | if (!p->membase) { | |
679 | printk(KERN_ERR "ioremap failed for uart%i\n", i + 1); | |
680 | continue; | |
681 | } | |
682 | ||
21b90340 | 683 | sprintf(name, "uart%d_ick", i + 1); |
4af4016c KH |
684 | uart->ick = clk_get(NULL, name); |
685 | if (IS_ERR(uart->ick)) { | |
21b90340 | 686 | printk(KERN_ERR "Could not get uart%d_ick\n", i + 1); |
4af4016c KH |
687 | uart->ick = NULL; |
688 | } | |
6e81176d JH |
689 | |
690 | sprintf(name, "uart%d_fck", i+1); | |
4af4016c KH |
691 | uart->fck = clk_get(NULL, name); |
692 | if (IS_ERR(uart->fck)) { | |
21b90340 | 693 | printk(KERN_ERR "Could not get uart%d_fck\n", i + 1); |
4af4016c KH |
694 | uart->fck = NULL; |
695 | } | |
696 | ||
aae290fb SS |
697 | /* FIXME: Remove this once the clkdev is ready */ |
698 | if (!cpu_is_omap44xx()) { | |
699 | if (!uart->ick || !uart->fck) | |
700 | continue; | |
701 | } | |
4af4016c KH |
702 | |
703 | uart->num = i; | |
704 | p->private_data = uart; | |
705 | uart->p = p; | |
1dbae815 | 706 | |
4789998a KH |
707 | if (cpu_is_omap44xx()) |
708 | p->irq += 32; | |
b3c6df3a PW |
709 | } |
710 | } | |
711 | ||
f62349ee MW |
712 | /** |
713 | * omap_serial_init_port() - initialize single serial port | |
714 | * @port: serial port number (0-3) | |
715 | * | |
716 | * This function initialies serial driver for given @port only. | |
717 | * Platforms can call this function instead of omap_serial_init() | |
718 | * if they don't plan to use all available UARTs as serial ports. | |
719 | * | |
720 | * Don't mix calls to omap_serial_init_port() and omap_serial_init(), | |
721 | * use only one of the two. | |
722 | */ | |
723 | void __init omap_serial_init_port(int port) | |
b3c6df3a | 724 | { |
f62349ee MW |
725 | struct omap_uart_state *uart; |
726 | struct platform_device *pdev; | |
727 | struct device *dev; | |
b3c6df3a | 728 | |
f62349ee MW |
729 | BUG_ON(port < 0); |
730 | BUG_ON(port >= ARRAY_SIZE(omap_uart)); | |
b3c6df3a | 731 | |
f62349ee MW |
732 | uart = &omap_uart[port]; |
733 | pdev = &uart->pdev; | |
734 | dev = &pdev->dev; | |
970a724d | 735 | |
e88d556d SA |
736 | /* Don't proceed if there's no clocks available */ |
737 | if (unlikely(!uart->ick || !uart->fck)) { | |
738 | WARN(1, "%s: can't init uart%d, no clocks available\n", | |
739 | kobject_name(&dev->kobj), port); | |
740 | return; | |
741 | } | |
742 | ||
f2eeeae0 MW |
743 | omap_uart_enable_clocks(uart); |
744 | ||
f62349ee MW |
745 | omap_uart_reset(uart); |
746 | omap_uart_idle_init(uart); | |
747 | ||
f2eeeae0 MW |
748 | list_add_tail(&uart->node, &uart_list); |
749 | ||
f62349ee MW |
750 | if (WARN_ON(platform_device_register(pdev))) |
751 | return; | |
752 | ||
753 | if ((cpu_is_omap34xx() && uart->padconf) || | |
754 | (uart->wk_en && uart->wk_mask)) { | |
755 | device_init_wakeup(dev, true); | |
756 | DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout); | |
fd455ea8 | 757 | } |
f62349ee | 758 | |
30e53bcc | 759 | /* |
760 | * omap44xx: Never read empty UART fifo | |
761 | * omap3xxx: Never read empty UART fifo on UARTs | |
762 | * with IP rev >=0x52 | |
763 | */ | |
e03d37d8 | 764 | if (cpu_is_omap44xx()) { |
30e53bcc | 765 | uart->p->serial_in = serial_in_override; |
e03d37d8 SS |
766 | uart->p->serial_out = serial_out_override; |
767 | } else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) | |
768 | >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) { | |
30e53bcc | 769 | uart->p->serial_in = serial_in_override; |
e03d37d8 SS |
770 | uart->p->serial_out = serial_out_override; |
771 | } | |
f62349ee MW |
772 | } |
773 | ||
774 | /** | |
775 | * omap_serial_init() - intialize all supported serial ports | |
776 | * | |
777 | * Initializes all available UARTs as serial ports. Platforms | |
778 | * can call this function when they want to have default behaviour | |
779 | * for serial ports (e.g initialize them all as serial ports). | |
780 | */ | |
781 | void __init omap_serial_init(void) | |
782 | { | |
a3a9b36e TL |
783 | int i, nr_ports; |
784 | ||
785 | if (!(cpu_is_omap3630() || cpu_is_omap4430())) | |
786 | nr_ports = 3; | |
787 | else | |
788 | nr_ports = ARRAY_SIZE(omap_uart); | |
f62349ee | 789 | |
a3a9b36e | 790 | for (i = 0; i < nr_ports; i++) |
f62349ee | 791 | omap_serial_init_port(i); |
1dbae815 | 792 | } |