[deliverable/linux.git] / arch / arm / mach-omap2 / sram34xx.S

/*
 * linux/arch/arm/mach-omap3/sram.S
 *
 * Omap3 specific functions that need to be run in internal SRAM
 *
 * (C) Copyright 2007
 * Texas Instruments Inc.
 * Rajendra Nayak <rnayak@ti.com>
 *
 * (C) Copyright 2004
 * Texas Instruments, <www.ti.com>
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <mach/hardware.h>

#include <mach/io.h>

#include "sdrc.h"
#include "cm.h"

	.text

/*
 * Change frequency of core dpll
 * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
 * r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for
 *      SDRC rates < 83MHz
 */
ENTRY(omap3_sram_configure_core_dpll)
	stmfd	sp!, {r1-r12, lr}	@ store regs to stack
	ldr	r4, [sp, #52]		@ pull extra args off the stack
	dsb				@ flush buffered writes to interconnect
	cmp	r3, #0x2
	blne	configure_sdrc
	cmp	r4, #0x1
	bleq	unlock_dll
	blne	lock_dll
	bl	sdram_in_selfrefresh	@ put the SDRAM in self refresh
	bl 	configure_core_dpll
	bl	enable_sdrc
	cmp	r4, #0x1
	bleq	wait_dll_unlock
	blne	wait_dll_lock
	cmp	r3, #0x1
	blne	configure_sdrc
	isb				@ prevent speculative exec past here
	mov 	r0, #0 			@ return value
	ldmfd	sp!, {r1-r12, pc}	@ restore regs and return
unlock_dll:
	ldr	r11, omap3_sdrc_dlla_ctrl
	ldr	r12, [r11]
	orr	r12, r12, #0x4
	str	r12, [r11]		@ (no OCP barrier needed)
	bx	lr
lock_dll:
	ldr	r11, omap3_sdrc_dlla_ctrl
	ldr	r12, [r11]
	bic	r12, r12, #0x4
	str	r12, [r11]		@ (no OCP barrier needed)
	bx	lr
sdram_in_selfrefresh:
	ldr	r11, omap3_sdrc_power	@ read the SDRC_POWER register
	ldr	r12, [r11]		@ read the contents of SDRC_POWER
	mov	r9, r12			@ keep a copy of SDRC_POWER bits
	orr 	r12, r12, #0x40		@ enable self refresh on idle req
	bic 	r12, r12, #0x4		@ clear PWDENA
	str 	r12, [r11]		@ write back to SDRC_POWER register
	ldr	r12, [r11]		@ posted-write barrier for SDRC
	ldr	r11, omap3_cm_iclken1_core	@ read the CM_ICLKEN1_CORE reg
	ldr	r12, [r11]
	bic	r12, r12, #0x2		@ disable iclk bit for SDRC
	str 	r12, [r11]
wait_sdrc_idle:
	ldr 	r11, omap3_cm_idlest1_core
	ldr 	r12, [r11]
	and 	r12, r12, #0x2		@ check for SDRC idle
	cmp 	r12, #2
	bne 	wait_sdrc_idle
	bx 	lr
configure_core_dpll:
	ldr 	r11, omap3_cm_clksel1_pll
	ldr	r12, [r11]
	ldr	r10, core_m2_mask_val	@ modify m2 for core dpll
	and	r12, r12, r10
	orr	r12, r12, r3, lsl #0x1B	@ r3 contains the M2 val
	str	r12, [r11]
	ldr	r12, [r11]		@ posted-write barrier for CM
	bx	lr
wait_clk_stable:
	subs 	r12, r12, #1
	bne	wait_clk_stable
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	bx	lr
enable_sdrc:
	ldr 	r11, omap3_cm_iclken1_core
	ldr	r12, [r11]
	orr 	r12, r12, #0x2		@ enable iclk bit for SDRC
	str 	r12, [r11]
wait_sdrc_idle1:
	ldr 	r11, omap3_cm_idlest1_core
	ldr	r12, [r11]
	and 	r12, r12, #0x2
	cmp	r12, #0
	bne	wait_sdrc_idle1
restore_sdrc_power_val:
	ldr	r11, omap3_sdrc_power
	str	r9, [r11]		@ restore SDRC_POWER, no barrier needed
	bx	lr
wait_dll_lock:
	ldr	r11, omap3_sdrc_dlla_status
	ldr	r12, [r11]
	and 	r12, r12, #0x4
	cmp	r12, #0x4
	bne	wait_dll_lock
	bx	lr
wait_dll_unlock:
	ldr	r11, omap3_sdrc_dlla_status
	ldr	r12, [r11]
	and	r12, r12, #0x4
	cmp	r12, #0x0
	bne	wait_dll_unlock
	bx	lr
configure_sdrc:
	ldr	r11, omap3_sdrc_rfr_ctrl
	str	r0, [r11]
	ldr	r11, omap3_sdrc_actim_ctrla
	str	r1, [r11]
	ldr	r11, omap3_sdrc_actim_ctrlb
	str	r2, [r11]
	ldr	r2, [r11]		@ posted-write barrier for SDRC
	bx	lr

omap3_sdrc_power:
	.word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
omap3_cm_clksel1_pll:
	.word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
omap3_cm_idlest1_core:
	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
omap3_cm_iclken1_core:
	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
omap3_sdrc_rfr_ctrl:
	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
omap3_sdrc_actim_ctrla:
	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
omap3_sdrc_actim_ctrlb:
	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
omap3_sdrc_dlla_status:
	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
omap3_sdrc_dlla_ctrl:
	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
core_m2_mask_val:
	.word 0x07FFFFFF

ENTRY(omap3_sram_configure_core_dpll_sz)
	.word	. - omap3_sram_configure_core_dpll
Commit	Line	Data
cc26b3b0 SMK	1	/*
	2	* linux/arch/arm/mach-omap3/sram.S
	3	*
	4	* Omap3 specific functions that need to be run in internal SRAM
	5	*
	6	* (C) Copyright 2007
	7	* Texas Instruments Inc.
	8	* Rajendra Nayak <rnayak@ti.com>
	9	*
	10	* (C) Copyright 2004
	11	* Texas Instruments, <www.ti.com>
	12	* Richard Woodruff <r-woodruff2@ti.com>
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29	#include <linux/linkage.h>
	30	#include <asm/assembler.h>
	31	#include <mach/hardware.h>
	32
	33	#include <mach/io.h>
	34
	35	#include "sdrc.h"
	36	#include "cm.h"
	37
	38	.text
	39
	40	/*
	41	* Change frequency of core dpll
	42	* r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
4519c2bf PW	43	* r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for
4519c2bf PW	44	* SDRC rates < 83MHz
cc26b3b0 SMK	45	*/
	46	ENTRY(omap3_sram_configure_core_dpll)
	47	stmfd sp!, {r1-r12, lr} @ store regs to stack
4519c2bf	48	ldr r4, [sp, #52] @ pull extra args off the stack
69d4255b	49	dsb @ flush buffered writes to interconnect
cc26b3b0 SMK	50	cmp r3, #0x2
cc26b3b0 SMK	51	blne configure_sdrc
4519c2bf PW	52	cmp r4, #0x1
4519c2bf PW	53	bleq unlock_dll
cc26b3b0	54	blne lock_dll
cc26b3b0 SMK	55	bl sdram_in_selfrefresh @ put the SDRAM in self refresh
	56	bl configure_core_dpll
	57	bl enable_sdrc
4519c2bf PW	58	cmp r4, #0x1
4519c2bf PW	59	bleq wait_dll_unlock
cc26b3b0 SMK	60	blne wait_dll_lock
	61	cmp r3, #0x1
	62	blne configure_sdrc
69d4255b	63	isb @ prevent speculative exec past here
cc26b3b0 SMK	64	mov r0, #0 @ return value
	65	ldmfd sp!, {r1-r12, pc} @ restore regs and return
	66	unlock_dll:
b2abb271 PW	67	ldr r11, omap3_sdrc_dlla_ctrl
	68	ldr r12, [r11]
	69	orr r12, r12, #0x4
	70	str r12, [r11] @ (no OCP barrier needed)
cc26b3b0 SMK	71	bx lr
cc26b3b0 SMK	72	lock_dll:
b2abb271 PW	73	ldr r11, omap3_sdrc_dlla_ctrl
	74	ldr r12, [r11]
	75	bic r12, r12, #0x4
	76	str r12, [r11] @ (no OCP barrier needed)
cc26b3b0 SMK	77	bx lr
cc26b3b0 SMK	78	sdram_in_selfrefresh:
b2abb271 PW	79	ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
	80	ldr r12, [r11] @ read the contents of SDRC_POWER
	81	mov r9, r12 @ keep a copy of SDRC_POWER bits
	82	orr r12, r12, #0x40 @ enable self refresh on idle req
	83	bic r12, r12, #0x4 @ clear PWDENA
	84	str r12, [r11] @ write back to SDRC_POWER register
	85	ldr r12, [r11] @ posted-write barrier for SDRC
	86	ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
	87	ldr r12, [r11]
	88	bic r12, r12, #0x2 @ disable iclk bit for SDRC
	89	str r12, [r11]
cc26b3b0	90	wait_sdrc_idle:
b2abb271 PW	91	ldr r11, omap3_cm_idlest1_core
	92	ldr r12, [r11]
	93	and r12, r12, #0x2 @ check for SDRC idle
	94	cmp r12, #2
cc26b3b0 SMK	95	bne wait_sdrc_idle
	96	bx lr
	97	configure_core_dpll:
b2abb271 PW	98	ldr r11, omap3_cm_clksel1_pll
	99	ldr r12, [r11]
	100	ldr r10, core_m2_mask_val @ modify m2 for core dpll
	101	and r12, r12, r10
	102	orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val
	103	str r12, [r11]
	104	ldr r12, [r11] @ posted-write barrier for CM
cc26b3b0 SMK	105	bx lr
cc26b3b0 SMK	106	wait_clk_stable:
b2abb271	107	subs r12, r12, #1
cc26b3b0 SMK	108	bne wait_clk_stable
	109	nop
	110	nop
	111	nop
	112	nop
	113	nop
	114	nop
	115	nop
	116	nop
	117	nop
	118	nop
	119	bx lr
	120	enable_sdrc:
b2abb271 PW	121	ldr r11, omap3_cm_iclken1_core
	122	ldr r12, [r11]
	123	orr r12, r12, #0x2 @ enable iclk bit for SDRC
	124	str r12, [r11]
cc26b3b0	125	wait_sdrc_idle1:
b2abb271 PW	126	ldr r11, omap3_cm_idlest1_core
	127	ldr r12, [r11]
	128	and r12, r12, #0x2
	129	cmp r12, #0
cc26b3b0	130	bne wait_sdrc_idle1
fa0406a8	131	restore_sdrc_power_val:
b2abb271 PW	132	ldr r11, omap3_sdrc_power
b2abb271 PW	133	str r9, [r11] @ restore SDRC_POWER, no barrier needed
cc26b3b0 SMK	134	bx lr
cc26b3b0 SMK	135	wait_dll_lock:
b2abb271 PW	136	ldr r11, omap3_sdrc_dlla_status
	137	ldr r12, [r11]
	138	and r12, r12, #0x4
	139	cmp r12, #0x4
cc26b3b0 SMK	140	bne wait_dll_lock
	141	bx lr
	142	wait_dll_unlock:
b2abb271 PW	143	ldr r11, omap3_sdrc_dlla_status
	144	ldr r12, [r11]
	145	and r12, r12, #0x4
	146	cmp r12, #0x0
cc26b3b0 SMK	147	bne wait_dll_unlock
	148	bx lr
	149	configure_sdrc:
b2abb271 PW	150	ldr r11, omap3_sdrc_rfr_ctrl
	151	str r0, [r11]
	152	ldr r11, omap3_sdrc_actim_ctrla
	153	str r1, [r11]
	154	ldr r11, omap3_sdrc_actim_ctrlb
	155	str r2, [r11]
	156	ldr r2, [r11] @ posted-write barrier for SDRC
cc26b3b0 SMK	157	bx lr
	158
	159	omap3_sdrc_power:
	160	.word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
	161	omap3_cm_clksel1_pll:
	162	.word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
	163	omap3_cm_idlest1_core:
	164	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
	165	omap3_cm_iclken1_core:
	166	.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
	167	omap3_sdrc_rfr_ctrl:
	168	.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
	169	omap3_sdrc_actim_ctrla:
	170	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
	171	omap3_sdrc_actim_ctrlb:
	172	.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
	173	omap3_sdrc_dlla_status:
	174	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
	175	omap3_sdrc_dlla_ctrl:
	176	.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
	177	core_m2_mask_val:
	178	.word 0x07FFFFFF
	179
	180	ENTRY(omap3_sram_configure_core_dpll_sz)
	181	.word . - omap3_sram_configure_core_dpll