Commit | Line | Data |
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1dbae815 | 1 | /* |
0f622e8c | 2 | * linux/arch/arm/mach-omap2/timer.c |
1dbae815 TL |
3 | * |
4 | * OMAP2 GP timer support. | |
5 | * | |
f248076c PW |
6 | * Copyright (C) 2009 Nokia Corporation |
7 | * | |
5a3a388f KH |
8 | * Update to use new clocksource/clockevent layers |
9 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | |
10 | * Copyright (C) 2007 MontaVista Software, Inc. | |
11 | * | |
12 | * Original driver: | |
1dbae815 TL |
13 | * Copyright (C) 2005 Nokia Corporation |
14 | * Author: Paul Mundt <paul.mundt@nokia.com> | |
96de0e25 | 15 | * Juha Yrjölä <juha.yrjola@nokia.com> |
77900a2f | 16 | * OMAP Dual-mode timer framework support by Timo Teras |
1dbae815 TL |
17 | * |
18 | * Some parts based off of TI's 24xx code: | |
19 | * | |
44169075 | 20 | * Copyright (C) 2004-2009 Texas Instruments, Inc. |
1dbae815 TL |
21 | * |
22 | * Roughly modelled after the OMAP1 MPU timer code. | |
44169075 | 23 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
1dbae815 TL |
24 | * |
25 | * This file is subject to the terms and conditions of the GNU General Public | |
26 | * License. See the file "COPYING" in the main directory of this archive | |
27 | * for more details. | |
28 | */ | |
29 | #include <linux/init.h> | |
30 | #include <linux/time.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/err.h> | |
f8ce2547 | 33 | #include <linux/clk.h> |
77900a2f | 34 | #include <linux/delay.h> |
e6687290 | 35 | #include <linux/irq.h> |
5a3a388f KH |
36 | #include <linux/clocksource.h> |
37 | #include <linux/clockchips.h> | |
c345c8b0 | 38 | #include <linux/slab.h> |
eed0de27 | 39 | #include <linux/of.h> |
9725f445 JH |
40 | #include <linux/of_address.h> |
41 | #include <linux/of_irq.h> | |
40fc3bb5 JH |
42 | #include <linux/platform_device.h> |
43 | #include <linux/platform_data/dmtimer-omap.h> | |
38ff87f7 | 44 | #include <linux/sched_clock.h> |
f8ce2547 | 45 | |
1dbae815 | 46 | #include <asm/mach/time.h> |
a45c983f | 47 | #include <asm/smp_twd.h> |
7d7e1eba | 48 | |
2a296c8f | 49 | #include "omap_hwmod.h" |
25c7d49e | 50 | #include "omap_device.h" |
5c2e8852 | 51 | #include <plat/counter-32k.h> |
7d7e1eba | 52 | #include <plat/dmtimer.h> |
1d5aef49 | 53 | #include "omap-pm.h" |
b481113a | 54 | |
dbc04161 | 55 | #include "soc.h" |
7d7e1eba | 56 | #include "common.h" |
b481113a | 57 | #include "powerdomain.h" |
5523e409 | 58 | #include "omap-secure.h" |
1dbae815 | 59 | |
fa6d79d2 SS |
60 | #define REALTIME_COUNTER_BASE 0x48243200 |
61 | #define INCREMENTER_NUMERATOR_OFFSET 0x10 | |
62 | #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 | |
63 | #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 | |
64 | ||
aa561889 TL |
65 | /* Clockevent code */ |
66 | ||
67 | static struct omap_dm_timer clkev; | |
5a3a388f | 68 | static struct clock_event_device clockevent_gpt; |
1dbae815 | 69 | |
d5da94b8 | 70 | #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER |
5523e409 S |
71 | static unsigned long arch_timer_freq; |
72 | ||
73 | void set_cntfreq(void) | |
74 | { | |
75 | omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq); | |
76 | } | |
d5da94b8 | 77 | #endif |
1dbae815 | 78 | |
0cd61b68 | 79 | static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) |
1dbae815 | 80 | { |
5a3a388f KH |
81 | struct clock_event_device *evt = &clockevent_gpt; |
82 | ||
ee17f114 | 83 | __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); |
1dbae815 | 84 | |
5a3a388f | 85 | evt->event_handler(evt); |
1dbae815 TL |
86 | return IRQ_HANDLED; |
87 | } | |
88 | ||
89 | static struct irqaction omap2_gp_timer_irq = { | |
f36921be | 90 | .name = "gp_timer", |
fe806d04 | 91 | .flags = IRQF_TIMER | IRQF_IRQPOLL, |
1dbae815 TL |
92 | .handler = omap2_gp_timer_interrupt, |
93 | }; | |
94 | ||
5a3a388f KH |
95 | static int omap2_gp_timer_set_next_event(unsigned long cycles, |
96 | struct clock_event_device *evt) | |
1dbae815 | 97 | { |
ee17f114 | 98 | __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, |
971d0254 | 99 | 0xffffffff - cycles, OMAP_TIMER_POSTED); |
5a3a388f KH |
100 | |
101 | return 0; | |
102 | } | |
103 | ||
104 | static void omap2_gp_timer_set_mode(enum clock_event_mode mode, | |
105 | struct clock_event_device *evt) | |
106 | { | |
107 | u32 period; | |
108 | ||
971d0254 | 109 | __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); |
5a3a388f KH |
110 | |
111 | switch (mode) { | |
112 | case CLOCK_EVT_MODE_PERIODIC: | |
aa561889 | 113 | period = clkev.rate / HZ; |
5a3a388f | 114 | period -= 1; |
aa561889 | 115 | /* Looks like we need to first set the load value separately */ |
ee17f114 | 116 | __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, |
971d0254 | 117 | 0xffffffff - period, OMAP_TIMER_POSTED); |
ee17f114 | 118 | __omap_dm_timer_load_start(&clkev, |
aa561889 | 119 | OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, |
971d0254 | 120 | 0xffffffff - period, OMAP_TIMER_POSTED); |
5a3a388f KH |
121 | break; |
122 | case CLOCK_EVT_MODE_ONESHOT: | |
123 | break; | |
124 | case CLOCK_EVT_MODE_UNUSED: | |
125 | case CLOCK_EVT_MODE_SHUTDOWN: | |
126 | case CLOCK_EVT_MODE_RESUME: | |
127 | break; | |
128 | } | |
129 | } | |
130 | ||
131 | static struct clock_event_device clockevent_gpt = { | |
5a3a388f | 132 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
11d6ec2e | 133 | .rating = 300, |
5a3a388f KH |
134 | .set_next_event = omap2_gp_timer_set_next_event, |
135 | .set_mode = omap2_gp_timer_set_mode, | |
136 | }; | |
137 | ||
ad24bde8 JH |
138 | static struct property device_disabled = { |
139 | .name = "status", | |
140 | .length = sizeof("disabled"), | |
141 | .value = "disabled", | |
142 | }; | |
143 | ||
144 | static struct of_device_id omap_timer_match[] __initdata = { | |
002e1ec5 JH |
145 | { .compatible = "ti,omap2420-timer", }, |
146 | { .compatible = "ti,omap3430-timer", }, | |
147 | { .compatible = "ti,omap4430-timer", }, | |
148 | { .compatible = "ti,omap5430-timer", }, | |
149 | { .compatible = "ti,am335x-timer", }, | |
150 | { .compatible = "ti,am335x-timer-1ms", }, | |
ad24bde8 JH |
151 | { } |
152 | }; | |
153 | ||
9725f445 JH |
154 | /** |
155 | * omap_get_timer_dt - get a timer using device-tree | |
156 | * @match - device-tree match structure for matching a device type | |
157 | * @property - optional timer property to match | |
158 | * | |
159 | * Helper function to get a timer during early boot using device-tree for use | |
160 | * as kernel system timer. Optionally, the property argument can be used to | |
161 | * select a timer with a specific property. Once a timer is found then mark | |
162 | * the timer node in device-tree as disabled, to prevent the kernel from | |
163 | * registering this timer as a platform device and so no one else can use it. | |
164 | */ | |
165 | static struct device_node * __init omap_get_timer_dt(struct of_device_id *match, | |
166 | const char *property) | |
167 | { | |
168 | struct device_node *np; | |
169 | ||
170 | for_each_matching_node(np, match) { | |
034bf091 | 171 | if (!of_device_is_available(np)) |
9725f445 | 172 | continue; |
9725f445 | 173 | |
034bf091 | 174 | if (property && !of_get_property(np, property, NULL)) |
9725f445 | 175 | continue; |
9725f445 | 176 | |
2eb03937 JH |
177 | if (!property && (of_get_property(np, "ti,timer-alwon", NULL) || |
178 | of_get_property(np, "ti,timer-dsp", NULL) || | |
179 | of_get_property(np, "ti,timer-pwm", NULL) || | |
180 | of_get_property(np, "ti,timer-secure", NULL))) | |
181 | continue; | |
182 | ||
2727da85 | 183 | of_add_property(np, &device_disabled); |
9725f445 JH |
184 | return np; |
185 | } | |
186 | ||
187 | return NULL; | |
188 | } | |
189 | ||
ad24bde8 JH |
190 | /** |
191 | * omap_dmtimer_init - initialisation function when device tree is used | |
192 | * | |
193 | * For secure OMAP3 devices, timers with device type "timer-secure" cannot | |
194 | * be used by the kernel as they are reserved. Therefore, to prevent the | |
195 | * kernel registering these devices remove them dynamically from the device | |
196 | * tree on boot. | |
197 | */ | |
bf85f205 | 198 | static void __init omap_dmtimer_init(void) |
ad24bde8 JH |
199 | { |
200 | struct device_node *np; | |
201 | ||
202 | if (!cpu_is_omap34xx()) | |
203 | return; | |
204 | ||
205 | /* If we are a secure device, remove any secure timer nodes */ | |
206 | if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { | |
9725f445 JH |
207 | np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure"); |
208 | if (np) | |
209 | of_node_put(np); | |
ad24bde8 JH |
210 | } |
211 | } | |
212 | ||
bfd6d021 JH |
213 | /** |
214 | * omap_dm_timer_get_errata - get errata flags for a timer | |
215 | * | |
216 | * Get the timer errata flags that are specific to the OMAP device being used. | |
217 | */ | |
bf85f205 | 218 | static u32 __init omap_dm_timer_get_errata(void) |
bfd6d021 JH |
219 | { |
220 | if (cpu_is_omap24xx()) | |
221 | return 0; | |
222 | ||
223 | return OMAP_TIMER_ERRATA_I103_I767; | |
224 | } | |
225 | ||
aa561889 | 226 | static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, |
e95ea43a JH |
227 | const char *fck_source, |
228 | const char *property, | |
229 | const char **timer_name, | |
230 | int posted) | |
5a3a388f | 231 | { |
aa561889 | 232 | char name[10]; /* 10 = sizeof("gptXX_Xck0") */ |
37bd6ca8 | 233 | const char *oh_name = NULL; |
9725f445 | 234 | struct device_node *np; |
aa561889 | 235 | struct omap_hwmod *oh; |
61b001c5 | 236 | struct resource irq, mem; |
a7990a19 | 237 | struct clk *src; |
f88095ba | 238 | int r = 0; |
aa561889 | 239 | |
9725f445 | 240 | if (of_have_populated_dt()) { |
61338d59 | 241 | np = omap_get_timer_dt(omap_timer_match, property); |
9725f445 JH |
242 | if (!np) |
243 | return -ENODEV; | |
244 | ||
245 | of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); | |
246 | if (!oh_name) | |
247 | return -ENODEV; | |
248 | ||
249 | timer->irq = irq_of_parse_and_map(np, 0); | |
250 | if (!timer->irq) | |
251 | return -ENXIO; | |
252 | ||
253 | timer->io_base = of_iomap(np, 0); | |
254 | ||
255 | of_node_put(np); | |
256 | } else { | |
8f6924dc | 257 | if (omap_dm_timer_reserve_systimer(timer->id)) |
9725f445 JH |
258 | return -ENODEV; |
259 | ||
8f6924dc | 260 | sprintf(name, "timer%d", timer->id); |
9725f445 JH |
261 | oh_name = name; |
262 | } | |
263 | ||
9725f445 | 264 | oh = omap_hwmod_lookup(oh_name); |
aa561889 TL |
265 | if (!oh) |
266 | return -ENODEV; | |
267 | ||
e95ea43a JH |
268 | *timer_name = oh->name; |
269 | ||
9725f445 JH |
270 | if (!of_have_populated_dt()) { |
271 | r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, | |
61b001c5 | 272 | &irq); |
9725f445 JH |
273 | if (r) |
274 | return -ENXIO; | |
61b001c5 | 275 | timer->irq = irq.start; |
9725f445 JH |
276 | |
277 | r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, | |
61b001c5 | 278 | &mem); |
9725f445 JH |
279 | if (r) |
280 | return -ENXIO; | |
9725f445 JH |
281 | |
282 | /* Static mapping, never released */ | |
61b001c5 | 283 | timer->io_base = ioremap(mem.start, mem.end - mem.start); |
9725f445 | 284 | } |
aa561889 | 285 | |
aa561889 TL |
286 | if (!timer->io_base) |
287 | return -ENXIO; | |
288 | ||
289 | /* After the dmtimer is using hwmod these clocks won't be needed */ | |
ae6df418 | 290 | timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); |
aa561889 | 291 | if (IS_ERR(timer->fclk)) |
a7990a19 | 292 | return PTR_ERR(timer->fclk); |
aa561889 | 293 | |
a7990a19 JH |
294 | src = clk_get(NULL, fck_source); |
295 | if (IS_ERR(src)) | |
296 | return PTR_ERR(src); | |
aa561889 | 297 | |
a7990a19 JH |
298 | if (clk_get_parent(timer->fclk) != src) { |
299 | r = clk_set_parent(timer->fclk, src); | |
300 | if (r < 0) { | |
301 | pr_warn("%s: %s cannot set source\n", __func__, | |
302 | oh->name); | |
aa561889 | 303 | clk_put(src); |
a7990a19 | 304 | return r; |
aa561889 TL |
305 | } |
306 | } | |
b1538832 | 307 | |
a7990a19 JH |
308 | clk_put(src); |
309 | ||
b1538832 JH |
310 | omap_hwmod_setup_one(oh_name); |
311 | omap_hwmod_enable(oh); | |
ee17f114 | 312 | __omap_dm_timer_init_regs(timer); |
aa561889 | 313 | |
bfd6d021 JH |
314 | if (posted) |
315 | __omap_dm_timer_enable_posted(timer); | |
316 | ||
317 | /* Check that the intended posted configuration matches the actual */ | |
318 | if (posted != timer->posted) | |
319 | return -EINVAL; | |
1dbae815 | 320 | |
bfd6d021 | 321 | timer->rate = clk_get_rate(timer->fclk); |
aa561889 | 322 | timer->reserved = 1; |
38698bef | 323 | |
f88095ba | 324 | return r; |
aa561889 | 325 | } |
f248076c | 326 | |
aa561889 | 327 | static void __init omap2_gp_clockevent_init(int gptimer_id, |
9725f445 JH |
328 | const char *fck_source, |
329 | const char *property) | |
aa561889 TL |
330 | { |
331 | int res; | |
f248076c | 332 | |
8f6924dc | 333 | clkev.id = gptimer_id; |
bfd6d021 JH |
334 | clkev.errata = omap_dm_timer_get_errata(); |
335 | ||
336 | /* | |
337 | * For clock-event timers we never read the timer counter and | |
338 | * so we are not impacted by errata i103 and i767. Therefore, | |
339 | * we can safely ignore this errata for clock-event timers. | |
340 | */ | |
341 | __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); | |
342 | ||
8f6924dc | 343 | res = omap_dm_timer_init_one(&clkev, fck_source, property, |
e95ea43a | 344 | &clockevent_gpt.name, OMAP_TIMER_POSTED); |
aa561889 | 345 | BUG_ON(res); |
f248076c | 346 | |
a032d33b | 347 | omap2_gp_timer_irq.dev_id = &clkev; |
aa561889 | 348 | setup_irq(clkev.irq, &omap2_gp_timer_irq); |
5a3a388f | 349 | |
ee17f114 | 350 | __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); |
aa561889 | 351 | |
11d6ec2e SS |
352 | clockevent_gpt.cpumask = cpu_possible_mask; |
353 | clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); | |
838a2ae8 SG |
354 | clockevents_config_and_register(&clockevent_gpt, clkev.rate, |
355 | 3, /* Timer internal resynch latency */ | |
356 | 0xffffffff); | |
aa561889 | 357 | |
e95ea43a JH |
358 | pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name, |
359 | clkev.rate); | |
5a3a388f KH |
360 | } |
361 | ||
f248076c | 362 | /* Clocksource code */ |
3d05a3e8 | 363 | static struct omap_dm_timer clksrc; |
1fe97c8f | 364 | static bool use_gptimer_clksrc; |
3d05a3e8 | 365 | |
5a3a388f KH |
366 | /* |
367 | * clocksource | |
368 | */ | |
8e19608e | 369 | static cycle_t clocksource_read_cycles(struct clocksource *cs) |
5a3a388f | 370 | { |
971d0254 | 371 | return (cycle_t)__omap_dm_timer_read_counter(&clksrc, |
bfd6d021 | 372 | OMAP_TIMER_NONPOSTED); |
5a3a388f KH |
373 | } |
374 | ||
375 | static struct clocksource clocksource_gpt = { | |
5a3a388f KH |
376 | .rating = 300, |
377 | .read = clocksource_read_cycles, | |
378 | .mask = CLOCKSOURCE_MASK(32), | |
5a3a388f KH |
379 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
380 | }; | |
381 | ||
2f0778af | 382 | static u32 notrace dmtimer_read_sched_clock(void) |
cbc94380 | 383 | { |
3d05a3e8 | 384 | if (clksrc.reserved) |
971d0254 | 385 | return __omap_dm_timer_read_counter(&clksrc, |
bfd6d021 | 386 | OMAP_TIMER_NONPOSTED); |
5a3a388f | 387 | |
2f0778af | 388 | return 0; |
3d05a3e8 TL |
389 | } |
390 | ||
258e84af JH |
391 | static struct of_device_id omap_counter_match[] __initdata = { |
392 | { .compatible = "ti,omap-counter32k", }, | |
393 | { } | |
394 | }; | |
395 | ||
3d05a3e8 | 396 | /* Setup free-running counter for clocksource */ |
e0c3e27c | 397 | static int __init __maybe_unused omap2_sync32k_clocksource_init(void) |
1fe97c8f VH |
398 | { |
399 | int ret; | |
9883f7c8 | 400 | struct device_node *np = NULL; |
1fe97c8f VH |
401 | struct omap_hwmod *oh; |
402 | void __iomem *vbase; | |
403 | const char *oh_name = "counter_32k"; | |
404 | ||
9883f7c8 JH |
405 | /* |
406 | * If device-tree is present, then search the DT blob | |
407 | * to see if the 32kHz counter is supported. | |
408 | */ | |
409 | if (of_have_populated_dt()) { | |
410 | np = omap_get_timer_dt(omap_counter_match, NULL); | |
411 | if (!np) | |
412 | return -ENODEV; | |
413 | ||
414 | of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); | |
415 | if (!oh_name) | |
416 | return -ENODEV; | |
417 | } | |
418 | ||
1fe97c8f VH |
419 | /* |
420 | * First check hwmod data is available for sync32k counter | |
421 | */ | |
422 | oh = omap_hwmod_lookup(oh_name); | |
423 | if (!oh || oh->slaves_cnt == 0) | |
424 | return -ENODEV; | |
425 | ||
426 | omap_hwmod_setup_one(oh_name); | |
427 | ||
9883f7c8 JH |
428 | if (np) { |
429 | vbase = of_iomap(np, 0); | |
430 | of_node_put(np); | |
431 | } else { | |
432 | vbase = omap_hwmod_get_mpu_rt_va(oh); | |
433 | } | |
434 | ||
1fe97c8f VH |
435 | if (!vbase) { |
436 | pr_warn("%s: failed to get counter_32k resource\n", __func__); | |
437 | return -ENXIO; | |
438 | } | |
439 | ||
440 | ret = omap_hwmod_enable(oh); | |
441 | if (ret) { | |
442 | pr_warn("%s: failed to enable counter_32k module (%d)\n", | |
443 | __func__, ret); | |
444 | return ret; | |
445 | } | |
446 | ||
447 | ret = omap_init_clocksource_32k(vbase); | |
448 | if (ret) { | |
449 | pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", | |
450 | __func__, ret); | |
451 | omap_hwmod_idle(oh); | |
452 | } | |
453 | ||
454 | return ret; | |
455 | } | |
456 | ||
457 | static void __init omap2_gptimer_clocksource_init(int gptimer_id, | |
2eb03937 JH |
458 | const char *fck_source, |
459 | const char *property) | |
3d05a3e8 TL |
460 | { |
461 | int res; | |
462 | ||
8f6924dc | 463 | clksrc.id = gptimer_id; |
bfd6d021 JH |
464 | clksrc.errata = omap_dm_timer_get_errata(); |
465 | ||
8f6924dc | 466 | res = omap_dm_timer_init_one(&clksrc, fck_source, property, |
e95ea43a | 467 | &clocksource_gpt.name, |
bfd6d021 | 468 | OMAP_TIMER_NONPOSTED); |
3d05a3e8 | 469 | BUG_ON(res); |
5a3a388f | 470 | |
ee17f114 | 471 | __omap_dm_timer_load_start(&clksrc, |
971d0254 | 472 | OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, |
bfd6d021 | 473 | OMAP_TIMER_NONPOSTED); |
2f0778af | 474 | setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); |
cbc94380 | 475 | |
3d05a3e8 TL |
476 | if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) |
477 | pr_err("Could not register clocksource %s\n", | |
478 | clocksource_gpt.name); | |
1fe97c8f | 479 | else |
e95ea43a JH |
480 | pr_info("OMAP clocksource: %s at %lu Hz\n", |
481 | clocksource_gpt.name, clksrc.rate); | |
1fe97c8f VH |
482 | } |
483 | ||
fa6d79d2 SS |
484 | #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER |
485 | /* | |
486 | * The realtime counter also called master counter, is a free-running | |
487 | * counter, which is related to real time. It produces the count used | |
488 | * by the CPU local timer peripherals in the MPU cluster. The timer counts | |
489 | * at a rate of 6.144 MHz. Because the device operates on different clocks | |
490 | * in different power modes, the master counter shifts operation between | |
491 | * clocks, adjusting the increment per clock in hardware accordingly to | |
492 | * maintain a constant count rate. | |
493 | */ | |
494 | static void __init realtime_counter_init(void) | |
495 | { | |
496 | void __iomem *base; | |
497 | static struct clk *sys_clk; | |
498 | unsigned long rate; | |
499 | unsigned int reg, num, den; | |
500 | ||
501 | base = ioremap(REALTIME_COUNTER_BASE, SZ_32); | |
502 | if (!base) { | |
503 | pr_err("%s: ioremap failed\n", __func__); | |
504 | return; | |
505 | } | |
7f585bbf | 506 | sys_clk = clk_get(NULL, "sys_clkin"); |
533b2981 | 507 | if (IS_ERR(sys_clk)) { |
fa6d79d2 SS |
508 | pr_err("%s: failed to get system clock handle\n", __func__); |
509 | iounmap(base); | |
510 | return; | |
511 | } | |
512 | ||
513 | rate = clk_get_rate(sys_clk); | |
514 | /* Numerator/denumerator values refer TRM Realtime Counter section */ | |
515 | switch (rate) { | |
516 | case 1200000: | |
517 | num = 64; | |
518 | den = 125; | |
519 | break; | |
520 | case 1300000: | |
521 | num = 768; | |
522 | den = 1625; | |
523 | break; | |
524 | case 19200000: | |
525 | num = 8; | |
526 | den = 25; | |
527 | break; | |
38a1981c S |
528 | case 20000000: |
529 | num = 192; | |
530 | den = 625; | |
531 | break; | |
fa6d79d2 SS |
532 | case 2600000: |
533 | num = 384; | |
534 | den = 1625; | |
535 | break; | |
536 | case 2700000: | |
537 | num = 256; | |
538 | den = 1125; | |
539 | break; | |
540 | case 38400000: | |
541 | default: | |
542 | /* Program it for 38.4 MHz */ | |
543 | num = 4; | |
544 | den = 25; | |
545 | break; | |
546 | } | |
547 | ||
548 | /* Program numerator and denumerator registers */ | |
549 | reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & | |
550 | NUMERATOR_DENUMERATOR_MASK; | |
551 | reg |= num; | |
552 | __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); | |
553 | ||
42c604ba | 554 | reg = __raw_readl(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) & |
fa6d79d2 SS |
555 | NUMERATOR_DENUMERATOR_MASK; |
556 | reg |= den; | |
557 | __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); | |
558 | ||
5523e409 S |
559 | arch_timer_freq = (rate / den) * num; |
560 | set_cntfreq(); | |
561 | ||
fa6d79d2 SS |
562 | iounmap(base); |
563 | } | |
564 | #else | |
565 | static inline void __init realtime_counter_init(void) | |
566 | {} | |
567 | #endif | |
568 | ||
6f80b3bb | 569 | #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ |
2eb03937 | 570 | clksrc_nr, clksrc_src, clksrc_prop) \ |
6bb27d73 | 571 | void __init omap##name##_gptimer_timer_init(void) \ |
6f80b3bb | 572 | { \ |
9affd6be LT |
573 | if (omap_clk_init) \ |
574 | omap_clk_init(); \ | |
6f80b3bb IG |
575 | omap_dmtimer_init(); \ |
576 | omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ | |
2eb03937 JH |
577 | omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \ |
578 | clksrc_prop); \ | |
6f80b3bb IG |
579 | } |
580 | ||
581 | #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ | |
2eb03937 | 582 | clksrc_nr, clksrc_src, clksrc_prop) \ |
6bb27d73 | 583 | void __init omap##name##_sync32k_timer_init(void) \ |
e74984e4 | 584 | { \ |
9affd6be LT |
585 | if (omap_clk_init) \ |
586 | omap_clk_init(); \ | |
ad24bde8 | 587 | omap_dmtimer_init(); \ |
9725f445 | 588 | omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ |
6f80b3bb IG |
589 | /* Enable the use of clocksource="gp_timer" kernel parameter */ \ |
590 | if (use_gptimer_clksrc) \ | |
2eb03937 JH |
591 | omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \ |
592 | clksrc_prop); \ | |
6f80b3bb IG |
593 | else \ |
594 | omap2_sync32k_clocksource_init(); \ | |
e74984e4 TL |
595 | } |
596 | ||
e74984e4 | 597 | #ifdef CONFIG_ARCH_OMAP2 |
7bdc83f7 | 598 | OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon", |
2eb03937 | 599 | 2, "timer_sys_ck", NULL); |
6f80b3bb | 600 | #endif /* CONFIG_ARCH_OMAP2 */ |
e74984e4 | 601 | |
bb256f80 | 602 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX) |
7bdc83f7 | 603 | OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon", |
2eb03937 | 604 | 2, "timer_sys_ck", NULL); |
7bdc83f7 | 605 | OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure", |
2eb03937 | 606 | 2, "timer_sys_ck", NULL); |
6f80b3bb | 607 | #endif /* CONFIG_ARCH_OMAP3 */ |
e74984e4 | 608 | |
00ea4d56 | 609 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) |
2eb03937 JH |
610 | OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL, |
611 | 1, "timer_sys_ck", "ti,timer-alwon"); | |
00ea4d56 | 612 | #endif |
08f30989 | 613 | |
f18153f9 S |
614 | #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ |
615 | defined(CONFIG_SOC_DRA7XX) | |
4615943c JH |
616 | static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon", |
617 | 2, "sys_clkin_ck", NULL); | |
00ea4d56 | 618 | #endif |
08f30989 | 619 | |
e74984e4 | 620 | #ifdef CONFIG_ARCH_OMAP4 |
18060f35 | 621 | #ifdef CONFIG_HAVE_ARM_TWD |
6f80b3bb | 622 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29); |
6bb27d73 | 623 | void __init omap4_local_timer_init(void) |
a45c983f | 624 | { |
6f80b3bb | 625 | omap4_sync32k_timer_init(); |
a45c983f MZ |
626 | /* Local timers are not supprted on OMAP4430 ES1.0 */ |
627 | if (omap_rev() != OMAP4430_REV_ES1_0) { | |
628 | int err; | |
629 | ||
eed0de27 | 630 | if (of_have_populated_dt()) { |
da4a686a | 631 | clocksource_of_init(); |
eed0de27 SS |
632 | return; |
633 | } | |
634 | ||
a45c983f MZ |
635 | err = twd_local_timer_register(&twd_local_timer); |
636 | if (err) | |
637 | pr_err("twd_local_timer_register failed %d\n", err); | |
638 | } | |
1dbae815 | 639 | } |
18060f35 | 640 | #else |
6bb27d73 | 641 | void __init omap4_local_timer_init(void) |
6f80b3bb | 642 | { |
73f14f6d | 643 | omap4_sync32k_timer_init(); |
6f80b3bb | 644 | } |
18060f35 | 645 | #endif /* CONFIG_HAVE_ARM_TWD */ |
6f80b3bb | 646 | #endif /* CONFIG_ARCH_OMAP4 */ |
c345c8b0 | 647 | |
0b8214fe | 648 | #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) |
6bb27d73 | 649 | void __init omap5_realtime_timer_init(void) |
fa6d79d2 | 650 | { |
00ea4d56 | 651 | omap4_sync32k_timer_init(); |
fa6d79d2 | 652 | realtime_counter_init(); |
3c7c5dab | 653 | |
405f5e5e | 654 | clocksource_of_init(); |
fa6d79d2 | 655 | } |
0b8214fe | 656 | #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */ |
37b3280d | 657 | |
c345c8b0 TKD |
658 | /** |
659 | * omap_timer_init - build and register timer device with an | |
660 | * associated timer hwmod | |
661 | * @oh: timer hwmod pointer to be used to build timer device | |
662 | * @user: parameter that can be passed from calling hwmod API | |
663 | * | |
664 | * Called by omap_hwmod_for_each_by_class to register each of the timer | |
665 | * devices present in the system. The number of timer devices is known | |
666 | * by parsing through the hwmod database for a given class name. At the | |
667 | * end of function call memory is allocated for timer device and it is | |
668 | * registered to the framework ready to be proved by the driver. | |
669 | */ | |
670 | static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) | |
671 | { | |
672 | int id; | |
673 | int ret = 0; | |
674 | char *name = "omap_timer"; | |
675 | struct dmtimer_platform_data *pdata; | |
c541c15f | 676 | struct platform_device *pdev; |
c345c8b0 TKD |
677 | struct omap_timer_capability_dev_attr *timer_dev_attr; |
678 | ||
679 | pr_debug("%s: %s\n", __func__, oh->name); | |
680 | ||
681 | /* on secure device, do not register secure timer */ | |
682 | timer_dev_attr = oh->dev_attr; | |
683 | if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) | |
684 | if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) | |
685 | return ret; | |
686 | ||
687 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); | |
688 | if (!pdata) { | |
689 | pr_err("%s: No memory for [%s]\n", __func__, oh->name); | |
690 | return -ENOMEM; | |
691 | } | |
692 | ||
693 | /* | |
694 | * Extract the IDs from name field in hwmod database | |
695 | * and use the same for constructing ids' for the | |
696 | * timer devices. In a way, we are avoiding usage of | |
697 | * static variable witin the function to do the same. | |
698 | * CAUTION: We have to be careful and make sure the | |
699 | * name in hwmod database does not change in which case | |
700 | * we might either make corresponding change here or | |
701 | * switch back static variable mechanism. | |
702 | */ | |
703 | sscanf(oh->name, "timer%2d", &id); | |
704 | ||
d1c1691b JH |
705 | if (timer_dev_attr) |
706 | pdata->timer_capability = timer_dev_attr->timer_capability; | |
0dad9fae | 707 | |
bfd6d021 | 708 | pdata->timer_errata = omap_dm_timer_get_errata(); |
6e740f9a TL |
709 | pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; |
710 | ||
c1d1cd59 | 711 | pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata)); |
c345c8b0 | 712 | |
c541c15f | 713 | if (IS_ERR(pdev)) { |
c345c8b0 TKD |
714 | pr_err("%s: Can't build omap_device for %s: %s.\n", |
715 | __func__, name, oh->name); | |
716 | ret = -EINVAL; | |
717 | } | |
718 | ||
719 | kfree(pdata); | |
720 | ||
721 | return ret; | |
722 | } | |
3392cdd3 TKD |
723 | |
724 | /** | |
725 | * omap2_dm_timer_init - top level regular device initialization | |
726 | * | |
727 | * Uses dedicated hwmod api to parse through hwmod database for | |
728 | * given class name and then build and register the timer device. | |
729 | */ | |
730 | static int __init omap2_dm_timer_init(void) | |
731 | { | |
732 | int ret; | |
733 | ||
9725f445 JH |
734 | /* If dtb is there, the devices will be created dynamically */ |
735 | if (of_have_populated_dt()) | |
736 | return -ENODEV; | |
737 | ||
3392cdd3 TKD |
738 | ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); |
739 | if (unlikely(ret)) { | |
740 | pr_err("%s: device registration failed.\n", __func__); | |
741 | return -EINVAL; | |
742 | } | |
743 | ||
744 | return 0; | |
745 | } | |
b76c8b19 | 746 | omap_arch_initcall(omap2_dm_timer_init); |
1fe97c8f VH |
747 | |
748 | /** | |
749 | * omap2_override_clocksource - clocksource override with user configuration | |
750 | * | |
751 | * Allows user to override default clocksource, using kernel parameter | |
752 | * clocksource="gp_timer" (For all OMAP2PLUS architectures) | |
753 | * | |
754 | * Note that, here we are using same standard kernel parameter "clocksource=", | |
755 | * and not introducing any OMAP specific interface. | |
756 | */ | |
757 | static int __init omap2_override_clocksource(char *str) | |
758 | { | |
759 | if (!str) | |
760 | return 0; | |
761 | /* | |
762 | * For OMAP architecture, we only have two options | |
763 | * - sync_32k (default) | |
764 | * - gp_timer (sys_clk based) | |
765 | */ | |
766 | if (!strcmp(str, "gp_timer")) | |
767 | use_gptimer_clksrc = true; | |
768 | ||
769 | return 0; | |
770 | } | |
771 | early_param("clocksource", omap2_override_clocksource); |