Commit | Line | Data |
---|---|---|
1dbae815 | 1 | /* |
0f622e8c | 2 | * linux/arch/arm/mach-omap2/timer.c |
1dbae815 TL |
3 | * |
4 | * OMAP2 GP timer support. | |
5 | * | |
f248076c PW |
6 | * Copyright (C) 2009 Nokia Corporation |
7 | * | |
5a3a388f KH |
8 | * Update to use new clocksource/clockevent layers |
9 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | |
10 | * Copyright (C) 2007 MontaVista Software, Inc. | |
11 | * | |
12 | * Original driver: | |
1dbae815 TL |
13 | * Copyright (C) 2005 Nokia Corporation |
14 | * Author: Paul Mundt <paul.mundt@nokia.com> | |
96de0e25 | 15 | * Juha Yrjölä <juha.yrjola@nokia.com> |
77900a2f | 16 | * OMAP Dual-mode timer framework support by Timo Teras |
1dbae815 TL |
17 | * |
18 | * Some parts based off of TI's 24xx code: | |
19 | * | |
44169075 | 20 | * Copyright (C) 2004-2009 Texas Instruments, Inc. |
1dbae815 TL |
21 | * |
22 | * Roughly modelled after the OMAP1 MPU timer code. | |
44169075 | 23 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
1dbae815 TL |
24 | * |
25 | * This file is subject to the terms and conditions of the GNU General Public | |
26 | * License. See the file "COPYING" in the main directory of this archive | |
27 | * for more details. | |
28 | */ | |
29 | #include <linux/init.h> | |
30 | #include <linux/time.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/err.h> | |
f8ce2547 | 33 | #include <linux/clk.h> |
77900a2f | 34 | #include <linux/delay.h> |
e6687290 | 35 | #include <linux/irq.h> |
5a3a388f KH |
36 | #include <linux/clocksource.h> |
37 | #include <linux/clockchips.h> | |
c345c8b0 | 38 | #include <linux/slab.h> |
f8ce2547 | 39 | |
1dbae815 | 40 | #include <asm/mach/time.h> |
ce491cf8 | 41 | #include <plat/dmtimer.h> |
39e1d4c1 | 42 | #include <asm/localtimer.h> |
cbc94380 | 43 | #include <asm/sched_clock.h> |
4e65331c | 44 | #include "common.h" |
38698bef | 45 | #include <plat/omap_hwmod.h> |
c345c8b0 | 46 | #include <plat/omap_device.h> |
b481113a TKD |
47 | #include <plat/omap-pm.h> |
48 | ||
49 | #include "powerdomain.h" | |
1dbae815 | 50 | |
aa561889 TL |
51 | /* Parent clocks, eventually these will come from the clock framework */ |
52 | ||
53 | #define OMAP2_MPU_SOURCE "sys_ck" | |
54 | #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE | |
55 | #define OMAP4_MPU_SOURCE "sys_clkin_ck" | |
56 | #define OMAP2_32K_SOURCE "func_32k_ck" | |
57 | #define OMAP3_32K_SOURCE "omap_32k_fck" | |
58 | #define OMAP4_32K_SOURCE "sys_32k_ck" | |
59 | ||
60 | #ifdef CONFIG_OMAP_32K_TIMER | |
61 | #define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE | |
62 | #define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE | |
63 | #define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE | |
64 | #define OMAP3_SECURE_TIMER 12 | |
65 | #else | |
66 | #define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE | |
67 | #define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE | |
68 | #define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE | |
69 | #define OMAP3_SECURE_TIMER 1 | |
70 | #endif | |
d8328f3b | 71 | |
f248076c PW |
72 | /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ |
73 | #define MAX_GPTIMER_ID 12 | |
74 | ||
0dad9fae | 75 | static u32 sys_timer_reserved; |
11a0186f | 76 | |
aa561889 TL |
77 | /* Clockevent code */ |
78 | ||
79 | static struct omap_dm_timer clkev; | |
5a3a388f | 80 | static struct clock_event_device clockevent_gpt; |
1dbae815 | 81 | |
0cd61b68 | 82 | static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) |
1dbae815 | 83 | { |
5a3a388f KH |
84 | struct clock_event_device *evt = &clockevent_gpt; |
85 | ||
ee17f114 | 86 | __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); |
1dbae815 | 87 | |
5a3a388f | 88 | evt->event_handler(evt); |
1dbae815 TL |
89 | return IRQ_HANDLED; |
90 | } | |
91 | ||
92 | static struct irqaction omap2_gp_timer_irq = { | |
93 | .name = "gp timer", | |
b30fabad | 94 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
1dbae815 TL |
95 | .handler = omap2_gp_timer_interrupt, |
96 | }; | |
97 | ||
5a3a388f KH |
98 | static int omap2_gp_timer_set_next_event(unsigned long cycles, |
99 | struct clock_event_device *evt) | |
1dbae815 | 100 | { |
ee17f114 | 101 | __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, |
aa561889 | 102 | 0xffffffff - cycles, 1); |
5a3a388f KH |
103 | |
104 | return 0; | |
105 | } | |
106 | ||
107 | static void omap2_gp_timer_set_mode(enum clock_event_mode mode, | |
108 | struct clock_event_device *evt) | |
109 | { | |
110 | u32 period; | |
111 | ||
ee17f114 | 112 | __omap_dm_timer_stop(&clkev, 1, clkev.rate); |
5a3a388f KH |
113 | |
114 | switch (mode) { | |
115 | case CLOCK_EVT_MODE_PERIODIC: | |
aa561889 | 116 | period = clkev.rate / HZ; |
5a3a388f | 117 | period -= 1; |
aa561889 | 118 | /* Looks like we need to first set the load value separately */ |
ee17f114 | 119 | __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, |
aa561889 | 120 | 0xffffffff - period, 1); |
ee17f114 | 121 | __omap_dm_timer_load_start(&clkev, |
aa561889 TL |
122 | OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, |
123 | 0xffffffff - period, 1); | |
5a3a388f KH |
124 | break; |
125 | case CLOCK_EVT_MODE_ONESHOT: | |
126 | break; | |
127 | case CLOCK_EVT_MODE_UNUSED: | |
128 | case CLOCK_EVT_MODE_SHUTDOWN: | |
129 | case CLOCK_EVT_MODE_RESUME: | |
130 | break; | |
131 | } | |
132 | } | |
133 | ||
134 | static struct clock_event_device clockevent_gpt = { | |
135 | .name = "gp timer", | |
136 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
137 | .shift = 32, | |
138 | .set_next_event = omap2_gp_timer_set_next_event, | |
139 | .set_mode = omap2_gp_timer_set_mode, | |
140 | }; | |
141 | ||
aa561889 TL |
142 | static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, |
143 | int gptimer_id, | |
144 | const char *fck_source) | |
5a3a388f | 145 | { |
aa561889 TL |
146 | char name[10]; /* 10 = sizeof("gptXX_Xck0") */ |
147 | struct omap_hwmod *oh; | |
148 | size_t size; | |
149 | int res = 0; | |
150 | ||
151 | sprintf(name, "timer%d", gptimer_id); | |
152 | omap_hwmod_setup_one(name); | |
153 | oh = omap_hwmod_lookup(name); | |
154 | if (!oh) | |
155 | return -ENODEV; | |
156 | ||
157 | timer->irq = oh->mpu_irqs[0].irq; | |
158 | timer->phys_base = oh->slaves[0]->addr->pa_start; | |
159 | size = oh->slaves[0]->addr->pa_end - timer->phys_base; | |
160 | ||
161 | /* Static mapping, never released */ | |
162 | timer->io_base = ioremap(timer->phys_base, size); | |
163 | if (!timer->io_base) | |
164 | return -ENXIO; | |
165 | ||
166 | /* After the dmtimer is using hwmod these clocks won't be needed */ | |
167 | sprintf(name, "gpt%d_fck", gptimer_id); | |
168 | timer->fclk = clk_get(NULL, name); | |
169 | if (IS_ERR(timer->fclk)) | |
170 | return -ENODEV; | |
171 | ||
172 | sprintf(name, "gpt%d_ick", gptimer_id); | |
173 | timer->iclk = clk_get(NULL, name); | |
174 | if (IS_ERR(timer->iclk)) { | |
175 | clk_put(timer->fclk); | |
176 | return -ENODEV; | |
177 | } | |
f248076c | 178 | |
aa561889 TL |
179 | omap_hwmod_enable(oh); |
180 | ||
11a0186f TL |
181 | sys_timer_reserved |= (1 << (gptimer_id - 1)); |
182 | ||
aa561889 TL |
183 | if (gptimer_id != 12) { |
184 | struct clk *src; | |
185 | ||
186 | src = clk_get(NULL, fck_source); | |
187 | if (IS_ERR(src)) { | |
188 | res = -EINVAL; | |
189 | } else { | |
190 | res = __omap_dm_timer_set_source(timer->fclk, src); | |
191 | if (IS_ERR_VALUE(res)) | |
192 | pr_warning("%s: timer%i cannot set source\n", | |
193 | __func__, gptimer_id); | |
194 | clk_put(src); | |
195 | } | |
196 | } | |
ee17f114 TL |
197 | __omap_dm_timer_init_regs(timer); |
198 | __omap_dm_timer_reset(timer, 1, 1); | |
aa561889 TL |
199 | timer->posted = 1; |
200 | ||
201 | timer->rate = clk_get_rate(timer->fclk); | |
1dbae815 | 202 | |
aa561889 | 203 | timer->reserved = 1; |
38698bef | 204 | |
aa561889 TL |
205 | return res; |
206 | } | |
f248076c | 207 | |
aa561889 TL |
208 | static void __init omap2_gp_clockevent_init(int gptimer_id, |
209 | const char *fck_source) | |
210 | { | |
211 | int res; | |
f248076c | 212 | |
aa561889 TL |
213 | res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source); |
214 | BUG_ON(res); | |
f248076c | 215 | |
98e182a2 | 216 | omap2_gp_timer_irq.dev_id = (void *)&clkev; |
aa561889 | 217 | setup_irq(clkev.irq, &omap2_gp_timer_irq); |
5a3a388f | 218 | |
ee17f114 | 219 | __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); |
aa561889 TL |
220 | |
221 | clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC, | |
5a3a388f KH |
222 | clockevent_gpt.shift); |
223 | clockevent_gpt.max_delta_ns = | |
224 | clockevent_delta2ns(0xffffffff, &clockevent_gpt); | |
225 | clockevent_gpt.min_delta_ns = | |
df88acbb AK |
226 | clockevent_delta2ns(3, &clockevent_gpt); |
227 | /* Timer internal resynch latency. */ | |
5a3a388f | 228 | |
320ab2b0 | 229 | clockevent_gpt.cpumask = cpumask_of(0); |
5a3a388f | 230 | clockevents_register_device(&clockevent_gpt); |
aa561889 TL |
231 | |
232 | pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n", | |
233 | gptimer_id, clkev.rate); | |
5a3a388f KH |
234 | } |
235 | ||
f248076c PW |
236 | /* Clocksource code */ |
237 | ||
5a3a388f | 238 | #ifdef CONFIG_OMAP_32K_TIMER |
0f622e8c | 239 | /* |
5a3a388f KH |
240 | * When 32k-timer is enabled, don't use GPTimer for clocksource |
241 | * instead, just leave default clocksource which uses the 32k | |
d8328f3b | 242 | * sync counter. See clocksource setup in plat-omap/counter_32k.c |
5a3a388f KH |
243 | */ |
244 | ||
3d05a3e8 | 245 | static void __init omap2_gp_clocksource_init(int unused, const char *dummy) |
d8328f3b PW |
246 | { |
247 | omap_init_clocksource_32k(); | |
248 | } | |
249 | ||
5a3a388f | 250 | #else |
3d05a3e8 TL |
251 | |
252 | static struct omap_dm_timer clksrc; | |
253 | ||
5a3a388f KH |
254 | /* |
255 | * clocksource | |
256 | */ | |
cbc94380 | 257 | static DEFINE_CLOCK_DATA(cd); |
8e19608e | 258 | static cycle_t clocksource_read_cycles(struct clocksource *cs) |
5a3a388f | 259 | { |
ee17f114 | 260 | return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1); |
5a3a388f KH |
261 | } |
262 | ||
263 | static struct clocksource clocksource_gpt = { | |
264 | .name = "gp timer", | |
265 | .rating = 300, | |
266 | .read = clocksource_read_cycles, | |
267 | .mask = CLOCKSOURCE_MASK(32), | |
5a3a388f KH |
268 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
269 | }; | |
270 | ||
cbc94380 PW |
271 | static void notrace dmtimer_update_sched_clock(void) |
272 | { | |
273 | u32 cyc; | |
274 | ||
ee17f114 | 275 | cyc = __omap_dm_timer_read_counter(&clksrc, 1); |
cbc94380 PW |
276 | |
277 | update_sched_clock(&cd, cyc, (u32)~0); | |
278 | } | |
279 | ||
3d05a3e8 | 280 | unsigned long long notrace sched_clock(void) |
5a3a388f | 281 | { |
3d05a3e8 | 282 | u32 cyc = 0; |
5a3a388f | 283 | |
3d05a3e8 | 284 | if (clksrc.reserved) |
ee17f114 | 285 | cyc = __omap_dm_timer_read_counter(&clksrc, 1); |
5a3a388f | 286 | |
3d05a3e8 TL |
287 | return cyc_to_sched_clock(&cd, cyc, (u32)~0); |
288 | } | |
289 | ||
290 | /* Setup free-running counter for clocksource */ | |
291 | static void __init omap2_gp_clocksource_init(int gptimer_id, | |
292 | const char *fck_source) | |
293 | { | |
294 | int res; | |
295 | ||
296 | res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source); | |
297 | BUG_ON(res); | |
5a3a388f | 298 | |
3d05a3e8 TL |
299 | pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n", |
300 | gptimer_id, clksrc.rate); | |
5a3a388f | 301 | |
ee17f114 | 302 | __omap_dm_timer_load_start(&clksrc, |
e9d0b97e | 303 | OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1); |
3d05a3e8 | 304 | init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate); |
cbc94380 | 305 | |
3d05a3e8 TL |
306 | if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) |
307 | pr_err("Could not register clocksource %s\n", | |
308 | clocksource_gpt.name); | |
5a3a388f KH |
309 | } |
310 | #endif | |
311 | ||
3d05a3e8 TL |
312 | #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \ |
313 | clksrc_nr, clksrc_src) \ | |
e74984e4 TL |
314 | static void __init omap##name##_timer_init(void) \ |
315 | { \ | |
aa561889 | 316 | omap2_gp_clockevent_init((clkev_nr), clkev_src); \ |
3d05a3e8 | 317 | omap2_gp_clocksource_init((clksrc_nr), clksrc_src); \ |
e74984e4 TL |
318 | } |
319 | ||
320 | #define OMAP_SYS_TIMER(name) \ | |
321 | struct sys_timer omap##name##_timer = { \ | |
322 | .init = omap##name##_timer_init, \ | |
323 | }; | |
324 | ||
325 | #ifdef CONFIG_ARCH_OMAP2 | |
3d05a3e8 | 326 | OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE) |
e74984e4 TL |
327 | OMAP_SYS_TIMER(2) |
328 | #endif | |
329 | ||
330 | #ifdef CONFIG_ARCH_OMAP3 | |
3d05a3e8 | 331 | OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE) |
e74984e4 | 332 | OMAP_SYS_TIMER(3) |
3d05a3e8 TL |
333 | OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE, |
334 | 2, OMAP3_MPU_SOURCE) | |
e74984e4 TL |
335 | OMAP_SYS_TIMER(3_secure) |
336 | #endif | |
337 | ||
338 | #ifdef CONFIG_ARCH_OMAP4 | |
339 | static void __init omap4_timer_init(void) | |
5a3a388f | 340 | { |
39e1d4c1 | 341 | #ifdef CONFIG_LOCAL_TIMERS |
e74984e4 TL |
342 | twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256); |
343 | BUG_ON(!twd_base); | |
39e1d4c1 | 344 | #endif |
aa561889 | 345 | omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); |
3d05a3e8 | 346 | omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE); |
1dbae815 | 347 | } |
e74984e4 TL |
348 | OMAP_SYS_TIMER(4) |
349 | #endif | |
c345c8b0 TKD |
350 | |
351 | /** | |
352 | * omap2_dm_timer_set_src - change the timer input clock source | |
353 | * @pdev: timer platform device pointer | |
354 | * @source: array index of parent clock source | |
355 | */ | |
356 | static int omap2_dm_timer_set_src(struct platform_device *pdev, int source) | |
357 | { | |
358 | int ret; | |
359 | struct dmtimer_platform_data *pdata = pdev->dev.platform_data; | |
360 | struct clk *fclk, *parent; | |
361 | char *parent_name = NULL; | |
362 | ||
363 | fclk = clk_get(&pdev->dev, "fck"); | |
364 | if (IS_ERR_OR_NULL(fclk)) { | |
365 | dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n", | |
366 | __func__, __LINE__); | |
367 | return -EINVAL; | |
368 | } | |
369 | ||
370 | switch (source) { | |
371 | case OMAP_TIMER_SRC_SYS_CLK: | |
372 | parent_name = "sys_ck"; | |
373 | break; | |
374 | ||
375 | case OMAP_TIMER_SRC_32_KHZ: | |
376 | parent_name = "32k_ck"; | |
377 | break; | |
378 | ||
379 | case OMAP_TIMER_SRC_EXT_CLK: | |
380 | if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) { | |
381 | parent_name = "alt_ck"; | |
382 | break; | |
383 | } | |
384 | dev_err(&pdev->dev, "%s: %d: invalid clk src.\n", | |
385 | __func__, __LINE__); | |
386 | clk_put(fclk); | |
387 | return -EINVAL; | |
388 | } | |
389 | ||
390 | parent = clk_get(&pdev->dev, parent_name); | |
391 | if (IS_ERR_OR_NULL(parent)) { | |
392 | dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n", | |
393 | __func__, __LINE__, parent_name); | |
394 | clk_put(fclk); | |
395 | return -EINVAL; | |
396 | } | |
397 | ||
398 | ret = clk_set_parent(fclk, parent); | |
399 | if (IS_ERR_VALUE(ret)) { | |
400 | dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n", | |
401 | __func__, parent_name); | |
402 | ret = -EINVAL; | |
403 | } | |
404 | ||
405 | clk_put(parent); | |
406 | clk_put(fclk); | |
407 | ||
408 | return ret; | |
409 | } | |
410 | ||
c345c8b0 TKD |
411 | /** |
412 | * omap_timer_init - build and register timer device with an | |
413 | * associated timer hwmod | |
414 | * @oh: timer hwmod pointer to be used to build timer device | |
415 | * @user: parameter that can be passed from calling hwmod API | |
416 | * | |
417 | * Called by omap_hwmod_for_each_by_class to register each of the timer | |
418 | * devices present in the system. The number of timer devices is known | |
419 | * by parsing through the hwmod database for a given class name. At the | |
420 | * end of function call memory is allocated for timer device and it is | |
421 | * registered to the framework ready to be proved by the driver. | |
422 | */ | |
423 | static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) | |
424 | { | |
425 | int id; | |
426 | int ret = 0; | |
427 | char *name = "omap_timer"; | |
428 | struct dmtimer_platform_data *pdata; | |
c541c15f | 429 | struct platform_device *pdev; |
c345c8b0 | 430 | struct omap_timer_capability_dev_attr *timer_dev_attr; |
b481113a | 431 | struct powerdomain *pwrdm; |
c345c8b0 TKD |
432 | |
433 | pr_debug("%s: %s\n", __func__, oh->name); | |
434 | ||
435 | /* on secure device, do not register secure timer */ | |
436 | timer_dev_attr = oh->dev_attr; | |
437 | if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) | |
438 | if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) | |
439 | return ret; | |
440 | ||
441 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); | |
442 | if (!pdata) { | |
443 | pr_err("%s: No memory for [%s]\n", __func__, oh->name); | |
444 | return -ENOMEM; | |
445 | } | |
446 | ||
447 | /* | |
448 | * Extract the IDs from name field in hwmod database | |
449 | * and use the same for constructing ids' for the | |
450 | * timer devices. In a way, we are avoiding usage of | |
451 | * static variable witin the function to do the same. | |
452 | * CAUTION: We have to be careful and make sure the | |
453 | * name in hwmod database does not change in which case | |
454 | * we might either make corresponding change here or | |
455 | * switch back static variable mechanism. | |
456 | */ | |
457 | sscanf(oh->name, "timer%2d", &id); | |
458 | ||
459 | pdata->set_timer_src = omap2_dm_timer_set_src; | |
460 | pdata->timer_ip_version = oh->class->rev; | |
461 | ||
0dad9fae TL |
462 | /* Mark clocksource and clockevent timers as reserved */ |
463 | if ((sys_timer_reserved >> (id - 1)) & 0x1) | |
464 | pdata->reserved = 1; | |
465 | ||
b481113a TKD |
466 | pwrdm = omap_hwmod_get_pwrdm(oh); |
467 | pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm); | |
468 | #ifdef CONFIG_PM | |
469 | pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; | |
470 | #endif | |
c541c15f | 471 | pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata), |
c16ae1e6 | 472 | NULL, 0, 0); |
c345c8b0 | 473 | |
c541c15f | 474 | if (IS_ERR(pdev)) { |
c345c8b0 TKD |
475 | pr_err("%s: Can't build omap_device for %s: %s.\n", |
476 | __func__, name, oh->name); | |
477 | ret = -EINVAL; | |
478 | } | |
479 | ||
480 | kfree(pdata); | |
481 | ||
482 | return ret; | |
483 | } | |
3392cdd3 TKD |
484 | |
485 | /** | |
486 | * omap2_dm_timer_init - top level regular device initialization | |
487 | * | |
488 | * Uses dedicated hwmod api to parse through hwmod database for | |
489 | * given class name and then build and register the timer device. | |
490 | */ | |
491 | static int __init omap2_dm_timer_init(void) | |
492 | { | |
493 | int ret; | |
494 | ||
495 | ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); | |
496 | if (unlikely(ret)) { | |
497 | pr_err("%s: device registration failed.\n", __func__); | |
498 | return -EINVAL; | |
499 | } | |
500 | ||
501 | return 0; | |
502 | } | |
503 | arch_initcall(omap2_dm_timer_init); |