Commit | Line | Data |
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1dbae815 | 1 | /* |
0f622e8c | 2 | * linux/arch/arm/mach-omap2/timer.c |
1dbae815 TL |
3 | * |
4 | * OMAP2 GP timer support. | |
5 | * | |
f248076c PW |
6 | * Copyright (C) 2009 Nokia Corporation |
7 | * | |
5a3a388f KH |
8 | * Update to use new clocksource/clockevent layers |
9 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | |
10 | * Copyright (C) 2007 MontaVista Software, Inc. | |
11 | * | |
12 | * Original driver: | |
1dbae815 TL |
13 | * Copyright (C) 2005 Nokia Corporation |
14 | * Author: Paul Mundt <paul.mundt@nokia.com> | |
96de0e25 | 15 | * Juha Yrjölä <juha.yrjola@nokia.com> |
77900a2f | 16 | * OMAP Dual-mode timer framework support by Timo Teras |
1dbae815 TL |
17 | * |
18 | * Some parts based off of TI's 24xx code: | |
19 | * | |
44169075 | 20 | * Copyright (C) 2004-2009 Texas Instruments, Inc. |
1dbae815 TL |
21 | * |
22 | * Roughly modelled after the OMAP1 MPU timer code. | |
44169075 | 23 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
1dbae815 TL |
24 | * |
25 | * This file is subject to the terms and conditions of the GNU General Public | |
26 | * License. See the file "COPYING" in the main directory of this archive | |
27 | * for more details. | |
28 | */ | |
29 | #include <linux/init.h> | |
30 | #include <linux/time.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/err.h> | |
f8ce2547 | 33 | #include <linux/clk.h> |
77900a2f | 34 | #include <linux/delay.h> |
e6687290 | 35 | #include <linux/irq.h> |
5a3a388f KH |
36 | #include <linux/clocksource.h> |
37 | #include <linux/clockchips.h> | |
c345c8b0 | 38 | #include <linux/slab.h> |
eed0de27 | 39 | #include <linux/of.h> |
9725f445 JH |
40 | #include <linux/of_address.h> |
41 | #include <linux/of_irq.h> | |
f8ce2547 | 42 | |
1dbae815 | 43 | #include <asm/mach/time.h> |
a45c983f | 44 | #include <asm/smp_twd.h> |
cbc94380 | 45 | #include <asm/sched_clock.h> |
7d7e1eba | 46 | |
3c7c5dab | 47 | #include <asm/arch_timer.h> |
2a296c8f | 48 | #include "omap_hwmod.h" |
25c7d49e | 49 | #include "omap_device.h" |
5c2e8852 | 50 | #include <plat/counter-32k.h> |
7d7e1eba | 51 | #include <plat/dmtimer.h> |
1d5aef49 | 52 | #include "omap-pm.h" |
b481113a | 53 | |
dbc04161 | 54 | #include "soc.h" |
7d7e1eba | 55 | #include "common.h" |
b481113a | 56 | #include "powerdomain.h" |
1dbae815 | 57 | |
aa561889 TL |
58 | /* Parent clocks, eventually these will come from the clock framework */ |
59 | ||
60 | #define OMAP2_MPU_SOURCE "sys_ck" | |
61 | #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE | |
62 | #define OMAP4_MPU_SOURCE "sys_clkin_ck" | |
63 | #define OMAP2_32K_SOURCE "func_32k_ck" | |
64 | #define OMAP3_32K_SOURCE "omap_32k_fck" | |
65 | #define OMAP4_32K_SOURCE "sys_32k_ck" | |
66 | ||
67 | #ifdef CONFIG_OMAP_32K_TIMER | |
68 | #define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE | |
69 | #define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE | |
70 | #define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE | |
71 | #define OMAP3_SECURE_TIMER 12 | |
9725f445 | 72 | #define TIMER_PROP_SECURE "ti,timer-secure" |
aa561889 TL |
73 | #else |
74 | #define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE | |
75 | #define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE | |
76 | #define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE | |
77 | #define OMAP3_SECURE_TIMER 1 | |
9725f445 | 78 | #define TIMER_PROP_SECURE "ti,timer-alwon" |
aa561889 | 79 | #endif |
d8328f3b | 80 | |
fa6d79d2 SS |
81 | #define REALTIME_COUNTER_BASE 0x48243200 |
82 | #define INCREMENTER_NUMERATOR_OFFSET 0x10 | |
83 | #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 | |
84 | #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 | |
85 | ||
aa561889 TL |
86 | /* Clockevent code */ |
87 | ||
88 | static struct omap_dm_timer clkev; | |
5a3a388f | 89 | static struct clock_event_device clockevent_gpt; |
1dbae815 | 90 | |
0cd61b68 | 91 | static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) |
1dbae815 | 92 | { |
5a3a388f KH |
93 | struct clock_event_device *evt = &clockevent_gpt; |
94 | ||
ee17f114 | 95 | __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); |
1dbae815 | 96 | |
5a3a388f | 97 | evt->event_handler(evt); |
1dbae815 TL |
98 | return IRQ_HANDLED; |
99 | } | |
100 | ||
101 | static struct irqaction omap2_gp_timer_irq = { | |
f36921be | 102 | .name = "gp_timer", |
b30fabad | 103 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
1dbae815 TL |
104 | .handler = omap2_gp_timer_interrupt, |
105 | }; | |
106 | ||
5a3a388f KH |
107 | static int omap2_gp_timer_set_next_event(unsigned long cycles, |
108 | struct clock_event_device *evt) | |
1dbae815 | 109 | { |
ee17f114 | 110 | __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, |
971d0254 | 111 | 0xffffffff - cycles, OMAP_TIMER_POSTED); |
5a3a388f KH |
112 | |
113 | return 0; | |
114 | } | |
115 | ||
116 | static void omap2_gp_timer_set_mode(enum clock_event_mode mode, | |
117 | struct clock_event_device *evt) | |
118 | { | |
119 | u32 period; | |
120 | ||
971d0254 | 121 | __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); |
5a3a388f KH |
122 | |
123 | switch (mode) { | |
124 | case CLOCK_EVT_MODE_PERIODIC: | |
aa561889 | 125 | period = clkev.rate / HZ; |
5a3a388f | 126 | period -= 1; |
aa561889 | 127 | /* Looks like we need to first set the load value separately */ |
ee17f114 | 128 | __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, |
971d0254 | 129 | 0xffffffff - period, OMAP_TIMER_POSTED); |
ee17f114 | 130 | __omap_dm_timer_load_start(&clkev, |
aa561889 | 131 | OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, |
971d0254 | 132 | 0xffffffff - period, OMAP_TIMER_POSTED); |
5a3a388f KH |
133 | break; |
134 | case CLOCK_EVT_MODE_ONESHOT: | |
135 | break; | |
136 | case CLOCK_EVT_MODE_UNUSED: | |
137 | case CLOCK_EVT_MODE_SHUTDOWN: | |
138 | case CLOCK_EVT_MODE_RESUME: | |
139 | break; | |
140 | } | |
141 | } | |
142 | ||
143 | static struct clock_event_device clockevent_gpt = { | |
f36921be | 144 | .name = "gp_timer", |
5a3a388f KH |
145 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
146 | .shift = 32, | |
11d6ec2e | 147 | .rating = 300, |
5a3a388f KH |
148 | .set_next_event = omap2_gp_timer_set_next_event, |
149 | .set_mode = omap2_gp_timer_set_mode, | |
150 | }; | |
151 | ||
ad24bde8 JH |
152 | static struct property device_disabled = { |
153 | .name = "status", | |
154 | .length = sizeof("disabled"), | |
155 | .value = "disabled", | |
156 | }; | |
157 | ||
158 | static struct of_device_id omap_timer_match[] __initdata = { | |
159 | { .compatible = "ti,omap2-timer", }, | |
160 | { } | |
161 | }; | |
162 | ||
9883f7c8 JH |
163 | static struct of_device_id omap_counter_match[] __initdata = { |
164 | { .compatible = "ti,omap-counter32k", }, | |
165 | { } | |
166 | }; | |
167 | ||
9725f445 JH |
168 | /** |
169 | * omap_get_timer_dt - get a timer using device-tree | |
170 | * @match - device-tree match structure for matching a device type | |
171 | * @property - optional timer property to match | |
172 | * | |
173 | * Helper function to get a timer during early boot using device-tree for use | |
174 | * as kernel system timer. Optionally, the property argument can be used to | |
175 | * select a timer with a specific property. Once a timer is found then mark | |
176 | * the timer node in device-tree as disabled, to prevent the kernel from | |
177 | * registering this timer as a platform device and so no one else can use it. | |
178 | */ | |
179 | static struct device_node * __init omap_get_timer_dt(struct of_device_id *match, | |
180 | const char *property) | |
181 | { | |
182 | struct device_node *np; | |
183 | ||
184 | for_each_matching_node(np, match) { | |
185 | if (!of_device_is_available(np)) { | |
186 | of_node_put(np); | |
187 | continue; | |
188 | } | |
189 | ||
190 | if (property && !of_get_property(np, property, NULL)) { | |
191 | of_node_put(np); | |
192 | continue; | |
193 | } | |
194 | ||
195 | prom_add_property(np, &device_disabled); | |
196 | return np; | |
197 | } | |
198 | ||
199 | return NULL; | |
200 | } | |
201 | ||
ad24bde8 JH |
202 | /** |
203 | * omap_dmtimer_init - initialisation function when device tree is used | |
204 | * | |
205 | * For secure OMAP3 devices, timers with device type "timer-secure" cannot | |
206 | * be used by the kernel as they are reserved. Therefore, to prevent the | |
207 | * kernel registering these devices remove them dynamically from the device | |
208 | * tree on boot. | |
209 | */ | |
210 | void __init omap_dmtimer_init(void) | |
211 | { | |
212 | struct device_node *np; | |
213 | ||
214 | if (!cpu_is_omap34xx()) | |
215 | return; | |
216 | ||
217 | /* If we are a secure device, remove any secure timer nodes */ | |
218 | if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { | |
9725f445 JH |
219 | np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure"); |
220 | if (np) | |
221 | of_node_put(np); | |
ad24bde8 JH |
222 | } |
223 | } | |
224 | ||
bfd6d021 JH |
225 | /** |
226 | * omap_dm_timer_get_errata - get errata flags for a timer | |
227 | * | |
228 | * Get the timer errata flags that are specific to the OMAP device being used. | |
229 | */ | |
230 | u32 __init omap_dm_timer_get_errata(void) | |
231 | { | |
232 | if (cpu_is_omap24xx()) | |
233 | return 0; | |
234 | ||
235 | return OMAP_TIMER_ERRATA_I103_I767; | |
236 | } | |
237 | ||
aa561889 TL |
238 | static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, |
239 | int gptimer_id, | |
9725f445 | 240 | const char *fck_source, |
bfd6d021 JH |
241 | const char *property, |
242 | int posted) | |
5a3a388f | 243 | { |
aa561889 | 244 | char name[10]; /* 10 = sizeof("gptXX_Xck0") */ |
9725f445 JH |
245 | const char *oh_name; |
246 | struct device_node *np; | |
aa561889 | 247 | struct omap_hwmod *oh; |
61b001c5 | 248 | struct resource irq, mem; |
aa561889 | 249 | int res = 0; |
6c0c27fd | 250 | int r; |
aa561889 | 251 | |
9725f445 JH |
252 | if (of_have_populated_dt()) { |
253 | np = omap_get_timer_dt(omap_timer_match, NULL); | |
254 | if (!np) | |
255 | return -ENODEV; | |
256 | ||
257 | of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); | |
258 | if (!oh_name) | |
259 | return -ENODEV; | |
260 | ||
261 | timer->irq = irq_of_parse_and_map(np, 0); | |
262 | if (!timer->irq) | |
263 | return -ENXIO; | |
264 | ||
265 | timer->io_base = of_iomap(np, 0); | |
266 | ||
267 | of_node_put(np); | |
268 | } else { | |
269 | if (omap_dm_timer_reserve_systimer(gptimer_id)) | |
270 | return -ENODEV; | |
271 | ||
272 | sprintf(name, "timer%d", gptimer_id); | |
273 | oh_name = name; | |
274 | } | |
275 | ||
9725f445 | 276 | oh = omap_hwmod_lookup(oh_name); |
aa561889 TL |
277 | if (!oh) |
278 | return -ENODEV; | |
279 | ||
9725f445 JH |
280 | if (!of_have_populated_dt()) { |
281 | r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, | |
61b001c5 | 282 | &irq); |
9725f445 JH |
283 | if (r) |
284 | return -ENXIO; | |
61b001c5 | 285 | timer->irq = irq.start; |
9725f445 JH |
286 | |
287 | r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, | |
61b001c5 | 288 | &mem); |
9725f445 JH |
289 | if (r) |
290 | return -ENXIO; | |
9725f445 JH |
291 | |
292 | /* Static mapping, never released */ | |
61b001c5 | 293 | timer->io_base = ioremap(mem.start, mem.end - mem.start); |
9725f445 | 294 | } |
aa561889 | 295 | |
aa561889 TL |
296 | if (!timer->io_base) |
297 | return -ENXIO; | |
298 | ||
299 | /* After the dmtimer is using hwmod these clocks won't be needed */ | |
ae6df418 | 300 | timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); |
aa561889 TL |
301 | if (IS_ERR(timer->fclk)) |
302 | return -ENODEV; | |
303 | ||
9725f445 | 304 | /* FIXME: Need to remove hard-coded test on timer ID */ |
aa561889 TL |
305 | if (gptimer_id != 12) { |
306 | struct clk *src; | |
307 | ||
308 | src = clk_get(NULL, fck_source); | |
309 | if (IS_ERR(src)) { | |
310 | res = -EINVAL; | |
311 | } else { | |
b1538832 | 312 | res = clk_set_parent(timer->fclk, src); |
aa561889 | 313 | if (IS_ERR_VALUE(res)) |
9725f445 JH |
314 | pr_warn("%s: %s cannot set source\n", |
315 | __func__, oh->name); | |
aa561889 TL |
316 | clk_put(src); |
317 | } | |
318 | } | |
b1538832 JH |
319 | |
320 | omap_hwmod_setup_one(oh_name); | |
321 | omap_hwmod_enable(oh); | |
ee17f114 | 322 | __omap_dm_timer_init_regs(timer); |
aa561889 | 323 | |
bfd6d021 JH |
324 | if (posted) |
325 | __omap_dm_timer_enable_posted(timer); | |
326 | ||
327 | /* Check that the intended posted configuration matches the actual */ | |
328 | if (posted != timer->posted) | |
329 | return -EINVAL; | |
1dbae815 | 330 | |
bfd6d021 | 331 | timer->rate = clk_get_rate(timer->fclk); |
aa561889 | 332 | timer->reserved = 1; |
38698bef | 333 | |
aa561889 TL |
334 | return res; |
335 | } | |
f248076c | 336 | |
aa561889 | 337 | static void __init omap2_gp_clockevent_init(int gptimer_id, |
9725f445 JH |
338 | const char *fck_source, |
339 | const char *property) | |
aa561889 TL |
340 | { |
341 | int res; | |
f248076c | 342 | |
bfd6d021 JH |
343 | clkev.errata = omap_dm_timer_get_errata(); |
344 | ||
345 | /* | |
346 | * For clock-event timers we never read the timer counter and | |
347 | * so we are not impacted by errata i103 and i767. Therefore, | |
348 | * we can safely ignore this errata for clock-event timers. | |
349 | */ | |
350 | __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); | |
351 | ||
352 | res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property, | |
353 | OMAP_TIMER_POSTED); | |
aa561889 | 354 | BUG_ON(res); |
f248076c | 355 | |
a032d33b | 356 | omap2_gp_timer_irq.dev_id = &clkev; |
aa561889 | 357 | setup_irq(clkev.irq, &omap2_gp_timer_irq); |
5a3a388f | 358 | |
ee17f114 | 359 | __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); |
aa561889 TL |
360 | |
361 | clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC, | |
5a3a388f KH |
362 | clockevent_gpt.shift); |
363 | clockevent_gpt.max_delta_ns = | |
364 | clockevent_delta2ns(0xffffffff, &clockevent_gpt); | |
365 | clockevent_gpt.min_delta_ns = | |
df88acbb AK |
366 | clockevent_delta2ns(3, &clockevent_gpt); |
367 | /* Timer internal resynch latency. */ | |
5a3a388f | 368 | |
11d6ec2e SS |
369 | clockevent_gpt.cpumask = cpu_possible_mask; |
370 | clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); | |
5a3a388f | 371 | clockevents_register_device(&clockevent_gpt); |
aa561889 TL |
372 | |
373 | pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n", | |
374 | gptimer_id, clkev.rate); | |
5a3a388f KH |
375 | } |
376 | ||
f248076c | 377 | /* Clocksource code */ |
3d05a3e8 | 378 | static struct omap_dm_timer clksrc; |
1fe97c8f | 379 | static bool use_gptimer_clksrc; |
3d05a3e8 | 380 | |
5a3a388f KH |
381 | /* |
382 | * clocksource | |
383 | */ | |
8e19608e | 384 | static cycle_t clocksource_read_cycles(struct clocksource *cs) |
5a3a388f | 385 | { |
971d0254 | 386 | return (cycle_t)__omap_dm_timer_read_counter(&clksrc, |
bfd6d021 | 387 | OMAP_TIMER_NONPOSTED); |
5a3a388f KH |
388 | } |
389 | ||
390 | static struct clocksource clocksource_gpt = { | |
f36921be | 391 | .name = "gp_timer", |
5a3a388f KH |
392 | .rating = 300, |
393 | .read = clocksource_read_cycles, | |
394 | .mask = CLOCKSOURCE_MASK(32), | |
5a3a388f KH |
395 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
396 | }; | |
397 | ||
2f0778af | 398 | static u32 notrace dmtimer_read_sched_clock(void) |
cbc94380 | 399 | { |
3d05a3e8 | 400 | if (clksrc.reserved) |
971d0254 | 401 | return __omap_dm_timer_read_counter(&clksrc, |
bfd6d021 | 402 | OMAP_TIMER_NONPOSTED); |
5a3a388f | 403 | |
2f0778af | 404 | return 0; |
3d05a3e8 TL |
405 | } |
406 | ||
45caae74 | 407 | #ifdef CONFIG_OMAP_32K_TIMER |
3d05a3e8 | 408 | /* Setup free-running counter for clocksource */ |
1fe97c8f VH |
409 | static int __init omap2_sync32k_clocksource_init(void) |
410 | { | |
411 | int ret; | |
9883f7c8 | 412 | struct device_node *np = NULL; |
1fe97c8f VH |
413 | struct omap_hwmod *oh; |
414 | void __iomem *vbase; | |
415 | const char *oh_name = "counter_32k"; | |
416 | ||
9883f7c8 JH |
417 | /* |
418 | * If device-tree is present, then search the DT blob | |
419 | * to see if the 32kHz counter is supported. | |
420 | */ | |
421 | if (of_have_populated_dt()) { | |
422 | np = omap_get_timer_dt(omap_counter_match, NULL); | |
423 | if (!np) | |
424 | return -ENODEV; | |
425 | ||
426 | of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); | |
427 | if (!oh_name) | |
428 | return -ENODEV; | |
429 | } | |
430 | ||
1fe97c8f VH |
431 | /* |
432 | * First check hwmod data is available for sync32k counter | |
433 | */ | |
434 | oh = omap_hwmod_lookup(oh_name); | |
435 | if (!oh || oh->slaves_cnt == 0) | |
436 | return -ENODEV; | |
437 | ||
438 | omap_hwmod_setup_one(oh_name); | |
439 | ||
9883f7c8 JH |
440 | if (np) { |
441 | vbase = of_iomap(np, 0); | |
442 | of_node_put(np); | |
443 | } else { | |
444 | vbase = omap_hwmod_get_mpu_rt_va(oh); | |
445 | } | |
446 | ||
1fe97c8f VH |
447 | if (!vbase) { |
448 | pr_warn("%s: failed to get counter_32k resource\n", __func__); | |
449 | return -ENXIO; | |
450 | } | |
451 | ||
452 | ret = omap_hwmod_enable(oh); | |
453 | if (ret) { | |
454 | pr_warn("%s: failed to enable counter_32k module (%d)\n", | |
455 | __func__, ret); | |
456 | return ret; | |
457 | } | |
458 | ||
459 | ret = omap_init_clocksource_32k(vbase); | |
460 | if (ret) { | |
461 | pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", | |
462 | __func__, ret); | |
463 | omap_hwmod_idle(oh); | |
464 | } | |
465 | ||
466 | return ret; | |
467 | } | |
45caae74 IG |
468 | #else |
469 | static inline int omap2_sync32k_clocksource_init(void) | |
470 | { | |
471 | return -ENODEV; | |
472 | } | |
473 | #endif | |
1fe97c8f VH |
474 | |
475 | static void __init omap2_gptimer_clocksource_init(int gptimer_id, | |
3d05a3e8 TL |
476 | const char *fck_source) |
477 | { | |
478 | int res; | |
479 | ||
bfd6d021 JH |
480 | clksrc.errata = omap_dm_timer_get_errata(); |
481 | ||
482 | res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL, | |
483 | OMAP_TIMER_NONPOSTED); | |
3d05a3e8 | 484 | BUG_ON(res); |
5a3a388f | 485 | |
ee17f114 | 486 | __omap_dm_timer_load_start(&clksrc, |
971d0254 | 487 | OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, |
bfd6d021 | 488 | OMAP_TIMER_NONPOSTED); |
2f0778af | 489 | setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); |
cbc94380 | 490 | |
3d05a3e8 TL |
491 | if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) |
492 | pr_err("Could not register clocksource %s\n", | |
493 | clocksource_gpt.name); | |
1fe97c8f VH |
494 | else |
495 | pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n", | |
496 | gptimer_id, clksrc.rate); | |
497 | } | |
498 | ||
499 | static void __init omap2_clocksource_init(int gptimer_id, | |
500 | const char *fck_source) | |
501 | { | |
502 | /* | |
503 | * First give preference to kernel parameter configuration | |
504 | * by user (clocksource="gp_timer"). | |
505 | * | |
506 | * In case of missing kernel parameter for clocksource, | |
507 | * first check for availability for 32k-sync timer, in case | |
508 | * of failure in finding 32k_counter module or registering | |
509 | * it as clocksource, execution will fallback to gp-timer. | |
510 | */ | |
511 | if (use_gptimer_clksrc == true) | |
512 | omap2_gptimer_clocksource_init(gptimer_id, fck_source); | |
513 | else if (omap2_sync32k_clocksource_init()) | |
514 | /* Fall back to gp-timer code */ | |
515 | omap2_gptimer_clocksource_init(gptimer_id, fck_source); | |
5a3a388f | 516 | } |
5a3a388f | 517 | |
fa6d79d2 SS |
518 | #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER |
519 | /* | |
520 | * The realtime counter also called master counter, is a free-running | |
521 | * counter, which is related to real time. It produces the count used | |
522 | * by the CPU local timer peripherals in the MPU cluster. The timer counts | |
523 | * at a rate of 6.144 MHz. Because the device operates on different clocks | |
524 | * in different power modes, the master counter shifts operation between | |
525 | * clocks, adjusting the increment per clock in hardware accordingly to | |
526 | * maintain a constant count rate. | |
527 | */ | |
528 | static void __init realtime_counter_init(void) | |
529 | { | |
530 | void __iomem *base; | |
531 | static struct clk *sys_clk; | |
532 | unsigned long rate; | |
533 | unsigned int reg, num, den; | |
534 | ||
535 | base = ioremap(REALTIME_COUNTER_BASE, SZ_32); | |
536 | if (!base) { | |
537 | pr_err("%s: ioremap failed\n", __func__); | |
538 | return; | |
539 | } | |
540 | sys_clk = clk_get(NULL, "sys_clkin_ck"); | |
533b2981 | 541 | if (IS_ERR(sys_clk)) { |
fa6d79d2 SS |
542 | pr_err("%s: failed to get system clock handle\n", __func__); |
543 | iounmap(base); | |
544 | return; | |
545 | } | |
546 | ||
547 | rate = clk_get_rate(sys_clk); | |
548 | /* Numerator/denumerator values refer TRM Realtime Counter section */ | |
549 | switch (rate) { | |
550 | case 1200000: | |
551 | num = 64; | |
552 | den = 125; | |
553 | break; | |
554 | case 1300000: | |
555 | num = 768; | |
556 | den = 1625; | |
557 | break; | |
558 | case 19200000: | |
559 | num = 8; | |
560 | den = 25; | |
561 | break; | |
562 | case 2600000: | |
563 | num = 384; | |
564 | den = 1625; | |
565 | break; | |
566 | case 2700000: | |
567 | num = 256; | |
568 | den = 1125; | |
569 | break; | |
570 | case 38400000: | |
571 | default: | |
572 | /* Program it for 38.4 MHz */ | |
573 | num = 4; | |
574 | den = 25; | |
575 | break; | |
576 | } | |
577 | ||
578 | /* Program numerator and denumerator registers */ | |
579 | reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & | |
580 | NUMERATOR_DENUMERATOR_MASK; | |
581 | reg |= num; | |
582 | __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); | |
583 | ||
584 | reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & | |
585 | NUMERATOR_DENUMERATOR_MASK; | |
586 | reg |= den; | |
587 | __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); | |
588 | ||
589 | iounmap(base); | |
590 | } | |
591 | #else | |
592 | static inline void __init realtime_counter_init(void) | |
593 | {} | |
594 | #endif | |
595 | ||
9725f445 | 596 | #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ |
3d05a3e8 | 597 | clksrc_nr, clksrc_src) \ |
e74984e4 TL |
598 | static void __init omap##name##_timer_init(void) \ |
599 | { \ | |
ad24bde8 | 600 | omap_dmtimer_init(); \ |
9725f445 | 601 | omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ |
1fe97c8f | 602 | omap2_clocksource_init((clksrc_nr), clksrc_src); \ |
e74984e4 TL |
603 | } |
604 | ||
605 | #define OMAP_SYS_TIMER(name) \ | |
606 | struct sys_timer omap##name##_timer = { \ | |
607 | .init = omap##name##_timer_init, \ | |
608 | }; | |
609 | ||
610 | #ifdef CONFIG_ARCH_OMAP2 | |
9725f445 JH |
611 | OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, "ti,timer-alwon", |
612 | 2, OMAP2_MPU_SOURCE) | |
e74984e4 TL |
613 | OMAP_SYS_TIMER(2) |
614 | #endif | |
615 | ||
616 | #ifdef CONFIG_ARCH_OMAP3 | |
9725f445 JH |
617 | OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, "ti,timer-alwon", |
618 | 2, OMAP3_MPU_SOURCE) | |
e74984e4 | 619 | OMAP_SYS_TIMER(3) |
3d05a3e8 | 620 | OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE, |
9725f445 | 621 | TIMER_PROP_SECURE, 2, OMAP3_MPU_SOURCE) |
e74984e4 TL |
622 | OMAP_SYS_TIMER(3_secure) |
623 | #endif | |
624 | ||
08f30989 | 625 | #ifdef CONFIG_SOC_AM33XX |
9725f445 JH |
626 | OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon", |
627 | 2, OMAP4_MPU_SOURCE) | |
08f30989 AM |
628 | OMAP_SYS_TIMER(3_am33xx) |
629 | #endif | |
630 | ||
e74984e4 | 631 | #ifdef CONFIG_ARCH_OMAP4 |
39e1d4c1 | 632 | #ifdef CONFIG_LOCAL_TIMERS |
a45c983f | 633 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, |
3f216ef3 | 634 | OMAP44XX_LOCAL_TWD_BASE, 29); |
39e1d4c1 | 635 | #endif |
a45c983f MZ |
636 | |
637 | static void __init omap4_timer_init(void) | |
638 | { | |
9725f445 | 639 | omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE, "ti,timer-alwon"); |
1fe97c8f | 640 | omap2_clocksource_init(2, OMAP4_MPU_SOURCE); |
a45c983f MZ |
641 | #ifdef CONFIG_LOCAL_TIMERS |
642 | /* Local timers are not supprted on OMAP4430 ES1.0 */ | |
643 | if (omap_rev() != OMAP4430_REV_ES1_0) { | |
644 | int err; | |
645 | ||
eed0de27 SS |
646 | if (of_have_populated_dt()) { |
647 | twd_local_timer_of_register(); | |
648 | return; | |
649 | } | |
650 | ||
a45c983f MZ |
651 | err = twd_local_timer_register(&twd_local_timer); |
652 | if (err) | |
653 | pr_err("twd_local_timer_register failed %d\n", err); | |
654 | } | |
655 | #endif | |
1dbae815 | 656 | } |
e74984e4 TL |
657 | OMAP_SYS_TIMER(4) |
658 | #endif | |
c345c8b0 | 659 | |
37b3280d | 660 | #ifdef CONFIG_SOC_OMAP5 |
fa6d79d2 SS |
661 | static void __init omap5_timer_init(void) |
662 | { | |
3c7c5dab SS |
663 | int err; |
664 | ||
9725f445 | 665 | omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE, "ti,timer-alwon"); |
fa6d79d2 SS |
666 | omap2_clocksource_init(2, OMAP4_MPU_SOURCE); |
667 | realtime_counter_init(); | |
3c7c5dab SS |
668 | |
669 | err = arch_timer_of_register(); | |
670 | if (err) | |
671 | pr_err("%s: arch_timer_register failed %d\n", __func__, err); | |
fa6d79d2 | 672 | } |
37b3280d S |
673 | OMAP_SYS_TIMER(5) |
674 | #endif | |
675 | ||
c345c8b0 TKD |
676 | /** |
677 | * omap_timer_init - build and register timer device with an | |
678 | * associated timer hwmod | |
679 | * @oh: timer hwmod pointer to be used to build timer device | |
680 | * @user: parameter that can be passed from calling hwmod API | |
681 | * | |
682 | * Called by omap_hwmod_for_each_by_class to register each of the timer | |
683 | * devices present in the system. The number of timer devices is known | |
684 | * by parsing through the hwmod database for a given class name. At the | |
685 | * end of function call memory is allocated for timer device and it is | |
686 | * registered to the framework ready to be proved by the driver. | |
687 | */ | |
688 | static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) | |
689 | { | |
690 | int id; | |
691 | int ret = 0; | |
692 | char *name = "omap_timer"; | |
693 | struct dmtimer_platform_data *pdata; | |
c541c15f | 694 | struct platform_device *pdev; |
c345c8b0 TKD |
695 | struct omap_timer_capability_dev_attr *timer_dev_attr; |
696 | ||
697 | pr_debug("%s: %s\n", __func__, oh->name); | |
698 | ||
699 | /* on secure device, do not register secure timer */ | |
700 | timer_dev_attr = oh->dev_attr; | |
701 | if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) | |
702 | if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) | |
703 | return ret; | |
704 | ||
705 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); | |
706 | if (!pdata) { | |
707 | pr_err("%s: No memory for [%s]\n", __func__, oh->name); | |
708 | return -ENOMEM; | |
709 | } | |
710 | ||
711 | /* | |
712 | * Extract the IDs from name field in hwmod database | |
713 | * and use the same for constructing ids' for the | |
714 | * timer devices. In a way, we are avoiding usage of | |
715 | * static variable witin the function to do the same. | |
716 | * CAUTION: We have to be careful and make sure the | |
717 | * name in hwmod database does not change in which case | |
718 | * we might either make corresponding change here or | |
719 | * switch back static variable mechanism. | |
720 | */ | |
721 | sscanf(oh->name, "timer%2d", &id); | |
722 | ||
d1c1691b JH |
723 | if (timer_dev_attr) |
724 | pdata->timer_capability = timer_dev_attr->timer_capability; | |
0dad9fae | 725 | |
bfd6d021 | 726 | pdata->timer_errata = omap_dm_timer_get_errata(); |
6e740f9a TL |
727 | pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; |
728 | ||
c541c15f | 729 | pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata), |
c16ae1e6 | 730 | NULL, 0, 0); |
c345c8b0 | 731 | |
c541c15f | 732 | if (IS_ERR(pdev)) { |
c345c8b0 TKD |
733 | pr_err("%s: Can't build omap_device for %s: %s.\n", |
734 | __func__, name, oh->name); | |
735 | ret = -EINVAL; | |
736 | } | |
737 | ||
738 | kfree(pdata); | |
739 | ||
740 | return ret; | |
741 | } | |
3392cdd3 TKD |
742 | |
743 | /** | |
744 | * omap2_dm_timer_init - top level regular device initialization | |
745 | * | |
746 | * Uses dedicated hwmod api to parse through hwmod database for | |
747 | * given class name and then build and register the timer device. | |
748 | */ | |
749 | static int __init omap2_dm_timer_init(void) | |
750 | { | |
751 | int ret; | |
752 | ||
9725f445 JH |
753 | /* If dtb is there, the devices will be created dynamically */ |
754 | if (of_have_populated_dt()) | |
755 | return -ENODEV; | |
756 | ||
3392cdd3 TKD |
757 | ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); |
758 | if (unlikely(ret)) { | |
759 | pr_err("%s: device registration failed.\n", __func__); | |
760 | return -EINVAL; | |
761 | } | |
762 | ||
763 | return 0; | |
764 | } | |
765 | arch_initcall(omap2_dm_timer_init); | |
1fe97c8f VH |
766 | |
767 | /** | |
768 | * omap2_override_clocksource - clocksource override with user configuration | |
769 | * | |
770 | * Allows user to override default clocksource, using kernel parameter | |
771 | * clocksource="gp_timer" (For all OMAP2PLUS architectures) | |
772 | * | |
773 | * Note that, here we are using same standard kernel parameter "clocksource=", | |
774 | * and not introducing any OMAP specific interface. | |
775 | */ | |
776 | static int __init omap2_override_clocksource(char *str) | |
777 | { | |
778 | if (!str) | |
779 | return 0; | |
780 | /* | |
781 | * For OMAP architecture, we only have two options | |
782 | * - sync_32k (default) | |
783 | * - gp_timer (sys_clk based) | |
784 | */ | |
785 | if (!strcmp(str, "gp_timer")) | |
786 | use_gptimer_clksrc = true; | |
787 | ||
788 | return 0; | |
789 | } | |
790 | early_param("clocksource", omap2_override_clocksource); |