Commit | Line | Data |
---|---|---|
1dbae815 | 1 | /* |
0f622e8c | 2 | * linux/arch/arm/mach-omap2/timer.c |
1dbae815 TL |
3 | * |
4 | * OMAP2 GP timer support. | |
5 | * | |
f248076c PW |
6 | * Copyright (C) 2009 Nokia Corporation |
7 | * | |
5a3a388f KH |
8 | * Update to use new clocksource/clockevent layers |
9 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | |
10 | * Copyright (C) 2007 MontaVista Software, Inc. | |
11 | * | |
12 | * Original driver: | |
1dbae815 TL |
13 | * Copyright (C) 2005 Nokia Corporation |
14 | * Author: Paul Mundt <paul.mundt@nokia.com> | |
96de0e25 | 15 | * Juha Yrjölä <juha.yrjola@nokia.com> |
77900a2f | 16 | * OMAP Dual-mode timer framework support by Timo Teras |
1dbae815 TL |
17 | * |
18 | * Some parts based off of TI's 24xx code: | |
19 | * | |
44169075 | 20 | * Copyright (C) 2004-2009 Texas Instruments, Inc. |
1dbae815 TL |
21 | * |
22 | * Roughly modelled after the OMAP1 MPU timer code. | |
44169075 | 23 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
1dbae815 TL |
24 | * |
25 | * This file is subject to the terms and conditions of the GNU General Public | |
26 | * License. See the file "COPYING" in the main directory of this archive | |
27 | * for more details. | |
28 | */ | |
29 | #include <linux/init.h> | |
30 | #include <linux/time.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/err.h> | |
f8ce2547 | 33 | #include <linux/clk.h> |
77900a2f | 34 | #include <linux/delay.h> |
e6687290 | 35 | #include <linux/irq.h> |
5a3a388f KH |
36 | #include <linux/clocksource.h> |
37 | #include <linux/clockchips.h> | |
c345c8b0 | 38 | #include <linux/slab.h> |
eed0de27 | 39 | #include <linux/of.h> |
f8ce2547 | 40 | |
1dbae815 | 41 | #include <asm/mach/time.h> |
a45c983f | 42 | #include <asm/smp_twd.h> |
cbc94380 | 43 | #include <asm/sched_clock.h> |
7d7e1eba | 44 | |
3c7c5dab | 45 | #include <asm/arch_timer.h> |
38698bef | 46 | #include <plat/omap_hwmod.h> |
c345c8b0 | 47 | #include <plat/omap_device.h> |
7d7e1eba | 48 | #include <plat/dmtimer.h> |
b481113a TKD |
49 | #include <plat/omap-pm.h> |
50 | ||
dbc04161 | 51 | #include "soc.h" |
7d7e1eba | 52 | #include "common.h" |
b481113a | 53 | #include "powerdomain.h" |
1dbae815 | 54 | |
aa561889 TL |
55 | /* Parent clocks, eventually these will come from the clock framework */ |
56 | ||
57 | #define OMAP2_MPU_SOURCE "sys_ck" | |
58 | #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE | |
59 | #define OMAP4_MPU_SOURCE "sys_clkin_ck" | |
60 | #define OMAP2_32K_SOURCE "func_32k_ck" | |
61 | #define OMAP3_32K_SOURCE "omap_32k_fck" | |
62 | #define OMAP4_32K_SOURCE "sys_32k_ck" | |
63 | ||
64 | #ifdef CONFIG_OMAP_32K_TIMER | |
65 | #define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE | |
66 | #define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE | |
67 | #define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE | |
68 | #define OMAP3_SECURE_TIMER 12 | |
69 | #else | |
70 | #define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE | |
71 | #define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE | |
72 | #define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE | |
73 | #define OMAP3_SECURE_TIMER 1 | |
74 | #endif | |
d8328f3b | 75 | |
fa6d79d2 SS |
76 | #define REALTIME_COUNTER_BASE 0x48243200 |
77 | #define INCREMENTER_NUMERATOR_OFFSET 0x10 | |
78 | #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 | |
79 | #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 | |
80 | ||
aa561889 TL |
81 | /* Clockevent code */ |
82 | ||
83 | static struct omap_dm_timer clkev; | |
5a3a388f | 84 | static struct clock_event_device clockevent_gpt; |
1dbae815 | 85 | |
0cd61b68 | 86 | static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) |
1dbae815 | 87 | { |
5a3a388f KH |
88 | struct clock_event_device *evt = &clockevent_gpt; |
89 | ||
ee17f114 | 90 | __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); |
1dbae815 | 91 | |
5a3a388f | 92 | evt->event_handler(evt); |
1dbae815 TL |
93 | return IRQ_HANDLED; |
94 | } | |
95 | ||
96 | static struct irqaction omap2_gp_timer_irq = { | |
f36921be | 97 | .name = "gp_timer", |
b30fabad | 98 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
1dbae815 TL |
99 | .handler = omap2_gp_timer_interrupt, |
100 | }; | |
101 | ||
5a3a388f KH |
102 | static int omap2_gp_timer_set_next_event(unsigned long cycles, |
103 | struct clock_event_device *evt) | |
1dbae815 | 104 | { |
ee17f114 | 105 | __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, |
aa561889 | 106 | 0xffffffff - cycles, 1); |
5a3a388f KH |
107 | |
108 | return 0; | |
109 | } | |
110 | ||
111 | static void omap2_gp_timer_set_mode(enum clock_event_mode mode, | |
112 | struct clock_event_device *evt) | |
113 | { | |
114 | u32 period; | |
115 | ||
ee17f114 | 116 | __omap_dm_timer_stop(&clkev, 1, clkev.rate); |
5a3a388f KH |
117 | |
118 | switch (mode) { | |
119 | case CLOCK_EVT_MODE_PERIODIC: | |
aa561889 | 120 | period = clkev.rate / HZ; |
5a3a388f | 121 | period -= 1; |
aa561889 | 122 | /* Looks like we need to first set the load value separately */ |
ee17f114 | 123 | __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, |
aa561889 | 124 | 0xffffffff - period, 1); |
ee17f114 | 125 | __omap_dm_timer_load_start(&clkev, |
aa561889 TL |
126 | OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, |
127 | 0xffffffff - period, 1); | |
5a3a388f KH |
128 | break; |
129 | case CLOCK_EVT_MODE_ONESHOT: | |
130 | break; | |
131 | case CLOCK_EVT_MODE_UNUSED: | |
132 | case CLOCK_EVT_MODE_SHUTDOWN: | |
133 | case CLOCK_EVT_MODE_RESUME: | |
134 | break; | |
135 | } | |
136 | } | |
137 | ||
138 | static struct clock_event_device clockevent_gpt = { | |
f36921be | 139 | .name = "gp_timer", |
5a3a388f KH |
140 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
141 | .shift = 32, | |
11d6ec2e | 142 | .rating = 300, |
5a3a388f KH |
143 | .set_next_event = omap2_gp_timer_set_next_event, |
144 | .set_mode = omap2_gp_timer_set_mode, | |
145 | }; | |
146 | ||
ad24bde8 JH |
147 | static struct property device_disabled = { |
148 | .name = "status", | |
149 | .length = sizeof("disabled"), | |
150 | .value = "disabled", | |
151 | }; | |
152 | ||
153 | static struct of_device_id omap_timer_match[] __initdata = { | |
154 | { .compatible = "ti,omap2-timer", }, | |
155 | { } | |
156 | }; | |
157 | ||
158 | /** | |
159 | * omap_dmtimer_init - initialisation function when device tree is used | |
160 | * | |
161 | * For secure OMAP3 devices, timers with device type "timer-secure" cannot | |
162 | * be used by the kernel as they are reserved. Therefore, to prevent the | |
163 | * kernel registering these devices remove them dynamically from the device | |
164 | * tree on boot. | |
165 | */ | |
166 | void __init omap_dmtimer_init(void) | |
167 | { | |
168 | struct device_node *np; | |
169 | ||
170 | if (!cpu_is_omap34xx()) | |
171 | return; | |
172 | ||
173 | /* If we are a secure device, remove any secure timer nodes */ | |
174 | if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { | |
175 | for_each_matching_node(np, omap_timer_match) { | |
176 | if (of_get_property(np, "ti,timer-secure", NULL)) | |
177 | prom_add_property(np, &device_disabled); | |
178 | } | |
179 | } | |
180 | } | |
181 | ||
aa561889 TL |
182 | static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, |
183 | int gptimer_id, | |
184 | const char *fck_source) | |
5a3a388f | 185 | { |
aa561889 TL |
186 | char name[10]; /* 10 = sizeof("gptXX_Xck0") */ |
187 | struct omap_hwmod *oh; | |
6c0c27fd | 188 | struct resource irq_rsrc, mem_rsrc; |
aa561889 TL |
189 | size_t size; |
190 | int res = 0; | |
6c0c27fd | 191 | int r; |
aa561889 TL |
192 | |
193 | sprintf(name, "timer%d", gptimer_id); | |
194 | omap_hwmod_setup_one(name); | |
195 | oh = omap_hwmod_lookup(name); | |
196 | if (!oh) | |
197 | return -ENODEV; | |
198 | ||
6c0c27fd PW |
199 | r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc); |
200 | if (r) | |
201 | return -ENXIO; | |
202 | timer->irq = irq_rsrc.start; | |
203 | ||
204 | r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc); | |
205 | if (r) | |
206 | return -ENXIO; | |
207 | timer->phys_base = mem_rsrc.start; | |
208 | size = mem_rsrc.end - mem_rsrc.start; | |
aa561889 TL |
209 | |
210 | /* Static mapping, never released */ | |
211 | timer->io_base = ioremap(timer->phys_base, size); | |
212 | if (!timer->io_base) | |
213 | return -ENXIO; | |
214 | ||
215 | /* After the dmtimer is using hwmod these clocks won't be needed */ | |
ae6df418 | 216 | timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); |
aa561889 TL |
217 | if (IS_ERR(timer->fclk)) |
218 | return -ENODEV; | |
219 | ||
aa561889 TL |
220 | omap_hwmod_enable(oh); |
221 | ||
b7b4ff76 JH |
222 | if (omap_dm_timer_reserve_systimer(gptimer_id)) |
223 | return -ENODEV; | |
11a0186f | 224 | |
aa561889 TL |
225 | if (gptimer_id != 12) { |
226 | struct clk *src; | |
227 | ||
228 | src = clk_get(NULL, fck_source); | |
229 | if (IS_ERR(src)) { | |
230 | res = -EINVAL; | |
231 | } else { | |
232 | res = __omap_dm_timer_set_source(timer->fclk, src); | |
233 | if (IS_ERR_VALUE(res)) | |
234 | pr_warning("%s: timer%i cannot set source\n", | |
235 | __func__, gptimer_id); | |
236 | clk_put(src); | |
237 | } | |
238 | } | |
ee17f114 TL |
239 | __omap_dm_timer_init_regs(timer); |
240 | __omap_dm_timer_reset(timer, 1, 1); | |
aa561889 TL |
241 | timer->posted = 1; |
242 | ||
243 | timer->rate = clk_get_rate(timer->fclk); | |
1dbae815 | 244 | |
aa561889 | 245 | timer->reserved = 1; |
38698bef | 246 | |
aa561889 TL |
247 | return res; |
248 | } | |
f248076c | 249 | |
aa561889 TL |
250 | static void __init omap2_gp_clockevent_init(int gptimer_id, |
251 | const char *fck_source) | |
252 | { | |
253 | int res; | |
f248076c | 254 | |
aa561889 TL |
255 | res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source); |
256 | BUG_ON(res); | |
f248076c | 257 | |
a032d33b | 258 | omap2_gp_timer_irq.dev_id = &clkev; |
aa561889 | 259 | setup_irq(clkev.irq, &omap2_gp_timer_irq); |
5a3a388f | 260 | |
ee17f114 | 261 | __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); |
aa561889 TL |
262 | |
263 | clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC, | |
5a3a388f KH |
264 | clockevent_gpt.shift); |
265 | clockevent_gpt.max_delta_ns = | |
266 | clockevent_delta2ns(0xffffffff, &clockevent_gpt); | |
267 | clockevent_gpt.min_delta_ns = | |
df88acbb AK |
268 | clockevent_delta2ns(3, &clockevent_gpt); |
269 | /* Timer internal resynch latency. */ | |
5a3a388f | 270 | |
11d6ec2e SS |
271 | clockevent_gpt.cpumask = cpu_possible_mask; |
272 | clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); | |
5a3a388f | 273 | clockevents_register_device(&clockevent_gpt); |
aa561889 TL |
274 | |
275 | pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n", | |
276 | gptimer_id, clkev.rate); | |
5a3a388f KH |
277 | } |
278 | ||
f248076c | 279 | /* Clocksource code */ |
3d05a3e8 | 280 | static struct omap_dm_timer clksrc; |
1fe97c8f | 281 | static bool use_gptimer_clksrc; |
3d05a3e8 | 282 | |
5a3a388f KH |
283 | /* |
284 | * clocksource | |
285 | */ | |
8e19608e | 286 | static cycle_t clocksource_read_cycles(struct clocksource *cs) |
5a3a388f | 287 | { |
ee17f114 | 288 | return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1); |
5a3a388f KH |
289 | } |
290 | ||
291 | static struct clocksource clocksource_gpt = { | |
f36921be | 292 | .name = "gp_timer", |
5a3a388f KH |
293 | .rating = 300, |
294 | .read = clocksource_read_cycles, | |
295 | .mask = CLOCKSOURCE_MASK(32), | |
5a3a388f KH |
296 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
297 | }; | |
298 | ||
2f0778af | 299 | static u32 notrace dmtimer_read_sched_clock(void) |
cbc94380 | 300 | { |
3d05a3e8 | 301 | if (clksrc.reserved) |
dbc3982a | 302 | return __omap_dm_timer_read_counter(&clksrc, 1); |
5a3a388f | 303 | |
2f0778af | 304 | return 0; |
3d05a3e8 TL |
305 | } |
306 | ||
45caae74 | 307 | #ifdef CONFIG_OMAP_32K_TIMER |
3d05a3e8 | 308 | /* Setup free-running counter for clocksource */ |
1fe97c8f VH |
309 | static int __init omap2_sync32k_clocksource_init(void) |
310 | { | |
311 | int ret; | |
312 | struct omap_hwmod *oh; | |
313 | void __iomem *vbase; | |
314 | const char *oh_name = "counter_32k"; | |
315 | ||
316 | /* | |
317 | * First check hwmod data is available for sync32k counter | |
318 | */ | |
319 | oh = omap_hwmod_lookup(oh_name); | |
320 | if (!oh || oh->slaves_cnt == 0) | |
321 | return -ENODEV; | |
322 | ||
323 | omap_hwmod_setup_one(oh_name); | |
324 | ||
325 | vbase = omap_hwmod_get_mpu_rt_va(oh); | |
326 | if (!vbase) { | |
327 | pr_warn("%s: failed to get counter_32k resource\n", __func__); | |
328 | return -ENXIO; | |
329 | } | |
330 | ||
331 | ret = omap_hwmod_enable(oh); | |
332 | if (ret) { | |
333 | pr_warn("%s: failed to enable counter_32k module (%d)\n", | |
334 | __func__, ret); | |
335 | return ret; | |
336 | } | |
337 | ||
338 | ret = omap_init_clocksource_32k(vbase); | |
339 | if (ret) { | |
340 | pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n", | |
341 | __func__, ret); | |
342 | omap_hwmod_idle(oh); | |
343 | } | |
344 | ||
345 | return ret; | |
346 | } | |
45caae74 IG |
347 | #else |
348 | static inline int omap2_sync32k_clocksource_init(void) | |
349 | { | |
350 | return -ENODEV; | |
351 | } | |
352 | #endif | |
1fe97c8f VH |
353 | |
354 | static void __init omap2_gptimer_clocksource_init(int gptimer_id, | |
3d05a3e8 TL |
355 | const char *fck_source) |
356 | { | |
357 | int res; | |
358 | ||
359 | res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source); | |
360 | BUG_ON(res); | |
5a3a388f | 361 | |
ee17f114 | 362 | __omap_dm_timer_load_start(&clksrc, |
e9d0b97e | 363 | OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1); |
2f0778af | 364 | setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); |
cbc94380 | 365 | |
3d05a3e8 TL |
366 | if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) |
367 | pr_err("Could not register clocksource %s\n", | |
368 | clocksource_gpt.name); | |
1fe97c8f VH |
369 | else |
370 | pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n", | |
371 | gptimer_id, clksrc.rate); | |
372 | } | |
373 | ||
374 | static void __init omap2_clocksource_init(int gptimer_id, | |
375 | const char *fck_source) | |
376 | { | |
377 | /* | |
378 | * First give preference to kernel parameter configuration | |
379 | * by user (clocksource="gp_timer"). | |
380 | * | |
381 | * In case of missing kernel parameter for clocksource, | |
382 | * first check for availability for 32k-sync timer, in case | |
383 | * of failure in finding 32k_counter module or registering | |
384 | * it as clocksource, execution will fallback to gp-timer. | |
385 | */ | |
386 | if (use_gptimer_clksrc == true) | |
387 | omap2_gptimer_clocksource_init(gptimer_id, fck_source); | |
388 | else if (omap2_sync32k_clocksource_init()) | |
389 | /* Fall back to gp-timer code */ | |
390 | omap2_gptimer_clocksource_init(gptimer_id, fck_source); | |
5a3a388f | 391 | } |
5a3a388f | 392 | |
fa6d79d2 SS |
393 | #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER |
394 | /* | |
395 | * The realtime counter also called master counter, is a free-running | |
396 | * counter, which is related to real time. It produces the count used | |
397 | * by the CPU local timer peripherals in the MPU cluster. The timer counts | |
398 | * at a rate of 6.144 MHz. Because the device operates on different clocks | |
399 | * in different power modes, the master counter shifts operation between | |
400 | * clocks, adjusting the increment per clock in hardware accordingly to | |
401 | * maintain a constant count rate. | |
402 | */ | |
403 | static void __init realtime_counter_init(void) | |
404 | { | |
405 | void __iomem *base; | |
406 | static struct clk *sys_clk; | |
407 | unsigned long rate; | |
408 | unsigned int reg, num, den; | |
409 | ||
410 | base = ioremap(REALTIME_COUNTER_BASE, SZ_32); | |
411 | if (!base) { | |
412 | pr_err("%s: ioremap failed\n", __func__); | |
413 | return; | |
414 | } | |
415 | sys_clk = clk_get(NULL, "sys_clkin_ck"); | |
533b2981 | 416 | if (IS_ERR(sys_clk)) { |
fa6d79d2 SS |
417 | pr_err("%s: failed to get system clock handle\n", __func__); |
418 | iounmap(base); | |
419 | return; | |
420 | } | |
421 | ||
422 | rate = clk_get_rate(sys_clk); | |
423 | /* Numerator/denumerator values refer TRM Realtime Counter section */ | |
424 | switch (rate) { | |
425 | case 1200000: | |
426 | num = 64; | |
427 | den = 125; | |
428 | break; | |
429 | case 1300000: | |
430 | num = 768; | |
431 | den = 1625; | |
432 | break; | |
433 | case 19200000: | |
434 | num = 8; | |
435 | den = 25; | |
436 | break; | |
437 | case 2600000: | |
438 | num = 384; | |
439 | den = 1625; | |
440 | break; | |
441 | case 2700000: | |
442 | num = 256; | |
443 | den = 1125; | |
444 | break; | |
445 | case 38400000: | |
446 | default: | |
447 | /* Program it for 38.4 MHz */ | |
448 | num = 4; | |
449 | den = 25; | |
450 | break; | |
451 | } | |
452 | ||
453 | /* Program numerator and denumerator registers */ | |
454 | reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & | |
455 | NUMERATOR_DENUMERATOR_MASK; | |
456 | reg |= num; | |
457 | __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); | |
458 | ||
459 | reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & | |
460 | NUMERATOR_DENUMERATOR_MASK; | |
461 | reg |= den; | |
462 | __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); | |
463 | ||
464 | iounmap(base); | |
465 | } | |
466 | #else | |
467 | static inline void __init realtime_counter_init(void) | |
468 | {} | |
469 | #endif | |
470 | ||
3d05a3e8 TL |
471 | #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \ |
472 | clksrc_nr, clksrc_src) \ | |
e74984e4 TL |
473 | static void __init omap##name##_timer_init(void) \ |
474 | { \ | |
ad24bde8 | 475 | omap_dmtimer_init(); \ |
aa561889 | 476 | omap2_gp_clockevent_init((clkev_nr), clkev_src); \ |
1fe97c8f | 477 | omap2_clocksource_init((clksrc_nr), clksrc_src); \ |
e74984e4 TL |
478 | } |
479 | ||
480 | #define OMAP_SYS_TIMER(name) \ | |
481 | struct sys_timer omap##name##_timer = { \ | |
482 | .init = omap##name##_timer_init, \ | |
483 | }; | |
484 | ||
485 | #ifdef CONFIG_ARCH_OMAP2 | |
3d05a3e8 | 486 | OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE) |
e74984e4 TL |
487 | OMAP_SYS_TIMER(2) |
488 | #endif | |
489 | ||
490 | #ifdef CONFIG_ARCH_OMAP3 | |
3d05a3e8 | 491 | OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE) |
e74984e4 | 492 | OMAP_SYS_TIMER(3) |
3d05a3e8 TL |
493 | OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE, |
494 | 2, OMAP3_MPU_SOURCE) | |
e74984e4 TL |
495 | OMAP_SYS_TIMER(3_secure) |
496 | #endif | |
497 | ||
08f30989 AM |
498 | #ifdef CONFIG_SOC_AM33XX |
499 | OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE) | |
500 | OMAP_SYS_TIMER(3_am33xx) | |
501 | #endif | |
502 | ||
e74984e4 | 503 | #ifdef CONFIG_ARCH_OMAP4 |
39e1d4c1 | 504 | #ifdef CONFIG_LOCAL_TIMERS |
a45c983f | 505 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, |
3f216ef3 | 506 | OMAP44XX_LOCAL_TWD_BASE, 29); |
39e1d4c1 | 507 | #endif |
a45c983f MZ |
508 | |
509 | static void __init omap4_timer_init(void) | |
510 | { | |
aa561889 | 511 | omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); |
1fe97c8f | 512 | omap2_clocksource_init(2, OMAP4_MPU_SOURCE); |
a45c983f MZ |
513 | #ifdef CONFIG_LOCAL_TIMERS |
514 | /* Local timers are not supprted on OMAP4430 ES1.0 */ | |
515 | if (omap_rev() != OMAP4430_REV_ES1_0) { | |
516 | int err; | |
517 | ||
eed0de27 SS |
518 | if (of_have_populated_dt()) { |
519 | twd_local_timer_of_register(); | |
520 | return; | |
521 | } | |
522 | ||
a45c983f MZ |
523 | err = twd_local_timer_register(&twd_local_timer); |
524 | if (err) | |
525 | pr_err("twd_local_timer_register failed %d\n", err); | |
526 | } | |
527 | #endif | |
1dbae815 | 528 | } |
e74984e4 TL |
529 | OMAP_SYS_TIMER(4) |
530 | #endif | |
c345c8b0 | 531 | |
37b3280d | 532 | #ifdef CONFIG_SOC_OMAP5 |
fa6d79d2 SS |
533 | static void __init omap5_timer_init(void) |
534 | { | |
3c7c5dab SS |
535 | int err; |
536 | ||
fa6d79d2 SS |
537 | omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); |
538 | omap2_clocksource_init(2, OMAP4_MPU_SOURCE); | |
539 | realtime_counter_init(); | |
3c7c5dab SS |
540 | |
541 | err = arch_timer_of_register(); | |
542 | if (err) | |
543 | pr_err("%s: arch_timer_register failed %d\n", __func__, err); | |
fa6d79d2 | 544 | } |
37b3280d S |
545 | OMAP_SYS_TIMER(5) |
546 | #endif | |
547 | ||
c345c8b0 TKD |
548 | /** |
549 | * omap_timer_init - build and register timer device with an | |
550 | * associated timer hwmod | |
551 | * @oh: timer hwmod pointer to be used to build timer device | |
552 | * @user: parameter that can be passed from calling hwmod API | |
553 | * | |
554 | * Called by omap_hwmod_for_each_by_class to register each of the timer | |
555 | * devices present in the system. The number of timer devices is known | |
556 | * by parsing through the hwmod database for a given class name. At the | |
557 | * end of function call memory is allocated for timer device and it is | |
558 | * registered to the framework ready to be proved by the driver. | |
559 | */ | |
560 | static int __init omap_timer_init(struct omap_hwmod *oh, void *unused) | |
561 | { | |
562 | int id; | |
563 | int ret = 0; | |
564 | char *name = "omap_timer"; | |
565 | struct dmtimer_platform_data *pdata; | |
c541c15f | 566 | struct platform_device *pdev; |
c345c8b0 TKD |
567 | struct omap_timer_capability_dev_attr *timer_dev_attr; |
568 | ||
569 | pr_debug("%s: %s\n", __func__, oh->name); | |
570 | ||
571 | /* on secure device, do not register secure timer */ | |
572 | timer_dev_attr = oh->dev_attr; | |
573 | if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr) | |
574 | if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE) | |
575 | return ret; | |
576 | ||
577 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); | |
578 | if (!pdata) { | |
579 | pr_err("%s: No memory for [%s]\n", __func__, oh->name); | |
580 | return -ENOMEM; | |
581 | } | |
582 | ||
583 | /* | |
584 | * Extract the IDs from name field in hwmod database | |
585 | * and use the same for constructing ids' for the | |
586 | * timer devices. In a way, we are avoiding usage of | |
587 | * static variable witin the function to do the same. | |
588 | * CAUTION: We have to be careful and make sure the | |
589 | * name in hwmod database does not change in which case | |
590 | * we might either make corresponding change here or | |
591 | * switch back static variable mechanism. | |
592 | */ | |
593 | sscanf(oh->name, "timer%2d", &id); | |
594 | ||
d1c1691b JH |
595 | if (timer_dev_attr) |
596 | pdata->timer_capability = timer_dev_attr->timer_capability; | |
0dad9fae | 597 | |
c541c15f | 598 | pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata), |
c16ae1e6 | 599 | NULL, 0, 0); |
c345c8b0 | 600 | |
c541c15f | 601 | if (IS_ERR(pdev)) { |
c345c8b0 TKD |
602 | pr_err("%s: Can't build omap_device for %s: %s.\n", |
603 | __func__, name, oh->name); | |
604 | ret = -EINVAL; | |
605 | } | |
606 | ||
607 | kfree(pdata); | |
608 | ||
609 | return ret; | |
610 | } | |
3392cdd3 TKD |
611 | |
612 | /** | |
613 | * omap2_dm_timer_init - top level regular device initialization | |
614 | * | |
615 | * Uses dedicated hwmod api to parse through hwmod database for | |
616 | * given class name and then build and register the timer device. | |
617 | */ | |
618 | static int __init omap2_dm_timer_init(void) | |
619 | { | |
620 | int ret; | |
621 | ||
622 | ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); | |
623 | if (unlikely(ret)) { | |
624 | pr_err("%s: device registration failed.\n", __func__); | |
625 | return -EINVAL; | |
626 | } | |
627 | ||
628 | return 0; | |
629 | } | |
630 | arch_initcall(omap2_dm_timer_init); | |
1fe97c8f VH |
631 | |
632 | /** | |
633 | * omap2_override_clocksource - clocksource override with user configuration | |
634 | * | |
635 | * Allows user to override default clocksource, using kernel parameter | |
636 | * clocksource="gp_timer" (For all OMAP2PLUS architectures) | |
637 | * | |
638 | * Note that, here we are using same standard kernel parameter "clocksource=", | |
639 | * and not introducing any OMAP specific interface. | |
640 | */ | |
641 | static int __init omap2_override_clocksource(char *str) | |
642 | { | |
643 | if (!str) | |
644 | return 0; | |
645 | /* | |
646 | * For OMAP architecture, we only have two options | |
647 | * - sync_32k (default) | |
648 | * - gp_timer (sys_clk based) | |
649 | */ | |
650 | if (!strcmp(str, "gp_timer")) | |
651 | use_gptimer_clksrc = true; | |
652 | ||
653 | return 0; | |
654 | } | |
655 | early_param("clocksource", omap2_override_clocksource); |