[deliverable/linux.git] / arch / arm / mach-orion5x / common.c

/*
 * arch/arm/mach-orion5x/common.c
 *
 * Core functions for Marvell Orion 5x SoCs
 *
 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/mbus.h>
#include <linux/mv643xx_eth.h>
#include <linux/mv643xx_i2c.h>
#include <linux/ata_platform.h>
#include <linux/spi/orion_spi.h>
#include <net/dsa.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/timex.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/hardware.h>
#include <mach/orion5x.h>
#include <plat/ehci-orion.h>
#include <plat/mv_xor.h>
#include <plat/orion_nand.h>
#include <plat/time.h>
#include "common.h"

/*****************************************************************************
 * I/O Address Mapping
 ****************************************************************************/
static struct map_desc orion5x_io_desc[] __initdata = {
	{
		.virtual	= ORION5X_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
		.length		= ORION5X_REGS_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= ORION5X_PCIE_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
		.length		= ORION5X_PCIE_IO_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= ORION5X_PCI_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
		.length		= ORION5X_PCI_IO_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= ORION5X_PCIE_WA_VIRT_BASE,
		.pfn		= __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
		.length		= ORION5X_PCIE_WA_SIZE,
		.type		= MT_DEVICE,
	},
};

void __init orion5x_map_io(void)
{
	iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
}


/*****************************************************************************
 * EHCI
 ****************************************************************************/
static struct orion_ehci_data orion5x_ehci_data = {
	.dram		= &orion5x_mbus_dram_info,
};

static u64 ehci_dmamask = 0xffffffffUL;


/*****************************************************************************
 * EHCI0
 ****************************************************************************/
static struct resource orion5x_ehci0_resources[] = {
	{
		.start	= ORION5X_USB0_PHYS_BASE,
		.end	= ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_ORION5X_USB0_CTRL,
		.end	= IRQ_ORION5X_USB0_CTRL,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_ehci0 = {
	.name		= "orion-ehci",
	.id		= 0,
	.dev		= {
		.dma_mask		= &ehci_dmamask,
		.coherent_dma_mask	= 0xffffffff,
		.platform_data		= &orion5x_ehci_data,
	},
	.resource	= orion5x_ehci0_resources,
	.num_resources	= ARRAY_SIZE(orion5x_ehci0_resources),
};

void __init orion5x_ehci0_init(void)
{
	platform_device_register(&orion5x_ehci0);
}


/*****************************************************************************
 * EHCI1
 ****************************************************************************/
static struct resource orion5x_ehci1_resources[] = {
	{
		.start	= ORION5X_USB1_PHYS_BASE,
		.end	= ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_ORION5X_USB1_CTRL,
		.end	= IRQ_ORION5X_USB1_CTRL,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_ehci1 = {
	.name		= "orion-ehci",
	.id		= 1,
	.dev		= {
		.dma_mask		= &ehci_dmamask,
		.coherent_dma_mask	= 0xffffffff,
		.platform_data		= &orion5x_ehci_data,
	},
	.resource	= orion5x_ehci1_resources,
	.num_resources	= ARRAY_SIZE(orion5x_ehci1_resources),
};

void __init orion5x_ehci1_init(void)
{
	platform_device_register(&orion5x_ehci1);
}


/*****************************************************************************
 * GigE
 ****************************************************************************/
struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
	.dram		= &orion5x_mbus_dram_info,
};

static struct resource orion5x_eth_shared_resources[] = {
	{
		.start	= ORION5X_ETH_PHYS_BASE + 0x2000,
		.end	= ORION5X_ETH_PHYS_BASE + 0x3fff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_ORION5X_ETH_ERR,
		.end	= IRQ_ORION5X_ETH_ERR,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_eth_shared = {
	.name		= MV643XX_ETH_SHARED_NAME,
	.id		= 0,
	.dev		= {
		.platform_data	= &orion5x_eth_shared_data,
	},
	.num_resources	= ARRAY_SIZE(orion5x_eth_shared_resources),
	.resource	= orion5x_eth_shared_resources,
};

static struct resource orion5x_eth_resources[] = {
	{
		.name	= "eth irq",
		.start	= IRQ_ORION5X_ETH_SUM,
		.end	= IRQ_ORION5X_ETH_SUM,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_eth = {
	.name		= MV643XX_ETH_NAME,
	.id		= 0,
	.num_resources	= 1,
	.resource	= orion5x_eth_resources,
};

void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
{
	eth_data->shared = &orion5x_eth_shared;
	orion5x_eth.dev.platform_data = eth_data;

	platform_device_register(&orion5x_eth_shared);
	platform_device_register(&orion5x_eth);
}


/*****************************************************************************
 * Ethernet switch
 ****************************************************************************/
static struct resource orion5x_switch_resources[] = {
	{
		.start	= 0,
		.end	= 0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_switch_device = {
	.name		= "dsa",
	.id		= 0,
	.num_resources	= 0,
	.resource	= orion5x_switch_resources,
};

void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
{
	if (irq != NO_IRQ) {
		orion5x_switch_resources[0].start = irq;
		orion5x_switch_resources[0].end = irq;
		orion5x_switch_device.num_resources = 1;
	}

	d->mii_bus = &orion5x_eth_shared.dev;
	d->netdev = &orion5x_eth.dev;
	orion5x_switch_device.dev.platform_data = d;

	platform_device_register(&orion5x_switch_device);
}


/*****************************************************************************
 * I2C
 ****************************************************************************/
static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
	.freq_m		= 8, /* assumes 166 MHz TCLK */
	.freq_n		= 3,
	.timeout	= 1000, /* Default timeout of 1 second */
};

static struct resource orion5x_i2c_resources[] = {
	{
		.name	= "i2c base",
		.start	= I2C_PHYS_BASE,
		.end	= I2C_PHYS_BASE + 0x1f,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "i2c irq",
		.start	= IRQ_ORION5X_I2C,
		.end	= IRQ_ORION5X_I2C,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_i2c = {
	.name		= MV64XXX_I2C_CTLR_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(orion5x_i2c_resources),
	.resource	= orion5x_i2c_resources,
	.dev		= {
		.platform_data	= &orion5x_i2c_pdata,
	},
};

void __init orion5x_i2c_init(void)
{
	platform_device_register(&orion5x_i2c);
}


/*****************************************************************************
 * SATA
 ****************************************************************************/
static struct resource orion5x_sata_resources[] = {
	{
		.name	= "sata base",
		.start	= ORION5X_SATA_PHYS_BASE,
		.end	= ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "sata irq",
		.start	= IRQ_ORION5X_SATA,
		.end	= IRQ_ORION5X_SATA,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_sata = {
	.name		= "sata_mv",
	.id		= 0,
	.dev		= {
		.coherent_dma_mask	= 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(orion5x_sata_resources),
	.resource	= orion5x_sata_resources,
};

void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
{
	sata_data->dram = &orion5x_mbus_dram_info;
	orion5x_sata.dev.platform_data = sata_data;
	platform_device_register(&orion5x_sata);
}


/*****************************************************************************
 * SPI
 ****************************************************************************/
static struct orion_spi_info orion5x_spi_plat_data = {
	.tclk		= 0,
};

static struct resource orion5x_spi_resources[] = {
	{
		.name	= "spi base",
		.start	= SPI_PHYS_BASE,
		.end	= SPI_PHYS_BASE + 0x1f,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device orion5x_spi = {
	.name		= "orion_spi",
	.id		= 0,
	.dev		= {
		.platform_data	= &orion5x_spi_plat_data,
	},
	.num_resources	= ARRAY_SIZE(orion5x_spi_resources),
	.resource	= orion5x_spi_resources,
};

void __init orion5x_spi_init()
{
	platform_device_register(&orion5x_spi);
}


/*****************************************************************************
 * UART0
 ****************************************************************************/
static struct plat_serial8250_port orion5x_uart0_data[] = {
	{
		.mapbase	= UART0_PHYS_BASE,
		.membase	= (char *)UART0_VIRT_BASE,
		.irq		= IRQ_ORION5X_UART0,
		.flags		= UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= 0,
	}, {
	},
};

static struct resource orion5x_uart0_resources[] = {
	{
		.start		= UART0_PHYS_BASE,
		.end		= UART0_PHYS_BASE + 0xff,
		.flags		= IORESOURCE_MEM,
	}, {
		.start		= IRQ_ORION5X_UART0,
		.end		= IRQ_ORION5X_UART0,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_uart0 = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= orion5x_uart0_data,
	},
	.resource		= orion5x_uart0_resources,
	.num_resources		= ARRAY_SIZE(orion5x_uart0_resources),
};

void __init orion5x_uart0_init(void)
{
	platform_device_register(&orion5x_uart0);
}


/*****************************************************************************
 * UART1
 ****************************************************************************/
static struct plat_serial8250_port orion5x_uart1_data[] = {
	{
		.mapbase	= UART1_PHYS_BASE,
		.membase	= (char *)UART1_VIRT_BASE,
		.irq		= IRQ_ORION5X_UART1,
		.flags		= UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
		.uartclk	= 0,
	}, {
	},
};

static struct resource orion5x_uart1_resources[] = {
	{
		.start		= UART1_PHYS_BASE,
		.end		= UART1_PHYS_BASE + 0xff,
		.flags		= IORESOURCE_MEM,
	}, {
		.start		= IRQ_ORION5X_UART1,
		.end		= IRQ_ORION5X_UART1,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_uart1 = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM1,
	.dev			= {
		.platform_data	= orion5x_uart1_data,
	},
	.resource		= orion5x_uart1_resources,
	.num_resources		= ARRAY_SIZE(orion5x_uart1_resources),
};

void __init orion5x_uart1_init(void)
{
	platform_device_register(&orion5x_uart1);
}


/*****************************************************************************
 * XOR engine
 ****************************************************************************/
static struct resource orion5x_xor_shared_resources[] = {
	{
		.name	= "xor low",
		.start	= ORION5X_XOR_PHYS_BASE,
		.end	= ORION5X_XOR_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "xor high",
		.start	= ORION5X_XOR_PHYS_BASE + 0x200,
		.end	= ORION5X_XOR_PHYS_BASE + 0x2ff,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device orion5x_xor_shared = {
	.name		= MV_XOR_SHARED_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(orion5x_xor_shared_resources),
	.resource	= orion5x_xor_shared_resources,
};

static u64 orion5x_xor_dmamask = DMA_32BIT_MASK;

static struct resource orion5x_xor0_resources[] = {
	[0] = {
		.start	= IRQ_ORION5X_XOR0,
		.end	= IRQ_ORION5X_XOR0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv_xor_platform_data orion5x_xor0_data = {
	.shared		= &orion5x_xor_shared,
	.hw_id		= 0,
	.pool_size	= PAGE_SIZE,
};

static struct platform_device orion5x_xor0_channel = {
	.name		= MV_XOR_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(orion5x_xor0_resources),
	.resource	= orion5x_xor0_resources,
	.dev		= {
		.dma_mask		= &orion5x_xor_dmamask,
		.coherent_dma_mask	= DMA_64BIT_MASK,
		.platform_data		= (void *)&orion5x_xor0_data,
	},
};

static struct resource orion5x_xor1_resources[] = {
	[0] = {
		.start	= IRQ_ORION5X_XOR1,
		.end	= IRQ_ORION5X_XOR1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv_xor_platform_data orion5x_xor1_data = {
	.shared		= &orion5x_xor_shared,
	.hw_id		= 1,
	.pool_size	= PAGE_SIZE,
};

static struct platform_device orion5x_xor1_channel = {
	.name		= MV_XOR_NAME,
	.id		= 1,
	.num_resources	= ARRAY_SIZE(orion5x_xor1_resources),
	.resource	= orion5x_xor1_resources,
	.dev		= {
		.dma_mask		= &orion5x_xor_dmamask,
		.coherent_dma_mask	= DMA_64BIT_MASK,
		.platform_data		= (void *)&orion5x_xor1_data,
	},
};

void __init orion5x_xor_init(void)
{
	platform_device_register(&orion5x_xor_shared);

	/*
	 * two engines can't do memset simultaneously, this limitation
	 * satisfied by removing memset support from one of the engines.
	 */
	dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask);
	dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask);
	platform_device_register(&orion5x_xor0_channel);

	dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask);
	dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask);
	dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask);
	platform_device_register(&orion5x_xor1_channel);
}


/*****************************************************************************
 * Time handling
 ****************************************************************************/
int orion5x_tclk;

int __init orion5x_find_tclk(void)
{
	u32 dev, rev;

	orion5x_pcie_id(&dev, &rev);
	if (dev == MV88F6183_DEV_ID &&
	    (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
		return 133333333;

	return 166666667;
}

static void orion5x_timer_init(void)
{
	orion5x_tclk = orion5x_find_tclk();
	orion_time_init(IRQ_ORION5X_BRIDGE, orion5x_tclk);
}

struct sys_timer orion5x_timer = {
	.init = orion5x_timer_init,
};


/*****************************************************************************
 * General
 ****************************************************************************/
/*
 * Identify device ID and rev from PCIe configuration header space '0'.
 */
static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
{
	orion5x_pcie_id(dev, rev);

	if (*dev == MV88F5281_DEV_ID) {
		if (*rev == MV88F5281_REV_D2) {
			*dev_name = "MV88F5281-D2";
		} else if (*rev == MV88F5281_REV_D1) {
			*dev_name = "MV88F5281-D1";
		} else if (*rev == MV88F5281_REV_D0) {
			*dev_name = "MV88F5281-D0";
		} else {
			*dev_name = "MV88F5281-Rev-Unsupported";
		}
	} else if (*dev == MV88F5182_DEV_ID) {
		if (*rev == MV88F5182_REV_A2) {
			*dev_name = "MV88F5182-A2";
		} else {
			*dev_name = "MV88F5182-Rev-Unsupported";
		}
	} else if (*dev == MV88F5181_DEV_ID) {
		if (*rev == MV88F5181_REV_B1) {
			*dev_name = "MV88F5181-Rev-B1";
		} else if (*rev == MV88F5181L_REV_A1) {
			*dev_name = "MV88F5181L-Rev-A1";
		} else {
			*dev_name = "MV88F5181(L)-Rev-Unsupported";
		}
	} else if (*dev == MV88F6183_DEV_ID) {
		if (*rev == MV88F6183_REV_B0) {
			*dev_name = "MV88F6183-Rev-B0";
		} else {
			*dev_name = "MV88F6183-Rev-Unsupported";
		}
	} else {
		*dev_name = "Device-Unknown";
	}
}

void __init orion5x_init(void)
{
	char *dev_name;
	u32 dev, rev;

	orion5x_id(&dev, &rev, &dev_name);
	printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);

	orion5x_eth_shared_data.t_clk = orion5x_tclk;
	orion5x_spi_plat_data.tclk = orion5x_tclk;
	orion5x_uart0_data[0].uartclk = orion5x_tclk;
	orion5x_uart1_data[0].uartclk = orion5x_tclk;

	/*
	 * Setup Orion address map
	 */
	orion5x_setup_cpu_mbus_bridge();

	/*
	 * Don't issue "Wait for Interrupt" instruction if we are
	 * running on D0 5281 silicon.
	 */
	if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
		printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
		disable_hlt();
	}
}

/*
 * Many orion-based systems have buggy bootloader implementations.
 * This is a common fixup for bogus memory tags.
 */
void __init tag_fixup_mem32(struct machine_desc *mdesc, struct tag *t,
			    char **from, struct meminfo *meminfo)
{
	for (; t->hdr.size; t = tag_next(t))
		if (t->hdr.tag == ATAG_MEM &&
		    (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
		     t->u.mem.start & ~PAGE_MASK)) {
			printk(KERN_WARNING
			       "Clearing invalid memory bank %dKB@0x%08x\n",
			       t->u.mem.size / 1024, t->u.mem.start);
			t->hdr.tag = 0;
		}
}
Commit	Line	Data
585cf175	1	/*
9dd0b194	2	* arch/arm/mach-orion5x/common.c
585cf175	3	*
9dd0b194	4	* Core functions for Marvell Orion 5x SoCs
585cf175 TP	5	*
	6	* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
	7	*
159ffb3a LB	8	* This file is licensed under the terms of the GNU General Public
159ffb3a LB	9	* License version 2. This program is licensed "as is" without any
585cf175 TP	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
ca26f7d3 TP	15	#include <linux/platform_device.h>
ca26f7d3 TP	16	#include <linux/serial_8250.h>
83b6d822	17	#include <linux/mbus.h>
e07c9d85	18	#include <linux/mv643xx_eth.h>
144aa3db	19	#include <linux/mv643xx_i2c.h>
15a32632	20	#include <linux/ata_platform.h>
d323ade1	21	#include <linux/spi/orion_spi.h>
dcf1cece	22	#include <net/dsa.h>
585cf175	23	#include <asm/page.h>
be73a347	24	#include <asm/setup.h>
c67de5b3	25	#include <asm/timex.h>
be73a347	26	#include <asm/mach/arch.h>
585cf175	27	#include <asm/mach/map.h>
2bac1de2	28	#include <asm/mach/time.h>
a09e64fb RK	29	#include <mach/hardware.h>
a09e64fb RK	30	#include <mach/orion5x.h>
6f088f1d	31	#include <plat/ehci-orion.h>
1d5a1a6e	32	#include <plat/mv_xor.h>
6f088f1d LB	33	#include <plat/orion_nand.h>
6f088f1d LB	34	#include <plat/time.h>
585cf175 TP	35	#include "common.h"
	36
	37	/*****************************************************************************
	38	* I/O Address Mapping
	39	****************************************************************************/
9dd0b194	40	static struct map_desc orion5x_io_desc[] __initdata = {
585cf175	41	{
9dd0b194 LB	42	.virtual = ORION5X_REGS_VIRT_BASE,
	43	.pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
	44	.length = ORION5X_REGS_SIZE,
e7068ad3 LB	45	.type = MT_DEVICE,
e7068ad3 LB	46	}, {
9dd0b194 LB	47	.virtual = ORION5X_PCIE_IO_VIRT_BASE,
	48	.pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
	49	.length = ORION5X_PCIE_IO_SIZE,
e7068ad3 LB	50	.type = MT_DEVICE,
e7068ad3 LB	51	}, {
9dd0b194 LB	52	.virtual = ORION5X_PCI_IO_VIRT_BASE,
	53	.pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
	54	.length = ORION5X_PCI_IO_SIZE,
e7068ad3 LB	55	.type = MT_DEVICE,
e7068ad3 LB	56	}, {
9dd0b194 LB	57	.virtual = ORION5X_PCIE_WA_VIRT_BASE,
	58	.pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
	59	.length = ORION5X_PCIE_WA_SIZE,
e7068ad3	60	.type = MT_DEVICE,
585cf175 TP	61	},
	62	};
	63
9dd0b194	64	void __init orion5x_map_io(void)
585cf175	65	{
9dd0b194	66	iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
585cf175	67	}
c67de5b3	68
044f6c7c	69
ca26f7d3	70	/*****************************************************************************
044f6c7c	71	* EHCI
ca26f7d3	72	****************************************************************************/
044f6c7c LB	73	static struct orion_ehci_data orion5x_ehci_data = {
044f6c7c LB	74	.dram = &orion5x_mbus_dram_info,
ca26f7d3 TP	75	};
ca26f7d3 TP	76
044f6c7c	77	static u64 ehci_dmamask = 0xffffffffUL;
ca26f7d3	78
ca26f7d3	79
044f6c7c LB	80	/*****************************************************************************
	81	* EHCI0
	82	****************************************************************************/
9dd0b194	83	static struct resource orion5x_ehci0_resources[] = {
ca26f7d3	84	{
9dd0b194	85	.start = ORION5X_USB0_PHYS_BASE,
994cab84	86	.end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
ca26f7d3	87	.flags = IORESOURCE_MEM,
e7068ad3	88	}, {
9dd0b194 LB	89	.start = IRQ_ORION5X_USB0_CTRL,
9dd0b194 LB	90	.end = IRQ_ORION5X_USB0_CTRL,
ca26f7d3 TP	91	.flags = IORESOURCE_IRQ,
	92	},
	93	};
	94
9dd0b194	95	static struct platform_device orion5x_ehci0 = {
ca26f7d3 TP	96	.name = "orion-ehci",
	97	.id = 0,
	98	.dev = {
	99	.dma_mask = &ehci_dmamask,
	100	.coherent_dma_mask = 0xffffffff,
9dd0b194	101	.platform_data = &orion5x_ehci_data,
ca26f7d3	102	},
9dd0b194 LB	103	.resource = orion5x_ehci0_resources,
9dd0b194 LB	104	.num_resources = ARRAY_SIZE(orion5x_ehci0_resources),
ca26f7d3 TP	105	};
ca26f7d3 TP	106
044f6c7c LB	107	void __init orion5x_ehci0_init(void)
	108	{
	109	platform_device_register(&orion5x_ehci0);
	110	}
	111
	112
	113	/*****************************************************************************
	114	* EHCI1
	115	****************************************************************************/
	116	static struct resource orion5x_ehci1_resources[] = {
	117	{
	118	.start = ORION5X_USB1_PHYS_BASE,
	119	.end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
	120	.flags = IORESOURCE_MEM,
	121	}, {
	122	.start = IRQ_ORION5X_USB1_CTRL,
	123	.end = IRQ_ORION5X_USB1_CTRL,
	124	.flags = IORESOURCE_IRQ,
	125	},
	126	};
	127
9dd0b194	128	static struct platform_device orion5x_ehci1 = {
ca26f7d3 TP	129	.name = "orion-ehci",
	130	.id = 1,
	131	.dev = {
	132	.dma_mask = &ehci_dmamask,
	133	.coherent_dma_mask = 0xffffffff,
9dd0b194	134	.platform_data = &orion5x_ehci_data,
ca26f7d3	135	},
9dd0b194 LB	136	.resource = orion5x_ehci1_resources,
9dd0b194 LB	137	.num_resources = ARRAY_SIZE(orion5x_ehci1_resources),
ca26f7d3 TP	138	};
ca26f7d3 TP	139
044f6c7c LB	140	void __init orion5x_ehci1_init(void)
	141	{
	142	platform_device_register(&orion5x_ehci1);
	143	}
	144
	145
e07c9d85	146	/*****************************************************************************
044f6c7c	147	* GigE
e07c9d85	148	****************************************************************************/
d236f5a5 LB	149	struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
	150	.dram = &orion5x_mbus_dram_info,
	151	};
	152
9dd0b194	153	static struct resource orion5x_eth_shared_resources[] = {
e07c9d85	154	{
9dd0b194 LB	155	.start = ORION5X_ETH_PHYS_BASE + 0x2000,
9dd0b194 LB	156	.end = ORION5X_ETH_PHYS_BASE + 0x3fff,
e07c9d85	157	.flags = IORESOURCE_MEM,
eeff6d86 LB	158	}, {
	159	.start = IRQ_ORION5X_ETH_ERR,
	160	.end = IRQ_ORION5X_ETH_ERR,
	161	.flags = IORESOURCE_IRQ,
e07c9d85 TP	162	},
	163	};
	164
9dd0b194	165	static struct platform_device orion5x_eth_shared = {
e07c9d85 TP	166	.name = MV643XX_ETH_SHARED_NAME,
e07c9d85 TP	167	.id = 0,
d236f5a5 LB	168	.dev = {
	169	.platform_data = &orion5x_eth_shared_data,
	170	},
eeff6d86	171	.num_resources = ARRAY_SIZE(orion5x_eth_shared_resources),
9dd0b194	172	.resource = orion5x_eth_shared_resources,
e07c9d85 TP	173	};
e07c9d85 TP	174
9dd0b194	175	static struct resource orion5x_eth_resources[] = {
e07c9d85 TP	176	{
e07c9d85 TP	177	.name = "eth irq",
9dd0b194 LB	178	.start = IRQ_ORION5X_ETH_SUM,
9dd0b194 LB	179	.end = IRQ_ORION5X_ETH_SUM,
e07c9d85	180	.flags = IORESOURCE_IRQ,
e7068ad3	181	},
e07c9d85 TP	182	};
e07c9d85 TP	183
9dd0b194	184	static struct platform_device orion5x_eth = {
e07c9d85 TP	185	.name = MV643XX_ETH_NAME,
	186	.id = 0,
	187	.num_resources = 1,
9dd0b194	188	.resource = orion5x_eth_resources,
e07c9d85 TP	189	};
e07c9d85 TP	190
9dd0b194	191	void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
e07c9d85	192	{
fa3959f4	193	eth_data->shared = &orion5x_eth_shared;
9dd0b194	194	orion5x_eth.dev.platform_data = eth_data;
fa3959f4	195
9dd0b194 LB	196	platform_device_register(&orion5x_eth_shared);
9dd0b194 LB	197	platform_device_register(&orion5x_eth);
e07c9d85 TP	198	}
e07c9d85 TP	199
044f6c7c	200
dcf1cece LB	201	/*****************************************************************************
	202	* Ethernet switch
	203	****************************************************************************/
	204	static struct resource orion5x_switch_resources[] = {
	205	{
	206	.start = 0,
	207	.end = 0,
	208	.flags = IORESOURCE_IRQ,
	209	},
	210	};
	211
	212	static struct platform_device orion5x_switch_device = {
	213	.name = "dsa",
	214	.id = 0,
	215	.num_resources = 0,
	216	.resource = orion5x_switch_resources,
	217	};
	218
	219	void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
	220	{
	221	if (irq != NO_IRQ) {
	222	orion5x_switch_resources[0].start = irq;
	223	orion5x_switch_resources[0].end = irq;
	224	orion5x_switch_device.num_resources = 1;
	225	}
	226
	227	d->mii_bus = &orion5x_eth_shared.dev;
	228	d->netdev = &orion5x_eth.dev;
	229	orion5x_switch_device.dev.platform_data = d;
	230
	231	platform_device_register(&orion5x_switch_device);
	232	}
	233
	234
144aa3db	235	/*****************************************************************************
044f6c7c	236	* I2C
144aa3db	237	****************************************************************************/
9dd0b194	238	static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
144aa3db HVR	239	.freq_m = 8, /* assumes 166 MHz TCLK */
	240	.freq_n = 3,
	241	.timeout = 1000, /* Default timeout of 1 second */
	242	};
	243
9dd0b194	244	static struct resource orion5x_i2c_resources[] = {
144aa3db	245	{
e7068ad3 LB	246	.name = "i2c base",
e7068ad3 LB	247	.start = I2C_PHYS_BASE,
044f6c7c	248	.end = I2C_PHYS_BASE + 0x1f,
e7068ad3 LB	249	.flags = IORESOURCE_MEM,
	250	}, {
	251	.name = "i2c irq",
	252	.start = IRQ_ORION5X_I2C,
	253	.end = IRQ_ORION5X_I2C,
	254	.flags = IORESOURCE_IRQ,
144aa3db HVR	255	},
	256	};
	257
9dd0b194	258	static struct platform_device orion5x_i2c = {
144aa3db HVR	259	.name = MV64XXX_I2C_CTLR_NAME,
144aa3db HVR	260	.id = 0,
9dd0b194 LB	261	.num_resources = ARRAY_SIZE(orion5x_i2c_resources),
9dd0b194 LB	262	.resource = orion5x_i2c_resources,
144aa3db	263	.dev = {
e7068ad3	264	.platform_data = &orion5x_i2c_pdata,
144aa3db HVR	265	},
	266	};
	267
044f6c7c LB	268	void __init orion5x_i2c_init(void)
	269	{
	270	platform_device_register(&orion5x_i2c);
	271	}
	272
	273
f244baa3	274	/*****************************************************************************
044f6c7c	275	* SATA
f244baa3	276	****************************************************************************/
9dd0b194	277	static struct resource orion5x_sata_resources[] = {
f244baa3	278	{
e7068ad3 LB	279	.name = "sata base",
	280	.start = ORION5X_SATA_PHYS_BASE,
	281	.end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
	282	.flags = IORESOURCE_MEM,
	283	}, {
	284	.name = "sata irq",
	285	.start = IRQ_ORION5X_SATA,
	286	.end = IRQ_ORION5X_SATA,
	287	.flags = IORESOURCE_IRQ,
	288	},
f244baa3 SB	289	};
f244baa3 SB	290
9dd0b194	291	static struct platform_device orion5x_sata = {
e7068ad3 LB	292	.name = "sata_mv",
e7068ad3 LB	293	.id = 0,
f244baa3 SB	294	.dev = {
	295	.coherent_dma_mask = 0xffffffff,
	296	},
e7068ad3 LB	297	.num_resources = ARRAY_SIZE(orion5x_sata_resources),
e7068ad3 LB	298	.resource = orion5x_sata_resources,
f244baa3 SB	299	};
f244baa3 SB	300
9dd0b194	301	void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
f244baa3	302	{
9dd0b194 LB	303	sata_data->dram = &orion5x_mbus_dram_info;
	304	orion5x_sata.dev.platform_data = sata_data;
	305	platform_device_register(&orion5x_sata);
f244baa3 SB	306	}
f244baa3 SB	307
044f6c7c	308
d323ade1 LB	309	/*****************************************************************************
	310	* SPI
	311	****************************************************************************/
	312	static struct orion_spi_info orion5x_spi_plat_data = {
	313	.tclk = 0,
	314	};
	315
	316	static struct resource orion5x_spi_resources[] = {
	317	{
	318	.name = "spi base",
	319	.start = SPI_PHYS_BASE,
	320	.end = SPI_PHYS_BASE + 0x1f,
	321	.flags = IORESOURCE_MEM,
	322	},
	323	};
	324
	325	static struct platform_device orion5x_spi = {
	326	.name = "orion_spi",
	327	.id = 0,
	328	.dev = {
	329	.platform_data = &orion5x_spi_plat_data,
	330	},
	331	.num_resources = ARRAY_SIZE(orion5x_spi_resources),
	332	.resource = orion5x_spi_resources,
	333	};
	334
	335	void __init orion5x_spi_init()
	336	{
	337	platform_device_register(&orion5x_spi);
	338	}
	339
	340
2bac1de2	341	/*****************************************************************************
044f6c7c LB	342	* UART0
	343	****************************************************************************/
	344	static struct plat_serial8250_port orion5x_uart0_data[] = {
	345	{
	346	.mapbase = UART0_PHYS_BASE,
	347	.membase = (char *)UART0_VIRT_BASE,
	348	.irq = IRQ_ORION5X_UART0,
	349	.flags = UPF_SKIP_TEST \| UPF_BOOT_AUTOCONF,
	350	.iotype = UPIO_MEM,
	351	.regshift = 2,
ebe35aff	352	.uartclk = 0,
044f6c7c LB	353	}, {
	354	},
	355	};
	356
	357	static struct resource orion5x_uart0_resources[] = {
	358	{
	359	.start = UART0_PHYS_BASE,
	360	.end = UART0_PHYS_BASE + 0xff,
	361	.flags = IORESOURCE_MEM,
	362	}, {
	363	.start = IRQ_ORION5X_UART0,
	364	.end = IRQ_ORION5X_UART0,
	365	.flags = IORESOURCE_IRQ,
	366	},
	367	};
	368
	369	static struct platform_device orion5x_uart0 = {
	370	.name = "serial8250",
	371	.id = PLAT8250_DEV_PLATFORM,
	372	.dev = {
	373	.platform_data = orion5x_uart0_data,
	374	},
	375	.resource = orion5x_uart0_resources,
	376	.num_resources = ARRAY_SIZE(orion5x_uart0_resources),
	377	};
	378
	379	void __init orion5x_uart0_init(void)
	380	{
	381	platform_device_register(&orion5x_uart0);
	382	}
	383
	384
	385	/*****************************************************************************
	386	* UART1
2bac1de2	387	****************************************************************************/
044f6c7c LB	388	static struct plat_serial8250_port orion5x_uart1_data[] = {
	389	{
	390	.mapbase = UART1_PHYS_BASE,
	391	.membase = (char *)UART1_VIRT_BASE,
	392	.irq = IRQ_ORION5X_UART1,
	393	.flags = UPF_SKIP_TEST \| UPF_BOOT_AUTOCONF,
	394	.iotype = UPIO_MEM,
	395	.regshift = 2,
ebe35aff	396	.uartclk = 0,
044f6c7c LB	397	}, {
	398	},
	399	};
	400
	401	static struct resource orion5x_uart1_resources[] = {
	402	{
	403	.start = UART1_PHYS_BASE,
	404	.end = UART1_PHYS_BASE + 0xff,
	405	.flags = IORESOURCE_MEM,
	406	}, {
	407	.start = IRQ_ORION5X_UART1,
	408	.end = IRQ_ORION5X_UART1,
	409	.flags = IORESOURCE_IRQ,
	410	},
	411	};
	412
	413	static struct platform_device orion5x_uart1 = {
	414	.name = "serial8250",
	415	.id = PLAT8250_DEV_PLATFORM1,
	416	.dev = {
	417	.platform_data = orion5x_uart1_data,
	418	},
	419	.resource = orion5x_uart1_resources,
	420	.num_resources = ARRAY_SIZE(orion5x_uart1_resources),
	421	};
	422
	423	void __init orion5x_uart1_init(void)
	424	{
	425	platform_device_register(&orion5x_uart1);
	426	}
2bac1de2	427
044f6c7c	428
1d5a1a6e SB	429	/*****************************************************************************
	430	* XOR engine
	431	****************************************************************************/
	432	static struct resource orion5x_xor_shared_resources[] = {
	433	{
	434	.name = "xor low",
	435	.start = ORION5X_XOR_PHYS_BASE,
	436	.end = ORION5X_XOR_PHYS_BASE + 0xff,
	437	.flags = IORESOURCE_MEM,
	438	}, {
	439	.name = "xor high",
	440	.start = ORION5X_XOR_PHYS_BASE + 0x200,
	441	.end = ORION5X_XOR_PHYS_BASE + 0x2ff,
	442	.flags = IORESOURCE_MEM,
	443	},
	444	};
	445
	446	static struct platform_device orion5x_xor_shared = {
	447	.name = MV_XOR_SHARED_NAME,
	448	.id = 0,
	449	.num_resources = ARRAY_SIZE(orion5x_xor_shared_resources),
	450	.resource = orion5x_xor_shared_resources,
	451	};
	452
	453	static u64 orion5x_xor_dmamask = DMA_32BIT_MASK;
	454
	455	static struct resource orion5x_xor0_resources[] = {
	456	[0] = {
	457	.start = IRQ_ORION5X_XOR0,
	458	.end = IRQ_ORION5X_XOR0,
	459	.flags = IORESOURCE_IRQ,
	460	},
	461	};
	462
	463	static struct mv_xor_platform_data orion5x_xor0_data = {
	464	.shared = &orion5x_xor_shared,
	465	.hw_id = 0,
	466	.pool_size = PAGE_SIZE,
	467	};
	468
	469	static struct platform_device orion5x_xor0_channel = {
	470	.name = MV_XOR_NAME,
	471	.id = 0,
	472	.num_resources = ARRAY_SIZE(orion5x_xor0_resources),
	473	.resource = orion5x_xor0_resources,
	474	.dev = {
	475	.dma_mask = &orion5x_xor_dmamask,
	476	.coherent_dma_mask = DMA_64BIT_MASK,
	477	.platform_data = (void *)&orion5x_xor0_data,
	478	},
	479	};
	480
	481	static struct resource orion5x_xor1_resources[] = {
	482	[0] = {
	483	.start = IRQ_ORION5X_XOR1,
	484	.end = IRQ_ORION5X_XOR1,
	485	.flags = IORESOURCE_IRQ,
	486	},
	487	};
	488
	489	static struct mv_xor_platform_data orion5x_xor1_data = {
	490	.shared = &orion5x_xor_shared,
	491	.hw_id = 1,
	492	.pool_size = PAGE_SIZE,
493	};
494
495	static struct platform_device orion5x_xor1_channel = {
496	.name = MV_XOR_NAME,
497	.id = 1,
498	.num_resources = ARRAY_SIZE(orion5x_xor1_resources),
499	.resource = orion5x_xor1_resources,
500	.dev = {
501	.dma_mask = &orion5x_xor_dmamask,
502	.coherent_dma_mask = DMA_64BIT_MASK,
503	.platform_data = (void *)&orion5x_xor1_data,
504	},
505	};
506
507	void __init orion5x_xor_init(void)
508	{
509	platform_device_register(&orion5x_xor_shared);
510
511	/*
512	* two engines can't do memset simultaneously, this limitation
513	* satisfied by removing memset support from one of the engines.
514	*/
515	dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask);
516	dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask);
517	platform_device_register(&orion5x_xor0_channel);
518
519	dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask);
520	dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask);
521	dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask);
522	platform_device_register(&orion5x_xor1_channel);
523	}
524
525
044f6c7c LB	526	/*****************************************************************************
	527	* Time handling
	528	****************************************************************************/
ebe35aff LB	529	int orion5x_tclk;
	530
	531	int __init orion5x_find_tclk(void)
	532	{
d323ade1 LB	533	u32 dev, rev;
	534
	535	orion5x_pcie_id(&dev, &rev);
	536	if (dev == MV88F6183_DEV_ID &&
	537	(readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
	538	return 133333333;
	539
ebe35aff LB	540	return 166666667;
	541	}
	542
9dd0b194	543	static void orion5x_timer_init(void)
2bac1de2	544	{
ebe35aff LB	545	orion5x_tclk = orion5x_find_tclk();
ebe35aff LB	546	orion_time_init(IRQ_ORION5X_BRIDGE, orion5x_tclk);
2bac1de2 LB	547	}
2bac1de2 LB	548
9dd0b194	549	struct sys_timer orion5x_timer = {
e7068ad3	550	.init = orion5x_timer_init,
2bac1de2 LB	551	};
2bac1de2 LB	552
044f6c7c	553
c67de5b3 TP	554	/*****************************************************************************
	555	* General
	556	****************************************************************************/
c67de5b3	557	/*
b46926bb	558	* Identify device ID and rev from PCIe configuration header space '0'.
c67de5b3	559	*/
9dd0b194	560	static void __init orion5x_id(u32 dev, u32 rev, char **dev_name)
c67de5b3	561	{
9dd0b194	562	orion5x_pcie_id(dev, rev);
c67de5b3 TP	563
	564	if (*dev == MV88F5281_DEV_ID) {
	565	if (*rev == MV88F5281_REV_D2) {
	566	*dev_name = "MV88F5281-D2";
	567	} else if (*rev == MV88F5281_REV_D1) {
	568	*dev_name = "MV88F5281-D1";
ce72e36e LB	569	} else if (*rev == MV88F5281_REV_D0) {
ce72e36e LB	570	*dev_name = "MV88F5281-D0";
c67de5b3 TP	571	} else {
	572	*dev_name = "MV88F5281-Rev-Unsupported";
	573	}
	574	} else if (*dev == MV88F5182_DEV_ID) {
	575	if (*rev == MV88F5182_REV_A2) {
	576	*dev_name = "MV88F5182-A2";
	577	} else {
	578	*dev_name = "MV88F5182-Rev-Unsupported";
	579	}
c9e3de94 HVR	580	} else if (*dev == MV88F5181_DEV_ID) {
	581	if (*rev == MV88F5181_REV_B1) {
	582	*dev_name = "MV88F5181-Rev-B1";
d2b2a6bb LB	583	} else if (*rev == MV88F5181L_REV_A1) {
d2b2a6bb LB	584	*dev_name = "MV88F5181L-Rev-A1";
c9e3de94	585	} else {
d2b2a6bb	586	*dev_name = "MV88F5181(L)-Rev-Unsupported";
c9e3de94	587	}
d323ade1 LB	588	} else if (*dev == MV88F6183_DEV_ID) {
	589	if (*rev == MV88F6183_REV_B0) {
	590	*dev_name = "MV88F6183-Rev-B0";
	591	} else {
	592	*dev_name = "MV88F6183-Rev-Unsupported";
	593	}
c67de5b3 TP	594	} else {
	595	*dev_name = "Device-Unknown";
	596	}
	597	}
	598
9dd0b194	599	void __init orion5x_init(void)
c67de5b3 TP	600	{
	601	char *dev_name;
	602	u32 dev, rev;
	603
9dd0b194	604	orion5x_id(&dev, &rev, &dev_name);
ebe35aff LB	605	printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
	606
	607	orion5x_eth_shared_data.t_clk = orion5x_tclk;
d323ade1	608	orion5x_spi_plat_data.tclk = orion5x_tclk;
ebe35aff LB	609	orion5x_uart0_data[0].uartclk = orion5x_tclk;
ebe35aff LB	610	orion5x_uart1_data[0].uartclk = orion5x_tclk;
c67de5b3 TP	611
	612	/*
	613	* Setup Orion address map
	614	*/
9dd0b194	615	orion5x_setup_cpu_mbus_bridge();
ce72e36e LB	616
	617	/*
	618	* Don't issue "Wait for Interrupt" instruction if we are
	619	* running on D0 5281 silicon.
	620	*/
	621	if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
	622	printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
	623	disable_hlt();
	624	}
c67de5b3	625	}
be73a347 GL	626
	627	/*
	628	* Many orion-based systems have buggy bootloader implementations.
	629	* This is a common fixup for bogus memory tags.
	630	*/
	631	void __init tag_fixup_mem32(struct machine_desc mdesc, struct tag t,
	632	char *from, struct meminfo meminfo)
	633	{
	634	for (; t->hdr.size; t = tag_next(t))
	635	if (t->hdr.tag == ATAG_MEM &&
	636	(!t->u.mem.size \|\| t->u.mem.size & ~PAGE_MASK \|\|
	637	t->u.mem.start & ~PAGE_MASK)) {
	638	printk(KERN_WARNING
	639	"Clearing invalid memory bank %dKB@0x%08x\n",
	640	t->u.mem.size / 1024, t->u.mem.start);
	641	t->hdr.tag = 0;
	642	}
	643	}