Commit | Line | Data |
---|---|---|
e448b12c | 1 | /* |
9dd0b194 | 2 | * arch/arm/mach-orion5x/db88f5281-setup.c |
e448b12c TP |
3 | * |
4 | * Marvell Orion-2 Development Board Setup | |
5 | * | |
6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | |
7 | * | |
159ffb3a LB |
8 | * This file is licensed under the terms of the GNU General Public |
9 | * License version 2. This program is licensed "as is" without any | |
e448b12c TP |
10 | * warranty of any kind, whether express or implied. |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/irq.h> | |
18 | #include <linux/mtd/physmap.h> | |
19 | #include <linux/mtd/nand.h> | |
20 | #include <linux/timer.h> | |
21 | #include <linux/mv643xx_eth.h> | |
22 | #include <linux/i2c.h> | |
23 | #include <asm/mach-types.h> | |
24 | #include <asm/gpio.h> | |
25 | #include <asm/mach/arch.h> | |
26 | #include <asm/mach/pci.h> | |
a09e64fb | 27 | #include <mach/orion5x.h> |
6f088f1d | 28 | #include <plat/orion_nand.h> |
e448b12c | 29 | #include "common.h" |
19cfd5c0 | 30 | #include "mpp.h" |
e448b12c TP |
31 | |
32 | /***************************************************************************** | |
33 | * DB-88F5281 on board devices | |
34 | ****************************************************************************/ | |
35 | ||
36 | /* | |
37 | * 512K NOR flash Device bus boot chip select | |
38 | */ | |
39 | ||
40 | #define DB88F5281_NOR_BOOT_BASE 0xf4000000 | |
41 | #define DB88F5281_NOR_BOOT_SIZE SZ_512K | |
42 | ||
43 | /* | |
44 | * 7-Segment on Device bus chip select 0 | |
45 | */ | |
46 | ||
47 | #define DB88F5281_7SEG_BASE 0xfa000000 | |
48 | #define DB88F5281_7SEG_SIZE SZ_1K | |
49 | ||
50 | /* | |
51 | * 32M NOR flash on Device bus chip select 1 | |
52 | */ | |
53 | ||
54 | #define DB88F5281_NOR_BASE 0xfc000000 | |
55 | #define DB88F5281_NOR_SIZE SZ_32M | |
56 | ||
57 | /* | |
58 | * 32M NAND flash on Device bus chip select 2 | |
59 | */ | |
60 | ||
61 | #define DB88F5281_NAND_BASE 0xfa800000 | |
62 | #define DB88F5281_NAND_SIZE SZ_1K | |
63 | ||
64 | /* | |
65 | * PCI | |
66 | */ | |
67 | ||
68 | #define DB88F5281_PCI_SLOT0_OFFS 7 | |
69 | #define DB88F5281_PCI_SLOT0_IRQ_PIN 12 | |
70 | #define DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN 13 | |
71 | ||
72 | /***************************************************************************** | |
73 | * 512M NOR Flash on Device bus Boot CS | |
74 | ****************************************************************************/ | |
75 | ||
76 | static struct physmap_flash_data db88f5281_boot_flash_data = { | |
77 | .width = 1, /* 8 bit bus width */ | |
78 | }; | |
79 | ||
80 | static struct resource db88f5281_boot_flash_resource = { | |
81 | .flags = IORESOURCE_MEM, | |
82 | .start = DB88F5281_NOR_BOOT_BASE, | |
83 | .end = DB88F5281_NOR_BOOT_BASE + DB88F5281_NOR_BOOT_SIZE - 1, | |
84 | }; | |
85 | ||
86 | static struct platform_device db88f5281_boot_flash = { | |
87 | .name = "physmap-flash", | |
88 | .id = 0, | |
89 | .dev = { | |
e7068ad3 | 90 | .platform_data = &db88f5281_boot_flash_data, |
e448b12c TP |
91 | }, |
92 | .num_resources = 1, | |
93 | .resource = &db88f5281_boot_flash_resource, | |
94 | }; | |
95 | ||
96 | /***************************************************************************** | |
97 | * 32M NOR Flash on Device bus CS1 | |
98 | ****************************************************************************/ | |
99 | ||
100 | static struct physmap_flash_data db88f5281_nor_flash_data = { | |
101 | .width = 4, /* 32 bit bus width */ | |
102 | }; | |
103 | ||
104 | static struct resource db88f5281_nor_flash_resource = { | |
105 | .flags = IORESOURCE_MEM, | |
106 | .start = DB88F5281_NOR_BASE, | |
107 | .end = DB88F5281_NOR_BASE + DB88F5281_NOR_SIZE - 1, | |
108 | }; | |
109 | ||
110 | static struct platform_device db88f5281_nor_flash = { | |
111 | .name = "physmap-flash", | |
112 | .id = 1, | |
113 | .dev = { | |
e7068ad3 | 114 | .platform_data = &db88f5281_nor_flash_data, |
e448b12c TP |
115 | }, |
116 | .num_resources = 1, | |
117 | .resource = &db88f5281_nor_flash_resource, | |
118 | }; | |
119 | ||
120 | /***************************************************************************** | |
121 | * 32M NAND Flash on Device bus CS2 | |
122 | ****************************************************************************/ | |
123 | ||
124 | static struct mtd_partition db88f5281_nand_parts[] = { | |
125 | { | |
126 | .name = "kernel", | |
127 | .offset = 0, | |
128 | .size = SZ_2M, | |
e7068ad3 | 129 | }, { |
e448b12c TP |
130 | .name = "root", |
131 | .offset = SZ_2M, | |
132 | .size = (SZ_16M - SZ_2M), | |
e7068ad3 | 133 | }, { |
e448b12c TP |
134 | .name = "user", |
135 | .offset = SZ_16M, | |
136 | .size = SZ_8M, | |
e7068ad3 | 137 | }, { |
e448b12c TP |
138 | .name = "recovery", |
139 | .offset = (SZ_16M + SZ_8M), | |
140 | .size = SZ_8M, | |
141 | }, | |
142 | }; | |
143 | ||
144 | static struct resource db88f5281_nand_resource = { | |
145 | .flags = IORESOURCE_MEM, | |
146 | .start = DB88F5281_NAND_BASE, | |
147 | .end = DB88F5281_NAND_BASE + DB88F5281_NAND_SIZE - 1, | |
148 | }; | |
149 | ||
150 | static struct orion_nand_data db88f5281_nand_data = { | |
151 | .parts = db88f5281_nand_parts, | |
152 | .nr_parts = ARRAY_SIZE(db88f5281_nand_parts), | |
153 | .cle = 0, | |
154 | .ale = 1, | |
155 | .width = 8, | |
156 | }; | |
157 | ||
158 | static struct platform_device db88f5281_nand_flash = { | |
159 | .name = "orion_nand", | |
160 | .id = -1, | |
161 | .dev = { | |
162 | .platform_data = &db88f5281_nand_data, | |
163 | }, | |
164 | .resource = &db88f5281_nand_resource, | |
165 | .num_resources = 1, | |
166 | }; | |
167 | ||
168 | /***************************************************************************** | |
169 | * 7-Segment on Device bus CS0 | |
170 | * Dummy counter every 2 sec | |
171 | ****************************************************************************/ | |
172 | ||
173 | static void __iomem *db88f5281_7seg; | |
174 | static struct timer_list db88f5281_timer; | |
175 | ||
176 | static void db88f5281_7seg_event(unsigned long data) | |
177 | { | |
178 | static int count = 0; | |
179 | writel(0, db88f5281_7seg + (count << 4)); | |
180 | count = (count + 1) & 7; | |
181 | mod_timer(&db88f5281_timer, jiffies + 2 * HZ); | |
182 | } | |
183 | ||
184 | static int __init db88f5281_7seg_init(void) | |
185 | { | |
186 | if (machine_is_db88f5281()) { | |
187 | db88f5281_7seg = ioremap(DB88F5281_7SEG_BASE, | |
188 | DB88F5281_7SEG_SIZE); | |
189 | if (!db88f5281_7seg) { | |
190 | printk(KERN_ERR "Failed to ioremap db88f5281_7seg\n"); | |
191 | return -EIO; | |
192 | } | |
193 | setup_timer(&db88f5281_timer, db88f5281_7seg_event, 0); | |
194 | mod_timer(&db88f5281_timer, jiffies + 2 * HZ); | |
195 | } | |
196 | ||
197 | return 0; | |
198 | } | |
199 | ||
200 | __initcall(db88f5281_7seg_init); | |
201 | ||
202 | /***************************************************************************** | |
203 | * PCI | |
204 | ****************************************************************************/ | |
205 | ||
206 | void __init db88f5281_pci_preinit(void) | |
207 | { | |
208 | int pin; | |
209 | ||
210 | /* | |
211 | * Configure PCI GPIO IRQ pins | |
212 | */ | |
213 | pin = DB88F5281_PCI_SLOT0_IRQ_PIN; | |
214 | if (gpio_request(pin, "PCI Int1") == 0) { | |
215 | if (gpio_direction_input(pin) == 0) { | |
6cab4860 | 216 | set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
e448b12c TP |
217 | } else { |
218 | printk(KERN_ERR "db88f5281_pci_preinit faield to " | |
219 | "set_irq_type pin %d\n", pin); | |
220 | gpio_free(pin); | |
221 | } | |
222 | } else { | |
223 | printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin); | |
224 | } | |
225 | ||
226 | pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN; | |
227 | if (gpio_request(pin, "PCI Int2") == 0) { | |
228 | if (gpio_direction_input(pin) == 0) { | |
6cab4860 | 229 | set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
e448b12c TP |
230 | } else { |
231 | printk(KERN_ERR "db88f5281_pci_preinit faield " | |
232 | "to set_irq_type pin %d\n", pin); | |
233 | gpio_free(pin); | |
234 | } | |
235 | } else { | |
236 | printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin); | |
237 | } | |
238 | } | |
239 | ||
240 | static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |
241 | { | |
92b913b0 LB |
242 | int irq; |
243 | ||
e448b12c | 244 | /* |
92b913b0 | 245 | * Check for devices with hard-wired IRQs. |
e448b12c | 246 | */ |
92b913b0 LB |
247 | irq = orion5x_pci_map_irq(dev, slot, pin); |
248 | if (irq != -1) | |
249 | return irq; | |
e448b12c TP |
250 | |
251 | /* | |
92b913b0 | 252 | * PCI IRQs are connected via GPIOs. |
e448b12c TP |
253 | */ |
254 | switch (slot - DB88F5281_PCI_SLOT0_OFFS) { | |
255 | case 0: | |
256 | return gpio_to_irq(DB88F5281_PCI_SLOT0_IRQ_PIN); | |
257 | case 1: | |
258 | case 2: | |
259 | return gpio_to_irq(DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN); | |
260 | default: | |
261 | return -1; | |
262 | } | |
263 | } | |
264 | ||
265 | static struct hw_pci db88f5281_pci __initdata = { | |
266 | .nr_controllers = 2, | |
267 | .preinit = db88f5281_pci_preinit, | |
268 | .swizzle = pci_std_swizzle, | |
9dd0b194 LB |
269 | .setup = orion5x_pci_sys_setup, |
270 | .scan = orion5x_pci_sys_scan_bus, | |
e448b12c TP |
271 | .map_irq = db88f5281_pci_map_irq, |
272 | }; | |
273 | ||
274 | static int __init db88f5281_pci_init(void) | |
275 | { | |
276 | if (machine_is_db88f5281()) | |
277 | pci_common_init(&db88f5281_pci); | |
278 | ||
279 | return 0; | |
280 | } | |
281 | ||
282 | subsys_initcall(db88f5281_pci_init); | |
283 | ||
284 | /***************************************************************************** | |
285 | * Ethernet | |
286 | ****************************************************************************/ | |
287 | static struct mv643xx_eth_platform_data db88f5281_eth_data = { | |
ac840605 | 288 | .phy_addr = MV643XX_ETH_PHY_ADDR(8), |
e448b12c TP |
289 | }; |
290 | ||
291 | /***************************************************************************** | |
292 | * RTC DS1339 on I2C bus | |
293 | ****************************************************************************/ | |
294 | static struct i2c_board_info __initdata db88f5281_i2c_rtc = { | |
3760f736 | 295 | I2C_BOARD_INFO("ds1339", 0x68), |
e448b12c TP |
296 | }; |
297 | ||
298 | /***************************************************************************** | |
299 | * General Setup | |
300 | ****************************************************************************/ | |
19cfd5c0 LB |
301 | static struct orion5x_mpp_mode db88f5281_mpp_modes[] __initdata = { |
302 | { 0, MPP_GPIO }, /* USB Over Current */ | |
303 | { 1, MPP_GPIO }, /* USB Vbat input */ | |
304 | { 2, MPP_PCI_ARB }, /* PCI_REQn[2] */ | |
305 | { 3, MPP_PCI_ARB }, /* PCI_GNTn[2] */ | |
306 | { 4, MPP_PCI_ARB }, /* PCI_REQn[3] */ | |
307 | { 5, MPP_PCI_ARB }, /* PCI_GNTn[3] */ | |
308 | { 6, MPP_GPIO }, /* JP0, CON17.2 */ | |
309 | { 7, MPP_GPIO }, /* JP1, CON17.1 */ | |
310 | { 8, MPP_GPIO }, /* JP2, CON11.2 */ | |
311 | { 9, MPP_GPIO }, /* JP3, CON11.3 */ | |
312 | { 10, MPP_GPIO }, /* RTC int */ | |
313 | { 11, MPP_GPIO }, /* Baud Rate Generator */ | |
314 | { 12, MPP_GPIO }, /* PCI int 1 */ | |
315 | { 13, MPP_GPIO }, /* PCI int 2 */ | |
316 | { 14, MPP_NAND }, /* NAND_REn[2] */ | |
317 | { 15, MPP_NAND }, /* NAND_WEn[2] */ | |
318 | { 16, MPP_UART }, /* UART1_RX */ | |
319 | { 17, MPP_UART }, /* UART1_TX */ | |
320 | { 18, MPP_UART }, /* UART1_CTSn */ | |
321 | { 19, MPP_UART }, /* UART1_RTSn */ | |
322 | { -1 }, | |
323 | }; | |
324 | ||
e448b12c TP |
325 | static void __init db88f5281_init(void) |
326 | { | |
327 | /* | |
328 | * Basic Orion setup. Need to be called early. | |
329 | */ | |
9dd0b194 | 330 | orion5x_init(); |
e448b12c | 331 | |
19cfd5c0 | 332 | orion5x_mpp_conf(db88f5281_mpp_modes); |
79e90dd5 | 333 | writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ |
e448b12c | 334 | |
044f6c7c LB |
335 | /* |
336 | * Configure peripherals. | |
337 | */ | |
338 | orion5x_ehci0_init(); | |
9dd0b194 | 339 | orion5x_eth_init(&db88f5281_eth_data); |
044f6c7c LB |
340 | orion5x_i2c_init(); |
341 | orion5x_uart0_init(); | |
342 | orion5x_uart1_init(); | |
343 | ||
344 | orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE, | |
345 | DB88F5281_NOR_BOOT_SIZE); | |
346 | platform_device_register(&db88f5281_boot_flash); | |
347 | ||
348 | orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE); | |
349 | ||
350 | orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); | |
351 | platform_device_register(&db88f5281_nor_flash); | |
352 | ||
353 | orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); | |
354 | platform_device_register(&db88f5281_nand_flash); | |
355 | ||
356 | i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); | |
e448b12c TP |
357 | } |
358 | ||
359 | MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") | |
360 | /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */ | |
9dd0b194 LB |
361 | .phys_io = ORION5X_REGS_PHYS_BASE, |
362 | .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xfffc, | |
e448b12c TP |
363 | .boot_params = 0x00000100, |
364 | .init_machine = db88f5281_init, | |
9dd0b194 LB |
365 | .map_io = orion5x_map_io, |
366 | .init_irq = orion5x_init_irq, | |
367 | .timer = &orion5x_timer, | |
e448b12c | 368 | MACHINE_END |