Commit | Line | Data |
---|---|---|
038ee083 | 1 | /* |
9dd0b194 | 2 | * arch/arm/mach-orion5x/pci.c |
038ee083 | 3 | * |
159ffb3a | 4 | * PCI and PCIe functions for Marvell Orion System On Chip |
038ee083 TP |
5 | * |
6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | |
7 | * | |
159ffb3a LB |
8 | * This file is licensed under the terms of the GNU General Public |
9 | * License version 2. This program is licensed "as is" without any | |
038ee083 TP |
10 | * warranty of any kind, whether express or implied. |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/pci.h> | |
1f2223b1 | 15 | #include <linux/mbus.h> |
038ee083 | 16 | #include <asm/mach/pci.h> |
6f088f1d | 17 | #include <plat/pcie.h> |
038ee083 TP |
18 | #include "common.h" |
19 | ||
20 | /***************************************************************************** | |
159ffb3a | 21 | * Orion has one PCIe controller and one PCI controller. |
038ee083 | 22 | * |
159ffb3a LB |
23 | * Note1: The local PCIe bus number is '0'. The local PCI bus number |
24 | * follows the scanned PCIe bridged busses, if any. | |
038ee083 | 25 | * |
159ffb3a | 26 | * Note2: It is possible for PCI/PCIe agents to access many subsystem's |
038ee083 TP |
27 | * space, by configuring BARs and Address Decode Windows, e.g. flashes on |
28 | * device bus, Orion registers, etc. However this code only enable the | |
29 | * access to DDR banks. | |
30 | ****************************************************************************/ | |
31 | ||
32 | ||
33 | /***************************************************************************** | |
159ffb3a | 34 | * PCIe controller |
038ee083 | 35 | ****************************************************************************/ |
9dd0b194 | 36 | #define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE) |
038ee083 | 37 | |
9dd0b194 | 38 | void __init orion5x_pcie_id(u32 *dev, u32 *rev) |
038ee083 | 39 | { |
abc0197d LB |
40 | *dev = orion_pcie_dev_id(PCIE_BASE); |
41 | *rev = orion_pcie_rev(PCIE_BASE); | |
038ee083 TP |
42 | } |
43 | ||
abc0197d | 44 | static int pcie_valid_config(int bus, int dev) |
038ee083 TP |
45 | { |
46 | /* | |
47 | * Don't go out when trying to access -- | |
d50c60a8 | 48 | * 1. nonexisting device on local bus |
038ee083 | 49 | * 2. where there's no device connected (no link) |
038ee083 | 50 | */ |
d50c60a8 LB |
51 | if (bus == 0 && dev == 0) |
52 | return 1; | |
038ee083 | 53 | |
abc0197d | 54 | if (!orion_pcie_link_up(PCIE_BASE)) |
038ee083 TP |
55 | return 0; |
56 | ||
d50c60a8 LB |
57 | if (bus == 0 && dev != 1) |
58 | return 0; | |
59 | ||
038ee083 TP |
60 | return 1; |
61 | } | |
62 | ||
abc0197d LB |
63 | |
64 | /* | |
159ffb3a | 65 | * PCIe config cycles are done by programming the PCIE_CONF_ADDR register |
abc0197d LB |
66 | * and then reading the PCIE_CONF_DATA register. Need to make sure these |
67 | * transactions are atomic. | |
68 | */ | |
9dd0b194 | 69 | static DEFINE_SPINLOCK(orion5x_pcie_lock); |
abc0197d LB |
70 | |
71 | static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, | |
72 | int size, u32 *val) | |
038ee083 TP |
73 | { |
74 | unsigned long flags; | |
abc0197d | 75 | int ret; |
038ee083 | 76 | |
abc0197d | 77 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { |
038ee083 TP |
78 | *val = 0xffffffff; |
79 | return PCIBIOS_DEVICE_NOT_FOUND; | |
80 | } | |
81 | ||
9dd0b194 | 82 | spin_lock_irqsave(&orion5x_pcie_lock, flags); |
abc0197d | 83 | ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); |
9dd0b194 | 84 | spin_unlock_irqrestore(&orion5x_pcie_lock, flags); |
038ee083 | 85 | |
abc0197d LB |
86 | return ret; |
87 | } | |
038ee083 | 88 | |
abc0197d LB |
89 | static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, |
90 | int where, int size, u32 *val) | |
91 | { | |
92 | int ret; | |
038ee083 | 93 | |
abc0197d LB |
94 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { |
95 | *val = 0xffffffff; | |
96 | return PCIBIOS_DEVICE_NOT_FOUND; | |
97 | } | |
038ee083 | 98 | |
abc0197d LB |
99 | /* |
100 | * We only support access to the non-extended configuration | |
101 | * space when using the WA access method (or we would have to | |
102 | * sacrifice 256M of CPU virtual address space.) | |
103 | */ | |
104 | if (where >= 0x100) { | |
105 | *val = 0xffffffff; | |
106 | return PCIBIOS_DEVICE_NOT_FOUND; | |
107 | } | |
038ee083 | 108 | |
9dd0b194 | 109 | ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE, |
abc0197d | 110 | bus, devfn, where, size, val); |
038ee083 | 111 | |
abc0197d LB |
112 | return ret; |
113 | } | |
038ee083 | 114 | |
abc0197d LB |
115 | static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, |
116 | int where, int size, u32 val) | |
038ee083 TP |
117 | { |
118 | unsigned long flags; | |
119 | int ret; | |
120 | ||
abc0197d | 121 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) |
038ee083 TP |
122 | return PCIBIOS_DEVICE_NOT_FOUND; |
123 | ||
9dd0b194 | 124 | spin_lock_irqsave(&orion5x_pcie_lock, flags); |
abc0197d | 125 | ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); |
9dd0b194 | 126 | spin_unlock_irqrestore(&orion5x_pcie_lock, flags); |
038ee083 TP |
127 | |
128 | return ret; | |
129 | } | |
130 | ||
159ffb3a | 131 | static struct pci_ops pcie_ops = { |
abc0197d LB |
132 | .read = pcie_rd_conf, |
133 | .write = pcie_wr_conf, | |
038ee083 TP |
134 | }; |
135 | ||
136 | ||
a9984270 | 137 | static int __init pcie_setup(struct pci_sys_data *sys) |
038ee083 TP |
138 | { |
139 | struct resource *res; | |
abc0197d | 140 | int dev; |
038ee083 | 141 | |
1f2223b1 | 142 | /* |
abc0197d | 143 | * Generic PCIe unit setup. |
038ee083 | 144 | */ |
9dd0b194 | 145 | orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info); |
038ee083 TP |
146 | |
147 | /* | |
abc0197d LB |
148 | * Check whether to apply Orion-1/Orion-NAS PCIe config |
149 | * read transaction workaround. | |
038ee083 | 150 | */ |
abc0197d LB |
151 | dev = orion_pcie_dev_id(PCIE_BASE); |
152 | if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { | |
153 | printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " | |
154 | "read transaction workaround\n"); | |
386a048a LB |
155 | orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, |
156 | ORION5X_PCIE_WA_SIZE); | |
abc0197d LB |
157 | pcie_ops.read = pcie_rd_conf_wa; |
158 | } | |
038ee083 TP |
159 | |
160 | /* | |
abc0197d | 161 | * Request resources. |
038ee083 TP |
162 | */ |
163 | res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); | |
164 | if (!res) | |
abc0197d | 165 | panic("pcie_setup unable to alloc resources"); |
038ee083 TP |
166 | |
167 | /* | |
168 | * IORESOURCE_IO | |
169 | */ | |
159ffb3a | 170 | res[0].name = "PCIe I/O Space"; |
038ee083 | 171 | res[0].flags = IORESOURCE_IO; |
9dd0b194 LB |
172 | res[0].start = ORION5X_PCIE_IO_BUS_BASE; |
173 | res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; | |
038ee083 | 174 | if (request_resource(&ioport_resource, &res[0])) |
159ffb3a | 175 | panic("Request PCIe IO resource failed\n"); |
038ee083 TP |
176 | sys->resource[0] = &res[0]; |
177 | ||
178 | /* | |
179 | * IORESOURCE_MEM | |
180 | */ | |
159ffb3a | 181 | res[1].name = "PCIe Memory Space"; |
038ee083 | 182 | res[1].flags = IORESOURCE_MEM; |
9dd0b194 LB |
183 | res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; |
184 | res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; | |
038ee083 | 185 | if (request_resource(&iomem_resource, &res[1])) |
159ffb3a | 186 | panic("Request PCIe Memory resource failed\n"); |
038ee083 TP |
187 | sys->resource[1] = &res[1]; |
188 | ||
189 | sys->resource[2] = NULL; | |
190 | sys->io_offset = 0; | |
191 | ||
192 | return 1; | |
193 | } | |
194 | ||
195 | /***************************************************************************** | |
196 | * PCI controller | |
197 | ****************************************************************************/ | |
9dd0b194 LB |
198 | #define PCI_MODE ORION5X_PCI_REG(0xd00) |
199 | #define PCI_CMD ORION5X_PCI_REG(0xc00) | |
200 | #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) | |
201 | #define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78) | |
202 | #define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c) | |
038ee083 TP |
203 | |
204 | /* | |
205 | * PCI_MODE bits | |
206 | */ | |
207 | #define PCI_MODE_64BIT (1 << 2) | |
208 | #define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) | |
209 | ||
210 | /* | |
211 | * PCI_CMD bits | |
212 | */ | |
213 | #define PCI_CMD_HOST_REORDER (1 << 29) | |
214 | ||
215 | /* | |
216 | * PCI_P2P_CONF bits | |
217 | */ | |
218 | #define PCI_P2P_BUS_OFFS 16 | |
219 | #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) | |
220 | #define PCI_P2P_DEV_OFFS 24 | |
221 | #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) | |
222 | ||
223 | /* | |
224 | * PCI_CONF_ADDR bits | |
225 | */ | |
226 | #define PCI_CONF_REG(reg) ((reg) & 0xfc) | |
227 | #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) | |
228 | #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) | |
229 | #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) | |
230 | #define PCI_CONF_ADDR_EN (1 << 31) | |
231 | ||
232 | /* | |
233 | * Internal configuration space | |
234 | */ | |
235 | #define PCI_CONF_FUNC_STAT_CMD 0 | |
236 | #define PCI_CONF_REG_STAT_CMD 4 | |
237 | #define PCIX_STAT 0x64 | |
238 | #define PCIX_STAT_BUS_OFFS 8 | |
239 | #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) | |
240 | ||
1f2223b1 LB |
241 | /* |
242 | * PCI Address Decode Windows registers | |
243 | */ | |
9dd0b194 | 244 | #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ |
e7068ad3 LB |
245 | ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ |
246 | ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ | |
247 | ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) | |
248 | #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \ | |
249 | ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ | |
250 | ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ | |
251 | ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) | |
9dd0b194 LB |
252 | #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) |
253 | #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) | |
1f2223b1 LB |
254 | |
255 | /* | |
256 | * PCI configuration helpers for BAR settings | |
257 | */ | |
258 | #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) | |
259 | #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) | |
260 | #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) | |
261 | ||
038ee083 TP |
262 | /* |
263 | * PCI config cycles are done by programming the PCI_CONF_ADDR register | |
264 | * and then reading the PCI_CONF_DATA register. Need to make sure these | |
265 | * transactions are atomic. | |
266 | */ | |
9dd0b194 | 267 | static DEFINE_SPINLOCK(orion5x_pci_lock); |
038ee083 | 268 | |
da01bba3 LB |
269 | static int orion5x_pci_cardbus_mode; |
270 | ||
92b913b0 | 271 | static int orion5x_pci_local_bus_nr(void) |
038ee083 | 272 | { |
79e90dd5 | 273 | u32 conf = readl(PCI_P2P_CONF); |
038ee083 TP |
274 | return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); |
275 | } | |
276 | ||
9dd0b194 | 277 | static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, |
038ee083 TP |
278 | u32 where, u32 size, u32 *val) |
279 | { | |
280 | unsigned long flags; | |
9dd0b194 | 281 | spin_lock_irqsave(&orion5x_pci_lock, flags); |
038ee083 | 282 | |
79e90dd5 LB |
283 | writel(PCI_CONF_BUS(bus) | |
284 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | | |
285 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); | |
038ee083 | 286 | |
79e90dd5 | 287 | *val = readl(PCI_CONF_DATA); |
038ee083 TP |
288 | |
289 | if (size == 1) | |
290 | *val = (*val >> (8*(where & 0x3))) & 0xff; | |
291 | else if (size == 2) | |
292 | *val = (*val >> (8*(where & 0x3))) & 0xffff; | |
293 | ||
9dd0b194 | 294 | spin_unlock_irqrestore(&orion5x_pci_lock, flags); |
038ee083 TP |
295 | |
296 | return PCIBIOS_SUCCESSFUL; | |
297 | } | |
298 | ||
9dd0b194 | 299 | static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, |
038ee083 TP |
300 | u32 where, u32 size, u32 val) |
301 | { | |
302 | unsigned long flags; | |
303 | int ret = PCIBIOS_SUCCESSFUL; | |
304 | ||
9dd0b194 | 305 | spin_lock_irqsave(&orion5x_pci_lock, flags); |
038ee083 | 306 | |
79e90dd5 LB |
307 | writel(PCI_CONF_BUS(bus) | |
308 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | | |
309 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); | |
038ee083 TP |
310 | |
311 | if (size == 4) { | |
312 | __raw_writel(val, PCI_CONF_DATA); | |
313 | } else if (size == 2) { | |
314 | __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); | |
315 | } else if (size == 1) { | |
316 | __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); | |
317 | } else { | |
318 | ret = PCIBIOS_BAD_REGISTER_NUMBER; | |
319 | } | |
320 | ||
9dd0b194 | 321 | spin_unlock_irqrestore(&orion5x_pci_lock, flags); |
038ee083 TP |
322 | |
323 | return ret; | |
324 | } | |
325 | ||
da01bba3 LB |
326 | static int orion5x_pci_valid_config(int bus, u32 devfn) |
327 | { | |
328 | if (bus == orion5x_pci_local_bus_nr()) { | |
329 | /* | |
330 | * Don't go out for local device | |
331 | */ | |
332 | if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) | |
333 | return 0; | |
334 | ||
335 | /* | |
336 | * When the PCI signals are directly connected to a | |
337 | * Cardbus slot, ignore all but device IDs 0 and 1. | |
338 | */ | |
339 | if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1) | |
340 | return 0; | |
341 | } | |
342 | ||
343 | return 1; | |
344 | } | |
345 | ||
9dd0b194 | 346 | static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, |
038ee083 TP |
347 | int where, int size, u32 *val) |
348 | { | |
da01bba3 | 349 | if (!orion5x_pci_valid_config(bus->number, devfn)) { |
038ee083 TP |
350 | *val = 0xffffffff; |
351 | return PCIBIOS_DEVICE_NOT_FOUND; | |
352 | } | |
353 | ||
9dd0b194 | 354 | return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), |
038ee083 TP |
355 | PCI_FUNC(devfn), where, size, val); |
356 | } | |
357 | ||
9dd0b194 | 358 | static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, |
038ee083 TP |
359 | int where, int size, u32 val) |
360 | { | |
da01bba3 | 361 | if (!orion5x_pci_valid_config(bus->number, devfn)) |
038ee083 TP |
362 | return PCIBIOS_DEVICE_NOT_FOUND; |
363 | ||
9dd0b194 | 364 | return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), |
038ee083 TP |
365 | PCI_FUNC(devfn), where, size, val); |
366 | } | |
367 | ||
159ffb3a | 368 | static struct pci_ops pci_ops = { |
9dd0b194 LB |
369 | .read = orion5x_pci_rd_conf, |
370 | .write = orion5x_pci_wr_conf, | |
038ee083 TP |
371 | }; |
372 | ||
9dd0b194 | 373 | static void __init orion5x_pci_set_bus_nr(int nr) |
038ee083 | 374 | { |
79e90dd5 | 375 | u32 p2p = readl(PCI_P2P_CONF); |
038ee083 | 376 | |
79e90dd5 | 377 | if (readl(PCI_MODE) & PCI_MODE_PCIX) { |
038ee083 TP |
378 | /* |
379 | * PCI-X mode | |
380 | */ | |
381 | u32 pcix_status, bus, dev; | |
382 | bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; | |
383 | dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; | |
9dd0b194 | 384 | orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); |
038ee083 TP |
385 | pcix_status &= ~PCIX_STAT_BUS_MASK; |
386 | pcix_status |= (nr << PCIX_STAT_BUS_OFFS); | |
9dd0b194 | 387 | orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); |
038ee083 TP |
388 | } else { |
389 | /* | |
390 | * PCI Conventional mode | |
391 | */ | |
392 | p2p &= ~PCI_P2P_BUS_MASK; | |
393 | p2p |= (nr << PCI_P2P_BUS_OFFS); | |
79e90dd5 | 394 | writel(p2p, PCI_P2P_CONF); |
038ee083 TP |
395 | } |
396 | } | |
397 | ||
9dd0b194 | 398 | static void __init orion5x_pci_master_slave_enable(void) |
038ee083 | 399 | { |
d50c60a8 | 400 | int bus_nr, func, reg; |
abc0197d | 401 | u32 val; |
038ee083 | 402 | |
9dd0b194 | 403 | bus_nr = orion5x_pci_local_bus_nr(); |
038ee083 TP |
404 | func = PCI_CONF_FUNC_STAT_CMD; |
405 | reg = PCI_CONF_REG_STAT_CMD; | |
9dd0b194 | 406 | orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); |
038ee083 | 407 | val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
9dd0b194 | 408 | orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); |
038ee083 TP |
409 | } |
410 | ||
9dd0b194 | 411 | static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) |
1f2223b1 LB |
412 | { |
413 | u32 win_enable; | |
abc0197d | 414 | int bus; |
1f2223b1 LB |
415 | int i; |
416 | ||
417 | /* | |
418 | * First, disable windows. | |
419 | */ | |
420 | win_enable = 0xffffffff; | |
79e90dd5 | 421 | writel(win_enable, PCI_BAR_ENABLE); |
1f2223b1 LB |
422 | |
423 | /* | |
424 | * Setup windows for DDR banks. | |
425 | */ | |
9dd0b194 | 426 | bus = orion5x_pci_local_bus_nr(); |
1f2223b1 LB |
427 | |
428 | for (i = 0; i < dram->num_cs; i++) { | |
429 | struct mbus_dram_window *cs = dram->cs + i; | |
430 | u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); | |
431 | u32 reg; | |
432 | u32 val; | |
433 | ||
434 | /* | |
435 | * Write DRAM bank base address register. | |
436 | */ | |
437 | reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); | |
9dd0b194 | 438 | orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); |
1f2223b1 | 439 | val = (cs->base & 0xfffff000) | (val & 0xfff); |
9dd0b194 | 440 | orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); |
1f2223b1 LB |
441 | |
442 | /* | |
443 | * Write DRAM bank size register. | |
444 | */ | |
445 | reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); | |
9dd0b194 | 446 | orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); |
79e90dd5 LB |
447 | writel((cs->size - 1) & 0xfffff000, |
448 | PCI_BAR_SIZE_DDR_CS(cs->cs_index)); | |
449 | writel(cs->base & 0xfffff000, | |
450 | PCI_BAR_REMAP_DDR_CS(cs->cs_index)); | |
1f2223b1 LB |
451 | |
452 | /* | |
453 | * Enable decode window for this chip select. | |
454 | */ | |
455 | win_enable &= ~(1 << cs->cs_index); | |
456 | } | |
457 | ||
458 | /* | |
459 | * Re-enable decode windows. | |
460 | */ | |
79e90dd5 | 461 | writel(win_enable, PCI_BAR_ENABLE); |
1f2223b1 LB |
462 | |
463 | /* | |
464 | * Disable automatic update of address remaping when writing to BARs. | |
465 | */ | |
9dd0b194 | 466 | orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1); |
1f2223b1 LB |
467 | } |
468 | ||
a9984270 | 469 | static int __init pci_setup(struct pci_sys_data *sys) |
038ee083 TP |
470 | { |
471 | struct resource *res; | |
472 | ||
1f2223b1 LB |
473 | /* |
474 | * Point PCI unit MBUS decode windows to DRAM space. | |
475 | */ | |
9dd0b194 | 476 | orion5x_setup_pci_wins(&orion5x_mbus_dram_info); |
1f2223b1 | 477 | |
038ee083 TP |
478 | /* |
479 | * Master + Slave enable | |
480 | */ | |
9dd0b194 | 481 | orion5x_pci_master_slave_enable(); |
038ee083 TP |
482 | |
483 | /* | |
484 | * Force ordering | |
485 | */ | |
9dd0b194 | 486 | orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); |
038ee083 TP |
487 | |
488 | /* | |
489 | * Request resources | |
490 | */ | |
491 | res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); | |
492 | if (!res) | |
abc0197d | 493 | panic("pci_setup unable to alloc resources"); |
038ee083 TP |
494 | |
495 | /* | |
496 | * IORESOURCE_IO | |
497 | */ | |
498 | res[0].name = "PCI I/O Space"; | |
499 | res[0].flags = IORESOURCE_IO; | |
9dd0b194 LB |
500 | res[0].start = ORION5X_PCI_IO_BUS_BASE; |
501 | res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; | |
038ee083 TP |
502 | if (request_resource(&ioport_resource, &res[0])) |
503 | panic("Request PCI IO resource failed\n"); | |
504 | sys->resource[0] = &res[0]; | |
505 | ||
506 | /* | |
507 | * IORESOURCE_MEM | |
508 | */ | |
509 | res[1].name = "PCI Memory Space"; | |
510 | res[1].flags = IORESOURCE_MEM; | |
9dd0b194 LB |
511 | res[1].start = ORION5X_PCI_MEM_PHYS_BASE; |
512 | res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; | |
038ee083 TP |
513 | if (request_resource(&iomem_resource, &res[1])) |
514 | panic("Request PCI Memory resource failed\n"); | |
515 | sys->resource[1] = &res[1]; | |
516 | ||
517 | sys->resource[2] = NULL; | |
518 | sys->io_offset = 0; | |
519 | ||
520 | return 1; | |
521 | } | |
522 | ||
523 | ||
524 | /***************************************************************************** | |
159ffb3a | 525 | * General PCIe + PCI |
038ee083 | 526 | ****************************************************************************/ |
d50c60a8 LB |
527 | static void __devinit rc_pci_fixup(struct pci_dev *dev) |
528 | { | |
529 | /* | |
530 | * Prevent enumeration of root complex. | |
531 | */ | |
532 | if (dev->bus->parent == NULL && dev->devfn == 0) { | |
533 | int i; | |
534 | ||
535 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
536 | dev->resource[i].start = 0; | |
537 | dev->resource[i].end = 0; | |
538 | dev->resource[i].flags = 0; | |
539 | } | |
540 | } | |
541 | } | |
542 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); | |
543 | ||
7a6bb262 PA |
544 | static int orion5x_pci_disabled __initdata; |
545 | ||
546 | void __init orion5x_pci_disable(void) | |
547 | { | |
548 | orion5x_pci_disabled = 1; | |
549 | } | |
550 | ||
da01bba3 LB |
551 | void __init orion5x_pci_set_cardbus_mode(void) |
552 | { | |
553 | orion5x_pci_cardbus_mode = 1; | |
554 | } | |
555 | ||
9dd0b194 | 556 | int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) |
038ee083 TP |
557 | { |
558 | int ret = 0; | |
559 | ||
560 | if (nr == 0) { | |
abc0197d LB |
561 | orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); |
562 | ret = pcie_setup(sys); | |
7a6bb262 | 563 | } else if (nr == 1 && !orion5x_pci_disabled) { |
9dd0b194 | 564 | orion5x_pci_set_bus_nr(sys->busnr); |
abc0197d | 565 | ret = pci_setup(sys); |
038ee083 TP |
566 | } |
567 | ||
568 | return ret; | |
569 | } | |
570 | ||
9dd0b194 | 571 | struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) |
038ee083 | 572 | { |
038ee083 TP |
573 | struct pci_bus *bus; |
574 | ||
038ee083 | 575 | if (nr == 0) { |
abc0197d | 576 | bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); |
7a6bb262 | 577 | } else if (nr == 1 && !orion5x_pci_disabled) { |
abc0197d | 578 | bus = pci_scan_bus(sys->busnr, &pci_ops, sys); |
038ee083 | 579 | } else { |
038ee083 | 580 | bus = NULL; |
abc0197d | 581 | BUG(); |
038ee083 TP |
582 | } |
583 | ||
584 | return bus; | |
585 | } | |
92b913b0 LB |
586 | |
587 | int __init orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |
588 | { | |
589 | int bus = dev->bus->number; | |
590 | ||
591 | /* | |
592 | * PCIe endpoint? | |
593 | */ | |
7a6bb262 | 594 | if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr()) |
92b913b0 LB |
595 | return IRQ_ORION5X_PCIE0_INT; |
596 | ||
597 | return -1; | |
598 | } |