Commit | Line | Data |
---|---|---|
038ee083 | 1 | /* |
9dd0b194 | 2 | * arch/arm/mach-orion5x/pci.c |
038ee083 | 3 | * |
159ffb3a | 4 | * PCI and PCIe functions for Marvell Orion System On Chip |
038ee083 TP |
5 | * |
6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | |
7 | * | |
159ffb3a LB |
8 | * This file is licensed under the terms of the GNU General Public |
9 | * License version 2. This program is licensed "as is" without any | |
038ee083 TP |
10 | * warranty of any kind, whether express or implied. |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/pci.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
1f2223b1 | 16 | #include <linux/mbus.h> |
158c0c62 | 17 | #include <video/vga.h> |
ff89c462 | 18 | #include <asm/irq.h> |
038ee083 | 19 | #include <asm/mach/pci.h> |
6f088f1d | 20 | #include <plat/pcie.h> |
45173d5e | 21 | #include <plat/addr-map.h> |
038ee083 TP |
22 | #include "common.h" |
23 | ||
24 | /***************************************************************************** | |
159ffb3a | 25 | * Orion has one PCIe controller and one PCI controller. |
038ee083 | 26 | * |
159ffb3a LB |
27 | * Note1: The local PCIe bus number is '0'. The local PCI bus number |
28 | * follows the scanned PCIe bridged busses, if any. | |
038ee083 | 29 | * |
159ffb3a | 30 | * Note2: It is possible for PCI/PCIe agents to access many subsystem's |
038ee083 TP |
31 | * space, by configuring BARs and Address Decode Windows, e.g. flashes on |
32 | * device bus, Orion registers, etc. However this code only enable the | |
33 | * access to DDR banks. | |
34 | ****************************************************************************/ | |
35 | ||
36 | ||
37 | /***************************************************************************** | |
159ffb3a | 38 | * PCIe controller |
038ee083 | 39 | ****************************************************************************/ |
9dd0b194 | 40 | #define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE) |
038ee083 | 41 | |
9dd0b194 | 42 | void __init orion5x_pcie_id(u32 *dev, u32 *rev) |
038ee083 | 43 | { |
abc0197d LB |
44 | *dev = orion_pcie_dev_id(PCIE_BASE); |
45 | *rev = orion_pcie_rev(PCIE_BASE); | |
038ee083 TP |
46 | } |
47 | ||
abc0197d | 48 | static int pcie_valid_config(int bus, int dev) |
038ee083 TP |
49 | { |
50 | /* | |
51 | * Don't go out when trying to access -- | |
d50c60a8 | 52 | * 1. nonexisting device on local bus |
038ee083 | 53 | * 2. where there's no device connected (no link) |
038ee083 | 54 | */ |
d50c60a8 LB |
55 | if (bus == 0 && dev == 0) |
56 | return 1; | |
038ee083 | 57 | |
abc0197d | 58 | if (!orion_pcie_link_up(PCIE_BASE)) |
038ee083 TP |
59 | return 0; |
60 | ||
d50c60a8 LB |
61 | if (bus == 0 && dev != 1) |
62 | return 0; | |
63 | ||
038ee083 TP |
64 | return 1; |
65 | } | |
66 | ||
abc0197d LB |
67 | |
68 | /* | |
159ffb3a | 69 | * PCIe config cycles are done by programming the PCIE_CONF_ADDR register |
abc0197d LB |
70 | * and then reading the PCIE_CONF_DATA register. Need to make sure these |
71 | * transactions are atomic. | |
72 | */ | |
9dd0b194 | 73 | static DEFINE_SPINLOCK(orion5x_pcie_lock); |
abc0197d LB |
74 | |
75 | static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, | |
76 | int size, u32 *val) | |
038ee083 TP |
77 | { |
78 | unsigned long flags; | |
abc0197d | 79 | int ret; |
038ee083 | 80 | |
abc0197d | 81 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { |
038ee083 TP |
82 | *val = 0xffffffff; |
83 | return PCIBIOS_DEVICE_NOT_FOUND; | |
84 | } | |
85 | ||
9dd0b194 | 86 | spin_lock_irqsave(&orion5x_pcie_lock, flags); |
abc0197d | 87 | ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); |
9dd0b194 | 88 | spin_unlock_irqrestore(&orion5x_pcie_lock, flags); |
038ee083 | 89 | |
abc0197d LB |
90 | return ret; |
91 | } | |
038ee083 | 92 | |
abc0197d LB |
93 | static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, |
94 | int where, int size, u32 *val) | |
95 | { | |
96 | int ret; | |
038ee083 | 97 | |
abc0197d LB |
98 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { |
99 | *val = 0xffffffff; | |
100 | return PCIBIOS_DEVICE_NOT_FOUND; | |
101 | } | |
038ee083 | 102 | |
abc0197d LB |
103 | /* |
104 | * We only support access to the non-extended configuration | |
105 | * space when using the WA access method (or we would have to | |
106 | * sacrifice 256M of CPU virtual address space.) | |
107 | */ | |
108 | if (where >= 0x100) { | |
109 | *val = 0xffffffff; | |
110 | return PCIBIOS_DEVICE_NOT_FOUND; | |
111 | } | |
038ee083 | 112 | |
9dd0b194 | 113 | ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE, |
abc0197d | 114 | bus, devfn, where, size, val); |
038ee083 | 115 | |
abc0197d LB |
116 | return ret; |
117 | } | |
038ee083 | 118 | |
abc0197d LB |
119 | static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, |
120 | int where, int size, u32 val) | |
038ee083 TP |
121 | { |
122 | unsigned long flags; | |
123 | int ret; | |
124 | ||
abc0197d | 125 | if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) |
038ee083 TP |
126 | return PCIBIOS_DEVICE_NOT_FOUND; |
127 | ||
9dd0b194 | 128 | spin_lock_irqsave(&orion5x_pcie_lock, flags); |
abc0197d | 129 | ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); |
9dd0b194 | 130 | spin_unlock_irqrestore(&orion5x_pcie_lock, flags); |
038ee083 TP |
131 | |
132 | return ret; | |
133 | } | |
134 | ||
159ffb3a | 135 | static struct pci_ops pcie_ops = { |
abc0197d LB |
136 | .read = pcie_rd_conf, |
137 | .write = pcie_wr_conf, | |
038ee083 TP |
138 | }; |
139 | ||
140 | ||
a9984270 | 141 | static int __init pcie_setup(struct pci_sys_data *sys) |
038ee083 TP |
142 | { |
143 | struct resource *res; | |
abc0197d | 144 | int dev; |
038ee083 | 145 | |
1f2223b1 | 146 | /* |
abc0197d | 147 | * Generic PCIe unit setup. |
038ee083 | 148 | */ |
63a9332b | 149 | orion_pcie_setup(PCIE_BASE); |
038ee083 TP |
150 | |
151 | /* | |
abc0197d LB |
152 | * Check whether to apply Orion-1/Orion-NAS PCIe config |
153 | * read transaction workaround. | |
038ee083 | 154 | */ |
abc0197d LB |
155 | dev = orion_pcie_dev_id(PCIE_BASE); |
156 | if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { | |
157 | printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " | |
158 | "read transaction workaround\n"); | |
386a048a LB |
159 | orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, |
160 | ORION5X_PCIE_WA_SIZE); | |
abc0197d LB |
161 | pcie_ops.read = pcie_rd_conf_wa; |
162 | } | |
038ee083 TP |
163 | |
164 | /* | |
abc0197d | 165 | * Request resources. |
038ee083 TP |
166 | */ |
167 | res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); | |
168 | if (!res) | |
abc0197d | 169 | panic("pcie_setup unable to alloc resources"); |
038ee083 TP |
170 | |
171 | /* | |
172 | * IORESOURCE_IO | |
173 | */ | |
9f786d03 | 174 | sys->io_offset = 0; |
159ffb3a | 175 | res[0].name = "PCIe I/O Space"; |
038ee083 | 176 | res[0].flags = IORESOURCE_IO; |
9dd0b194 LB |
177 | res[0].start = ORION5X_PCIE_IO_BUS_BASE; |
178 | res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; | |
038ee083 | 179 | if (request_resource(&ioport_resource, &res[0])) |
159ffb3a | 180 | panic("Request PCIe IO resource failed\n"); |
9f786d03 | 181 | pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); |
038ee083 TP |
182 | |
183 | /* | |
184 | * IORESOURCE_MEM | |
185 | */ | |
159ffb3a | 186 | res[1].name = "PCIe Memory Space"; |
038ee083 | 187 | res[1].flags = IORESOURCE_MEM; |
9dd0b194 LB |
188 | res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; |
189 | res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; | |
038ee083 | 190 | if (request_resource(&iomem_resource, &res[1])) |
159ffb3a | 191 | panic("Request PCIe Memory resource failed\n"); |
9f786d03 | 192 | pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); |
038ee083 TP |
193 | |
194 | return 1; | |
195 | } | |
196 | ||
197 | /***************************************************************************** | |
198 | * PCI controller | |
199 | ****************************************************************************/ | |
fdd8b079 | 200 | #define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) |
9dd0b194 LB |
201 | #define PCI_MODE ORION5X_PCI_REG(0xd00) |
202 | #define PCI_CMD ORION5X_PCI_REG(0xc00) | |
203 | #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) | |
204 | #define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78) | |
205 | #define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c) | |
038ee083 TP |
206 | |
207 | /* | |
208 | * PCI_MODE bits | |
209 | */ | |
210 | #define PCI_MODE_64BIT (1 << 2) | |
211 | #define PCI_MODE_PCIX ((1 << 4) | (1 << 5)) | |
212 | ||
213 | /* | |
214 | * PCI_CMD bits | |
215 | */ | |
216 | #define PCI_CMD_HOST_REORDER (1 << 29) | |
217 | ||
218 | /* | |
219 | * PCI_P2P_CONF bits | |
220 | */ | |
221 | #define PCI_P2P_BUS_OFFS 16 | |
222 | #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS) | |
223 | #define PCI_P2P_DEV_OFFS 24 | |
224 | #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) | |
225 | ||
226 | /* | |
227 | * PCI_CONF_ADDR bits | |
228 | */ | |
229 | #define PCI_CONF_REG(reg) ((reg) & 0xfc) | |
230 | #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) | |
231 | #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) | |
232 | #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) | |
233 | #define PCI_CONF_ADDR_EN (1 << 31) | |
234 | ||
235 | /* | |
236 | * Internal configuration space | |
237 | */ | |
238 | #define PCI_CONF_FUNC_STAT_CMD 0 | |
239 | #define PCI_CONF_REG_STAT_CMD 4 | |
240 | #define PCIX_STAT 0x64 | |
241 | #define PCIX_STAT_BUS_OFFS 8 | |
242 | #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS) | |
243 | ||
1f2223b1 LB |
244 | /* |
245 | * PCI Address Decode Windows registers | |
246 | */ | |
9dd0b194 | 247 | #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ |
e7068ad3 LB |
248 | ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ |
249 | ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ | |
250 | ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) | |
251 | #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \ | |
252 | ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ | |
253 | ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ | |
254 | ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) | |
9dd0b194 LB |
255 | #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) |
256 | #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) | |
1f2223b1 LB |
257 | |
258 | /* | |
259 | * PCI configuration helpers for BAR settings | |
260 | */ | |
261 | #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1) | |
262 | #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10) | |
263 | #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14) | |
264 | ||
038ee083 TP |
265 | /* |
266 | * PCI config cycles are done by programming the PCI_CONF_ADDR register | |
267 | * and then reading the PCI_CONF_DATA register. Need to make sure these | |
268 | * transactions are atomic. | |
269 | */ | |
9dd0b194 | 270 | static DEFINE_SPINLOCK(orion5x_pci_lock); |
038ee083 | 271 | |
da01bba3 LB |
272 | static int orion5x_pci_cardbus_mode; |
273 | ||
92b913b0 | 274 | static int orion5x_pci_local_bus_nr(void) |
038ee083 | 275 | { |
79e90dd5 | 276 | u32 conf = readl(PCI_P2P_CONF); |
038ee083 TP |
277 | return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); |
278 | } | |
279 | ||
9dd0b194 | 280 | static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, |
038ee083 TP |
281 | u32 where, u32 size, u32 *val) |
282 | { | |
283 | unsigned long flags; | |
9dd0b194 | 284 | spin_lock_irqsave(&orion5x_pci_lock, flags); |
038ee083 | 285 | |
79e90dd5 LB |
286 | writel(PCI_CONF_BUS(bus) | |
287 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | | |
288 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); | |
038ee083 | 289 | |
79e90dd5 | 290 | *val = readl(PCI_CONF_DATA); |
038ee083 TP |
291 | |
292 | if (size == 1) | |
293 | *val = (*val >> (8*(where & 0x3))) & 0xff; | |
294 | else if (size == 2) | |
295 | *val = (*val >> (8*(where & 0x3))) & 0xffff; | |
296 | ||
9dd0b194 | 297 | spin_unlock_irqrestore(&orion5x_pci_lock, flags); |
038ee083 TP |
298 | |
299 | return PCIBIOS_SUCCESSFUL; | |
300 | } | |
301 | ||
9dd0b194 | 302 | static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, |
038ee083 TP |
303 | u32 where, u32 size, u32 val) |
304 | { | |
305 | unsigned long flags; | |
306 | int ret = PCIBIOS_SUCCESSFUL; | |
307 | ||
9dd0b194 | 308 | spin_lock_irqsave(&orion5x_pci_lock, flags); |
038ee083 | 309 | |
79e90dd5 LB |
310 | writel(PCI_CONF_BUS(bus) | |
311 | PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | | |
312 | PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); | |
038ee083 TP |
313 | |
314 | if (size == 4) { | |
315 | __raw_writel(val, PCI_CONF_DATA); | |
316 | } else if (size == 2) { | |
317 | __raw_writew(val, PCI_CONF_DATA + (where & 0x3)); | |
318 | } else if (size == 1) { | |
319 | __raw_writeb(val, PCI_CONF_DATA + (where & 0x3)); | |
320 | } else { | |
321 | ret = PCIBIOS_BAD_REGISTER_NUMBER; | |
322 | } | |
323 | ||
9dd0b194 | 324 | spin_unlock_irqrestore(&orion5x_pci_lock, flags); |
038ee083 TP |
325 | |
326 | return ret; | |
327 | } | |
328 | ||
da01bba3 LB |
329 | static int orion5x_pci_valid_config(int bus, u32 devfn) |
330 | { | |
331 | if (bus == orion5x_pci_local_bus_nr()) { | |
332 | /* | |
333 | * Don't go out for local device | |
334 | */ | |
335 | if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) | |
336 | return 0; | |
337 | ||
338 | /* | |
339 | * When the PCI signals are directly connected to a | |
340 | * Cardbus slot, ignore all but device IDs 0 and 1. | |
341 | */ | |
342 | if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1) | |
343 | return 0; | |
344 | } | |
345 | ||
346 | return 1; | |
347 | } | |
348 | ||
9dd0b194 | 349 | static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, |
038ee083 TP |
350 | int where, int size, u32 *val) |
351 | { | |
da01bba3 | 352 | if (!orion5x_pci_valid_config(bus->number, devfn)) { |
038ee083 TP |
353 | *val = 0xffffffff; |
354 | return PCIBIOS_DEVICE_NOT_FOUND; | |
355 | } | |
356 | ||
9dd0b194 | 357 | return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), |
038ee083 TP |
358 | PCI_FUNC(devfn), where, size, val); |
359 | } | |
360 | ||
9dd0b194 | 361 | static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, |
038ee083 TP |
362 | int where, int size, u32 val) |
363 | { | |
da01bba3 | 364 | if (!orion5x_pci_valid_config(bus->number, devfn)) |
038ee083 TP |
365 | return PCIBIOS_DEVICE_NOT_FOUND; |
366 | ||
9dd0b194 | 367 | return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), |
038ee083 TP |
368 | PCI_FUNC(devfn), where, size, val); |
369 | } | |
370 | ||
159ffb3a | 371 | static struct pci_ops pci_ops = { |
9dd0b194 LB |
372 | .read = orion5x_pci_rd_conf, |
373 | .write = orion5x_pci_wr_conf, | |
038ee083 TP |
374 | }; |
375 | ||
9dd0b194 | 376 | static void __init orion5x_pci_set_bus_nr(int nr) |
038ee083 | 377 | { |
79e90dd5 | 378 | u32 p2p = readl(PCI_P2P_CONF); |
038ee083 | 379 | |
79e90dd5 | 380 | if (readl(PCI_MODE) & PCI_MODE_PCIX) { |
038ee083 TP |
381 | /* |
382 | * PCI-X mode | |
383 | */ | |
384 | u32 pcix_status, bus, dev; | |
385 | bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; | |
386 | dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; | |
9dd0b194 | 387 | orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); |
038ee083 TP |
388 | pcix_status &= ~PCIX_STAT_BUS_MASK; |
389 | pcix_status |= (nr << PCIX_STAT_BUS_OFFS); | |
9dd0b194 | 390 | orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); |
038ee083 TP |
391 | } else { |
392 | /* | |
393 | * PCI Conventional mode | |
394 | */ | |
395 | p2p &= ~PCI_P2P_BUS_MASK; | |
396 | p2p |= (nr << PCI_P2P_BUS_OFFS); | |
79e90dd5 | 397 | writel(p2p, PCI_P2P_CONF); |
038ee083 TP |
398 | } |
399 | } | |
400 | ||
9dd0b194 | 401 | static void __init orion5x_pci_master_slave_enable(void) |
038ee083 | 402 | { |
d50c60a8 | 403 | int bus_nr, func, reg; |
abc0197d | 404 | u32 val; |
038ee083 | 405 | |
9dd0b194 | 406 | bus_nr = orion5x_pci_local_bus_nr(); |
038ee083 TP |
407 | func = PCI_CONF_FUNC_STAT_CMD; |
408 | reg = PCI_CONF_REG_STAT_CMD; | |
9dd0b194 | 409 | orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); |
038ee083 | 410 | val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
9dd0b194 | 411 | orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); |
038ee083 TP |
412 | } |
413 | ||
9dd0b194 | 414 | static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) |
1f2223b1 LB |
415 | { |
416 | u32 win_enable; | |
abc0197d | 417 | int bus; |
1f2223b1 LB |
418 | int i; |
419 | ||
420 | /* | |
421 | * First, disable windows. | |
422 | */ | |
423 | win_enable = 0xffffffff; | |
79e90dd5 | 424 | writel(win_enable, PCI_BAR_ENABLE); |
1f2223b1 LB |
425 | |
426 | /* | |
427 | * Setup windows for DDR banks. | |
428 | */ | |
9dd0b194 | 429 | bus = orion5x_pci_local_bus_nr(); |
1f2223b1 LB |
430 | |
431 | for (i = 0; i < dram->num_cs; i++) { | |
432 | struct mbus_dram_window *cs = dram->cs + i; | |
433 | u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); | |
434 | u32 reg; | |
435 | u32 val; | |
436 | ||
437 | /* | |
438 | * Write DRAM bank base address register. | |
439 | */ | |
440 | reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); | |
9dd0b194 | 441 | orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); |
1f2223b1 | 442 | val = (cs->base & 0xfffff000) | (val & 0xfff); |
9dd0b194 | 443 | orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); |
1f2223b1 LB |
444 | |
445 | /* | |
446 | * Write DRAM bank size register. | |
447 | */ | |
448 | reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); | |
9dd0b194 | 449 | orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); |
79e90dd5 LB |
450 | writel((cs->size - 1) & 0xfffff000, |
451 | PCI_BAR_SIZE_DDR_CS(cs->cs_index)); | |
452 | writel(cs->base & 0xfffff000, | |
453 | PCI_BAR_REMAP_DDR_CS(cs->cs_index)); | |
1f2223b1 LB |
454 | |
455 | /* | |
456 | * Enable decode window for this chip select. | |
457 | */ | |
458 | win_enable &= ~(1 << cs->cs_index); | |
459 | } | |
460 | ||
461 | /* | |
462 | * Re-enable decode windows. | |
463 | */ | |
79e90dd5 | 464 | writel(win_enable, PCI_BAR_ENABLE); |
1f2223b1 LB |
465 | |
466 | /* | |
af901ca1 | 467 | * Disable automatic update of address remapping when writing to BARs. |
1f2223b1 | 468 | */ |
9dd0b194 | 469 | orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1); |
1f2223b1 LB |
470 | } |
471 | ||
a9984270 | 472 | static int __init pci_setup(struct pci_sys_data *sys) |
038ee083 TP |
473 | { |
474 | struct resource *res; | |
475 | ||
1f2223b1 LB |
476 | /* |
477 | * Point PCI unit MBUS decode windows to DRAM space. | |
478 | */ | |
45173d5e | 479 | orion5x_setup_pci_wins(&orion_mbus_dram_info); |
1f2223b1 | 480 | |
038ee083 TP |
481 | /* |
482 | * Master + Slave enable | |
483 | */ | |
9dd0b194 | 484 | orion5x_pci_master_slave_enable(); |
038ee083 TP |
485 | |
486 | /* | |
487 | * Force ordering | |
488 | */ | |
9dd0b194 | 489 | orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); |
038ee083 TP |
490 | |
491 | /* | |
492 | * Request resources | |
493 | */ | |
494 | res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); | |
495 | if (!res) | |
abc0197d | 496 | panic("pci_setup unable to alloc resources"); |
038ee083 TP |
497 | |
498 | /* | |
499 | * IORESOURCE_IO | |
500 | */ | |
9f786d03 | 501 | sys->io_offset = 0; |
038ee083 TP |
502 | res[0].name = "PCI I/O Space"; |
503 | res[0].flags = IORESOURCE_IO; | |
9dd0b194 LB |
504 | res[0].start = ORION5X_PCI_IO_BUS_BASE; |
505 | res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; | |
038ee083 TP |
506 | if (request_resource(&ioport_resource, &res[0])) |
507 | panic("Request PCI IO resource failed\n"); | |
9f786d03 | 508 | pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); |
038ee083 TP |
509 | |
510 | /* | |
511 | * IORESOURCE_MEM | |
512 | */ | |
513 | res[1].name = "PCI Memory Space"; | |
514 | res[1].flags = IORESOURCE_MEM; | |
9dd0b194 LB |
515 | res[1].start = ORION5X_PCI_MEM_PHYS_BASE; |
516 | res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; | |
038ee083 TP |
517 | if (request_resource(&iomem_resource, &res[1])) |
518 | panic("Request PCI Memory resource failed\n"); | |
9f786d03 | 519 | pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); |
038ee083 TP |
520 | |
521 | return 1; | |
522 | } | |
523 | ||
524 | ||
525 | /***************************************************************************** | |
159ffb3a | 526 | * General PCIe + PCI |
038ee083 | 527 | ****************************************************************************/ |
d50c60a8 LB |
528 | static void __devinit rc_pci_fixup(struct pci_dev *dev) |
529 | { | |
530 | /* | |
531 | * Prevent enumeration of root complex. | |
532 | */ | |
533 | if (dev->bus->parent == NULL && dev->devfn == 0) { | |
534 | int i; | |
535 | ||
536 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
537 | dev->resource[i].start = 0; | |
538 | dev->resource[i].end = 0; | |
539 | dev->resource[i].flags = 0; | |
540 | } | |
541 | } | |
542 | } | |
543 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); | |
544 | ||
7a6bb262 PA |
545 | static int orion5x_pci_disabled __initdata; |
546 | ||
547 | void __init orion5x_pci_disable(void) | |
548 | { | |
549 | orion5x_pci_disabled = 1; | |
550 | } | |
551 | ||
da01bba3 LB |
552 | void __init orion5x_pci_set_cardbus_mode(void) |
553 | { | |
554 | orion5x_pci_cardbus_mode = 1; | |
555 | } | |
556 | ||
9dd0b194 | 557 | int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) |
038ee083 TP |
558 | { |
559 | int ret = 0; | |
560 | ||
cc22b4c1 RH |
561 | vga_base = ORION5X_PCIE_MEM_PHYS_BASE; |
562 | ||
038ee083 | 563 | if (nr == 0) { |
abc0197d LB |
564 | orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr); |
565 | ret = pcie_setup(sys); | |
7a6bb262 | 566 | } else if (nr == 1 && !orion5x_pci_disabled) { |
9dd0b194 | 567 | orion5x_pci_set_bus_nr(sys->busnr); |
abc0197d | 568 | ret = pci_setup(sys); |
038ee083 TP |
569 | } |
570 | ||
571 | return ret; | |
572 | } | |
573 | ||
9dd0b194 | 574 | struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys) |
038ee083 | 575 | { |
038ee083 TP |
576 | struct pci_bus *bus; |
577 | ||
038ee083 | 578 | if (nr == 0) { |
37d15909 BH |
579 | bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, |
580 | &sys->resources); | |
7a6bb262 | 581 | } else if (nr == 1 && !orion5x_pci_disabled) { |
37d15909 BH |
582 | bus = pci_scan_root_bus(NULL, sys->busnr, &pci_ops, sys, |
583 | &sys->resources); | |
038ee083 | 584 | } else { |
038ee083 | 585 | bus = NULL; |
abc0197d | 586 | BUG(); |
038ee083 TP |
587 | } |
588 | ||
589 | return bus; | |
590 | } | |
92b913b0 | 591 | |
d5341942 | 592 | int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
92b913b0 LB |
593 | { |
594 | int bus = dev->bus->number; | |
595 | ||
596 | /* | |
597 | * PCIe endpoint? | |
598 | */ | |
7a6bb262 | 599 | if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr()) |
92b913b0 LB |
600 | return IRQ_ORION5X_PCIE0_INT; |
601 | ||
602 | return -1; | |
603 | } |