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4898de3d BS |
1 | /* |
2 | * plat smp support for CSR Marco dual-core SMP SoCs | |
3 | * | |
4 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. | |
5 | * | |
6 | * Licensed under GPLv2 or later. | |
7 | */ | |
8 | ||
9 | #include <linux/init.h> | |
10 | #include <linux/smp.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/of.h> | |
13 | #include <linux/of_address.h> | |
14 | #include <asm/page.h> | |
15 | #include <asm/mach/map.h> | |
16 | #include <asm/smp_plat.h> | |
17 | #include <asm/smp_scu.h> | |
18 | #include <asm/cacheflush.h> | |
19 | #include <asm/cputype.h> | |
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20 | |
21 | #include "common.h" | |
22 | ||
23 | static void __iomem *scu_base; | |
24 | static void __iomem *rsc_base; | |
25 | ||
26 | static DEFINE_SPINLOCK(boot_lock); | |
27 | ||
28 | static struct map_desc scu_io_desc __initdata = { | |
29 | .length = SZ_4K, | |
30 | .type = MT_DEVICE, | |
31 | }; | |
32 | ||
33 | void __init sirfsoc_map_scu(void) | |
34 | { | |
35 | unsigned long base; | |
36 | ||
37 | /* Get SCU base */ | |
38 | asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base)); | |
39 | ||
40 | scu_io_desc.virtual = SIRFSOC_VA(base); | |
41 | scu_io_desc.pfn = __phys_to_pfn(base); | |
42 | iotable_init(&scu_io_desc, 1); | |
43 | ||
44 | scu_base = (void __iomem *)SIRFSOC_VA(base); | |
45 | } | |
46 | ||
8bd26e3a | 47 | static void sirfsoc_secondary_init(unsigned int cpu) |
4898de3d | 48 | { |
4898de3d BS |
49 | /* |
50 | * let the primary processor know we're out of the | |
51 | * pen, then head off into the C entry point | |
52 | */ | |
53 | pen_release = -1; | |
54 | smp_wmb(); | |
55 | ||
56 | /* | |
57 | * Synchronise with the boot thread. | |
58 | */ | |
59 | spin_lock(&boot_lock); | |
60 | spin_unlock(&boot_lock); | |
61 | } | |
62 | ||
63 | static struct of_device_id rsc_ids[] = { | |
64 | { .compatible = "sirf,marco-rsc" }, | |
65 | {}, | |
66 | }; | |
67 | ||
8bd26e3a | 68 | static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle) |
4898de3d BS |
69 | { |
70 | unsigned long timeout; | |
71 | struct device_node *np; | |
72 | ||
73 | np = of_find_matching_node(NULL, rsc_ids); | |
74 | if (!np) | |
75 | return -ENODEV; | |
76 | ||
77 | rsc_base = of_iomap(np, 0); | |
78 | if (!rsc_base) | |
79 | return -ENOMEM; | |
80 | ||
81 | /* | |
82 | * write the address of secondary startup into the sram register | |
83 | * at offset 0x2C, then write the magic number 0x3CAF5D62 to the | |
84 | * RSC register at offset 0x28, which is what boot rom code is | |
85 | * waiting for. This would wake up the secondary core from WFE | |
86 | */ | |
87 | #define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2C | |
88 | __raw_writel(virt_to_phys(sirfsoc_secondary_startup), | |
89 | rsc_base + SIRFSOC_CPU1_JUMPADDR_OFFSET); | |
90 | ||
91 | #define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x28 | |
92 | __raw_writel(0x3CAF5D62, | |
93 | rsc_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET); | |
94 | ||
95 | /* make sure write buffer is drained */ | |
96 | mb(); | |
97 | ||
98 | spin_lock(&boot_lock); | |
99 | ||
100 | /* | |
101 | * The secondary processor is waiting to be released from | |
102 | * the holding pen - release it, then wait for it to flag | |
103 | * that it has been released by resetting pen_release. | |
104 | * | |
105 | * Note that "pen_release" is the hardware CPU ID, whereas | |
106 | * "cpu" is Linux's internal ID. | |
107 | */ | |
108 | pen_release = cpu_logical_map(cpu); | |
109 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); | |
110 | outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); | |
111 | ||
112 | /* | |
113 | * Send the secondary CPU SEV, thereby causing the boot monitor to read | |
114 | * the JUMPADDR and WAKEMAGIC, and branch to the address found there. | |
115 | */ | |
116 | dsb_sev(); | |
117 | ||
118 | timeout = jiffies + (1 * HZ); | |
119 | while (time_before(jiffies, timeout)) { | |
120 | smp_rmb(); | |
121 | if (pen_release == -1) | |
122 | break; | |
123 | ||
124 | udelay(10); | |
125 | } | |
126 | ||
127 | /* | |
128 | * now the secondary core is starting up let it run its | |
129 | * calibrations, then wait for it to finish | |
130 | */ | |
131 | spin_unlock(&boot_lock); | |
132 | ||
133 | return pen_release != -1 ? -ENOSYS : 0; | |
134 | } | |
135 | ||
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136 | static void __init sirfsoc_smp_prepare_cpus(unsigned int max_cpus) |
137 | { | |
138 | scu_enable(scu_base); | |
139 | } | |
140 | ||
141 | struct smp_operations sirfsoc_smp_ops __initdata = { | |
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142 | .smp_prepare_cpus = sirfsoc_smp_prepare_cpus, |
143 | .smp_secondary_init = sirfsoc_secondary_init, | |
144 | .smp_boot_secondary = sirfsoc_boot_secondary, | |
145 | #ifdef CONFIG_HOTPLUG_CPU | |
146 | .cpu_die = sirfsoc_cpu_die, | |
147 | #endif | |
148 | }; |