[deliverable/linux.git] / arch / arm / mach-pxa / generic.c

/*
 *  linux/arch/arm/mach-pxa/generic.c
 *
 *  Author:	Nicolas Pitre
 *  Created:	Jun 15, 2001
 *  Copyright:	MontaVista Software Inc.
 *
 * Code common to all PXA machines.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Since this file should be linked before any other machine specific file,
 * the __initcall() here will be executed first.  This serves as default
 * initialization stuff for PXA machines which can be overridden later if
 * need be.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/ioport.h>
#include <linux/pm.h>
#include <linux/string.h>

#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>

#include <asm/arch/pxa-regs.h>
#include <asm/arch/gpio.h>
#include <asm/arch/udc.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/mmc.h>
#include <asm/arch/irda.h>
#include <asm/arch/i2c.h>

#include "devices.h"
#include "generic.h"

/*
 * Get the clock frequency as reflected by CCCR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int get_clk_frequency_khz(int info)
{
	if (cpu_is_pxa21x() || cpu_is_pxa25x())
		return pxa25x_get_clk_frequency_khz(info);
	else if (cpu_is_pxa27x())
		return pxa27x_get_clk_frequency_khz(info);
	else
		return pxa3xx_get_clk_frequency_khz(info);
}
EXPORT_SYMBOL(get_clk_frequency_khz);

/*
 * Return the current memory clock frequency in units of 10kHz
 */
unsigned int get_memclk_frequency_10khz(void)
{
	if (cpu_is_pxa21x() || cpu_is_pxa25x())
		return pxa25x_get_memclk_frequency_10khz();
	else if (cpu_is_pxa27x())
		return pxa27x_get_memclk_frequency_10khz();
	else
		return pxa3xx_get_memclk_frequency_10khz();
}
EXPORT_SYMBOL(get_memclk_frequency_10khz);

/*
 * Handy function to set GPIO alternate functions
 */
int pxa_last_gpio;

int pxa_gpio_mode(int gpio_mode)
{
	unsigned long flags;
	int gpio = gpio_mode & GPIO_MD_MASK_NR;
	int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
	int gafr;

	if (gpio > pxa_last_gpio)
		return -EINVAL;

	local_irq_save(flags);
	if (gpio_mode & GPIO_DFLT_LOW)
		GPCR(gpio) = GPIO_bit(gpio);
	else if (gpio_mode & GPIO_DFLT_HIGH)
		GPSR(gpio) = GPIO_bit(gpio);
	if (gpio_mode & GPIO_MD_MASK_DIR)
		GPDR(gpio) |= GPIO_bit(gpio);
	else
		GPDR(gpio) &= ~GPIO_bit(gpio);
	gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
	GAFR(gpio) = gafr |  (fn  << (((gpio) & 0xf)*2));
	local_irq_restore(flags);

	return 0;
}

EXPORT_SYMBOL(pxa_gpio_mode);

int gpio_direction_input(unsigned gpio)
{
	unsigned long flags;
	u32 mask;

	if (gpio > pxa_last_gpio)
		return -EINVAL;

	mask = GPIO_bit(gpio);
	local_irq_save(flags);
	GPDR(gpio) &= ~mask;
	local_irq_restore(flags);

	return 0;
}
EXPORT_SYMBOL(gpio_direction_input);

int gpio_direction_output(unsigned gpio, int value)
{
	unsigned long flags;
	u32 mask;

	if (gpio > pxa_last_gpio)
		return -EINVAL;

	mask = GPIO_bit(gpio);
	local_irq_save(flags);
	if (value)
		GPSR(gpio) = mask;
	else
		GPCR(gpio) = mask;
	GPDR(gpio) |= mask;
	local_irq_restore(flags);

	return 0;
}
EXPORT_SYMBOL(gpio_direction_output);

/*
 * Return GPIO level
 */
int pxa_gpio_get_value(unsigned gpio)
{
	return __gpio_get_value(gpio);
}

EXPORT_SYMBOL(pxa_gpio_get_value);

/*
 * Set output GPIO level
 */
void pxa_gpio_set_value(unsigned gpio, int value)
{
	__gpio_set_value(gpio, value);
}

EXPORT_SYMBOL(pxa_gpio_set_value);

/*
 * Routine to safely enable or disable a clock in the CKEN
 */
void __pxa_set_cken(int clock, int enable)
{
	unsigned long flags;
	local_irq_save(flags);

	if (enable)
		CKEN |= (1 << clock);
	else
		CKEN &= ~(1 << clock);

	local_irq_restore(flags);
}

EXPORT_SYMBOL(__pxa_set_cken);

/*
 * Intel PXA2xx internal register mapping.
 *
 * Note 1: not all PXA2xx variants implement all those addresses.
 *
 * Note 2: virtual 0xfffe0000-0xffffffff is reserved for the vector table
 *         and cache flush area.
 */
static struct map_desc standard_io_desc[] __initdata = {
  	{	/* Devs */
		.virtual	=  0xf2000000,
		.pfn		= __phys_to_pfn(0x40000000),
		.length		= 0x02000000,
		.type		= MT_DEVICE
	}, {	/* LCD */
		.virtual	=  0xf4000000,
		.pfn		= __phys_to_pfn(0x44000000),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}, {	/* Mem Ctl */
		.virtual	=  0xf6000000,
		.pfn		= __phys_to_pfn(0x48000000),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}, {	/* USB host */
		.virtual	=  0xf8000000,
		.pfn		= __phys_to_pfn(0x4c000000),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}, {	/* Camera */
		.virtual	=  0xfa000000,
		.pfn		= __phys_to_pfn(0x50000000),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}, {	/* IMem ctl */
		.virtual	=  0xfe000000,
		.pfn		= __phys_to_pfn(0x58000000),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}, {	/* UNCACHED_PHYS_0 */
		.virtual	= 0xff000000,
		.pfn		= __phys_to_pfn(0x00000000),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}
};

void __init pxa_map_io(void)
{
	iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
	get_clk_frequency_khz(1);
}


void __init pxa_register_device(struct platform_device *dev, void *data)
{
	int ret;

	dev->dev.platform_data = data;

	ret = platform_device_register(dev);
	if (ret)
		dev_err(&dev->dev, "unable to register device: %d\n", ret);
}


static struct resource pxamci_resources[] = {
	[0] = {
		.start	= 0x41100000,
		.end	= 0x41100fff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_MMC,
		.end	= IRQ_MMC,
		.flags	= IORESOURCE_IRQ,
	},
};

static u64 pxamci_dmamask = 0xffffffffUL;

struct platform_device pxa_device_mci = {
	.name		= "pxa2xx-mci",
	.id		= -1,
	.dev		= {
		.dma_mask = &pxamci_dmamask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(pxamci_resources),
	.resource	= pxamci_resources,
};

void __init pxa_set_mci_info(struct pxamci_platform_data *info)
{
	pxa_register_device(&pxa_device_mci, info);
}


static struct pxa2xx_udc_mach_info pxa_udc_info;

void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
{
	memcpy(&pxa_udc_info, info, sizeof *info);
}

static struct resource pxa2xx_udc_resources[] = {
	[0] = {
		.start	= 0x40600000,
		.end	= 0x4060ffff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_USB,
		.end	= IRQ_USB,
		.flags	= IORESOURCE_IRQ,
	},
};

static u64 udc_dma_mask = ~(u32)0;

struct platform_device pxa_device_udc = {
	.name		= "pxa2xx-udc",
	.id		= -1,
	.resource	= pxa2xx_udc_resources,
	.num_resources	= ARRAY_SIZE(pxa2xx_udc_resources),
	.dev		=  {
		.platform_data	= &pxa_udc_info,
		.dma_mask	= &udc_dma_mask,
	}
};

static struct resource pxafb_resources[] = {
	[0] = {
		.start	= 0x44000000,
		.end	= 0x4400ffff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_LCD,
		.end	= IRQ_LCD,
		.flags	= IORESOURCE_IRQ,
	},
};

static u64 fb_dma_mask = ~(u64)0;

struct platform_device pxa_device_fb = {
	.name		= "pxa2xx-fb",
	.id		= -1,
	.dev		= {
		.dma_mask	= &fb_dma_mask,
		.coherent_dma_mask = 0xffffffff,
	},
	.num_resources	= ARRAY_SIZE(pxafb_resources),
	.resource	= pxafb_resources,
};

void __init set_pxa_fb_info(struct pxafb_mach_info *info)
{
	pxa_register_device(&pxa_device_fb, info);
}

void __init set_pxa_fb_parent(struct device *parent_dev)
{
	pxa_device_fb.dev.parent = parent_dev;
}

static struct resource pxa_resource_ffuart[] = {
	{
		.start	= __PREG(FFUART),
		.end	= __PREG(FFUART) + 35,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_FFUART,
		.end	= IRQ_FFUART,
		.flags	= IORESOURCE_IRQ,
	}
};

struct platform_device pxa_device_ffuart= {
	.name		= "pxa2xx-uart",
	.id		= 0,
	.resource	= pxa_resource_ffuart,
	.num_resources	= ARRAY_SIZE(pxa_resource_ffuart),
};

static struct resource pxa_resource_btuart[] = {
	{
		.start	= __PREG(BTUART),
		.end	= __PREG(BTUART) + 35,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_BTUART,
		.end	= IRQ_BTUART,
		.flags	= IORESOURCE_IRQ,
	}
};

struct platform_device pxa_device_btuart = {
	.name		= "pxa2xx-uart",
	.id		= 1,
	.resource	= pxa_resource_btuart,
	.num_resources	= ARRAY_SIZE(pxa_resource_btuart),
};

static struct resource pxa_resource_stuart[] = {
	{
		.start	= __PREG(STUART),
		.end	= __PREG(STUART) + 35,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_STUART,
		.end	= IRQ_STUART,
		.flags	= IORESOURCE_IRQ,
	}
};

struct platform_device pxa_device_stuart = {
	.name		= "pxa2xx-uart",
	.id		= 2,
	.resource	= pxa_resource_stuart,
	.num_resources	= ARRAY_SIZE(pxa_resource_stuart),
};

static struct resource pxa_resource_hwuart[] = {
	{
		.start	= __PREG(HWUART),
		.end	= __PREG(HWUART) + 47,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_HWUART,
		.end	= IRQ_HWUART,
		.flags	= IORESOURCE_IRQ,
	}
};

struct platform_device pxa_device_hwuart = {
	.name		= "pxa2xx-uart",
	.id		= 3,
	.resource	= pxa_resource_hwuart,
	.num_resources	= ARRAY_SIZE(pxa_resource_hwuart),
};

static struct resource pxai2c_resources[] = {
	{
		.start	= 0x40301680,
		.end	= 0x403016a3,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_I2C,
		.end	= IRQ_I2C,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device pxa_device_i2c = {
	.name		= "pxa2xx-i2c",
	.id		= 0,
	.resource	= pxai2c_resources,
	.num_resources	= ARRAY_SIZE(pxai2c_resources),
};

void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
{
	pxa_register_device(&pxa_device_i2c, info);
}

static struct resource pxai2s_resources[] = {
	{
		.start	= 0x40400000,
		.end	= 0x40400083,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_I2S,
		.end	= IRQ_I2S,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device pxa_device_i2s = {
	.name		= "pxa2xx-i2s",
	.id		= -1,
	.resource	= pxai2s_resources,
	.num_resources	= ARRAY_SIZE(pxai2s_resources),
};

static u64 pxaficp_dmamask = ~(u32)0;

struct platform_device pxa_device_ficp = {
	.name		= "pxa2xx-ir",
	.id		= -1,
	.dev		= {
		.dma_mask = &pxaficp_dmamask,
		.coherent_dma_mask = 0xffffffff,
	},
};

void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
{
	pxa_register_device(&pxa_device_ficp, info);
}

struct platform_device pxa_device_rtc = {
	.name		= "sa1100-rtc",
	.id		= -1,
};
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-pxa/generic.c
	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Jun 15, 2001
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* Code common to all PXA machines.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	* Since this file should be linked before any other machine specific file,
	15	* the __initcall() here will be executed first. This serves as default
	16	* initialization stuff for PXA machines which can be overridden later if
	17	* need be.
	18	*/
	19	#include <linux/module.h>
	20	#include <linux/kernel.h>
	21	#include <linux/init.h>
	22	#include <linux/delay.h>
d052d1be	23	#include <linux/platform_device.h>
1da177e4 LT	24	#include <linux/ioport.h>
1da177e4 LT	25	#include <linux/pm.h>
4e57b681	26	#include <linux/string.h>
1da177e4 LT	27
	28	#include <asm/hardware.h>
	29	#include <asm/irq.h>
	30	#include <asm/system.h>
	31	#include <asm/pgtable.h>
	32	#include <asm/mach/map.h>
	33
	34	#include <asm/arch/pxa-regs.h>
3deac046	35	#include <asm/arch/gpio.h>
1da177e4 LT	36	#include <asm/arch/udc.h>
	37	#include <asm/arch/pxafb.h>
	38	#include <asm/arch/mmc.h>
6f475c01	39	#include <asm/arch/irda.h>
eb9181a2	40	#include <asm/arch/i2c.h>
1da177e4	41
46c41e62	42	#include "devices.h"
1da177e4 LT	43	#include "generic.h"
1da177e4 LT	44
15a40333 RK	45	/*
	46	* Get the clock frequency as reflected by CCCR and the turbo flag.
	47	* We assume these values have been applied via a fcs.
	48	* If info is not 0 we also display the current settings.
	49	*/
	50	unsigned int get_clk_frequency_khz(int info)
	51	{
	52	if (cpu_is_pxa21x() \|\| cpu_is_pxa25x())
	53	return pxa25x_get_clk_frequency_khz(info);
2c8086a5	54	else if (cpu_is_pxa27x())
15a40333	55	return pxa27x_get_clk_frequency_khz(info);
2c8086a5	56	else
2c8086a5	57	return pxa3xx_get_clk_frequency_khz(info);
15a40333 RK	58	}
	59	EXPORT_SYMBOL(get_clk_frequency_khz);
	60
	61	/*
	62	* Return the current memory clock frequency in units of 10kHz
	63	*/
	64	unsigned int get_memclk_frequency_10khz(void)
	65	{
	66	if (cpu_is_pxa21x() \|\| cpu_is_pxa25x())
	67	return pxa25x_get_memclk_frequency_10khz();
2c8086a5	68	else if (cpu_is_pxa27x())
15a40333	69	return pxa27x_get_memclk_frequency_10khz();
2c8086a5	70	else
2c8086a5	71	return pxa3xx_get_memclk_frequency_10khz();
15a40333 RK	72	}
	73	EXPORT_SYMBOL(get_memclk_frequency_10khz);
	74
1da177e4 LT	75	/*
	76	* Handy function to set GPIO alternate functions
	77	*/
30f0b408	78	int pxa_last_gpio;
1da177e4	79
3deac046	80	int pxa_gpio_mode(int gpio_mode)
1da177e4 LT	81	{
	82	unsigned long flags;
	83	int gpio = gpio_mode & GPIO_MD_MASK_NR;
	84	int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
	85	int gafr;
	86
30f0b408	87	if (gpio > pxa_last_gpio)
3deac046 PZ	88	return -EINVAL;
3deac046 PZ	89
1da177e4 LT	90	local_irq_save(flags);
	91	if (gpio_mode & GPIO_DFLT_LOW)
	92	GPCR(gpio) = GPIO_bit(gpio);
	93	else if (gpio_mode & GPIO_DFLT_HIGH)
	94	GPSR(gpio) = GPIO_bit(gpio);
	95	if (gpio_mode & GPIO_MD_MASK_DIR)
	96	GPDR(gpio) \|= GPIO_bit(gpio);
	97	else
	98	GPDR(gpio) &= ~GPIO_bit(gpio);
	99	gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
	100	GAFR(gpio) = gafr \| (fn << (((gpio) & 0xf)*2));
	101	local_irq_restore(flags);
3deac046 PZ	102
3deac046 PZ	103	return 0;
1da177e4 LT	104	}
	105
	106	EXPORT_SYMBOL(pxa_gpio_mode);
	107
3e0cc7ee RK	108	int gpio_direction_input(unsigned gpio)
	109	{
	110	unsigned long flags;
	111	u32 mask;
	112
	113	if (gpio > pxa_last_gpio)
	114	return -EINVAL;
	115
	116	mask = GPIO_bit(gpio);
	117	local_irq_save(flags);
	118	GPDR(gpio) &= ~mask;
	119	local_irq_restore(flags);
	120
	121	return 0;
	122	}
	123	EXPORT_SYMBOL(gpio_direction_input);
	124
	125	int gpio_direction_output(unsigned gpio, int value)
	126	{
	127	unsigned long flags;
	128	u32 mask;
	129
	130	if (gpio > pxa_last_gpio)
	131	return -EINVAL;
	132
	133	mask = GPIO_bit(gpio);
	134	local_irq_save(flags);
	135	if (value)
	136	GPSR(gpio) = mask;
	137	else
	138	GPCR(gpio) = mask;
	139	GPDR(gpio) \|= mask;
	140	local_irq_restore(flags);
	141
	142	return 0;
	143	}
	144	EXPORT_SYMBOL(gpio_direction_output);
	145
3deac046 PZ	146	/*
	147	* Return GPIO level
	148	*/
	149	int pxa_gpio_get_value(unsigned gpio)
	150	{
	151	return __gpio_get_value(gpio);
	152	}
	153
	154	EXPORT_SYMBOL(pxa_gpio_get_value);
	155
	156	/*
	157	* Set output GPIO level
	158	*/
	159	void pxa_gpio_set_value(unsigned gpio, int value)
	160	{
	161	__gpio_set_value(gpio, value);
	162	}
	163
	164	EXPORT_SYMBOL(pxa_gpio_set_value);
	165
1da177e4 LT	166	/*
	167	* Routine to safely enable or disable a clock in the CKEN
	168	*/
a7073b8b	169	void __pxa_set_cken(int clock, int enable)
1da177e4 LT	170	{
	171	unsigned long flags;
	172	local_irq_save(flags);
	173
	174	if (enable)
7053acbd	175	CKEN \|= (1 << clock);
1da177e4	176	else
7053acbd	177	CKEN &= ~(1 << clock);
1da177e4 LT	178
	179	local_irq_restore(flags);
	180	}
	181
a7073b8b	182	EXPORT_SYMBOL(__pxa_set_cken);
1da177e4 LT	183
	184	/*
	185	* Intel PXA2xx internal register mapping.
	186	*
	187	* Note 1: not all PXA2xx variants implement all those addresses.
	188	*
	189	* Note 2: virtual 0xfffe0000-0xffffffff is reserved for the vector table
	190	* and cache flush area.
	191	*/
	192	static struct map_desc standard_io_desc[] __initdata = {
6f9182eb DS	193	{ /* Devs */
	194	.virtual = 0xf2000000,
	195	.pfn = __phys_to_pfn(0x40000000),
	196	.length = 0x02000000,
	197	.type = MT_DEVICE
	198	}, { /* LCD */
	199	.virtual = 0xf4000000,
	200	.pfn = __phys_to_pfn(0x44000000),
	201	.length = 0x00100000,
	202	.type = MT_DEVICE
	203	}, { /* Mem Ctl */
	204	.virtual = 0xf6000000,
	205	.pfn = __phys_to_pfn(0x48000000),
	206	.length = 0x00100000,
	207	.type = MT_DEVICE
	208	}, { /* USB host */
	209	.virtual = 0xf8000000,
	210	.pfn = __phys_to_pfn(0x4c000000),
	211	.length = 0x00100000,
	212	.type = MT_DEVICE
	213	}, { /* Camera */
	214	.virtual = 0xfa000000,
	215	.pfn = __phys_to_pfn(0x50000000),
	216	.length = 0x00100000,
	217	.type = MT_DEVICE
	218	}, { /* IMem ctl */
	219	.virtual = 0xfe000000,
	220	.pfn = __phys_to_pfn(0x58000000),
	221	.length = 0x00100000,
	222	.type = MT_DEVICE
	223	}, { /* UNCACHED_PHYS_0 */
	224	.virtual = 0xff000000,
	225	.pfn = __phys_to_pfn(0x00000000),
	226	.length = 0x00100000,
	227	.type = MT_DEVICE
	228	}
1da177e4 LT	229	};
	230
	231	void __init pxa_map_io(void)
	232	{
	233	iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
	234	get_clk_frequency_khz(1);
	235	}
	236
	237
03f5b2ce RK	238	void __init pxa_register_device(struct platform_device dev, void data)
	239	{
	240	int ret;
	241
	242	dev->dev.platform_data = data;
	243
	244	ret = platform_device_register(dev);
	245	if (ret)
	246	dev_err(&dev->dev, "unable to register device: %d\n", ret);
	247	}
	248
	249
1da177e4 LT	250	static struct resource pxamci_resources[] = {
	251	[0] = {
	252	.start = 0x41100000,
	253	.end = 0x41100fff,
	254	.flags = IORESOURCE_MEM,
	255	},
	256	[1] = {
	257	.start = IRQ_MMC,
	258	.end = IRQ_MMC,
	259	.flags = IORESOURCE_IRQ,
	260	},
	261	};
	262
	263	static u64 pxamci_dmamask = 0xffffffffUL;
	264
e09d02e1	265	struct platform_device pxa_device_mci = {
1da177e4 LT	266	.name = "pxa2xx-mci",
	267	.id = -1,
	268	.dev = {
	269	.dma_mask = &pxamci_dmamask,
	270	.coherent_dma_mask = 0xffffffff,
	271	},
	272	.num_resources = ARRAY_SIZE(pxamci_resources),
	273	.resource = pxamci_resources,
	274	};
	275
	276	void __init pxa_set_mci_info(struct pxamci_platform_data *info)
	277	{
03f5b2ce	278	pxa_register_device(&pxa_device_mci, info);
1da177e4 LT	279	}
	280
	281
	282	static struct pxa2xx_udc_mach_info pxa_udc_info;
	283
	284	void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
	285	{
	286	memcpy(&pxa_udc_info, info, sizeof *info);
	287	}
	288
	289	static struct resource pxa2xx_udc_resources[] = {
	290	[0] = {
	291	.start = 0x40600000,
	292	.end = 0x4060ffff,
	293	.flags = IORESOURCE_MEM,
	294	},
	295	[1] = {
	296	.start = IRQ_USB,
	297	.end = IRQ_USB,
	298	.flags = IORESOURCE_IRQ,
	299	},
	300	};
	301
	302	static u64 udc_dma_mask = ~(u32)0;
	303
e09d02e1	304	struct platform_device pxa_device_udc = {
1da177e4 LT	305	.name = "pxa2xx-udc",
	306	.id = -1,
	307	.resource = pxa2xx_udc_resources,
	308	.num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
	309	.dev = {
	310	.platform_data = &pxa_udc_info,
	311	.dma_mask = &udc_dma_mask,
	312	}
	313	};
	314
1da177e4 LT	315	static struct resource pxafb_resources[] = {
	316	[0] = {
	317	.start = 0x44000000,
	318	.end = 0x4400ffff,
	319	.flags = IORESOURCE_MEM,
	320	},
	321	[1] = {
	322	.start = IRQ_LCD,
	323	.end = IRQ_LCD,
	324	.flags = IORESOURCE_IRQ,
	325	},
	326	};
	327
	328	static u64 fb_dma_mask = ~(u64)0;
	329
e09d02e1	330	struct platform_device pxa_device_fb = {
1da177e4 LT	331	.name = "pxa2xx-fb",
	332	.id = -1,
	333	.dev = {
1da177e4 LT	334	.dma_mask = &fb_dma_mask,
	335	.coherent_dma_mask = 0xffffffff,
	336	},
	337	.num_resources = ARRAY_SIZE(pxafb_resources),
	338	.resource = pxafb_resources,
	339	};
	340
d14b272b RP	341	void __init set_pxa_fb_info(struct pxafb_mach_info *info)
d14b272b RP	342	{
03f5b2ce	343	pxa_register_device(&pxa_device_fb, info);
d14b272b RP	344	}
d14b272b RP	345
cb38c569 RP	346	void __init set_pxa_fb_parent(struct device *parent_dev)
cb38c569 RP	347	{
e09d02e1	348	pxa_device_fb.dev.parent = parent_dev;
cb38c569 RP	349	}
cb38c569 RP	350
e259a3ae RK	351	static struct resource pxa_resource_ffuart[] = {
	352	{
	353	.start = __PREG(FFUART),
	354	.end = __PREG(FFUART) + 35,
	355	.flags = IORESOURCE_MEM,
	356	}, {
	357	.start = IRQ_FFUART,
	358	.end = IRQ_FFUART,
	359	.flags = IORESOURCE_IRQ,
	360	}
	361	};
	362
e09d02e1	363	struct platform_device pxa_device_ffuart= {
1da177e4 LT	364	.name = "pxa2xx-uart",
1da177e4 LT	365	.id = 0,
e259a3ae RK	366	.resource = pxa_resource_ffuart,
	367	.num_resources = ARRAY_SIZE(pxa_resource_ffuart),
	368	};
	369
	370	static struct resource pxa_resource_btuart[] = {
	371	{
	372	.start = __PREG(BTUART),
	373	.end = __PREG(BTUART) + 35,
	374	.flags = IORESOURCE_MEM,
	375	}, {
	376	.start = IRQ_BTUART,
	377	.end = IRQ_BTUART,
	378	.flags = IORESOURCE_IRQ,
	379	}
1da177e4	380	};
e259a3ae	381
e09d02e1	382	struct platform_device pxa_device_btuart = {
1da177e4 LT	383	.name = "pxa2xx-uart",
1da177e4 LT	384	.id = 1,
e259a3ae RK	385	.resource = pxa_resource_btuart,
e259a3ae RK	386	.num_resources = ARRAY_SIZE(pxa_resource_btuart),
1da177e4	387	};
e259a3ae RK	388
	389	static struct resource pxa_resource_stuart[] = {
	390	{
	391	.start = __PREG(STUART),
	392	.end = __PREG(STUART) + 35,
	393	.flags = IORESOURCE_MEM,
	394	}, {
	395	.start = IRQ_STUART,
	396	.end = IRQ_STUART,
	397	.flags = IORESOURCE_IRQ,
	398	}
	399	};
	400
e09d02e1	401	struct platform_device pxa_device_stuart = {
1da177e4 LT	402	.name = "pxa2xx-uart",
1da177e4 LT	403	.id = 2,
e259a3ae RK	404	.resource = pxa_resource_stuart,
e259a3ae RK	405	.num_resources = ARRAY_SIZE(pxa_resource_stuart),
1da177e4	406	};
e259a3ae RK	407
	408	static struct resource pxa_resource_hwuart[] = {
	409	{
	410	.start = __PREG(HWUART),
	411	.end = __PREG(HWUART) + 47,
	412	.flags = IORESOURCE_MEM,
	413	}, {
	414	.start = IRQ_HWUART,
	415	.end = IRQ_HWUART,
	416	.flags = IORESOURCE_IRQ,
	417	}
	418	};
	419
e09d02e1	420	struct platform_device pxa_device_hwuart = {
d9e29649 MR	421	.name = "pxa2xx-uart",
d9e29649 MR	422	.id = 3,
e259a3ae RK	423	.resource = pxa_resource_hwuart,
e259a3ae RK	424	.num_resources = ARRAY_SIZE(pxa_resource_hwuart),
d9e29649	425	};
1da177e4	426
34f3231f	427	static struct resource pxai2c_resources[] = {
bb9bffcb RK	428	{
	429	.start = 0x40301680,
	430	.end = 0x403016a3,
	431	.flags = IORESOURCE_MEM,
	432	}, {
	433	.start = IRQ_I2C,
	434	.end = IRQ_I2C,
	435	.flags = IORESOURCE_IRQ,
	436	},
	437	};
	438
e09d02e1	439	struct platform_device pxa_device_i2c = {
bb9bffcb RK	440	.name = "pxa2xx-i2c",
bb9bffcb RK	441	.id = 0,
34f3231f RK	442	.resource = pxai2c_resources,
34f3231f RK	443	.num_resources = ARRAY_SIZE(pxai2c_resources),
bb9bffcb RK	444	};
	445
	446	void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
	447	{
03f5b2ce	448	pxa_register_device(&pxa_device_i2c, info);
bb9bffcb RK	449	}
bb9bffcb RK	450
34f3231f	451	static struct resource pxai2s_resources[] = {
b2640b42 MR	452	{
	453	.start = 0x40400000,
	454	.end = 0x40400083,
	455	.flags = IORESOURCE_MEM,
	456	}, {
	457	.start = IRQ_I2S,
	458	.end = IRQ_I2S,
	459	.flags = IORESOURCE_IRQ,
	460	},
	461	};
	462
e09d02e1	463	struct platform_device pxa_device_i2s = {
b2640b42 MR	464	.name = "pxa2xx-i2s",
b2640b42 MR	465	.id = -1,
34f3231f RK	466	.resource = pxai2s_resources,
34f3231f RK	467	.num_resources = ARRAY_SIZE(pxai2s_resources),
b2640b42 MR	468	};
b2640b42 MR	469
6f475c01 NP	470	static u64 pxaficp_dmamask = ~(u32)0;
6f475c01 NP	471
e09d02e1	472	struct platform_device pxa_device_ficp = {
6f475c01 NP	473	.name = "pxa2xx-ir",
	474	.id = -1,
	475	.dev = {
	476	.dma_mask = &pxaficp_dmamask,
	477	.coherent_dma_mask = 0xffffffff,
	478	},
	479	};
	480
	481	void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
	482	{
03f5b2ce	483	pxa_register_device(&pxa_device_ficp, info);
6f475c01 NP	484	}
6f475c01 NP	485
e09d02e1	486	struct platform_device pxa_device_rtc = {
e842f1c8 RP	487	.name = "sa1100-rtc",
	488	.id = -1,
	489	};