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1c44f5f1 PZ |
1 | /* |
2 | * linux/arch/arm/mach-pxa/gpio.c | |
3 | * | |
4 | * Generic PXA GPIO handling | |
5 | * | |
6 | * Author: Nicolas Pitre | |
7 | * Created: Jun 15, 2001 | |
8 | * Copyright: MontaVista Software Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/init.h> | |
16 | #include <linux/module.h> | |
e3630db1 | 17 | #include <linux/irq.h> |
1c44f5f1 PZ |
18 | |
19 | #include <asm/gpio.h> | |
20 | #include <asm/hardware.h> | |
21 | #include <asm/io.h> | |
22 | #include <asm/arch/pxa-regs.h> | |
23 | ||
24 | #include "generic.h" | |
25 | ||
26 | ||
27 | struct pxa_gpio_chip { | |
28 | struct gpio_chip chip; | |
29 | void __iomem *regbase; | |
30 | }; | |
31 | ||
32 | int pxa_last_gpio; | |
33 | ||
34 | /* | |
35 | * Configure pins for GPIO or other functions | |
36 | */ | |
37 | int pxa_gpio_mode(int gpio_mode) | |
38 | { | |
39 | unsigned long flags; | |
40 | int gpio = gpio_mode & GPIO_MD_MASK_NR; | |
41 | int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8; | |
42 | int gafr; | |
43 | ||
44 | if (gpio > pxa_last_gpio) | |
45 | return -EINVAL; | |
46 | ||
47 | local_irq_save(flags); | |
48 | if (gpio_mode & GPIO_DFLT_LOW) | |
49 | GPCR(gpio) = GPIO_bit(gpio); | |
50 | else if (gpio_mode & GPIO_DFLT_HIGH) | |
51 | GPSR(gpio) = GPIO_bit(gpio); | |
52 | if (gpio_mode & GPIO_MD_MASK_DIR) | |
53 | GPDR(gpio) |= GPIO_bit(gpio); | |
54 | else | |
55 | GPDR(gpio) &= ~GPIO_bit(gpio); | |
56 | gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2)); | |
57 | GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2)); | |
58 | local_irq_restore(flags); | |
59 | ||
60 | return 0; | |
61 | } | |
62 | EXPORT_SYMBOL(pxa_gpio_mode); | |
63 | ||
64 | static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
65 | { | |
66 | unsigned long flags; | |
67 | u32 mask = 1 << offset; | |
68 | u32 value; | |
69 | struct pxa_gpio_chip *pxa; | |
70 | void __iomem *gpdr; | |
71 | ||
72 | pxa = container_of(chip, struct pxa_gpio_chip, chip); | |
73 | gpdr = pxa->regbase + GPDR_OFFSET; | |
74 | local_irq_save(flags); | |
75 | value = __raw_readl(gpdr); | |
76 | value &= ~mask; | |
77 | __raw_writel(value, gpdr); | |
78 | local_irq_restore(flags); | |
79 | ||
80 | return 0; | |
81 | } | |
82 | ||
83 | static int pxa_gpio_direction_output(struct gpio_chip *chip, | |
84 | unsigned offset, int value) | |
85 | { | |
86 | unsigned long flags; | |
87 | u32 mask = 1 << offset; | |
88 | u32 tmp; | |
89 | struct pxa_gpio_chip *pxa; | |
90 | void __iomem *gpdr; | |
91 | ||
92 | pxa = container_of(chip, struct pxa_gpio_chip, chip); | |
93 | __raw_writel(mask, | |
94 | pxa->regbase + (value ? GPSR_OFFSET : GPCR_OFFSET)); | |
95 | gpdr = pxa->regbase + GPDR_OFFSET; | |
96 | local_irq_save(flags); | |
97 | tmp = __raw_readl(gpdr); | |
98 | tmp |= mask; | |
99 | __raw_writel(tmp, gpdr); | |
100 | local_irq_restore(flags); | |
101 | ||
102 | return 0; | |
103 | } | |
104 | ||
105 | /* | |
106 | * Return GPIO level | |
107 | */ | |
108 | static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) | |
109 | { | |
110 | u32 mask = 1 << offset; | |
111 | struct pxa_gpio_chip *pxa; | |
112 | ||
113 | pxa = container_of(chip, struct pxa_gpio_chip, chip); | |
114 | return __raw_readl(pxa->regbase + GPLR_OFFSET) & mask; | |
115 | } | |
116 | ||
117 | /* | |
118 | * Set output GPIO level | |
119 | */ | |
120 | static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
121 | { | |
122 | u32 mask = 1 << offset; | |
123 | struct pxa_gpio_chip *pxa; | |
124 | ||
125 | pxa = container_of(chip, struct pxa_gpio_chip, chip); | |
126 | ||
127 | if (value) | |
128 | __raw_writel(mask, pxa->regbase + GPSR_OFFSET); | |
129 | else | |
130 | __raw_writel(mask, pxa->regbase + GPCR_OFFSET); | |
131 | } | |
132 | ||
0e037bbb | 133 | #define GPIO_CHIP(_n) \ |
134 | [_n] = { \ | |
135 | .regbase = GPIO##_n##_BASE, \ | |
136 | .chip = { \ | |
137 | .label = "gpio-" #_n, \ | |
138 | .direction_input = pxa_gpio_direction_input, \ | |
139 | .direction_output = pxa_gpio_direction_output, \ | |
140 | .get = pxa_gpio_get, \ | |
141 | .set = pxa_gpio_set, \ | |
142 | .base = (_n) * 32, \ | |
143 | .ngpio = 32, \ | |
144 | }, \ | |
145 | } | |
146 | ||
1c44f5f1 | 147 | static struct pxa_gpio_chip pxa_gpio_chip[] = { |
0e037bbb | 148 | GPIO_CHIP(0), |
149 | GPIO_CHIP(1), | |
150 | GPIO_CHIP(2), | |
1c44f5f1 | 151 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) |
0e037bbb | 152 | GPIO_CHIP(3), |
1c44f5f1 PZ |
153 | #endif |
154 | }; | |
155 | ||
e3630db1 | 156 | /* |
157 | * PXA GPIO edge detection for IRQs: | |
158 | * IRQs are generated on Falling-Edge, Rising-Edge, or both. | |
159 | * Use this instead of directly setting GRER/GFER. | |
160 | */ | |
161 | ||
162 | static long GPIO_IRQ_rising_edge[4]; | |
163 | static long GPIO_IRQ_falling_edge[4]; | |
164 | static long GPIO_IRQ_mask[4]; | |
165 | ||
166 | static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) | |
167 | { | |
168 | int gpio, idx; | |
169 | ||
170 | gpio = IRQ_TO_GPIO(irq); | |
171 | idx = gpio >> 5; | |
172 | ||
173 | if (type == IRQ_TYPE_PROBE) { | |
174 | /* Don't mess with enabled GPIOs using preconfigured edges or | |
175 | * GPIOs set to alternate function or to output during probe | |
176 | */ | |
177 | if ((GPIO_IRQ_rising_edge[idx] | | |
178 | GPIO_IRQ_falling_edge[idx] | | |
179 | GPDR(gpio)) & GPIO_bit(gpio)) | |
180 | return 0; | |
181 | if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2))) | |
182 | return 0; | |
183 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | |
184 | } | |
185 | ||
186 | pxa_gpio_mode(gpio | GPIO_IN); | |
187 | ||
188 | if (type & IRQ_TYPE_EDGE_RISING) | |
189 | __set_bit(gpio, GPIO_IRQ_rising_edge); | |
190 | else | |
191 | __clear_bit(gpio, GPIO_IRQ_rising_edge); | |
192 | ||
193 | if (type & IRQ_TYPE_EDGE_FALLING) | |
194 | __set_bit(gpio, GPIO_IRQ_falling_edge); | |
195 | else | |
196 | __clear_bit(gpio, GPIO_IRQ_falling_edge); | |
197 | ||
198 | GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; | |
199 | GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; | |
200 | ||
201 | pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio, | |
202 | ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), | |
203 | ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); | |
204 | return 0; | |
205 | } | |
206 | ||
207 | /* | |
208 | * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1. | |
209 | */ | |
210 | ||
211 | static void pxa_ack_low_gpio(unsigned int irq) | |
212 | { | |
213 | GEDR0 = (1 << (irq - IRQ_GPIO0)); | |
214 | } | |
215 | ||
216 | static void pxa_mask_low_gpio(unsigned int irq) | |
217 | { | |
218 | ICMR &= ~(1 << (irq - PXA_IRQ(0))); | |
219 | } | |
220 | ||
221 | static void pxa_unmask_low_gpio(unsigned int irq) | |
222 | { | |
223 | ICMR |= 1 << (irq - PXA_IRQ(0)); | |
224 | } | |
225 | ||
226 | static struct irq_chip pxa_low_gpio_chip = { | |
227 | .name = "GPIO-l", | |
228 | .ack = pxa_ack_low_gpio, | |
229 | .mask = pxa_mask_low_gpio, | |
230 | .unmask = pxa_unmask_low_gpio, | |
231 | .set_type = pxa_gpio_irq_type, | |
232 | }; | |
233 | ||
234 | /* | |
235 | * Demux handler for GPIO>=2 edge detect interrupts | |
236 | */ | |
237 | ||
238 | #define GEDR_BITS (sizeof(gedr) * BITS_PER_BYTE) | |
239 | ||
240 | static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) | |
241 | { | |
242 | int loop, bit, n; | |
243 | unsigned long gedr[4]; | |
244 | ||
245 | do { | |
246 | gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3; | |
247 | gedr[1] = GEDR1 & GPIO_IRQ_mask[1]; | |
248 | gedr[2] = GEDR2 & GPIO_IRQ_mask[2]; | |
249 | gedr[3] = GEDR3 & GPIO_IRQ_mask[3]; | |
250 | ||
251 | GEDR0 = gedr[0]; GEDR1 = gedr[1]; | |
252 | GEDR2 = gedr[2]; GEDR3 = gedr[3]; | |
253 | ||
254 | loop = 0; | |
255 | bit = find_first_bit(gedr, GEDR_BITS); | |
256 | while (bit < GEDR_BITS) { | |
257 | loop = 1; | |
258 | ||
259 | n = PXA_GPIO_IRQ_BASE + bit; | |
260 | desc_handle_irq(n, irq_desc + n); | |
261 | ||
262 | bit = find_next_bit(gedr, GEDR_BITS, bit + 1); | |
263 | } | |
264 | } while (loop); | |
265 | } | |
266 | ||
267 | static void pxa_ack_muxed_gpio(unsigned int irq) | |
268 | { | |
269 | int gpio = irq - IRQ_GPIO(2) + 2; | |
270 | GEDR(gpio) = GPIO_bit(gpio); | |
271 | } | |
272 | ||
273 | static void pxa_mask_muxed_gpio(unsigned int irq) | |
274 | { | |
275 | int gpio = irq - IRQ_GPIO(2) + 2; | |
276 | __clear_bit(gpio, GPIO_IRQ_mask); | |
277 | GRER(gpio) &= ~GPIO_bit(gpio); | |
278 | GFER(gpio) &= ~GPIO_bit(gpio); | |
279 | } | |
280 | ||
281 | static void pxa_unmask_muxed_gpio(unsigned int irq) | |
282 | { | |
283 | int gpio = irq - IRQ_GPIO(2) + 2; | |
284 | int idx = gpio >> 5; | |
285 | __set_bit(gpio, GPIO_IRQ_mask); | |
286 | GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; | |
287 | GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; | |
288 | } | |
289 | ||
290 | static struct irq_chip pxa_muxed_gpio_chip = { | |
291 | .name = "GPIO", | |
292 | .ack = pxa_ack_muxed_gpio, | |
293 | .mask = pxa_mask_muxed_gpio, | |
294 | .unmask = pxa_unmask_muxed_gpio, | |
295 | .set_type = pxa_gpio_irq_type, | |
296 | }; | |
297 | ||
b9e25ace | 298 | void __init pxa_init_gpio(int gpio_nr, set_wake_t fn) |
e3630db1 | 299 | { |
b9e25ace | 300 | int irq, i, gpio; |
e3630db1 | 301 | |
302 | pxa_last_gpio = gpio_nr - 1; | |
303 | ||
304 | /* clear all GPIO edge detects */ | |
305 | for (i = 0; i < gpio_nr; i += 32) { | |
306 | GFER(i) = 0; | |
307 | GRER(i) = 0; | |
308 | GEDR(i) = GEDR(i); | |
309 | } | |
310 | ||
311 | /* GPIO 0 and 1 must have their mask bit always set */ | |
312 | GPIO_IRQ_mask[0] = 3; | |
313 | ||
314 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { | |
315 | set_irq_chip(irq, &pxa_low_gpio_chip); | |
316 | set_irq_handler(irq, handle_edge_irq); | |
317 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
318 | } | |
319 | ||
320 | for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) { | |
321 | set_irq_chip(irq, &pxa_muxed_gpio_chip); | |
322 | set_irq_handler(irq, handle_edge_irq); | |
323 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
324 | } | |
325 | ||
326 | /* Install handler for GPIO>=2 edge detect interrupts */ | |
327 | set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); | |
328 | ||
b9e25ace | 329 | pxa_low_gpio_chip.set_wake = fn; |
330 | pxa_muxed_gpio_chip.set_wake = fn; | |
e3630db1 | 331 | |
b9e25ace | 332 | /* add a GPIO chip for each register bank. |
333 | * the last PXA25x register only contains 21 GPIOs | |
334 | */ | |
335 | for (gpio = 0, i = 0; gpio < gpio_nr; gpio += 32, i++) { | |
336 | if (gpio + 32 > gpio_nr) | |
337 | pxa_gpio_chip[i].chip.ngpio = gpio_nr - gpio; | |
338 | gpiochip_add(&pxa_gpio_chip[i].chip); | |
339 | } | |
e3630db1 | 340 | } |