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1c44f5f1 PZ |
1 | /* |
2 | * linux/arch/arm/mach-pxa/gpio.c | |
3 | * | |
4 | * Generic PXA GPIO handling | |
5 | * | |
6 | * Author: Nicolas Pitre | |
7 | * Created: Jun 15, 2001 | |
8 | * Copyright: MontaVista Software Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/init.h> | |
e3630db1 | 16 | #include <linux/irq.h> |
fced80c7 | 17 | #include <linux/io.h> |
0807da59 EM |
18 | #include <linux/sysdev.h> |
19 | #include <linux/bootmem.h> | |
1c44f5f1 | 20 | |
da065a0b | 21 | #include <mach/gpio.h> |
1c44f5f1 | 22 | |
3b8e285c EM |
23 | int pxa_last_gpio; |
24 | ||
0807da59 EM |
25 | /* |
26 | * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with | |
27 | * one set of registers. The register offsets are organized below: | |
28 | * | |
29 | * GPLR GPDR GPSR GPCR GRER GFER GEDR | |
30 | * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 | |
31 | * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C | |
32 | * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 | |
33 | * | |
34 | * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 | |
35 | * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C | |
36 | * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 | |
37 | * | |
38 | * NOTE: | |
39 | * BANK 3 is only available on PXA27x and later processors. | |
40 | * BANK 4 and 5 are only available on PXA935 | |
41 | */ | |
42 | ||
43 | #define GPIO_BANK(n) (GPIO_REGS_VIRT + BANK_OFF(n)) | |
f1647e4c EM |
44 | |
45 | #define GPLR_OFFSET 0x00 | |
46 | #define GPDR_OFFSET 0x0C | |
47 | #define GPSR_OFFSET 0x18 | |
48 | #define GPCR_OFFSET 0x24 | |
49 | #define GRER_OFFSET 0x30 | |
50 | #define GFER_OFFSET 0x3C | |
51 | #define GEDR_OFFSET 0x48 | |
1c44f5f1 PZ |
52 | |
53 | struct pxa_gpio_chip { | |
54 | struct gpio_chip chip; | |
0807da59 EM |
55 | void __iomem *regbase; |
56 | char label[10]; | |
57 | ||
58 | unsigned long irq_mask; | |
59 | unsigned long irq_edge_rise; | |
60 | unsigned long irq_edge_fall; | |
61 | ||
62 | #ifdef CONFIG_PM | |
63 | unsigned long saved_gplr; | |
64 | unsigned long saved_gpdr; | |
65 | unsigned long saved_grer; | |
66 | unsigned long saved_gfer; | |
67 | #endif | |
1c44f5f1 PZ |
68 | }; |
69 | ||
0807da59 EM |
70 | static DEFINE_SPINLOCK(gpio_lock); |
71 | static struct pxa_gpio_chip *pxa_gpio_chips; | |
72 | ||
73 | #define for_each_gpio_chip(i, c) \ | |
74 | for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++) | |
75 | ||
76 | static inline void __iomem *gpio_chip_base(struct gpio_chip *c) | |
77 | { | |
78 | return container_of(c, struct pxa_gpio_chip, chip)->regbase; | |
79 | } | |
80 | ||
81 | static inline struct pxa_gpio_chip *gpio_to_chip(unsigned gpio) | |
82 | { | |
83 | return &pxa_gpio_chips[gpio_to_bank(gpio)]; | |
84 | } | |
85 | ||
1c44f5f1 PZ |
86 | static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
87 | { | |
0807da59 EM |
88 | void __iomem *base = gpio_chip_base(chip); |
89 | uint32_t value, mask = 1 << offset; | |
90 | unsigned long flags; | |
91 | ||
92 | spin_lock_irqsave(&gpio_lock, flags); | |
93 | ||
94 | value = __raw_readl(base + GPDR_OFFSET); | |
067455aa EM |
95 | if (__gpio_is_inverted(chip->base + offset)) |
96 | value |= mask; | |
97 | else | |
98 | value &= ~mask; | |
0807da59 | 99 | __raw_writel(value, base + GPDR_OFFSET); |
1c44f5f1 | 100 | |
0807da59 | 101 | spin_unlock_irqrestore(&gpio_lock, flags); |
1c44f5f1 PZ |
102 | return 0; |
103 | } | |
104 | ||
105 | static int pxa_gpio_direction_output(struct gpio_chip *chip, | |
0807da59 | 106 | unsigned offset, int value) |
1c44f5f1 | 107 | { |
0807da59 EM |
108 | void __iomem *base = gpio_chip_base(chip); |
109 | uint32_t tmp, mask = 1 << offset; | |
110 | unsigned long flags; | |
111 | ||
112 | __raw_writel(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); | |
113 | ||
114 | spin_lock_irqsave(&gpio_lock, flags); | |
115 | ||
116 | tmp = __raw_readl(base + GPDR_OFFSET); | |
067455aa EM |
117 | if (__gpio_is_inverted(chip->base + offset)) |
118 | tmp &= ~mask; | |
119 | else | |
120 | tmp |= mask; | |
0807da59 | 121 | __raw_writel(tmp, base + GPDR_OFFSET); |
1c44f5f1 | 122 | |
0807da59 | 123 | spin_unlock_irqrestore(&gpio_lock, flags); |
1c44f5f1 PZ |
124 | return 0; |
125 | } | |
126 | ||
1c44f5f1 PZ |
127 | static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) |
128 | { | |
0807da59 | 129 | return __raw_readl(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset); |
1c44f5f1 PZ |
130 | } |
131 | ||
1c44f5f1 PZ |
132 | static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
133 | { | |
0807da59 EM |
134 | __raw_writel(1 << offset, gpio_chip_base(chip) + |
135 | (value ? GPSR_OFFSET : GPCR_OFFSET)); | |
1c44f5f1 PZ |
136 | } |
137 | ||
0807da59 | 138 | static int __init pxa_init_gpio_chip(int gpio_end) |
a58fbcd8 | 139 | { |
0807da59 EM |
140 | int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1; |
141 | struct pxa_gpio_chip *chips; | |
a58fbcd8 | 142 | |
0807da59 EM |
143 | /* this is early, we have to use bootmem allocator, and we really |
144 | * want this to be allocated dynamically for different 'gpio_end' | |
a58fbcd8 | 145 | */ |
0807da59 EM |
146 | chips = alloc_bootmem_low(nbanks * sizeof(struct pxa_gpio_chip)); |
147 | if (chips == NULL) { | |
148 | pr_err("%s: failed to allocate GPIO chips\n", __func__); | |
149 | return -ENOMEM; | |
a58fbcd8 | 150 | } |
a58fbcd8 | 151 | |
0807da59 EM |
152 | for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) { |
153 | struct gpio_chip *c = &chips[i].chip; | |
e3630db1 | 154 | |
0807da59 EM |
155 | sprintf(chips[i].label, "gpio-%d", i); |
156 | chips[i].regbase = (void __iomem *)GPIO_BANK(i); | |
157 | ||
158 | c->base = gpio; | |
159 | c->label = chips[i].label; | |
160 | ||
161 | c->direction_input = pxa_gpio_direction_input; | |
162 | c->direction_output = pxa_gpio_direction_output; | |
163 | c->get = pxa_gpio_get; | |
164 | c->set = pxa_gpio_set; | |
165 | ||
166 | /* number of GPIOs on last bank may be less than 32 */ | |
167 | c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32; | |
168 | gpiochip_add(c); | |
169 | } | |
170 | pxa_gpio_chips = chips; | |
171 | return 0; | |
172 | } | |
e3630db1 | 173 | |
174 | static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) | |
175 | { | |
0807da59 EM |
176 | struct pxa_gpio_chip *c; |
177 | int gpio = irq_to_gpio(irq); | |
178 | unsigned long gpdr, mask = GPIO_bit(gpio); | |
e3630db1 | 179 | |
0807da59 | 180 | c = gpio_to_chip(gpio); |
e3630db1 | 181 | |
182 | if (type == IRQ_TYPE_PROBE) { | |
183 | /* Don't mess with enabled GPIOs using preconfigured edges or | |
184 | * GPIOs set to alternate function or to output during probe | |
185 | */ | |
0807da59 | 186 | if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio)) |
e3630db1 | 187 | return 0; |
689c04a3 | 188 | |
189 | if (__gpio_is_occupied(gpio)) | |
e3630db1 | 190 | return 0; |
689c04a3 | 191 | |
e3630db1 | 192 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
193 | } | |
194 | ||
0807da59 EM |
195 | gpdr = __raw_readl(c->regbase + GPDR_OFFSET); |
196 | ||
067455aa | 197 | if (__gpio_is_inverted(gpio)) |
0807da59 | 198 | __raw_writel(gpdr | mask, c->regbase + GPDR_OFFSET); |
067455aa | 199 | else |
0807da59 | 200 | __raw_writel(gpdr & ~mask, c->regbase + GPDR_OFFSET); |
e3630db1 | 201 | |
202 | if (type & IRQ_TYPE_EDGE_RISING) | |
0807da59 | 203 | c->irq_edge_rise |= mask; |
e3630db1 | 204 | else |
0807da59 | 205 | c->irq_edge_rise &= ~mask; |
e3630db1 | 206 | |
207 | if (type & IRQ_TYPE_EDGE_FALLING) | |
0807da59 | 208 | c->irq_edge_fall |= mask; |
e3630db1 | 209 | else |
0807da59 | 210 | c->irq_edge_fall &= ~mask; |
e3630db1 | 211 | |
0807da59 EM |
212 | __raw_writel(c->irq_edge_rise & c->irq_mask, c->regbase + GRER_OFFSET); |
213 | __raw_writel(c->irq_edge_fall & c->irq_mask, c->regbase + GFER_OFFSET); | |
e3630db1 | 214 | |
215 | pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio, | |
216 | ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), | |
217 | ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); | |
218 | return 0; | |
219 | } | |
220 | ||
e3630db1 | 221 | static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) |
222 | { | |
0807da59 EM |
223 | struct pxa_gpio_chip *c; |
224 | int loop, gpio, gpio_base, n; | |
225 | unsigned long gedr; | |
e3630db1 | 226 | |
227 | do { | |
e3630db1 | 228 | loop = 0; |
0807da59 EM |
229 | for_each_gpio_chip(gpio, c) { |
230 | gpio_base = c->chip.base; | |
231 | ||
232 | gedr = __raw_readl(c->regbase + GEDR_OFFSET); | |
233 | gedr = gedr & c->irq_mask; | |
234 | __raw_writel(gedr, c->regbase + GEDR_OFFSET); | |
e3630db1 | 235 | |
0807da59 EM |
236 | n = find_first_bit(&gedr, BITS_PER_LONG); |
237 | while (n < BITS_PER_LONG) { | |
238 | loop = 1; | |
e3630db1 | 239 | |
0807da59 EM |
240 | generic_handle_irq(gpio_to_irq(gpio_base + n)); |
241 | n = find_next_bit(&gedr, BITS_PER_LONG, n + 1); | |
242 | } | |
e3630db1 | 243 | } |
244 | } while (loop); | |
245 | } | |
246 | ||
247 | static void pxa_ack_muxed_gpio(unsigned int irq) | |
248 | { | |
0807da59 EM |
249 | int gpio = irq_to_gpio(irq); |
250 | struct pxa_gpio_chip *c = gpio_to_chip(gpio); | |
251 | ||
252 | __raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET); | |
e3630db1 | 253 | } |
254 | ||
255 | static void pxa_mask_muxed_gpio(unsigned int irq) | |
256 | { | |
0807da59 EM |
257 | int gpio = irq_to_gpio(irq); |
258 | struct pxa_gpio_chip *c = gpio_to_chip(gpio); | |
259 | uint32_t grer, gfer; | |
260 | ||
261 | c->irq_mask &= ~GPIO_bit(gpio); | |
262 | ||
263 | grer = __raw_readl(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio); | |
264 | gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio); | |
265 | __raw_writel(grer, c->regbase + GRER_OFFSET); | |
266 | __raw_writel(gfer, c->regbase + GFER_OFFSET); | |
e3630db1 | 267 | } |
268 | ||
269 | static void pxa_unmask_muxed_gpio(unsigned int irq) | |
270 | { | |
0807da59 EM |
271 | int gpio = irq_to_gpio(irq); |
272 | struct pxa_gpio_chip *c = gpio_to_chip(gpio); | |
273 | ||
274 | c->irq_mask |= GPIO_bit(gpio); | |
275 | __raw_writel(c->irq_edge_rise & c->irq_mask, c->regbase + GRER_OFFSET); | |
276 | __raw_writel(c->irq_edge_fall & c->irq_mask, c->regbase + GFER_OFFSET); | |
e3630db1 | 277 | } |
278 | ||
279 | static struct irq_chip pxa_muxed_gpio_chip = { | |
280 | .name = "GPIO", | |
281 | .ack = pxa_ack_muxed_gpio, | |
282 | .mask = pxa_mask_muxed_gpio, | |
283 | .unmask = pxa_unmask_muxed_gpio, | |
284 | .set_type = pxa_gpio_irq_type, | |
285 | }; | |
286 | ||
a58fbcd8 | 287 | void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn) |
e3630db1 | 288 | { |
0807da59 EM |
289 | struct pxa_gpio_chip *c; |
290 | int gpio, irq; | |
e3630db1 | 291 | |
a58fbcd8 | 292 | pxa_last_gpio = end; |
e3630db1 | 293 | |
0807da59 EM |
294 | /* Initialize GPIO chips */ |
295 | pxa_init_gpio_chip(end); | |
296 | ||
e3630db1 | 297 | /* clear all GPIO edge detects */ |
0807da59 EM |
298 | for_each_gpio_chip(gpio, c) { |
299 | __raw_writel(0, c->regbase + GFER_OFFSET); | |
300 | __raw_writel(0, c->regbase + GRER_OFFSET); | |
301 | __raw_writel(~0,c->regbase + GEDR_OFFSET); | |
e3630db1 | 302 | } |
303 | ||
a58fbcd8 | 304 | for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) { |
e3630db1 | 305 | set_irq_chip(irq, &pxa_muxed_gpio_chip); |
306 | set_irq_handler(irq, handle_edge_irq); | |
307 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
308 | } | |
309 | ||
310 | /* Install handler for GPIO>=2 edge detect interrupts */ | |
a58fbcd8 | 311 | set_irq_chained_handler(mux_irq, pxa_gpio_demux_handler); |
b9e25ace | 312 | pxa_muxed_gpio_chip.set_wake = fn; |
e3630db1 | 313 | } |
663707c1 | 314 | |
315 | #ifdef CONFIG_PM | |
663707c1 | 316 | static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state) |
317 | { | |
0807da59 EM |
318 | struct pxa_gpio_chip *c; |
319 | int gpio; | |
663707c1 | 320 | |
0807da59 EM |
321 | for_each_gpio_chip(gpio, c) { |
322 | c->saved_gplr = __raw_readl(c->regbase + GPLR_OFFSET); | |
323 | c->saved_gpdr = __raw_readl(c->regbase + GPDR_OFFSET); | |
324 | c->saved_grer = __raw_readl(c->regbase + GRER_OFFSET); | |
325 | c->saved_gfer = __raw_readl(c->regbase + GFER_OFFSET); | |
663707c1 | 326 | |
327 | /* Clear GPIO transition detect bits */ | |
0807da59 | 328 | __raw_writel(0xffffffff, c->regbase + GEDR_OFFSET); |
663707c1 | 329 | } |
330 | return 0; | |
331 | } | |
332 | ||
333 | static int pxa_gpio_resume(struct sys_device *dev) | |
334 | { | |
0807da59 EM |
335 | struct pxa_gpio_chip *c; |
336 | int gpio; | |
663707c1 | 337 | |
0807da59 | 338 | for_each_gpio_chip(gpio, c) { |
663707c1 | 339 | /* restore level with set/clear */ |
0807da59 EM |
340 | __raw_writel( c->saved_gplr, c->regbase + GPSR_OFFSET); |
341 | __raw_writel(~c->saved_gplr, c->regbase + GPCR_OFFSET); | |
663707c1 | 342 | |
0807da59 EM |
343 | __raw_writel(c->saved_grer, c->regbase + GRER_OFFSET); |
344 | __raw_writel(c->saved_gfer, c->regbase + GFER_OFFSET); | |
345 | __raw_writel(c->saved_gpdr, c->regbase + GPDR_OFFSET); | |
663707c1 | 346 | } |
347 | return 0; | |
348 | } | |
349 | #else | |
350 | #define pxa_gpio_suspend NULL | |
351 | #define pxa_gpio_resume NULL | |
352 | #endif | |
353 | ||
354 | struct sysdev_class pxa_gpio_sysclass = { | |
355 | .name = "gpio", | |
356 | .suspend = pxa_gpio_suspend, | |
357 | .resume = pxa_gpio_resume, | |
358 | }; | |
359 | ||
360 | static int __init pxa_gpio_init(void) | |
361 | { | |
362 | return sysdev_class_register(&pxa_gpio_sysclass); | |
363 | } | |
364 | ||
365 | core_initcall(pxa_gpio_init); |