projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 | 1 | /* |
| a09e64fb | 2 | * arch/arm/mach-pxa/include/mach/pxa-regs.h |
| 1da177e4 LT |
3 | * |
| 4 | * Author: Nicolas Pitre | |
| 5 | * Created: Jun 15, 2001 | |
| 6 | * Copyright: MontaVista Software Inc. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License version 2 as | |
| 10 | * published by the Free Software Foundation. | |
| 11 | */ | |
| 12 | ||
| 13 | #ifndef __PXA_REGS_H | |
| 14 | #define __PXA_REGS_H | |
| 15 | ||
| 7e5abc46 | 16 | #include <mach/hardware.h> |
| 1da177e4 | 17 | |
| 1da177e4 LT |
18 | /* |
| 19 | * Real Time Clock | |
| 20 | */ | |
| 21 | ||
| 22 | #define RCNR __REG(0x40900000) /* RTC Count Register */ | |
| 23 | #define RTAR __REG(0x40900004) /* RTC Alarm Register */ | |
| 24 | #define RTSR __REG(0x40900008) /* RTC Status Register */ | |
| 25 | #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ | |
| 26 | #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */ | |
| 27 | ||
| 28 | #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */ | |
| 29 | #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */ | |
| 30 | #define RTSR_HZE (1 << 3) /* HZ interrupt enable */ | |
| 31 | #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ | |
| 32 | #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ | |
| 33 | #define RTSR_AL (1 << 0) /* RTC alarm detected */ | |
| 34 | ||
| 35 | ||
| 36 | /* | |
| 37 | * OS Timer & Match Registers | |
| 38 | */ | |
| 39 | ||
| 40 | #define OSMR0 __REG(0x40A00000) /* */ | |
| 41 | #define OSMR1 __REG(0x40A00004) /* */ | |
| 42 | #define OSMR2 __REG(0x40A00008) /* */ | |
| 43 | #define OSMR3 __REG(0x40A0000C) /* */ | |
| 44 | #define OSMR4 __REG(0x40A00080) /* */ | |
| 45 | #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ | |
| 46 | #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ | |
| 47 | #define OMCR4 __REG(0x40A000C0) /* */ | |
| 48 | #define OSSR __REG(0x40A00014) /* OS Timer Status Register */ | |
| 49 | #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ | |
| 50 | #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ | |
| 51 | ||
| 52 | #define OSSR_M3 (1 << 3) /* Match status channel 3 */ | |
| 53 | #define OSSR_M2 (1 << 2) /* Match status channel 2 */ | |
| 54 | #define OSSR_M1 (1 << 1) /* Match status channel 1 */ | |
| 55 | #define OSSR_M0 (1 << 0) /* Match status channel 0 */ | |
| 56 | ||
| 57 | #define OWER_WME (1 << 0) /* Watchdog Match Enable */ | |
| 58 | ||
| 59 | #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ | |
| 60 | #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ | |
| 61 | #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ | |
| 62 | #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ | |
| 63 | ||
| 64 | ||
| 1da177e4 LT |
65 | /* |
| 66 | * Interrupt Controller | |
| 67 | */ | |
| 68 | ||
| 69 | #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */ | |
| 70 | #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */ | |
| 71 | #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */ | |
| 72 | #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */ | |
| 73 | #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ | |
| 74 | #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ | |
| 75 | ||
| f6fb7af4 | 76 | #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ |
| 77 | #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ | |
| 78 | #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ | |
| 79 | #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ | |
| 80 | #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ | |
| 1da177e4 | 81 | |
| 1da177e4 | 82 | #endif |